homework_2/SRC/interface.sv


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

// using a virtual interface handle
interface des_if (
    input bit clk
);
  logic reset;
  logic inp;
  logic outp;

  clocking cb @(posedge clk);
    default input #1step output #3ns;
    input outp;
    output inp;
  endclocking
endinterface

// Top level test