blob: 89bd1ae7996899ad526380e3c97b672a5a7cec72 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
`include "macro.svh"
module tb;
logic clock = 1'b0;
logic reset;
logic input_;
logic output_;
localparam int SEQUENCE_LENGTH = 17;
logic [0:SEQUENCE_LENGTH-1] test_input = 17'b11110000101101100;
logic [0:SEQUENCE_LENGTH-1] expected_output = 17'b00000100000100101;
duv DUT (
.clock,
.reset,
.input_,
.output_
);
always #1ns clock = ~clock;
// Test sequence
initial begin
automatic int test_count = 0;
// Initialise
reset = 1'b1;
input_ = 1'b0;
// Hold reset for 2 cycles
repeat (2) @(posedge clock);
reset = 1'b0;
// Apply test sequence
for (int i = 0; i < SEQUENCE_LENGTH; i++) begin
input_ = test_input[i];
@(posedge clock);
// Check output
`FAIL_UNLESS_EQUAL(expected_output[i], output_, $sformatf("step=%0d input=%b", i + 1, input_))
test_count += 1;
end
$display("All tests passed! Total tests: %0d", test_count);
$display("Finished successfully!");
$finish;
end
endmodule
|