`include "macro.svh"

module tb;
  logic clock = 1'b0;
  logic reset;
  logic input_;
  logic output_;

  localparam int SEQUENCE_LENGTH = 17;

  logic [0:SEQUENCE_LENGTH-1] test_input = 17'b11110000101101100;
  logic [0:SEQUENCE_LENGTH-1] expected_output = 17'b00000100000100101;

  duv DUT (
      .clock,
      .reset,
      .input_,
      .output_
  );

  always #1ns clock = ~clock;

  // Test sequence
  initial begin
    automatic int test_count = 0;

    // Initialise
    reset  = 1'b1;
    input_ = 1'b0;

    // Hold reset for 2 cycles
    repeat (2) @(posedge clock);

    reset = 1'b0;

    // Apply test sequence
    for (int i = 0; i < SEQUENCE_LENGTH; i++) begin
      input_ = test_input[i];

      @(posedge clock);

      // Check output
      `FAIL_UNLESS_EQUAL(expected_output[i], output_, $sformatf("step=%0d input=%b", i + 1, input_))

      test_count += 1;
    end

    $display("All tests passed! Total tests: %0d", test_count);
    $display("Finished successfully!");
    $finish;
  end
endmodule