Added asmjit.

Fixed solution file.

28 files changed, 27154 insertions, 0 deletions

diff --git a/client/asmjit/x86/x86archdata.cpp b/client/asmjit/x86/x86archdata.cpp
new file mode 100644
index 0000000..cd928b2
--- /dev/null
+++ b/client/asmjit/x86/x86archdata.cpp
@@ -0,0 +1,137 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#include "../core/api-build_p.h"
+#ifdef ASMJIT_BUILD_X86
+
+#include "../core/support.h"
+#include "../core/type.h"
+#include "../x86/x86archdata_p.h"
+#include "../x86/x86operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::x86::ArchInternal]
+// ============================================================================
+
+namespace ArchInternal {
+
+Error typeIdToRegInfo(uint32_t arch, uint32_t typeId, uint32_t* typeIdOut, RegInfo* regInfoOut) noexcept {
+  // Passed RegType instead of TypeId?
+  if (typeId <= BaseReg::kTypeMax)
+    typeId = opData.archRegs.regTypeToTypeId[typeId];
+
+  if (ASMJIT_UNLIKELY(!Type::isValid(typeId)))
+    return DebugUtils::errored(kErrorInvalidTypeId);
+
+  // First normalize architecture dependent types.
+  if (Type::isAbstract(typeId)) {
+    bool is32Bit = arch == Environment::kArchX86;
+    if (typeId == Type::kIdIntPtr)
+      typeId = is32Bit ? Type::kIdI32 : Type::kIdI64;
+    else
+      typeId = is32Bit ? Type::kIdU32 : Type::kIdU64;
+  }
+
+  // Type size helps to construct all groups of registers.
+  // TypeId is invalid if the size is zero.
+  uint32_t size = Type::sizeOf(typeId);
+  if (ASMJIT_UNLIKELY(!size))
+    return DebugUtils::errored(kErrorInvalidTypeId);
+
+  if (ASMJIT_UNLIKELY(typeId == Type::kIdF80))
+    return DebugUtils::errored(kErrorInvalidUseOfF80);
+
+  uint32_t regType = 0;
+
+  switch (typeId) {
+    case Type::kIdI8:
+    case Type::kIdU8:
+      regType = Reg::kTypeGpbLo;
+      break;
+
+    case Type::kIdI16:
+    case Type::kIdU16:
+      regType = Reg::kTypeGpw;
+      break;
+
+    case Type::kIdI32:
+    case Type::kIdU32:
+      regType = Reg::kTypeGpd;
+      break;
+
+    case Type::kIdI64:
+    case Type::kIdU64:
+      if (arch == Environment::kArchX86)
+        return DebugUtils::errored(kErrorInvalidUseOfGpq);
+
+      regType = Reg::kTypeGpq;
+      break;
+
+    // F32 and F64 are always promoted to use vector registers.
+    case Type::kIdF32:
+      typeId = Type::kIdF32x1;
+      regType = Reg::kTypeXmm;
+      break;
+
+    case Type::kIdF64:
+      typeId = Type::kIdF64x1;
+      regType = Reg::kTypeXmm;
+      break;
+
+    // Mask registers {k}.
+    case Type::kIdMask8:
+    case Type::kIdMask16:
+    case Type::kIdMask32:
+    case Type::kIdMask64:
+      regType = Reg::kTypeKReg;
+      break;
+
+    // MMX registers.
+    case Type::kIdMmx32:
+    case Type::kIdMmx64:
+      regType = Reg::kTypeMm;
+      break;
+
+    // XMM|YMM|ZMM registers.
+    default:
+      if (size <= 16)
+        regType = Reg::kTypeXmm;
+      else if (size == 32)
+        regType = Reg::kTypeYmm;
+      else
+        regType = Reg::kTypeZmm;
+      break;
+  }
+
+  *typeIdOut = typeId;
+  regInfoOut->reset(opData.archRegs.regInfo[regType].signature());
+  return kErrorOk;
+}
+
+} // {ArchInternal}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86
diff --git a/client/asmjit/x86/x86archdata_p.h b/client/asmjit/x86/x86archdata_p.h
new file mode 100644
index 0000000..e765cb9
--- /dev/null
+++ b/client/asmjit/x86/x86archdata_p.h
@@ -0,0 +1,51 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86ARCHDATA_P_H_INCLUDED
+#define ASMJIT_X86_X86ARCHDATA_P_H_INCLUDED
+
+#include "../core/arch.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::x86::ArchInternal]
+// ============================================================================
+
+//! X86-specific function API (calling conventions and other utilities).
+namespace ArchInternal {
+
+Error typeIdToRegInfo(uint32_t arch, uint32_t typeId, uint32_t* typeIdOut, RegInfo* regInfoOut) noexcept;
+
+} // {ArchInternal}
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86ARCHDATA_P_H_INCLUDED
diff --git a/client/asmjit/x86/x86assembler.cpp b/client/asmjit/x86/x86assembler.cpp
new file mode 100644
index 0000000..7972283
--- /dev/null
+++ b/client/asmjit/x86/x86assembler.cpp
@@ -0,0 +1,4963 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#include "../core/api-build_p.h"
+#ifdef ASMJIT_BUILD_X86
+
+#include "../core/assembler.h"
+#include "../core/codebufferwriter_p.h"
+#include "../core/cpuinfo.h"
+#include "../core/emitterutils_p.h"
+#include "../core/formatter.h"
+#include "../core/logger.h"
+#include "../core/misc_p.h"
+#include "../core/support.h"
+#include "../x86/x86assembler.h"
+#include "../x86/x86instdb_p.h"
+#include "../x86/x86formatter_p.h"
+#include "../x86/x86opcode_p.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [TypeDefs]
+// ============================================================================
+
+typedef Support::FastUInt8 FastUInt8;
+
+// ============================================================================
+// [Constants]
+// ============================================================================
+
+//! X86 bytes used to encode important prefixes.
+enum X86Byte : uint32_t {
+  //! 1-byte REX prefix mask.
+  kX86ByteRex = 0x40,
+
+  //! 1-byte REX.W component.
+  kX86ByteRexW = 0x08,
+
+  kX86ByteInvalidRex = 0x80,
+
+  //! 2-byte VEX prefix:
+  //!   - `[0]` - `0xC5`.
+  //!   - `[1]` - `RvvvvLpp`.
+  kX86ByteVex2 = 0xC5,
+
+  //! 3-byte VEX prefix:
+  //!   - `[0]` - `0xC4`.
+  //!   - `[1]` - `RXBmmmmm`.
+  //!   - `[2]` - `WvvvvLpp`.
+  kX86ByteVex3 = 0xC4,
+
+  //! 3-byte XOP prefix:
+  //!   - `[0]` - `0x8F`.
+  //!   - `[1]` - `RXBmmmmm`.
+  //!   - `[2]` - `WvvvvLpp`.
+  kX86ByteXop3 = 0x8F,
+
+  //! 4-byte EVEX prefix:
+  //!   - `[0]` - `0x62`.
+  //!   - `[1]` - Payload0 or `P[ 7: 0]` - `[R  X  B  R' 0  0  m  m]`.
+  //!   - `[2]` - Payload1 or `P[15: 8]` - `[W  v  v  v  v  1  p  p]`.
+  //!   - `[3]` - Payload2 or `P[23:16]` - `[z  L' L  b  V' a  a  a]`.
+  //!
+  //! Payload:
+  //!   - `P[ 1: 0]` - OPCODE: EVEX.mmmmm, only lowest 2 bits [1:0] used.
+  //!   - `P[ 3: 2]` - ______: Must be 0.
+  //!   - `P[    4]` - REG-ID: EVEX.R' - 5th bit of 'RRRRR'.
+  //!   - `P[    5]` - REG-ID: EVEX.B  - 4th bit of 'BBBBB'.
+  //!   - `P[    6]` - REG-ID: EVEX.X  - 5th bit of 'BBBBB' or 4th bit of 'XXXX' (with SIB).
+  //!   - `P[    7]` - REG-ID: EVEX.R  - 4th bit of 'RRRRR'.
+  //!   - `P[ 9: 8]` - OPCODE: EVEX.pp.
+  //!   - `P[   10]` - ______: Must be 1.
+  //!   - `P[14:11]` - REG-ID: 4 bits of 'VVVV'.
+  //!   - `P[   15]` - OPCODE: EVEX.W.
+  //!   - `P[18:16]` - REG-ID: K register k0...k7 (Merging/Zeroing Vector Ops).
+  //!   - `P[   19]` - REG-ID: 5th bit of 'VVVVV'.
+  //!   - `P[   20]` - OPCODE: Broadcast/Rounding Control/SAE bit.
+  //!   - `P[22.21]` - OPCODE: Vector Length (L' and  L) / Rounding Control.
+  //!   - `P[   23]` - OPCODE: Zeroing/Merging.
+  kX86ByteEvex = 0x62
+};
+
+// AsmJit specific (used to encode VVVVV field in XOP/VEX/EVEX).
+enum VexVVVVV : uint32_t {
+  kVexVVVVVShift = 7,
+  kVexVVVVVMask = 0x1F << kVexVVVVVShift
+};
+
+//! Instruction 2-byte/3-byte opcode prefix definition.
+struct X86OpcodeMM {
+  uint8_t size;
+  uint8_t data[3];
+};
+
+//! Mandatory prefixes used to encode legacy [66, F3, F2] or [9B] byte.
+static const uint8_t x86OpcodePP[8] = { 0x00, 0x66, 0xF3, 0xF2, 0x00, 0x00, 0x00, 0x9B };
+
+//! Instruction 2-byte/3-byte opcode prefix data.
+static const X86OpcodeMM x86OpcodeMM[] = {
+  { 0, { 0x00, 0x00, 0 } }, // #00 (0b0000).
+  { 1, { 0x0F, 0x00, 0 } }, // #01 (0b0001).
+  { 2, { 0x0F, 0x38, 0 } }, // #02 (0b0010).
+  { 2, { 0x0F, 0x3A, 0 } }, // #03 (0b0011).
+  { 2, { 0x0F, 0x01, 0 } }, // #04 (0b0100).
+  { 0, { 0x00, 0x00, 0 } }, // #05 (0b0101).
+  { 0, { 0x00, 0x00, 0 } }, // #06 (0b0110).
+  { 0, { 0x00, 0x00, 0 } }, // #07 (0b0111).
+  { 0, { 0x00, 0x00, 0 } }, // #08 (0b1000).
+  { 0, { 0x00, 0x00, 0 } }, // #09 (0b1001).
+  { 0, { 0x00, 0x00, 0 } }, // #0A (0b1010).
+  { 0, { 0x00, 0x00, 0 } }, // #0B (0b1011).
+  { 0, { 0x00, 0x00, 0 } }, // #0C (0b1100).
+  { 0, { 0x00, 0x00, 0 } }, // #0D (0b1101).
+  { 0, { 0x00, 0x00, 0 } }, // #0E (0b1110).
+  { 0, { 0x00, 0x00, 0 } }  // #0F (0b1111).
+};
+
+static const uint8_t x86SegmentPrefix[8] = {
+  0x00, // None.
+  0x26, // ES.
+  0x2E, // CS.
+  0x36, // SS.
+  0x3E, // DS.
+  0x64, // FS.
+  0x65  // GS.
+};
+
+static const uint32_t x86OpcodePushSReg[8] = {
+  Opcode::k000000 | 0x00, // None.
+  Opcode::k000000 | 0x06, // Push ES.
+  Opcode::k000000 | 0x0E, // Push CS.
+  Opcode::k000000 | 0x16, // Push SS.
+  Opcode::k000000 | 0x1E, // Push DS.
+  Opcode::k000F00 | 0xA0, // Push FS.
+  Opcode::k000F00 | 0xA8  // Push GS.
+};
+
+static const uint32_t x86OpcodePopSReg[8]  = {
+  Opcode::k000000 | 0x00, // None.
+  Opcode::k000000 | 0x07, // Pop ES.
+  Opcode::k000000 | 0x00, // Pop CS.
+  Opcode::k000000 | 0x17, // Pop SS.
+  Opcode::k000000 | 0x1F, // Pop DS.
+  Opcode::k000F00 | 0xA1, // Pop FS.
+  Opcode::k000F00 | 0xA9  // Pop GS.
+};
+
+// ============================================================================
+// [asmjit::X86MemInfo | X86VEXPrefix | X86LLByRegType | X86CDisp8Table]
+// ============================================================================
+
+//! Memory operand's info bits.
+//!
+//! A lookup table that contains various information based on the BASE and INDEX
+//! information of a memory operand. This is much better and safer than playing
+//! with IFs in the code and can check for errors must faster and better.
+enum X86MemInfo_Enum {
+  kX86MemInfo_0         = 0x00,
+
+  kX86MemInfo_BaseGp    = 0x01, //!< Has BASE reg, REX.B can be 1, compatible with REX.B byte.
+  kX86MemInfo_Index     = 0x02, //!< Has INDEX reg, REX.X can be 1, compatible with REX.X byte.
+
+  kX86MemInfo_BaseLabel = 0x10, //!< Base is Label.
+  kX86MemInfo_BaseRip   = 0x20, //!< Base is RIP.
+
+  kX86MemInfo_67H_X86   = 0x40, //!< Address-size override in 32-bit mode.
+  kX86MemInfo_67H_X64   = 0x80, //!< Address-size override in 64-bit mode.
+  kX86MemInfo_67H_Mask  = 0xC0  //!< Contains all address-size override bits.
+};
+
+template<uint32_t X>
+struct X86MemInfo_T {
+  enum {
+    B = (X     ) & 0x1F,
+    I = (X >> 5) & 0x1F,
+
+    kBase  = (B >= Reg::kTypeGpw    && B <= Reg::kTypeGpq ) ? kX86MemInfo_BaseGp    :
+             (B == Reg::kTypeRip                          ) ? kX86MemInfo_BaseRip   :
+             (B == Label::kLabelTag                       ) ? kX86MemInfo_BaseLabel : 0,
+
+    kIndex = (I >= Reg::kTypeGpw    && I <= Reg::kTypeGpq ) ? kX86MemInfo_Index     :
+             (I >= Reg::kTypeXmm    && I <= Reg::kTypeZmm ) ? kX86MemInfo_Index     : 0,
+
+    k67H   = (B == Reg::kTypeGpw    && I == Reg::kTypeNone) ? kX86MemInfo_67H_X86   :
+             (B == Reg::kTypeGpd    && I == Reg::kTypeNone) ? kX86MemInfo_67H_X64   :
+             (B == Reg::kTypeNone   && I == Reg::kTypeGpw ) ? kX86MemInfo_67H_X86   :
+             (B == Reg::kTypeNone   && I == Reg::kTypeGpd ) ? kX86MemInfo_67H_X64   :
+             (B == Reg::kTypeGpw    && I == Reg::kTypeGpw ) ? kX86MemInfo_67H_X86   :
+             (B == Reg::kTypeGpd    && I == Reg::kTypeGpd ) ? kX86MemInfo_67H_X64   :
+             (B == Reg::kTypeGpw    && I == Reg::kTypeXmm ) ? kX86MemInfo_67H_X86   :
+             (B == Reg::kTypeGpd    && I == Reg::kTypeXmm ) ? kX86MemInfo_67H_X64   :
+             (B == Reg::kTypeGpw    && I == Reg::kTypeYmm ) ? kX86MemInfo_67H_X86   :
+             (B == Reg::kTypeGpd    && I == Reg::kTypeYmm ) ? kX86MemInfo_67H_X64   :
+             (B == Reg::kTypeGpw    && I == Reg::kTypeZmm ) ? kX86MemInfo_67H_X86   :
+             (B == Reg::kTypeGpd    && I == Reg::kTypeZmm ) ? kX86MemInfo_67H_X64   :
+             (B == Label::kLabelTag && I == Reg::kTypeGpw ) ? kX86MemInfo_67H_X86   :
+             (B == Label::kLabelTag && I == Reg::kTypeGpd ) ? kX86MemInfo_67H_X64   : 0,
+
+    kValue = kBase | kIndex | k67H | 0x04 | 0x08
+  };
+};
+
+// The result stored in the LUT is a combination of
+//   - 67H - Address override prefix - depends on BASE+INDEX register types and
+//           the target architecture.
+//   - REX - A possible combination of REX.[B|X|R|W] bits in REX prefix where
+//           REX.B and REX.X are possibly masked out, but REX.R and REX.W are
+//           kept as is.
+#define VALUE(X) X86MemInfo_T<X>::kValue
+static const uint8_t x86MemInfo[] = { ASMJIT_LOOKUP_TABLE_1024(VALUE, 0) };
+#undef VALUE
+
+// VEX3 or XOP xor bits applied to the opcode before emitted. The index to this
+// table is 'mmmmm' value, which contains all we need. This is only used by a
+// 3 BYTE VEX and XOP prefixes, 2 BYTE VEX prefix is handled differently. The
+// idea is to minimize the difference between VEX3 vs XOP when encoding VEX
+// or XOP instruction. This should minimize the code required to emit such
+// instructions and should also make it faster as we don't need any branch to
+// decide between VEX3 vs XOP.
+//            ____    ___
+// [_OPCODE_|WvvvvLpp|RXBmmmmm|VEX3_XOP]
+#define VALUE(X) ((X & 0x08) ? kX86ByteXop3 : kX86ByteVex3) | (0xF << 19) | (0x7 << 13)
+static const uint32_t x86VEXPrefix[] = { ASMJIT_LOOKUP_TABLE_16(VALUE, 0) };
+#undef VALUE
+
+// Table that contains LL opcode field addressed by a register size / 16. It's
+// used to propagate L.256 or L.512 when YMM or ZMM registers are used,
+// respectively.
+#define VALUE(X) (X & (64 >> 4)) ? Opcode::kLL_2 : \
+                 (X & (32 >> 4)) ? Opcode::kLL_1 : Opcode::kLL_0
+static const uint32_t x86LLBySizeDiv16[] = { ASMJIT_LOOKUP_TABLE_16(VALUE, 0) };
+#undef VALUE
+
+// Table that contains LL opcode field addressed by a register size / 16. It's
+// used to propagate L.256 or L.512 when YMM or ZMM registers are used,
+// respectively.
+#define VALUE(X) X == Reg::kTypeZmm ? Opcode::kLL_2 : \
+                 X == Reg::kTypeYmm ? Opcode::kLL_1 : Opcode::kLL_0
+static const uint32_t x86LLByRegType[] = { ASMJIT_LOOKUP_TABLE_16(VALUE, 0) };
+#undef VALUE
+
+// Table that contains a scale (shift left) based on 'TTWLL' field and
+// the instruction's tuple-type (TT) field. The scale is then applied to
+// the BASE-N stored in each opcode to calculate the final compressed
+// displacement used by all EVEX encoded instructions.
+template<uint32_t X>
+struct X86CDisp8SHL_T {
+  enum {
+    TT = (X >> 3) << Opcode::kCDTT_Shift,
+    LL = (X >> 0) & 0x3,
+    W  = (X >> 2) & 0x1,
+
+    kValue = (TT == Opcode::kCDTT_None ? ((LL==0) ? 0 : (LL==1) ? 0   : 0  ) :
+              TT == Opcode::kCDTT_ByLL ? ((LL==0) ? 0 : (LL==1) ? 1   : 2  ) :
+              TT == Opcode::kCDTT_T1W  ? ((LL==0) ? W : (LL==1) ? 1+W : 2+W) :
+              TT == Opcode::kCDTT_DUP  ? ((LL==0) ? 0 : (LL==1) ? 2   : 3  ) : 0) << Opcode::kCDSHL_Shift
+  };
+};
+
+#define VALUE(X) X86CDisp8SHL_T<X>::kValue
+static const uint32_t x86CDisp8SHL[] = { ASMJIT_LOOKUP_TABLE_32(VALUE, 0) };
+#undef VALUE
+
+// Table that contains MOD byte of a 16-bit [BASE + disp] address.
+//   0xFF == Invalid.
+static const uint8_t x86Mod16BaseTable[8] = {
+  0xFF, // AX -> N/A.
+  0xFF, // CX -> N/A.
+  0xFF, // DX -> N/A.
+  0x07, // BX -> 111.
+  0xFF, // SP -> N/A.
+  0x06, // BP -> 110.
+  0x04, // SI -> 100.
+  0x05  // DI -> 101.
+};
+
+// Table that contains MOD byte of a 16-bit [BASE + INDEX + disp] combination.
+//   0xFF == Invalid.
+template<uint32_t X>
+struct X86Mod16BaseIndexTable_T {
+  enum {
+    B = X >> 3,
+    I = X & 0x7,
+
+    kValue = ((B == Gp::kIdBx && I == Gp::kIdSi) || (B == Gp::kIdSi && I == Gp::kIdBx)) ? 0x00 :
+             ((B == Gp::kIdBx && I == Gp::kIdDi) || (B == Gp::kIdDi && I == Gp::kIdBx)) ? 0x01 :
+             ((B == Gp::kIdBp && I == Gp::kIdSi) || (B == Gp::kIdSi && I == Gp::kIdBp)) ? 0x02 :
+             ((B == Gp::kIdBp && I == Gp::kIdDi) || (B == Gp::kIdDi && I == Gp::kIdBp)) ? 0x03 : 0xFF
+  };
+};
+
+#define VALUE(X) X86Mod16BaseIndexTable_T<X>::kValue
+static const uint8_t x86Mod16BaseIndexTable[] = { ASMJIT_LOOKUP_TABLE_64(VALUE, 0) };
+#undef VALUE
+
+// ============================================================================
+// [asmjit::x86::Assembler - Helpers]
+// ============================================================================
+
+static ASMJIT_INLINE bool x86IsJmpOrCall(uint32_t instId) noexcept {
+  return instId == Inst::kIdJmp || instId == Inst::kIdCall;
+}
+
+static ASMJIT_INLINE bool x86IsImplicitMem(const Operand_& op, uint32_t base) noexcept {
+  return op.isMem() && op.as<Mem>().baseId() == base && !op.as<Mem>().hasOffset();
+}
+
+//! Combine `regId` and `vvvvvId` into a single value (used by AVX and AVX-512).
+static ASMJIT_INLINE uint32_t x86PackRegAndVvvvv(uint32_t regId, uint32_t vvvvvId) noexcept {
+  return regId + (vvvvvId << kVexVVVVVShift);
+}
+
+static ASMJIT_INLINE uint32_t x86OpcodeLByVMem(const Operand_& op) noexcept {
+  return x86LLByRegType[op.as<Mem>().indexType()];
+}
+
+static ASMJIT_INLINE uint32_t x86OpcodeLBySize(uint32_t size) noexcept {
+  return x86LLBySizeDiv16[size / 16];
+}
+
+//! Encode MOD byte.
+static ASMJIT_INLINE uint32_t x86EncodeMod(uint32_t m, uint32_t o, uint32_t rm) noexcept {
+  ASMJIT_ASSERT(m <= 3);
+  ASMJIT_ASSERT(o <= 7);
+  ASMJIT_ASSERT(rm <= 7);
+  return (m << 6) + (o << 3) + rm;
+}
+
+//! Encode SIB byte.
+static ASMJIT_INLINE uint32_t x86EncodeSib(uint32_t s, uint32_t i, uint32_t b) noexcept {
+  ASMJIT_ASSERT(s <= 3);
+  ASMJIT_ASSERT(i <= 7);
+  ASMJIT_ASSERT(b <= 7);
+  return (s << 6) + (i << 3) + b;
+}
+
+static ASMJIT_INLINE bool x86IsRexInvalid(uint32_t rex) noexcept {
+  // Validates the following possibilities:
+  //   REX == 0x00      -> OKAY (X86_32 / X86_64).
+  //   REX == 0x40-0x4F -> OKAY (X86_64).
+  //   REX == 0x80      -> OKAY (X86_32 mode, rex prefix not used).
+  //   REX == 0x81-0xCF -> BAD  (X86_32 mode, rex prefix used).
+  return rex > kX86ByteInvalidRex;
+}
+
+template<typename T>
+static constexpr T x86SignExtendI32(T imm) noexcept { return T(int64_t(int32_t(imm & T(0xFFFFFFFF)))); }
+
+static ASMJIT_INLINE uint32_t x86AltOpcodeOf(const InstDB::InstInfo* info) noexcept {
+  return InstDB::_altOpcodeTable[info->_altOpcodeIndex];
+}
+
+// ============================================================================
+// [asmjit::X86BufferWriter]
+// ============================================================================
+
+class X86BufferWriter : public CodeBufferWriter {
+public:
+  ASMJIT_INLINE explicit X86BufferWriter(Assembler* a) noexcept
+    : CodeBufferWriter(a) {}
+
+  ASMJIT_INLINE void emitPP(uint32_t opcode) noexcept {
+    uint32_t ppIndex = (opcode              >> Opcode::kPP_Shift) &
+                       (Opcode::kPP_FPUMask >> Opcode::kPP_Shift) ;
+    emit8If(x86OpcodePP[ppIndex], ppIndex != 0);
+  }
+
+  ASMJIT_INLINE void emitMMAndOpcode(uint32_t opcode) noexcept {
+    uint32_t mmIndex = (opcode & Opcode::kMM_Mask) >> Opcode::kMM_Shift;
+    const X86OpcodeMM& mmCode = x86OpcodeMM[mmIndex];
+
+    emit8If(mmCode.data[0], mmCode.size > 0);
+    emit8If(mmCode.data[1], mmCode.size > 1);
+    emit8(opcode);
+  }
+
+  ASMJIT_INLINE void emitSegmentOverride(uint32_t segmentId) noexcept {
+    ASMJIT_ASSERT(segmentId < ASMJIT_ARRAY_SIZE(x86SegmentPrefix));
+
+    FastUInt8 prefix = x86SegmentPrefix[segmentId];
+    emit8If(prefix, prefix != 0);
+  }
+
+  template<typename CondT>
+  ASMJIT_INLINE void emitAddressOverride(CondT condition) noexcept {
+    emit8If(0x67, condition);
+  }
+
+  ASMJIT_INLINE void emitImmByteOrDWord(uint64_t immValue, FastUInt8 immSize) noexcept {
+    if (!immSize)
+      return;
+
+    ASMJIT_ASSERT(immSize == 1 || immSize == 4);
+
+#if ASMJIT_ARCH_BITS >= 64
+    uint64_t imm = uint64_t(immValue);
+#else
+    uint32_t imm = uint32_t(immValue & 0xFFFFFFFFu);
+#endif
+
+    // Many instructions just use a single byte immediate, so make it fast.
+    emit8(imm & 0xFFu);
+    if (immSize == 1) return;
+
+    imm >>= 8;
+    emit8(imm & 0xFFu);
+    imm >>= 8;
+    emit8(imm & 0xFFu);
+    imm >>= 8;
+    emit8(imm & 0xFFu);
+  }
+
+  ASMJIT_INLINE void emitImmediate(uint64_t immValue, FastUInt8 immSize) noexcept {
+    if (!immSize)
+      return;
+
+#if ASMJIT_ARCH_BITS >= 64
+    uint64_t imm = uint64_t(immValue);
+#else
+    uint32_t imm = uint32_t(immValue & 0xFFFFFFFFu);
+#endif
+
+    // Many instructions just use a single byte immediate, so make it fast.
+    emit8(imm & 0xFFu);
+    if (--immSize == 0) return;
+
+    imm >>= 8;
+    emit8(imm & 0xFFu);
+    if (--immSize == 0) return;
+
+    imm >>= 8;
+    emit8(imm & 0xFFu);
+    if (--immSize == 0) return;
+
+    imm >>= 8;
+    emit8(imm & 0xFFu);
+    if (--immSize == 0) return;
+
+    // Can be 1, 2, 4 or 8 bytes, this handles the remaining high DWORD of an 8-byte immediate.
+    ASMJIT_ASSERT(immSize == 4);
+
+#if ASMJIT_ARCH_BITS >= 64
+    imm >>= 8;
+    emit32uLE(uint32_t(imm));
+#else
+    emit32uLE(uint32_t((uint64_t(immValue) >> 32) & 0xFFFFFFFFu));
+#endif
+  }
+};
+
+// If the operand is BPL|SPL|SIL|DIL|R8B-15B
+//   - Force REX prefix
+// If the operand is AH|BH|CH|DH
+//   - patch its index from 0..3 to 4..7 as encoded by X86.
+//   - Disallow REX prefix.
+#define FIXUP_GPB(REG_OP, REG_ID)                           \
+  do {                                                      \
+    if (!static_cast<const Gp&>(REG_OP).isGpbHi()) {        \
+      options |= (REG_ID >= 4) ? uint32_t(Inst::kOptionRex) \
+                               : uint32_t(0);               \
+    }                                                       \
+    else {                                                  \
+      options |= Inst::_kOptionInvalidRex;                  \
+      REG_ID += 4;                                          \
+    }                                                       \
+  } while (0)
+
+#define ENC_OPS1(OP0)                ((Operand::kOp##OP0))
+#define ENC_OPS2(OP0, OP1)           ((Operand::kOp##OP0) + ((Operand::kOp##OP1) << 3))
+#define ENC_OPS3(OP0, OP1, OP2)      ((Operand::kOp##OP0) + ((Operand::kOp##OP1) << 3) + ((Operand::kOp##OP2) << 6))
+#define ENC_OPS4(OP0, OP1, OP2, OP3) ((Operand::kOp##OP0) + ((Operand::kOp##OP1) << 3) + ((Operand::kOp##OP2) << 6) + ((Operand::kOp##OP3) << 9))
+
+// ============================================================================
+// [asmjit::x86::Assembler - Movabs Heuristics]
+// ============================================================================
+
+static ASMJIT_INLINE bool x86GetMovAbsInstSize64Bit(uint32_t regSize, uint32_t options, const Mem& rmRel) noexcept {
+  uint32_t segmentPrefixSize = rmRel.segmentId() != 0;
+  uint32_t _66hPrefixSize = regSize == 2;
+  uint32_t rexPrefixSize = (regSize == 8) || ((options & Inst::kOptionRex) != 0);
+  uint32_t opCodeByteSize = 1;
+  uint32_t immediateSize = 8;
+
+  return segmentPrefixSize + _66hPrefixSize + rexPrefixSize + opCodeByteSize + immediateSize;
+}
+
+static ASMJIT_INLINE uint32_t x86GetMovAbsAddrType(Assembler* self, X86BufferWriter& writer, uint32_t regSize, uint32_t options, const Mem& rmRel) noexcept {
+  uint32_t addrType = rmRel.addrType();
+  int64_t addrValue = rmRel.offset();
+
+  if (addrType == BaseMem::kAddrTypeDefault && !(options & Inst::kOptionModMR)) {
+    if (self->is64Bit()) {
+      uint64_t baseAddress = self->code()->baseAddress();
+      if (baseAddress != Globals::kNoBaseAddress && !rmRel.hasSegment()) {
+        uint32_t instructionSize = x86GetMovAbsInstSize64Bit(regSize, options, rmRel);
+        uint64_t virtualOffset = uint64_t(writer.offsetFrom(self->_bufferData));
+        uint64_t rip64 = baseAddress + self->_section->offset() + virtualOffset + instructionSize;
+        uint64_t rel64 = uint64_t(addrValue) - rip64;
+
+        if (!Support::isInt32(int64_t(rel64)))
+          addrType = BaseMem::kAddrTypeAbs;
+      }
+      else {
+        if (!Support::isInt32(addrValue))
+          addrType = BaseMem::kAddrTypeAbs;
+      }
+    }
+    else {
+      addrType = BaseMem::kAddrTypeAbs;
+    }
+  }
+
+  return addrType;
+}
+
+// ============================================================================
+// [asmjit::x86::Assembler - Construction / Destruction]
+// ============================================================================
+
+Assembler::Assembler(CodeHolder* code) noexcept : BaseAssembler() {
+  if (code)
+    code->attach(this);
+}
+Assembler::~Assembler() noexcept {}
+
+// ============================================================================
+// [asmjit::x86::Assembler - Emit (Low-Level)]
+// ============================================================================
+
+ASMJIT_FAVOR_SPEED Error Assembler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_* opExt) {
+  constexpr uint32_t kVSHR_W     = Opcode::kW_Shift  - 23;
+  constexpr uint32_t kVSHR_PP    = Opcode::kPP_Shift - 16;
+  constexpr uint32_t kVSHR_PP_EW = Opcode::kPP_Shift - 16;
+
+  constexpr uint32_t kRequiresSpecialHandling =
+    uint32_t(Inst::kOptionReserved) | // Logging/Validation/Error.
+    uint32_t(Inst::kOptionRep     ) | // REP/REPE prefix.
+    uint32_t(Inst::kOptionRepne   ) | // REPNE prefix.
+    uint32_t(Inst::kOptionLock    ) | // LOCK prefix.
+    uint32_t(Inst::kOptionXAcquire) | // XACQUIRE prefix.
+    uint32_t(Inst::kOptionXRelease) ; // XRELEASE prefix.
+
+  Error err;
+
+  Opcode opcode;                   // Instruction opcode.
+  uint32_t options;                // Instruction options.
+  uint32_t isign3;                 // A combined signature of first 3 operands.
+
+  const Operand_* rmRel;           // Memory operand or operand that holds Label|Imm.
+  uint32_t rmInfo;                 // Memory operand's info based on x86MemInfo.
+  uint32_t rbReg;                  // Memory base or modRM register.
+  uint32_t rxReg;                  // Memory index register.
+  uint32_t opReg;                  // ModR/M opcode or register id.
+
+  LabelEntry* label;               // Label entry.
+  RelocEntry* re = nullptr;        // Relocation entry.
+  int32_t relOffset;               // Relative offset
+  FastUInt8 relSize = 0;           // Relative size.
+  uint8_t* memOpAOMark = nullptr;  // Marker that points before 'address-override prefix' is emitted.
+
+  int64_t immValue = 0;            // Immediate value (must be 64-bit).
+  FastUInt8 immSize = 0;           // Immediate size.
+
+  X86BufferWriter writer(this);
+
+  if (instId >= Inst::_kIdCount)
+    instId = 0;
+
+  const InstDB::InstInfo* instInfo = &InstDB::_instInfoTable[instId];
+  const InstDB::CommonInfo* commonInfo = &instInfo->commonInfo();
+
+  // Signature of the first 3 operands.
+  isign3 = o0.opType() + (o1.opType() << 3) + (o2.opType() << 6);
+
+  // Combine all instruction options and also check whether the instruction
+  // is valid. All options that require special handling (including invalid
+  // instruction) are handled by the next branch.
+  options  = uint32_t(instId == 0);
+  options |= uint32_t((size_t)(_bufferEnd - writer.cursor()) < 16);
+  options |= uint32_t(instOptions() | forcedInstOptions());
+
+  // Handle failure and rare cases first.
+  if (ASMJIT_UNLIKELY(options & kRequiresSpecialHandling)) {
+    if (ASMJIT_UNLIKELY(!_code))
+      return reportError(DebugUtils::errored(kErrorNotInitialized));
+
+    // Unknown instruction.
+    if (ASMJIT_UNLIKELY(instId == 0))
+      goto InvalidInstruction;
+
+    // Grow request, happens rarely.
+    err = writer.ensureSpace(this, 16);
+    if (ASMJIT_UNLIKELY(err))
+      goto Failed;
+
+#ifndef ASMJIT_NO_VALIDATION
+    // Strict validation.
+    if (hasValidationOption(kValidationOptionAssembler)) {
+      Operand_ opArray[Globals::kMaxOpCount];
+      EmitterUtils::opArrayFromEmitArgs(opArray, o0, o1, o2, opExt);
+
+      err = InstAPI::validate(arch(), BaseInst(instId, options, _extraReg), opArray, Globals::kMaxOpCount);
+      if (ASMJIT_UNLIKELY(err))
+        goto Failed;
+    }
+#endif
+
+    uint32_t iFlags = instInfo->flags();
+
+    // LOCK, XACQUIRE, and XRELEASE prefixes.
+    if (options & Inst::kOptionLock) {
+      bool xAcqRel = (options & (Inst::kOptionXAcquire | Inst::kOptionXRelease)) != 0;
+
+      if (ASMJIT_UNLIKELY(!(iFlags & (InstDB::kFlagLock)) && !xAcqRel))
+        goto InvalidLockPrefix;
+
+      if (xAcqRel) {
+        if (ASMJIT_UNLIKELY((options & Inst::kOptionXAcquire) && !(iFlags & InstDB::kFlagXAcquire)))
+          goto InvalidXAcquirePrefix;
+
+        if (ASMJIT_UNLIKELY((options & Inst::kOptionXRelease) && !(iFlags & InstDB::kFlagXRelease)))
+          goto InvalidXReleasePrefix;
+
+        writer.emit8((options & Inst::kOptionXAcquire) ? 0xF2 : 0xF3);
+      }
+
+      writer.emit8(0xF0);
+    }
+
+    // REP and REPNE prefixes.
+    if (options & (Inst::kOptionRep | Inst::kOptionRepne)) {
+      if (ASMJIT_UNLIKELY(!(iFlags & InstDB::kFlagRep)))
+        goto InvalidRepPrefix;
+
+      if (_extraReg.isReg() && ASMJIT_UNLIKELY(_extraReg.group() != Reg::kGroupGp || _extraReg.id() != Gp::kIdCx))
+        goto InvalidRepPrefix;
+
+      writer.emit8((options & Inst::kOptionRepne) ? 0xF2 : 0xF3);
+    }
+  }
+
+  // This sequence seems to be the fastest.
+  opcode = InstDB::_mainOpcodeTable[instInfo->_mainOpcodeIndex];
+  opReg = opcode.extractModO();
+  rbReg = 0;
+  opcode |= instInfo->_mainOpcodeValue;
+
+  // --------------------------------------------------------------------------
+  // [Encoding Scope]
+  // --------------------------------------------------------------------------
+
+  // How it works? Each case here represents a unique encoding of a group of
+  // instructions, which is handled separately. The handlers check instruction
+  // signature, possibly register types, etc, and process this information by
+  // writing some bits to opcode, opReg/rbReg, immValue/immSize, etc, and then
+  // at the end of the sequence it uses goto to jump into a lower level handler,
+  // that actually encodes the instruction.
+
+  switch (instInfo->_encoding) {
+    case InstDB::kEncodingNone:
+      goto EmitDone;
+
+    // ------------------------------------------------------------------------
+    // [X86]
+    // ------------------------------------------------------------------------
+
+    case InstDB::kEncodingX86Op:
+      goto EmitX86Op;
+
+    case InstDB::kEncodingX86Op_Mod11RM:
+      rbReg = opcode.extractModRM();
+      goto EmitX86R;
+
+    case InstDB::kEncodingX86Op_Mod11RM_I8:
+      if (ASMJIT_UNLIKELY(isign3 != ENC_OPS1(Imm)))
+        goto InvalidInstruction;
+
+      rbReg = opcode.extractModRM();
+      immValue = o0.as<Imm>().valueAs<uint8_t>();
+      immSize = 1;
+      goto EmitX86R;
+
+    case InstDB::kEncodingX86Op_xAddr:
+      if (ASMJIT_UNLIKELY(!o0.isReg()))
+        goto InvalidInstruction;
+
+      rmInfo = x86MemInfo[o0.as<Reg>().type()];
+      writer.emitAddressOverride((rmInfo & _addressOverrideMask()) != 0);
+      goto EmitX86Op;
+
+    case InstDB::kEncodingX86Op_xAX:
+      if (isign3 == 0)
+        goto EmitX86Op;
+
+      if (isign3 == ENC_OPS1(Reg) && o0.id() == Gp::kIdAx)
+        goto EmitX86Op;
+      break;
+
+    case InstDB::kEncodingX86Op_xDX_xAX:
+      if (isign3 == 0)
+        goto EmitX86Op;
+
+      if (isign3 == ENC_OPS2(Reg, Reg) && o0.id() == Gp::kIdDx && o1.id() == Gp::kIdAx)
+        goto EmitX86Op;
+      break;
+
+    case InstDB::kEncodingX86Op_MemZAX:
+      if (isign3 == 0)
+        goto EmitX86Op;
+
+      rmRel = &o0;
+      if (isign3 == ENC_OPS1(Mem) && x86IsImplicitMem(o0, Gp::kIdAx))
+        goto EmitX86OpImplicitMem;
+
+      break;
+
+    case InstDB::kEncodingX86I_xAX:
+      // Implicit form.
+      if (isign3 == ENC_OPS1(Imm)) {
+        immValue = o0.as<Imm>().valueAs<uint8_t>();
+        immSize = 1;
+        goto EmitX86Op;
+      }
+
+      // Explicit form.
+      if (isign3 == ENC_OPS2(Reg, Imm) && o0.id() == Gp::kIdAx) {
+        immValue = o1.as<Imm>().valueAs<uint8_t>();
+        immSize = 1;
+        goto EmitX86Op;
+      }
+      break;
+
+    case InstDB::kEncodingX86M:
+      opcode.addPrefixBySize(o0.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingX86M_NoSize:
+      rbReg = o0.id();
+      if (isign3 == ENC_OPS1(Reg))
+        goto EmitX86R;
+
+      rmRel = &o0;
+      if (isign3 == ENC_OPS1(Mem))
+        goto EmitX86M;
+      break;
+
+    case InstDB::kEncodingX86M_GPB_MulDiv:
+CaseX86M_GPB_MulDiv:
+      // Explicit form?
+      if (isign3 > 0x7) {
+        // [AX] <- [AX] div|mul r8.
+        if (isign3 == ENC_OPS2(Reg, Reg)) {
+          if (ASMJIT_UNLIKELY(!Reg::isGpw(o0, Gp::kIdAx) || !Reg::isGpb(o1)))
+            goto InvalidInstruction;
+
+          rbReg = o1.id();
+          FIXUP_GPB(o1, rbReg);
+          goto EmitX86R;
+        }
+
+        // [AX] <- [AX] div|mul m8.
+        if (isign3 == ENC_OPS2(Reg, Mem)) {
+          if (ASMJIT_UNLIKELY(!Reg::isGpw(o0, Gp::kIdAx)))
+            goto InvalidInstruction;
+
+          rmRel = &o1;
+          goto EmitX86M;
+        }
+
+        // [?DX:?AX] <- [?DX:?AX] div|mul r16|r32|r64
+        if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+          if (ASMJIT_UNLIKELY(o0.size() != o1.size()))
+            goto InvalidInstruction;
+
+          opcode.addArithBySize(o0.size());
+          rbReg = o2.id();
+          goto EmitX86R;
+        }
+
+        // [?DX:?AX] <- [?DX:?AX] div|mul m16|m32|m64
+        if (isign3 == ENC_OPS3(Reg, Reg, Mem)) {
+          if (ASMJIT_UNLIKELY(o0.size() != o1.size()))
+            goto InvalidInstruction;
+
+          opcode.addArithBySize(o0.size());
+          rmRel = &o2;
+          goto EmitX86M;
+        }
+
+        goto InvalidInstruction;
+      }
+
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingX86M_GPB:
+      if (isign3 == ENC_OPS1(Reg)) {
+        opcode.addArithBySize(o0.size());
+        rbReg = o0.id();
+
+        if (o0.size() != 1)
+          goto EmitX86R;
+
+        FIXUP_GPB(o0, rbReg);
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS1(Mem)) {
+        if (ASMJIT_UNLIKELY(o0.size() == 0))
+          goto AmbiguousOperandSize;
+
+        opcode.addArithBySize(o0.size());
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86M_Only:
+      if (isign3 == ENC_OPS1(Mem)) {
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86M_Nop:
+      if (isign3 == ENC_OPS1(None))
+        goto EmitX86Op;
+
+      // Single operand NOP instruction "0F 1F /0".
+      opcode = Opcode::k000F00 | 0x1F;
+      opReg = 0;
+
+      if (isign3 == ENC_OPS1(Reg)) {
+        opcode.addPrefixBySize(o0.size());
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS1(Mem)) {
+        opcode.addPrefixBySize(o0.size());
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+
+      // Two operand NOP instruction "0F 1F /r".
+      opReg = o1.id();
+      opcode.addPrefixBySize(o1.size());
+
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86R_FromM:
+      if (isign3 == ENC_OPS1(Mem)) {
+        rmRel = &o0;
+        rbReg = o0.id();
+        goto EmitX86RFromM;
+      }
+      break;
+
+    case InstDB::kEncodingX86R32_EDX_EAX:
+      // Explicit form: R32, EDX, EAX.
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        if (!Reg::isGpd(o1, Gp::kIdDx) || !Reg::isGpd(o2, Gp::kIdAx))
+          goto InvalidInstruction;
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      // Implicit form: R32.
+      if (isign3 == ENC_OPS1(Reg)) {
+        if (!Reg::isGpd(o0))
+          goto InvalidInstruction;
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+      break;
+
+    case InstDB::kEncodingX86R_Native:
+      if (isign3 == ENC_OPS1(Reg)) {
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+      break;
+
+    case InstDB::kEncodingX86Rm:
+      opcode.addPrefixBySize(o0.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingX86Rm_NoSize:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Rm_Raw66H:
+      // We normally emit either [66|F2|F3], this instruction requires 66+[F2|F3].
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        if (o0.size() == 2)
+          writer.emit8(0x66);
+        else
+          opcode.addWBySize(o0.size());
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+
+        if (o0.size() == 2)
+          writer.emit8(0x66);
+        else
+          opcode.addWBySize(o0.size());
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Mr:
+      opcode.addPrefixBySize(o0.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingX86Mr_NoSize:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        rbReg = o0.id();
+        opReg = o1.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        rmRel = &o0;
+        opReg = o1.id();
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Arith:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opcode += 2;
+        opcode.addArithBySize(o0.size());
+
+        if (o0.size() != o1.size())
+          goto OperandSizeMismatch;
+
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        if (o0.size() == 1) {
+          FIXUP_GPB(o0, opReg);
+          FIXUP_GPB(o1, rbReg);
+
+          if (!(options & Inst::kOptionModMR))
+            goto EmitX86R;
+
+          opcode -= 2;
+          std::swap(opReg, rbReg);
+          goto EmitX86R;
+        }
+        else {
+          if (!(options & Inst::kOptionModMR))
+            goto EmitX86R;
+
+          opcode -= 2;
+          std::swap(opReg, rbReg);
+          goto EmitX86R;
+        }
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opcode += 2;
+        opcode.addArithBySize(o0.size());
+
+        opReg = o0.id();
+        rmRel = &o1;
+
+        if (o0.size() != 1)
+          goto EmitX86M;
+
+        FIXUP_GPB(o0, opReg);
+        goto EmitX86M;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opcode.addArithBySize(o1.size());
+        opReg = o1.id();
+        rmRel = &o0;
+
+        if (o1.size() != 1)
+          goto EmitX86M;
+
+        FIXUP_GPB(o1, opReg);
+        goto EmitX86M;
+      }
+
+      // The remaining instructions use 0x80 opcode.
+      opcode = 0x80;
+
+      if (isign3 == ENC_OPS2(Reg, Imm)) {
+        uint32_t size = o0.size();
+
+        rbReg = o0.id();
+        immValue = o1.as<Imm>().value();
+
+        if (size == 1) {
+          FIXUP_GPB(o0, rbReg);
+          immSize = 1;
+        }
+        else {
+          if (size == 2) {
+            opcode |= Opcode::kPP_66;
+          }
+          else if (size == 4) {
+            // Sign extend so isInt8 returns the right result.
+            immValue = x86SignExtendI32<int64_t>(immValue);
+          }
+          else if (size == 8) {
+            bool canTransformTo32Bit = instId == Inst::kIdAnd && Support::isUInt32(immValue);
+
+            if (!Support::isInt32(immValue)) {
+              // We would do this by default when `kOptionOptimizedForSize` is
+              // enabled, however, in this case we just force this as otherwise
+              // we would have to fail.
+              if (canTransformTo32Bit)
+                size = 4;
+              else
+                goto InvalidImmediate;
+            }
+            else if (canTransformTo32Bit && hasEncodingOption(kEncodingOptionOptimizeForSize)) {
+              size = 4;
+            }
+
+            opcode.addWBySize(size);
+          }
+
+          immSize = FastUInt8(Support::min<uint32_t>(size, 4));
+          if (Support::isInt8(immValue) && !(options & Inst::kOptionLongForm))
+            immSize = 1;
+        }
+
+        // Short form - AL, AX, EAX, RAX.
+        if (rbReg == 0 && (size == 1 || immSize != 1) && !(options & Inst::kOptionLongForm)) {
+          opcode &= Opcode::kPP_66 | Opcode::kW;
+          opcode |= ((opReg << 3) | (0x04 + (size != 1)));
+          immSize = FastUInt8(Support::min<uint32_t>(size, 4));
+          goto EmitX86Op;
+        }
+
+        opcode += size != 1 ? (immSize != 1 ? 1 : 3) : 0;
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Imm)) {
+        uint32_t memSize = o0.size();
+
+        if (ASMJIT_UNLIKELY(memSize == 0))
+          goto AmbiguousOperandSize;
+
+        immValue = o1.as<Imm>().value();
+        immSize = FastUInt8(Support::min<uint32_t>(memSize, 4));
+
+        // Sign extend so isInt8 returns the right result.
+        if (memSize == 4)
+          immValue = x86SignExtendI32<int64_t>(immValue);
+
+        if (Support::isInt8(immValue) && !(options & Inst::kOptionLongForm))
+          immSize = 1;
+
+        opcode += memSize != 1 ? (immSize != 1 ? 1 : 3) : 0;
+        opcode.addPrefixBySize(memSize);
+
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Bswap:
+      if (isign3 == ENC_OPS1(Reg)) {
+        if (ASMJIT_UNLIKELY(o0.size() == 1))
+          goto InvalidInstruction;
+
+        opReg = o0.id();
+        opcode.addPrefixBySize(o0.size());
+        goto EmitX86OpReg;
+      }
+      break;
+
+    case InstDB::kEncodingX86Bt:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opcode.addPrefixBySize(o1.size());
+        opReg = o1.id();
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opcode.addPrefixBySize(o1.size());
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+
+      // The remaining instructions use the secondary opcode/r.
+      immValue = o1.as<Imm>().value();
+      immSize = 1;
+
+      opcode = x86AltOpcodeOf(instInfo);
+      opcode.addPrefixBySize(o0.size());
+      opReg = opcode.extractModO();
+
+      if (isign3 == ENC_OPS2(Reg, Imm)) {
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Imm)) {
+        if (ASMJIT_UNLIKELY(o0.size() == 0))
+          goto AmbiguousOperandSize;
+
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Call:
+      if (isign3 == ENC_OPS1(Reg)) {
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      rmRel = &o0;
+      if (isign3 == ENC_OPS1(Mem))
+        goto EmitX86M;
+
+      // Call with 32-bit displacement use 0xE8 opcode. Call with 8-bit
+      // displacement is not encodable so the alternative opcode field
+      // in X86DB must be zero.
+      opcode = 0xE8;
+      opReg = 0;
+      goto EmitJmpCall;
+
+    case InstDB::kEncodingX86Cmpxchg: {
+      // Convert explicit to implicit.
+      if (isign3 & (0x7 << 6)) {
+        if (!Reg::isGp(o2) || o2.id() != Gp::kIdAx)
+          goto InvalidInstruction;
+        isign3 &= 0x3F;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        if (o0.size() != o1.size())
+          goto OperandSizeMismatch;
+
+        opcode.addArithBySize(o0.size());
+        rbReg = o0.id();
+        opReg = o1.id();
+
+        if (o0.size() != 1)
+          goto EmitX86R;
+
+        FIXUP_GPB(o0, rbReg);
+        FIXUP_GPB(o1, opReg);
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opcode.addArithBySize(o1.size());
+        opReg = o1.id();
+        rmRel = &o0;
+
+        if (o1.size() != 1)
+          goto EmitX86M;
+
+        FIXUP_GPB(o0, opReg);
+        goto EmitX86M;
+      }
+      break;
+    }
+
+    case InstDB::kEncodingX86Cmpxchg8b_16b: {
+      const Operand_& o3 = opExt[EmitterUtils::kOp3];
+      const Operand_& o4 = opExt[EmitterUtils::kOp4];
+
+      if (isign3 == ENC_OPS3(Mem, Reg, Reg)) {
+        if (o3.isReg() && o4.isReg()) {
+          rmRel = &o0;
+          goto EmitX86M;
+        }
+      }
+
+      if (isign3 == ENC_OPS1(Mem)) {
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+    }
+
+    case InstDB::kEncodingX86Crc:
+      opReg = o0.id();
+      opcode.addWBySize(o0.size());
+
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        rbReg = o1.id();
+
+        if (o1.size() == 1) {
+          FIXUP_GPB(o1, rbReg);
+          goto EmitX86R;
+        }
+        else {
+          // This seems to be the only exception of encoding '66F2' prefix.
+          if (o1.size() == 2) writer.emit8(0x66);
+
+          opcode.add(1);
+          goto EmitX86R;
+        }
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        rmRel = &o1;
+        if (o1.size() == 0)
+          goto AmbiguousOperandSize;
+
+        // This seems to be the only exception of encoding '66F2' prefix.
+        if (o1.size() == 2) writer.emit8(0x66);
+
+        opcode += o1.size() != 1;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Enter:
+      if (isign3 == ENC_OPS2(Imm, Imm)) {
+        uint32_t iw = o0.as<Imm>().valueAs<uint16_t>();
+        uint32_t ib = o1.as<Imm>().valueAs<uint8_t>();
+
+        immValue = iw | (ib << 16);
+        immSize = 3;
+        goto EmitX86Op;
+      }
+      break;
+
+    case InstDB::kEncodingX86Imul:
+      // First process all forms distinct of `kEncodingX86M_OptB_MulDiv`.
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opcode = 0x6B;
+        opcode.addPrefixBySize(o0.size());
+
+        immValue = o2.as<Imm>().value();
+        immSize = 1;
+
+        if (!Support::isInt8(immValue) || (options & Inst::kOptionLongForm)) {
+          opcode -= 2;
+          immSize = o0.size() == 2 ? 2 : 4;
+        }
+
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Imm)) {
+        opcode = 0x6B;
+        opcode.addPrefixBySize(o0.size());
+
+        immValue = o2.as<Imm>().value();
+        immSize = 1;
+
+        // Sign extend so isInt8 returns the right result.
+        if (o0.size() == 4)
+          immValue = x86SignExtendI32<int64_t>(immValue);
+
+        if (!Support::isInt8(immValue) || (options & Inst::kOptionLongForm)) {
+          opcode -= 2;
+          immSize = o0.size() == 2 ? 2 : 4;
+        }
+
+        opReg = o0.id();
+        rmRel = &o1;
+
+        goto EmitX86M;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        // Must be explicit 'ax, r8' form.
+        if (o1.size() == 1)
+          goto CaseX86M_GPB_MulDiv;
+
+        if (o0.size() != o1.size())
+          goto OperandSizeMismatch;
+
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        opcode = Opcode::k000F00 | 0xAF;
+        opcode.addPrefixBySize(o0.size());
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        // Must be explicit 'ax, m8' form.
+        if (o1.size() == 1)
+          goto CaseX86M_GPB_MulDiv;
+
+        opReg = o0.id();
+        rmRel = &o1;
+
+        opcode = Opcode::k000F00 | 0xAF;
+        opcode.addPrefixBySize(o0.size());
+        goto EmitX86M;
+      }
+
+      // Shorthand to imul 'reg, reg, imm'.
+      if (isign3 == ENC_OPS2(Reg, Imm)) {
+        opcode = 0x6B;
+        opcode.addPrefixBySize(o0.size());
+
+        immValue = o1.as<Imm>().value();
+        immSize = 1;
+
+        // Sign extend so isInt8 returns the right result.
+        if (o0.size() == 4)
+          immValue = x86SignExtendI32<int64_t>(immValue);
+
+        if (!Support::isInt8(immValue) || (options & Inst::kOptionLongForm)) {
+          opcode -= 2;
+          immSize = o0.size() == 2 ? 2 : 4;
+        }
+
+        opReg = rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      // Try implicit form.
+      goto CaseX86M_GPB_MulDiv;
+
+    case InstDB::kEncodingX86In:
+      if (isign3 == ENC_OPS2(Reg, Imm)) {
+        if (ASMJIT_UNLIKELY(o0.id() != Gp::kIdAx))
+          goto InvalidInstruction;
+
+        immValue = o1.as<Imm>().valueAs<uint8_t>();
+        immSize = 1;
+
+        opcode = x86AltOpcodeOf(instInfo) + (o0.size() != 1);
+        opcode.add66hBySize(o0.size());
+        goto EmitX86Op;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        if (ASMJIT_UNLIKELY(o0.id() != Gp::kIdAx || o1.id() != Gp::kIdDx))
+          goto InvalidInstruction;
+
+        opcode += o0.size() != 1;
+        opcode.add66hBySize(o0.size());
+        goto EmitX86Op;
+      }
+      break;
+
+    case InstDB::kEncodingX86Ins:
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        if (ASMJIT_UNLIKELY(!x86IsImplicitMem(o0, Gp::kIdDi) || o1.id() != Gp::kIdDx))
+          goto InvalidInstruction;
+
+        uint32_t size = o0.size();
+        if (ASMJIT_UNLIKELY(size == 0))
+          goto AmbiguousOperandSize;
+
+        rmRel = &o0;
+        opcode += (size != 1);
+
+        opcode.add66hBySize(size);
+        goto EmitX86OpImplicitMem;
+      }
+      break;
+
+    case InstDB::kEncodingX86IncDec:
+      if (isign3 == ENC_OPS1(Reg)) {
+        rbReg = o0.id();
+
+        if (o0.size() == 1) {
+          FIXUP_GPB(o0, rbReg);
+          goto EmitX86R;
+        }
+
+        if (is32Bit()) {
+          // INC r16|r32 is only encodable in 32-bit mode (collides with REX).
+          opcode = x86AltOpcodeOf(instInfo) + (rbReg & 0x07);
+          opcode.add66hBySize(o0.size());
+          goto EmitX86Op;
+        }
+        else {
+          opcode.addArithBySize(o0.size());
+          goto EmitX86R;
+        }
+      }
+
+      if (isign3 == ENC_OPS1(Mem)) {
+        opcode.addArithBySize(o0.size());
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Int:
+      if (isign3 == ENC_OPS1(Imm)) {
+        immValue = o0.as<Imm>().value();
+        immSize = 1;
+        goto EmitX86Op;
+      }
+      break;
+
+    case InstDB::kEncodingX86Jcc:
+      if ((options & (Inst::kOptionTaken | Inst::kOptionNotTaken)) && hasEncodingOption(kEncodingOptionPredictedJumps)) {
+        uint8_t prefix = (options & Inst::kOptionTaken) ? uint8_t(0x3E) : uint8_t(0x2E);
+        writer.emit8(prefix);
+      }
+
+      rmRel = &o0;
+      opReg = 0;
+      goto EmitJmpCall;
+
+    case InstDB::kEncodingX86JecxzLoop:
+      rmRel = &o0;
+      // Explicit jecxz|loop [r|e]cx, dst
+      if (o0.isReg()) {
+        if (ASMJIT_UNLIKELY(!Reg::isGp(o0, Gp::kIdCx)))
+          goto InvalidInstruction;
+
+        writer.emitAddressOverride((is32Bit() && o0.size() == 2) || (is64Bit() && o0.size() == 4));
+        rmRel = &o1;
+      }
+
+      opReg = 0;
+      goto EmitJmpCall;
+
+    case InstDB::kEncodingX86Jmp:
+      if (isign3 == ENC_OPS1(Reg)) {
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      rmRel = &o0;
+      if (isign3 == ENC_OPS1(Mem))
+        goto EmitX86M;
+
+      // Jump encoded with 32-bit displacement use 0xE9 opcode. Jump encoded
+      // with 8-bit displacement's opcode is stored as an alternative opcode.
+      opcode = 0xE9;
+      opReg = 0;
+      goto EmitJmpCall;
+
+    case InstDB::kEncodingX86JmpRel:
+      rmRel = &o0;
+      goto EmitJmpCall;
+
+    case InstDB::kEncodingX86Lea:
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opcode.addPrefixBySize(o0.size());
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Mov:
+      // Reg <- Reg
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        // Asmjit uses segment registers indexed from 1 to 6, leaving zero as
+        // "no segment register used". We have to fix this (decrement the index
+        // of the register) when emitting MOV instructions which move to/from
+        // a segment register. The segment register is always `opReg`, because
+        // the MOV instruction uses either RM or MR encoding.
+
+        // GP <- ??
+        if (Reg::isGp(o0)) {
+          // GP <- GP
+          if (Reg::isGp(o1)) {
+            uint32_t size0 = o0.size();
+            uint32_t size1 = o1.size();
+
+            if (size0 != size1) {
+              // We allow 'mov r64, r32' as it's basically zero-extend.
+              if (size0 == 8 && size1 == 4)
+                size0 = 4; // Zero extend, don't promote to 64-bit.
+              else
+                goto InvalidInstruction;
+            }
+
+            if (size0 == 1) {
+              FIXUP_GPB(o0, opReg);
+              FIXUP_GPB(o1, rbReg);
+              opcode = 0x8A;
+
+              if (!(options & Inst::kOptionModMR))
+                goto EmitX86R;
+
+              opcode -= 2;
+              std::swap(opReg, rbReg);
+              goto EmitX86R;
+            }
+            else {
+              opcode = 0x8B;
+              opcode.addPrefixBySize(size0);
+
+              if (!(options & Inst::kOptionModMR))
+                goto EmitX86R;
+
+              opcode -= 2;
+              std::swap(opReg, rbReg);
+              goto EmitX86R;
+            }
+          }
+
+          opReg = rbReg;
+          rbReg = o0.id();
+
+          // GP <- SReg
+          if (Reg::isSReg(o1)) {
+            opcode = 0x8C;
+            opcode.addPrefixBySize(o0.size());
+            opReg--;
+            goto EmitX86R;
+          }
+
+          // GP <- CReg
+          if (Reg::isCReg(o1)) {
+            opcode = Opcode::k000F00 | 0x20;
+
+            // Use `LOCK MOV` in 32-bit mode if CR8+ register is accessed (AMD extension).
+            if ((opReg & 0x8) && is32Bit()) {
+              writer.emit8(0xF0);
+              opReg &= 0x7;
+            }
+            goto EmitX86R;
+          }
+
+          // GP <- DReg
+          if (Reg::isDReg(o1)) {
+            opcode = Opcode::k000F00 | 0x21;
+            goto EmitX86R;
+          }
+        }
+        else {
+          // ?? <- GP
+          if (!Reg::isGp(o1))
+            goto InvalidInstruction;
+
+          // SReg <- GP
+          if (Reg::isSReg(o0)) {
+            opcode = 0x8E;
+            opcode.addPrefixBySize(o1.size());
+            opReg--;
+            goto EmitX86R;
+          }
+
+          // CReg <- GP
+          if (Reg::isCReg(o0)) {
+            opcode = Opcode::k000F00 | 0x22;
+
+            // Use `LOCK MOV` in 32-bit mode if CR8+ register is accessed (AMD extension).
+            if ((opReg & 0x8) && is32Bit()) {
+              writer.emit8(0xF0);
+              opReg &= 0x7;
+            }
+            goto EmitX86R;
+          }
+
+          // DReg <- GP
+          if (Reg::isDReg(o0)) {
+            opcode = Opcode::k000F00 | 0x23;
+            goto EmitX86R;
+          }
+        }
+
+        goto InvalidInstruction;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+
+        // SReg <- Mem
+        if (Reg::isSReg(o0)) {
+          opcode = 0x8E;
+          opcode.addPrefixBySize(o1.size());
+          opReg--;
+          goto EmitX86M;
+        }
+        // Reg <- Mem
+        else {
+          opcode = 0;
+          opcode.addArithBySize(o0.size());
+
+          if (o0.size() == 1)
+            FIXUP_GPB(o0, opReg);
+
+          // Handle a special form of `mov al|ax|eax|rax, [ptr64]` that doesn't use MOD.
+          if (opReg == Gp::kIdAx && !rmRel->as<Mem>().hasBaseOrIndex()) {
+            immValue = rmRel->as<Mem>().offset();
+            if (x86GetMovAbsAddrType(this, writer, o0.size(), options, rmRel->as<Mem>()) == BaseMem::kAddrTypeAbs) {
+              opcode += 0xA0;
+              goto EmitX86OpMovAbs;
+            }
+          }
+
+          opcode += 0x8A;
+          goto EmitX86M;
+        }
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opReg = o1.id();
+        rmRel = &o0;
+
+        // Mem <- SReg
+        if (Reg::isSReg(o1)) {
+          opcode = 0x8C;
+          opcode.addPrefixBySize(o0.size());
+          opReg--;
+          goto EmitX86M;
+        }
+        // Mem <- Reg
+        else {
+          opcode = 0;
+          opcode.addArithBySize(o1.size());
+
+          if (o1.size() == 1)
+            FIXUP_GPB(o1, opReg);
+
+          // Handle a special form of `mov [ptr64], al|ax|eax|rax` that doesn't use MOD.
+          if (opReg == Gp::kIdAx && !rmRel->as<Mem>().hasBaseOrIndex()) {
+            immValue = rmRel->as<Mem>().offset();
+            if (x86GetMovAbsAddrType(this, writer, o1.size(), options, rmRel->as<Mem>()) == BaseMem::kAddrTypeAbs) {
+              opcode += 0xA2;
+              goto EmitX86OpMovAbs;
+            }
+          }
+
+          opcode += 0x88;
+          goto EmitX86M;
+        }
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Imm)) {
+        opReg = o0.id();
+        immSize = FastUInt8(o0.size());
+
+        if (immSize == 1) {
+          FIXUP_GPB(o0, opReg);
+
+          opcode = 0xB0;
+          immValue = o1.as<Imm>().valueAs<uint8_t>();
+          goto EmitX86OpReg;
+        }
+        else {
+          // 64-bit immediate in 64-bit mode is allowed.
+          immValue = o1.as<Imm>().value();
+
+          // Optimize the instruction size by using a 32-bit immediate if possible.
+          if (immSize == 8 && !(options & Inst::kOptionLongForm)) {
+            if (Support::isUInt32(immValue) && hasEncodingOption(kEncodingOptionOptimizeForSize)) {
+              // Zero-extend by using a 32-bit GPD destination instead of a 64-bit GPQ.
+              immSize = 4;
+            }
+            else if (Support::isInt32(immValue)) {
+              // Sign-extend, uses 'C7 /0' opcode.
+              rbReg = opReg;
+
+              opcode = Opcode::kW | 0xC7;
+              opReg = 0;
+
+              immSize = 4;
+              goto EmitX86R;
+            }
+          }
+
+          opcode = 0xB8;
+          opcode.addPrefixBySize(immSize);
+          goto EmitX86OpReg;
+        }
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Imm)) {
+        uint32_t memSize = o0.size();
+        if (ASMJIT_UNLIKELY(memSize == 0))
+          goto AmbiguousOperandSize;
+
+        opcode = 0xC6 + (memSize != 1);
+        opcode.addPrefixBySize(memSize);
+        opReg = 0;
+        rmRel = &o0;
+
+        immValue = o1.as<Imm>().value();
+        immSize = FastUInt8(Support::min<uint32_t>(memSize, 4));
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86MovsxMovzx:
+      opcode.add(o1.size() != 1);
+      opcode.addPrefixBySize(o0.size());
+
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        if (o1.size() != 1)
+          goto EmitX86R;
+
+        FIXUP_GPB(o1, rbReg);
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86MovntiMovdiri:
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opcode.addWIf(Reg::isGpq(o1));
+
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86EnqcmdMovdir64b:
+      if (isign3 == ENC_OPS2(Mem, Mem)) {
+        const Mem& m0 = o0.as<Mem>();
+        // This is the only required validation, the rest is handled afterwards.
+        if (ASMJIT_UNLIKELY(m0.baseType() != o1.as<Mem>().baseType() ||
+                            m0.hasIndex() ||
+                            m0.hasOffset() ||
+                            (m0.hasSegment() && m0.segmentId() != SReg::kIdEs)))
+          goto InvalidInstruction;
+
+        // The first memory operand is passed via register, the second memory operand is RM.
+        opReg = o0.as<Mem>().baseId();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Out:
+      if (isign3 == ENC_OPS2(Imm, Reg)) {
+        if (ASMJIT_UNLIKELY(o1.id() != Gp::kIdAx))
+          goto InvalidInstruction;
+
+        opcode = x86AltOpcodeOf(instInfo) + (o1.size() != 1);
+        opcode.add66hBySize(o1.size());
+
+        immValue = o0.as<Imm>().valueAs<uint8_t>();
+        immSize = 1;
+        goto EmitX86Op;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        if (ASMJIT_UNLIKELY(o0.id() != Gp::kIdDx || o1.id() != Gp::kIdAx))
+          goto InvalidInstruction;
+
+        opcode.add(o1.size() != 1);
+        opcode.add66hBySize(o1.size());
+        goto EmitX86Op;
+      }
+      break;
+
+    case InstDB::kEncodingX86Outs:
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        if (ASMJIT_UNLIKELY(o0.id() != Gp::kIdDx || !x86IsImplicitMem(o1, Gp::kIdSi)))
+          goto InvalidInstruction;
+
+        uint32_t size = o1.size();
+        if (ASMJIT_UNLIKELY(size == 0))
+          goto AmbiguousOperandSize;
+
+        rmRel = &o1;
+        opcode.add(size != 1);
+        opcode.add66hBySize(size);
+        goto EmitX86OpImplicitMem;
+      }
+      break;
+
+    case InstDB::kEncodingX86Push:
+      if (isign3 == ENC_OPS1(Reg)) {
+        if (Reg::isSReg(o0)) {
+          uint32_t segment = o0.id();
+          if (ASMJIT_UNLIKELY(segment >= SReg::kIdCount))
+            goto InvalidSegment;
+
+          opcode = x86OpcodePushSReg[segment];
+          goto EmitX86Op;
+        }
+        else {
+          goto CaseX86PushPop_Gp;
+        }
+      }
+
+      if (isign3 == ENC_OPS1(Imm)) {
+        immValue = o0.as<Imm>().value();
+        immSize = 4;
+
+        if (Support::isInt8(immValue) && !(options & Inst::kOptionLongForm))
+          immSize = 1;
+
+        opcode = immSize == 1 ? 0x6A : 0x68;
+        goto EmitX86Op;
+      }
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingX86Pop:
+      if (isign3 == ENC_OPS1(Reg)) {
+        if (Reg::isSReg(o0)) {
+          uint32_t segment = o0.id();
+          if (ASMJIT_UNLIKELY(segment == SReg::kIdCs || segment >= SReg::kIdCount))
+            goto InvalidSegment;
+
+          opcode = x86OpcodePopSReg[segment];
+          goto EmitDone;
+        }
+        else {
+CaseX86PushPop_Gp:
+          // We allow 2 byte, 4 byte, and 8 byte register sizes, although PUSH
+          // and POP only allow 2 bytes or native size. On 64-bit we simply
+          // PUSH/POP 64-bit register even if 32-bit register was given.
+          if (ASMJIT_UNLIKELY(o0.size() < 2))
+            goto InvalidInstruction;
+
+          opcode = x86AltOpcodeOf(instInfo);
+          opcode.add66hBySize(o0.size());
+          opReg = o0.id();
+          goto EmitX86OpReg;
+        }
+      }
+
+      if (isign3 == ENC_OPS1(Mem)) {
+        if (ASMJIT_UNLIKELY(o0.size() == 0))
+          goto AmbiguousOperandSize;
+
+        if (ASMJIT_UNLIKELY(o0.size() != 2 && o0.size() != registerSize()))
+          goto InvalidInstruction;
+
+        opcode.add66hBySize(o0.size());
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Ret:
+      if (isign3 == 0) {
+        // 'ret' without immediate, change C2 to C3.
+        opcode.add(1);
+        goto EmitX86Op;
+      }
+
+      if (isign3 == ENC_OPS1(Imm)) {
+        immValue = o0.as<Imm>().value();
+        if (immValue == 0 && !(options & Inst::kOptionLongForm)) {
+          // 'ret' without immediate, change C2 to C3.
+          opcode.add(1);
+          goto EmitX86Op;
+        }
+        else {
+          immSize = 2;
+          goto EmitX86Op;
+        }
+      }
+      break;
+
+    case InstDB::kEncodingX86Rot:
+      if (o0.isReg()) {
+        opcode.addArithBySize(o0.size());
+        rbReg = o0.id();
+
+        if (o0.size() == 1)
+          FIXUP_GPB(o0, rbReg);
+
+        if (isign3 == ENC_OPS2(Reg, Reg)) {
+          if (ASMJIT_UNLIKELY(o1.id() != Gp::kIdCx))
+            goto InvalidInstruction;
+
+          opcode += 2;
+          goto EmitX86R;
+        }
+
+        if (isign3 == ENC_OPS2(Reg, Imm)) {
+          immValue = o1.as<Imm>().value() & 0xFF;
+          immSize = 0;
+
+          if (immValue == 1 && !(options & Inst::kOptionLongForm))
+            goto EmitX86R;
+
+          opcode -= 0x10;
+          immSize = 1;
+          goto EmitX86R;
+        }
+      }
+      else {
+        opcode.addArithBySize(o0.size());
+
+        if (isign3 == ENC_OPS2(Mem, Reg)) {
+          if (ASMJIT_UNLIKELY(o1.id() != Gp::kIdCx))
+            goto InvalidInstruction;
+
+          opcode += 2;
+          rmRel = &o0;
+          goto EmitX86M;
+        }
+
+        if (isign3 == ENC_OPS2(Mem, Imm)) {
+          if (ASMJIT_UNLIKELY(o0.size() == 0))
+            goto AmbiguousOperandSize;
+
+          rmRel = &o0;
+          immValue = o1.as<Imm>().value() & 0xFF;
+          immSize = 0;
+
+          if (immValue == 1 && !(options & Inst::kOptionLongForm))
+            goto EmitX86M;
+
+          opcode -= 0x10;
+          immSize = 1;
+          goto EmitX86M;
+        }
+      }
+      break;
+
+    case InstDB::kEncodingX86Set:
+      if (isign3 == ENC_OPS1(Reg)) {
+        rbReg = o0.id();
+        FIXUP_GPB(o0, rbReg);
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS1(Mem)) {
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86ShldShrd:
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opcode.addPrefixBySize(o0.size());
+        opReg = o1.id();
+        rbReg = o0.id();
+
+        immValue = o2.as<Imm>().value();
+        immSize = 1;
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS3(Mem, Reg, Imm)) {
+        opcode.addPrefixBySize(o1.size());
+        opReg = o1.id();
+        rmRel = &o0;
+
+        immValue = o2.as<Imm>().value();
+        immSize = 1;
+        goto EmitX86M;
+      }
+
+      // The following instructions use opcode + 1.
+      opcode.add(1);
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        if (ASMJIT_UNLIKELY(o2.id() != Gp::kIdCx))
+          goto InvalidInstruction;
+
+        opcode.addPrefixBySize(o0.size());
+        opReg = o1.id();
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS3(Mem, Reg, Reg)) {
+        if (ASMJIT_UNLIKELY(o2.id() != Gp::kIdCx))
+          goto InvalidInstruction;
+
+        opcode.addPrefixBySize(o1.size());
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86StrRm:
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        rmRel = &o1;
+        if (ASMJIT_UNLIKELY(rmRel->as<Mem>().offsetLo32() || !Reg::isGp(o0.as<Reg>(), Gp::kIdAx)))
+          goto InvalidInstruction;
+
+        uint32_t size = o0.size();
+        if (o1.hasSize() && ASMJIT_UNLIKELY(o1.size() != size))
+          goto OperandSizeMismatch;
+
+        opcode.addArithBySize(size);
+        goto EmitX86OpImplicitMem;
+      }
+      break;
+
+    case InstDB::kEncodingX86StrMr:
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        rmRel = &o0;
+        if (ASMJIT_UNLIKELY(rmRel->as<Mem>().offsetLo32() || !Reg::isGp(o1.as<Reg>(), Gp::kIdAx)))
+          goto InvalidInstruction;
+
+        uint32_t size = o1.size();
+        if (o0.hasSize() && ASMJIT_UNLIKELY(o0.size() != size))
+          goto OperandSizeMismatch;
+
+        opcode.addArithBySize(size);
+        goto EmitX86OpImplicitMem;
+      }
+      break;
+
+    case InstDB::kEncodingX86StrMm:
+      if (isign3 == ENC_OPS2(Mem, Mem)) {
+        if (ASMJIT_UNLIKELY(o0.as<Mem>().baseAndIndexTypes() !=
+                            o1.as<Mem>().baseAndIndexTypes()))
+          goto InvalidInstruction;
+
+        rmRel = &o1;
+        if (ASMJIT_UNLIKELY(o0.as<Mem>().hasOffset()))
+          goto InvalidInstruction;
+
+        uint32_t size = o1.size();
+        if (ASMJIT_UNLIKELY(size == 0))
+          goto AmbiguousOperandSize;
+
+        if (ASMJIT_UNLIKELY(o0.size() != size))
+          goto OperandSizeMismatch;
+
+        opcode.addArithBySize(size);
+        goto EmitX86OpImplicitMem;
+      }
+      break;
+
+    case InstDB::kEncodingX86Test:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        if (o0.size() != o1.size())
+          goto OperandSizeMismatch;
+
+        opcode.addArithBySize(o0.size());
+        rbReg = o0.id();
+        opReg = o1.id();
+
+        if (o0.size() != 1)
+          goto EmitX86R;
+
+        FIXUP_GPB(o0, rbReg);
+        FIXUP_GPB(o1, opReg);
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opcode.addArithBySize(o1.size());
+        opReg = o1.id();
+        rmRel = &o0;
+
+        if (o1.size() != 1)
+          goto EmitX86M;
+
+        FIXUP_GPB(o1, opReg);
+        goto EmitX86M;
+      }
+
+      // The following instructions use the secondary opcode.
+      opcode = x86AltOpcodeOf(instInfo);
+      opReg = opcode.extractModO();
+
+      if (isign3 == ENC_OPS2(Reg, Imm)) {
+        opcode.addArithBySize(o0.size());
+        rbReg = o0.id();
+
+        if (o0.size() == 1) {
+          FIXUP_GPB(o0, rbReg);
+          immValue = o1.as<Imm>().valueAs<uint8_t>();
+          immSize = 1;
+        }
+        else {
+          immValue = o1.as<Imm>().value();
+          immSize = FastUInt8(Support::min<uint32_t>(o0.size(), 4));
+        }
+
+        // Short form - AL, AX, EAX, RAX.
+        if (rbReg == 0 && !(options & Inst::kOptionLongForm)) {
+          opcode &= Opcode::kPP_66 | Opcode::kW;
+          opcode |= 0xA8 + (o0.size() != 1);
+          goto EmitX86Op;
+        }
+
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Imm)) {
+        if (ASMJIT_UNLIKELY(o0.size() == 0))
+          goto AmbiguousOperandSize;
+
+        opcode.addArithBySize(o0.size());
+        rmRel = &o0;
+
+        immValue = o1.as<Imm>().value();
+        immSize = FastUInt8(Support::min<uint32_t>(o0.size(), 4));
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Xchg:
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opcode.addArithBySize(o0.size());
+        opReg = o0.id();
+        rmRel = &o1;
+
+        if (o0.size() != 1)
+          goto EmitX86M;
+
+        FIXUP_GPB(o0, opReg);
+        goto EmitX86M;
+      }
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingX86Xadd:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opcode.addArithBySize(o0.size());
+        rbReg = o0.id();
+        opReg = o1.id();
+
+        if (o0.size() != o1.size())
+          goto OperandSizeMismatch;
+
+        if (o0.size() == 1) {
+          FIXUP_GPB(o0, rbReg);
+          FIXUP_GPB(o1, opReg);
+          goto EmitX86R;
+        }
+
+        // Special opcode for 'xchg ?ax, reg'.
+        if (instId == Inst::kIdXchg && (opReg == 0 || rbReg == 0)) {
+          opcode &= Opcode::kPP_66 | Opcode::kW;
+          opcode |= 0x90;
+          // One of `xchg a, b` or `xchg b, a` is AX/EAX/RAX.
+          opReg += rbReg;
+          goto EmitX86OpReg;
+        }
+        else {
+          goto EmitX86R;
+        }
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opcode.addArithBySize(o1.size());
+        opReg = o1.id();
+        rmRel = &o0;
+
+        if (o1.size() == 1) {
+          FIXUP_GPB(o1, opReg);
+        }
+
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingX86Fence:
+      rbReg = 0;
+      goto EmitX86R;
+
+    case InstDB::kEncodingX86Bndmov:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        // ModRM encoding:
+        if (!(options & Inst::kOptionModMR))
+          goto EmitX86R;
+
+        // ModMR encoding:
+        opcode = x86AltOpcodeOf(instInfo);
+        std::swap(opReg, rbReg);
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opcode = x86AltOpcodeOf(instInfo);
+
+        rmRel = &o0;
+        opReg = o1.id();
+        goto EmitX86M;
+      }
+      break;
+
+    // ------------------------------------------------------------------------
+    // [FPU]
+    // ------------------------------------------------------------------------
+
+    case InstDB::kEncodingFpuOp:
+      goto EmitFpuOp;
+
+    case InstDB::kEncodingFpuArith:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        // We switch to the alternative opcode if the first operand is zero.
+        if (opReg == 0) {
+CaseFpuArith_Reg:
+          opcode = ((0xD8   << Opcode::kFPU_2B_Shift)       ) +
+                   ((opcode >> Opcode::kFPU_2B_Shift) & 0xFF) + rbReg;
+          goto EmitFpuOp;
+        }
+        else if (rbReg == 0) {
+          rbReg = opReg;
+          opcode = ((0xDC   << Opcode::kFPU_2B_Shift)       ) +
+                   ((opcode                         ) & 0xFF) + rbReg;
+          goto EmitFpuOp;
+        }
+        else {
+          goto InvalidInstruction;
+        }
+      }
+
+      if (isign3 == ENC_OPS1(Mem)) {
+CaseFpuArith_Mem:
+        // 0xD8/0xDC, depends on the size of the memory operand; opReg is valid.
+        opcode = (o0.size() == 4) ? 0xD8 : 0xDC;
+        // Clear compressed displacement before going to EmitX86M.
+        opcode &= ~uint32_t(Opcode::kCDSHL_Mask);
+
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingFpuCom:
+      if (isign3 == 0) {
+        rbReg = 1;
+        goto CaseFpuArith_Reg;
+      }
+
+      if (isign3 == ENC_OPS1(Reg)) {
+        rbReg = o0.id();
+        goto CaseFpuArith_Reg;
+      }
+
+      if (isign3 == ENC_OPS1(Mem)) {
+        goto CaseFpuArith_Mem;
+      }
+      break;
+
+    case InstDB::kEncodingFpuFldFst:
+      if (isign3 == ENC_OPS1(Mem)) {
+        rmRel = &o0;
+
+        if (o0.size() == 4 && commonInfo->hasFlag(InstDB::kFlagFpuM32)) {
+          goto EmitX86M;
+        }
+
+        if (o0.size() == 8 && commonInfo->hasFlag(InstDB::kFlagFpuM64)) {
+          opcode += 4;
+          goto EmitX86M;
+        }
+
+        if (o0.size() == 10 && commonInfo->hasFlag(InstDB::kFlagFpuM80)) {
+          opcode = x86AltOpcodeOf(instInfo);
+          opReg  = opcode.extractModO();
+          goto EmitX86M;
+        }
+      }
+
+      if (isign3 == ENC_OPS1(Reg)) {
+        if (instId == Inst::kIdFld ) { opcode = (0xD9 << Opcode::kFPU_2B_Shift) + 0xC0 + o0.id(); goto EmitFpuOp; }
+        if (instId == Inst::kIdFst ) { opcode = (0xDD << Opcode::kFPU_2B_Shift) + 0xD0 + o0.id(); goto EmitFpuOp; }
+        if (instId == Inst::kIdFstp) { opcode = (0xDD << Opcode::kFPU_2B_Shift) + 0xD8 + o0.id(); goto EmitFpuOp; }
+      }
+      break;
+
+    case InstDB::kEncodingFpuM:
+      if (isign3 == ENC_OPS1(Mem)) {
+        // Clear compressed displacement before going to EmitX86M.
+        opcode &= ~uint32_t(Opcode::kCDSHL_Mask);
+
+        rmRel = &o0;
+        if (o0.size() == 2 && commonInfo->hasFlag(InstDB::kFlagFpuM16)) {
+          opcode += 4;
+          goto EmitX86M;
+        }
+
+        if (o0.size() == 4 && commonInfo->hasFlag(InstDB::kFlagFpuM32)) {
+          goto EmitX86M;
+        }
+
+        if (o0.size() == 8 && commonInfo->hasFlag(InstDB::kFlagFpuM64)) {
+          opcode = x86AltOpcodeOf(instInfo) & ~uint32_t(Opcode::kCDSHL_Mask);
+          opReg  = opcode.extractModO();
+          goto EmitX86M;
+        }
+      }
+      break;
+
+    case InstDB::kEncodingFpuRDef:
+      if (isign3 == 0) {
+        opcode += 1;
+        goto EmitFpuOp;
+      }
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingFpuR:
+      if (isign3 == ENC_OPS1(Reg)) {
+        opcode += o0.id();
+        goto EmitFpuOp;
+      }
+      break;
+
+    case InstDB::kEncodingFpuStsw:
+      if (isign3 == ENC_OPS1(Reg)) {
+        if (ASMJIT_UNLIKELY(o0.id() != Gp::kIdAx))
+          goto InvalidInstruction;
+
+        opcode = x86AltOpcodeOf(instInfo);
+        goto EmitFpuOp;
+      }
+
+      if (isign3 == ENC_OPS1(Mem)) {
+        // Clear compressed displacement before going to EmitX86M.
+        opcode &= ~uint32_t(Opcode::kCDSHL_Mask);
+
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    // ------------------------------------------------------------------------
+    // [Ext]
+    // ------------------------------------------------------------------------
+
+    case InstDB::kEncodingExtPextrw:
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opcode.add66hIf(Reg::isXmm(o1));
+
+        immValue = o2.as<Imm>().value();
+        immSize = 1;
+
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS3(Mem, Reg, Imm)) {
+        // Secondary opcode of 'pextrw' instruction (SSE4.1).
+        opcode = x86AltOpcodeOf(instInfo);
+        opcode.add66hIf(Reg::isXmm(o1));
+
+        immValue = o2.as<Imm>().value();
+        immSize = 1;
+
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingExtExtract:
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opcode.add66hIf(Reg::isXmm(o1));
+
+        immValue = o2.as<Imm>().value();
+        immSize = 1;
+
+        opReg = o1.id();
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS3(Mem, Reg, Imm)) {
+        opcode.add66hIf(Reg::isXmm(o1));
+
+        immValue = o2.as<Imm>().value();
+        immSize = 1;
+
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingExtMov:
+      // GP|MM|XMM <- GP|MM|XMM
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        if (!(options & Inst::kOptionModMR) || !instInfo->_altOpcodeIndex)
+          goto EmitX86R;
+
+        opcode = x86AltOpcodeOf(instInfo);
+        std::swap(opReg, rbReg);
+        goto EmitX86R;
+      }
+
+      // GP|MM|XMM <- Mem
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+
+      // The following instruction uses opcode[1].
+      opcode = x86AltOpcodeOf(instInfo);
+
+      // Mem <- GP|MM|XMM
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingExtMovbe:
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        if (o0.size() == 1)
+          goto InvalidInstruction;
+
+        opcode.addPrefixBySize(o0.size());
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+
+      // The following instruction uses the secondary opcode.
+      opcode = x86AltOpcodeOf(instInfo);
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        if (o1.size() == 1)
+          goto InvalidInstruction;
+
+        opcode.addPrefixBySize(o1.size());
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingExtMovd:
+CaseExtMovd:
+      opReg = o0.id();
+      opcode.add66hIf(Reg::isXmm(o0));
+
+      // MM/XMM <- Gp
+      if (isign3 == ENC_OPS2(Reg, Reg) && Reg::isGp(o1)) {
+        rbReg = o1.id();
+        goto EmitX86R;
+      }
+
+      // MM/XMM <- Mem
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+
+      // The following instructions use the secondary opcode.
+      opcode &= Opcode::kW;
+      opcode |= x86AltOpcodeOf(instInfo);
+      opReg = o1.id();
+      opcode.add66hIf(Reg::isXmm(o1));
+
+      // GP <- MM/XMM
+      if (isign3 == ENC_OPS2(Reg, Reg) && Reg::isGp(o0)) {
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+
+      // Mem <- MM/XMM
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        rmRel = &o0;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingExtMovq:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        // MM <- MM
+        if (Reg::isMm(o0) && Reg::isMm(o1)) {
+          opcode = Opcode::k000F00 | 0x6F;
+
+          if (!(options & Inst::kOptionModMR))
+            goto EmitX86R;
+
+          opcode += 0x10;
+          std::swap(opReg, rbReg);
+          goto EmitX86R;
+        }
+
+        // XMM <- XMM
+        if (Reg::isXmm(o0) && Reg::isXmm(o1)) {
+          opcode = Opcode::kF30F00 | 0x7E;
+
+          if (!(options & Inst::kOptionModMR))
+            goto EmitX86R;
+
+          opcode = Opcode::k660F00 | 0xD6;
+          std::swap(opReg, rbReg);
+          goto EmitX86R;
+        }
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+
+        // MM <- Mem
+        if (Reg::isMm(o0)) {
+          opcode = Opcode::k000F00 | 0x6F;
+          goto EmitX86M;
+        }
+
+        // XMM <- Mem
+        if (Reg::isXmm(o0)) {
+          opcode = Opcode::kF30F00 | 0x7E;
+          goto EmitX86M;
+        }
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opReg = o1.id();
+        rmRel = &o0;
+
+        // Mem <- MM
+        if (Reg::isMm(o1)) {
+          opcode = Opcode::k000F00 | 0x7F;
+          goto EmitX86M;
+        }
+
+        // Mem <- XMM
+        if (Reg::isXmm(o1)) {
+          opcode = Opcode::k660F00 | 0xD6;
+          goto EmitX86M;
+        }
+      }
+
+      // MOVQ in other case is simply a MOVD instruction promoted to 64-bit.
+      opcode |= Opcode::kW;
+      goto CaseExtMovd;
+
+    case InstDB::kEncodingExtRm_XMM0:
+      if (ASMJIT_UNLIKELY(!o2.isNone() && !Reg::isXmm(o2, 0)))
+        goto InvalidInstruction;
+
+      isign3 &= 0x3F;
+      goto CaseExtRm;
+
+    case InstDB::kEncodingExtRm_ZDI:
+      if (ASMJIT_UNLIKELY(!o2.isNone() && !x86IsImplicitMem(o2, Gp::kIdDi)))
+        goto InvalidInstruction;
+
+      isign3 &= 0x3F;
+      goto CaseExtRm;
+
+    case InstDB::kEncodingExtRm_Wx:
+      opcode.addWIf(Reg::isGpq(o0) || o1.size() == 8);
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingExtRm:
+CaseExtRm:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingExtRm_P:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opcode.add66hIf(Reg::isXmm(o0) | Reg::isXmm(o1));
+
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opcode.add66hIf(Reg::isXmm(o0));
+
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingExtRmRi:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+
+      // The following instruction uses the secondary opcode.
+      opcode = x86AltOpcodeOf(instInfo);
+      opReg  = opcode.extractModO();
+
+      if (isign3 == ENC_OPS2(Reg, Imm)) {
+        immValue = o1.as<Imm>().value();
+        immSize = 1;
+
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+      break;
+
+    case InstDB::kEncodingExtRmRi_P:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opcode.add66hIf(Reg::isXmm(o0) | Reg::isXmm(o1));
+
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opcode.add66hIf(Reg::isXmm(o0));
+
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+
+      // The following instruction uses the secondary opcode.
+      opcode = x86AltOpcodeOf(instInfo);
+      opReg  = opcode.extractModO();
+
+      if (isign3 == ENC_OPS2(Reg, Imm)) {
+        opcode.add66hIf(Reg::isXmm(o0));
+
+        immValue = o1.as<Imm>().value();
+        immSize = 1;
+
+        rbReg = o0.id();
+        goto EmitX86R;
+      }
+      break;
+
+    case InstDB::kEncodingExtRmi:
+      immValue = o2.as<Imm>().value();
+      immSize = 1;
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Imm)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+      break;
+
+    case InstDB::kEncodingExtRmi_P:
+      immValue = o2.as<Imm>().value();
+      immSize = 1;
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opcode.add66hIf(Reg::isXmm(o0) | Reg::isXmm(o1));
+
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Imm)) {
+        opcode.add66hIf(Reg::isXmm(o0));
+
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+      break;
+
+    // ------------------------------------------------------------------------
+    // [Extrq / Insertq (SSE4A)]
+    // ------------------------------------------------------------------------
+
+    case InstDB::kEncodingExtExtrq:
+      opReg = o0.id();
+      rbReg = o1.id();
+
+      if (isign3 == ENC_OPS2(Reg, Reg))
+        goto EmitX86R;
+
+      // The following instruction uses the secondary opcode.
+      opcode = x86AltOpcodeOf(instInfo);
+
+      if (isign3 == ENC_OPS3(Reg, Imm, Imm)) {
+        immValue = (uint32_t(o1.as<Imm>().valueAs<uint8_t>())     ) +
+                   (uint32_t(o2.as<Imm>().valueAs<uint8_t>()) << 8) ;
+        immSize = 2;
+
+        rbReg = opcode.extractModO();
+        goto EmitX86R;
+      }
+      break;
+
+    case InstDB::kEncodingExtInsertq: {
+      const Operand_& o3 = opExt[EmitterUtils::kOp3];
+      const uint32_t isign4 = isign3 + (o3.opType() << 9);
+
+      opReg = o0.id();
+      rbReg = o1.id();
+
+      if (isign4 == ENC_OPS2(Reg, Reg))
+        goto EmitX86R;
+
+      // The following instruction uses the secondary opcode.
+      opcode = x86AltOpcodeOf(instInfo);
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Imm, Imm)) {
+        immValue = (uint32_t(o2.as<Imm>().valueAs<uint8_t>())     ) +
+                   (uint32_t(o3.as<Imm>().valueAs<uint8_t>()) << 8) ;
+        immSize = 2;
+        goto EmitX86R;
+      }
+      break;
+    }
+
+    // ------------------------------------------------------------------------
+    // [3dNow]
+    // ------------------------------------------------------------------------
+
+    case InstDB::kEncodingExt3dNow:
+      // Every 3dNow instruction starts with 0x0F0F and the actual opcode is
+      // stored as 8-bit immediate.
+      immValue = opcode.v & 0xFFu;
+      immSize = 1;
+
+      opcode = Opcode::k000F00 | 0x0F;
+      opReg = o0.id();
+
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        rbReg = o1.id();
+        goto EmitX86R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        rmRel = &o1;
+        goto EmitX86M;
+      }
+      break;
+
+    // ------------------------------------------------------------------------
+    // [VEX/EVEX]
+    // ------------------------------------------------------------------------
+
+    case InstDB::kEncodingVexOp:
+      goto EmitVexEvexOp;
+
+    case InstDB::kEncodingVexOpMod:
+      rbReg = 0;
+      goto EmitVexEvexR;
+
+    case InstDB::kEncodingVexKmov:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+
+        // Form 'k, reg'.
+        if (Reg::isGp(o1)) {
+          opcode = x86AltOpcodeOf(instInfo);
+          goto EmitVexEvexR;
+        }
+
+        // Form 'reg, k'.
+        if (Reg::isGp(o0)) {
+          opcode = x86AltOpcodeOf(instInfo) + 1;
+          goto EmitVexEvexR;
+        }
+
+        // Form 'k, k'.
+        if (!(options & Inst::kOptionModMR))
+          goto EmitVexEvexR;
+
+        opcode.add(1);
+        std::swap(opReg, rbReg);
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+
+        goto EmitVexEvexM;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opcode.add(1);
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexR_Wx:
+      if (isign3 == ENC_OPS1(Reg)) {
+        rbReg = o0.id();
+        opcode.addWIf(o0.as<Reg>().isGpq());
+        goto EmitVexEvexR;
+      }
+      break;
+
+    case InstDB::kEncodingVexM:
+      if (isign3 == ENC_OPS1(Mem)) {
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexM_VM:
+      if (isign3 == ENC_OPS1(Mem)) {
+        opcode |= x86OpcodeLByVMem(o0);
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexMr_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o1.id();
+        rbReg = o0.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexMr_VM:
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opcode |= Support::max(x86OpcodeLByVMem(o0), x86OpcodeLBySize(o1.size()));
+
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexMri_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexMri:
+      immValue = o2.as<Imm>().value();
+      immSize = 1;
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opReg = o1.id();
+        rbReg = o0.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Mem, Reg, Imm)) {
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRm_ZDI:
+      if (ASMJIT_UNLIKELY(!o2.isNone() && !x86IsImplicitMem(o2, Gp::kIdDi)))
+        goto InvalidInstruction;
+
+      isign3 &= 0x3F;
+      goto CaseVexRm;
+
+    case InstDB::kEncodingVexRm_Wx:
+      opcode.addWIf(Reg::isGpq(o0) | Reg::isGpq(o1));
+      goto CaseVexRm;
+
+    case InstDB::kEncodingVexRm_Lx_Bcst:
+      if (isign3 == ENC_OPS2(Reg, Reg) && Reg::isGp(o1.as<Reg>())) {
+        opcode = x86AltOpcodeOf(instInfo) | x86OpcodeLBySize(o0.size() | o1.size());
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRm_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRm:
+CaseVexRm:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRm_VM:
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opcode |= Support::max(x86OpcodeLByVMem(o1), x86OpcodeLBySize(o0.size()));
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRm_T1_4X: {
+      const Operand_& o3 = opExt[EmitterUtils::kOp3];
+      const Operand_& o4 = opExt[EmitterUtils::kOp4];
+      const Operand_& o5 = opExt[EmitterUtils::kOp5];
+
+      if (Reg::isZmm(o0) && Reg::isZmm(o1) && Reg::isZmm(o2) && Reg::isZmm(o3) && Reg::isZmm(o4) && o5.isMem()) {
+        // Registers [o1, o2, o3, o4] must start aligned and must be consecutive.
+        uint32_t i1 = o1.id();
+        uint32_t i2 = o2.id();
+        uint32_t i3 = o3.id();
+        uint32_t i4 = o4.id();
+
+        if (ASMJIT_UNLIKELY((i1 & 0x3) != 0 || i2 != i1 + 1 || i3 != i1 + 2 || i4 != i1 + 3))
+          goto NotConsecutiveRegs;
+
+        opReg = o0.id();
+        rmRel = &o5;
+        goto EmitVexEvexM;
+      }
+      break;
+    }
+
+    case InstDB::kEncodingVexRmi_Wx:
+      opcode.addWIf(Reg::isGpq(o0) | Reg::isGpq(o1));
+      goto CaseVexRmi;
+
+    case InstDB::kEncodingVexRmi_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRmi:
+CaseVexRmi:
+      immValue = o2.as<Imm>().value();
+      immSize = 1;
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Imm)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRvm:
+CaseVexRvm:
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+CaseVexRvm_R:
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Mem)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRvm_ZDX_Wx: {
+      const Operand_& o3 = opExt[EmitterUtils::kOp3];
+      if (ASMJIT_UNLIKELY(!o3.isNone() && !Reg::isGp(o3, Gp::kIdDx)))
+        goto InvalidInstruction;
+      ASMJIT_FALLTHROUGH;
+    }
+
+    case InstDB::kEncodingVexRvm_Wx: {
+      opcode.addWIf(Reg::isGpq(o0) | (o2.size() == 8));
+      goto CaseVexRvm;
+    }
+
+    case InstDB::kEncodingVexRvm_Lx: {
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      goto CaseVexRvm;
+    }
+
+    case InstDB::kEncodingVexRvm_Lx_2xK: {
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        // Two registers are encoded as a single register.
+        //   - First K register must be even.
+        //   - Second K register must be first+1.
+        if ((o0.id() & 1) != 0 || o0.id() + 1 != o1.id())
+          goto InvalidPhysId;
+
+        const Operand_& o3 = opExt[EmitterUtils::kOp3];
+
+        opcode |= x86OpcodeLBySize(o2.size());
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+
+        if (o3.isReg()) {
+          rbReg = o3.id();
+          goto EmitVexEvexR;
+        }
+
+        if (o3.isMem()) {
+          rmRel = &o3;
+          goto EmitVexEvexM;
+        }
+      }
+      break;
+    }
+
+    case InstDB::kEncodingVexRvmr_Lx: {
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+    }
+
+    case InstDB::kEncodingVexRvmr: {
+      const Operand_& o3 = opExt[EmitterUtils::kOp3];
+      const uint32_t isign4 = isign3 + (o3.opType() << 9);
+
+      immValue = o3.id() << 4;
+      immSize = 1;
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Mem, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+        goto EmitVexEvexM;
+      }
+      break;
+    }
+
+    case InstDB::kEncodingVexRvmi_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRvmi: {
+      const Operand_& o3 = opExt[EmitterUtils::kOp3];
+      const uint32_t isign4 = isign3 + (o3.opType() << 9);
+
+      immValue = o3.as<Imm>().value();
+      immSize = 1;
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Mem, Imm)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+        goto EmitVexEvexM;
+      }
+      break;
+    }
+
+    case InstDB::kEncodingVexRmv_Wx:
+      opcode.addWIf(Reg::isGpq(o0) | Reg::isGpq(o2));
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRmv:
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRmvRm_VM:
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opcode  = x86AltOpcodeOf(instInfo);
+        opcode |= Support::max(x86OpcodeLByVMem(o1), x86OpcodeLBySize(o0.size()));
+
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRmv_VM:
+      if (isign3 == ENC_OPS3(Reg, Mem, Reg)) {
+        opcode |= Support::max(x86OpcodeLByVMem(o1), x86OpcodeLBySize(o0.size() | o2.size()));
+
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+
+    case InstDB::kEncodingVexRmvi: {
+      const Operand_& o3 = opExt[EmitterUtils::kOp3];
+      const uint32_t isign4 = isign3 + (o3.opType() << 9);
+
+      immValue = o3.as<Imm>().value();
+      immSize = 1;
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Reg, Imm)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign4 == ENC_OPS4(Reg, Mem, Reg, Imm)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+    }
+
+    case InstDB::kEncodingVexMovdMovq:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        if (Reg::isGp(o0)) {
+          opcode = x86AltOpcodeOf(instInfo);
+          opcode.addWBySize(o0.size());
+          opReg = o1.id();
+          rbReg = o0.id();
+          goto EmitVexEvexR;
+        }
+
+        if (Reg::isGp(o1)) {
+          opcode.addWBySize(o1.size());
+          opReg = o0.id();
+          rbReg = o1.id();
+          goto EmitVexEvexR;
+        }
+
+        // If this is a 'W' version (movq) then allow also vmovq 'xmm|xmm' form.
+        if (opcode & Opcode::kEvex_W_1) {
+          opcode &= ~(Opcode::kPP_VEXMask | Opcode::kMM_Mask | 0xFF);
+          opcode |=  (Opcode::kF30F00 | 0x7E);
+
+          opReg = o0.id();
+          rbReg = o1.id();
+          goto EmitVexEvexR;
+        }
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        if (opcode & Opcode::kEvex_W_1) {
+          opcode &= ~(Opcode::kPP_VEXMask | Opcode::kMM_Mask | 0xFF);
+          opcode |=  (Opcode::kF30F00 | 0x7E);
+        }
+
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+
+      // The following instruction uses the secondary opcode.
+      opcode = x86AltOpcodeOf(instInfo);
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        if (opcode & Opcode::kEvex_W_1) {
+          opcode &= ~(Opcode::kPP_VEXMask | Opcode::kMM_Mask | 0xFF);
+          opcode |=  (Opcode::k660F00 | 0xD6);
+        }
+
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRmMr_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRmMr:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+
+      // The following instruction uses the secondary opcode.
+      opcode &= Opcode::kLL_Mask;
+      opcode |= x86AltOpcodeOf(instInfo);
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRvmRmv:
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+        rbReg = o1.id();
+
+        if (!(options & Inst::kOptionModMR))
+          goto EmitVexEvexR;
+
+        opcode.addW();
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Mem)) {
+        opcode.addW();
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRvmRmi_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRvmRmi:
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Mem)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+        goto EmitVexEvexM;
+      }
+
+      // The following instructions use the secondary opcode.
+      opcode &= Opcode::kLL_Mask;
+      opcode |= x86AltOpcodeOf(instInfo);
+
+      immValue = o2.as<Imm>().value();
+      immSize = 1;
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Imm)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRvmRmvRmi:
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+        rbReg = o1.id();
+
+        if (!(options & Inst::kOptionModMR))
+          goto EmitVexEvexR;
+
+        opcode.addW();
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Mem)) {
+        opcode.addW();
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+        goto EmitVexEvexM;
+      }
+
+      // The following instructions use the secondary opcode.
+      opcode = x86AltOpcodeOf(instInfo);
+
+      immValue = o2.as<Imm>().value();
+      immSize = 1;
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opReg = o0.id();
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Imm)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRvmMr:
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Mem)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+        goto EmitVexEvexM;
+      }
+
+      // The following instructions use the secondary opcode.
+      opcode = x86AltOpcodeOf(instInfo);
+
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = o1.id();
+        rbReg = o0.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRvmMvr_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRvmMvr:
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Mem)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+        goto EmitVexEvexM;
+      }
+
+      // The following instruction uses the secondary opcode.
+      opcode &= Opcode::kLL_Mask;
+      opcode |= x86AltOpcodeOf(instInfo);
+
+      if (isign3 == ENC_OPS3(Mem, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o2.id(), o1.id());
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexRvmVmi_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRvmVmi:
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Mem)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+        goto EmitVexEvexM;
+      }
+
+      // The following instruction uses the secondary opcode.
+      opcode &= Opcode::kLL_Mask;
+      opcode |= x86AltOpcodeOf(instInfo);
+      opReg = opcode.extractModO();
+
+      immValue = o2.as<Imm>().value();
+      immSize = 1;
+
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opReg = x86PackRegAndVvvvv(opReg, o0.id());
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Imm)) {
+        opReg = x86PackRegAndVvvvv(opReg, o0.id());
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexVm_Wx:
+      opcode.addWIf(Reg::isGpq(o0) | Reg::isGpq(o1));
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexVm:
+      if (isign3 == ENC_OPS2(Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(opReg, o0.id());
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = x86PackRegAndVvvvv(opReg, o0.id());
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexEvexVmi_Lx:
+      if (isign3 == ENC_OPS3(Reg, Mem, Imm))
+        opcode |= Opcode::kMM_ForceEvex;
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexVmi_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexVmi:
+      immValue = o2.as<Imm>().value();
+      immSize = 1;
+
+CaseVexVmi_AfterImm:
+      if (isign3 == ENC_OPS3(Reg, Reg, Imm)) {
+        opReg = x86PackRegAndVvvvv(opReg, o0.id());
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+
+      if (isign3 == ENC_OPS3(Reg, Mem, Imm)) {
+        opReg = x86PackRegAndVvvvv(opReg, o0.id());
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingVexVmi4_Wx:
+      opcode.addWIf(Reg::isGpq(o0) || o1.size() == 8);
+      immValue = o2.as<Imm>().value();
+      immSize = 4;
+      goto CaseVexVmi_AfterImm;
+
+    case InstDB::kEncodingVexRvrmRvmr_Lx:
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingVexRvrmRvmr: {
+      const Operand_& o3 = opExt[EmitterUtils::kOp3];
+      const uint32_t isign4 = isign3 + (o3.opType() << 9);
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+
+        immValue = o3.id() << 4;
+        immSize = 1;
+        goto EmitVexEvexR;
+      }
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Reg, Mem)) {
+        opcode.addW();
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o3;
+
+        immValue = o2.id() << 4;
+        immSize = 1;
+        goto EmitVexEvexM;
+      }
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Mem, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+
+        immValue = o3.id() << 4;
+        immSize = 1;
+        goto EmitVexEvexM;
+      }
+      break;
+    }
+
+    case InstDB::kEncodingVexRvrmiRvmri_Lx: {
+      const Operand_& o3 = opExt[EmitterUtils::kOp3];
+      const Operand_& o4 = opExt[EmitterUtils::kOp4];
+
+      if (ASMJIT_UNLIKELY(!o4.isImm()))
+        goto InvalidInstruction;
+
+      const uint32_t isign4 = isign3 + (o3.opType() << 9);
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size() | o2.size() | o3.size());
+
+      immValue = o4.as<Imm>().valueAs<uint8_t>() & 0x0F;
+      immSize = 1;
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+
+        immValue |= o3.id() << 4;
+        goto EmitVexEvexR;
+      }
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Reg, Mem)) {
+        opcode.addW();
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o3;
+
+        immValue |= o2.id() << 4;
+        goto EmitVexEvexM;
+      }
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Mem, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+
+        immValue |= o3.id() << 4;
+        goto EmitVexEvexM;
+      }
+      break;
+    }
+
+    case InstDB::kEncodingVexMovssMovsd:
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        goto CaseVexRvm_R;
+      }
+
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opcode = x86AltOpcodeOf(instInfo);
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    // ------------------------------------------------------------------------
+    // [FMA4]
+    // ------------------------------------------------------------------------
+
+    case InstDB::kEncodingFma4_Lx:
+      // It's fine to just check the first operand, second is just for sanity.
+      opcode |= x86OpcodeLBySize(o0.size() | o1.size());
+      ASMJIT_FALLTHROUGH;
+
+    case InstDB::kEncodingFma4: {
+      const Operand_& o3 = opExt[EmitterUtils::kOp3];
+      const uint32_t isign4 = isign3 + (o3.opType() << 9);
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rbReg = o2.id();
+
+        immValue = o3.id() << 4;
+        immSize = 1;
+        goto EmitVexEvexR;
+      }
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Reg, Mem)) {
+        opcode.addW();
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o3;
+
+        immValue = o2.id() << 4;
+        immSize = 1;
+        goto EmitVexEvexM;
+      }
+
+      if (isign4 == ENC_OPS4(Reg, Reg, Mem, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o1.id());
+        rmRel = &o2;
+
+        immValue = o3.id() << 4;
+        immSize = 1;
+        goto EmitVexEvexM;
+      }
+      break;
+    }
+
+    // ------------------------------------------------------------------------
+    // [AMX]
+    // ------------------------------------------------------------------------
+
+    case InstDB::kEncodingAmxCfg:
+      if (isign3 == ENC_OPS1(Mem)) {
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingAmxR:
+      if (isign3 == ENC_OPS1(Reg)) {
+        opReg = o0.id();
+        rbReg = 0;
+        goto EmitVexEvexR;
+      }
+      break;
+
+    case InstDB::kEncodingAmxRm:
+      if (isign3 == ENC_OPS2(Reg, Mem)) {
+        opReg = o0.id();
+        rmRel = &o1;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingAmxMr:
+      if (isign3 == ENC_OPS2(Mem, Reg)) {
+        opReg = o1.id();
+        rmRel = &o0;
+        goto EmitVexEvexM;
+      }
+      break;
+
+    case InstDB::kEncodingAmxRmv:
+      if (isign3 == ENC_OPS3(Reg, Reg, Reg)) {
+        opReg = x86PackRegAndVvvvv(o0.id(), o2.id());
+        rbReg = o1.id();
+        goto EmitVexEvexR;
+      }
+      break;
+  }
+
+  goto InvalidInstruction;
+
+  // --------------------------------------------------------------------------
+  // [Emit - X86]
+  // --------------------------------------------------------------------------
+
+EmitX86OpMovAbs:
+  immSize = FastUInt8(registerSize());
+  writer.emitSegmentOverride(rmRel->as<Mem>().segmentId());
+
+EmitX86Op:
+  // Emit mandatory instruction prefix.
+  writer.emitPP(opcode.v);
+
+  // Emit REX prefix (64-bit only).
+  {
+    uint32_t rex = opcode.extractRex(options);
+    if (ASMJIT_UNLIKELY(x86IsRexInvalid(rex)))
+      goto InvalidRexPrefix;
+    rex &= ~kX86ByteInvalidRex & 0xFF;
+    writer.emit8If(rex | kX86ByteRex, rex != 0);
+  }
+
+  // Emit instruction opcodes.
+  writer.emitMMAndOpcode(opcode.v);
+  writer.emitImmediate(uint64_t(immValue), immSize);
+  goto EmitDone;
+
+  // --------------------------------------------------------------------------
+  // [Emit - X86 - Opcode + Reg]
+  // --------------------------------------------------------------------------
+
+EmitX86OpReg:
+  // Emit mandatory instruction prefix.
+  writer.emitPP(opcode.v);
+
+  // Emit REX prefix (64-bit only).
+  {
+    uint32_t rex = opcode.extractRex(options) | (opReg >> 3); // Rex.B (0x01).
+    if (ASMJIT_UNLIKELY(x86IsRexInvalid(rex)))
+      goto InvalidRexPrefix;
+    rex &= ~kX86ByteInvalidRex & 0xFF;
+    writer.emit8If(rex | kX86ByteRex, rex != 0);
+
+    opReg &= 0x7;
+  }
+
+  // Emit instruction opcodes.
+  opcode += opReg;
+  writer.emitMMAndOpcode(opcode.v);
+  writer.emitImmediate(uint64_t(immValue), immSize);
+  goto EmitDone;
+
+  // --------------------------------------------------------------------------
+  // [Emit - X86 - Opcode with implicit <mem> operand]
+  // --------------------------------------------------------------------------
+
+EmitX86OpImplicitMem:
+  rmInfo = x86MemInfo[rmRel->as<Mem>().baseAndIndexTypes()];
+  if (ASMJIT_UNLIKELY(rmRel->as<Mem>().hasOffset() || (rmInfo & kX86MemInfo_Index)))
+    goto InvalidInstruction;
+
+  // Emit mandatory instruction prefix.
+  writer.emitPP(opcode.v);
+
+  // Emit REX prefix (64-bit only).
+  {
+    uint32_t rex = opcode.extractRex(options);
+    if (ASMJIT_UNLIKELY(x86IsRexInvalid(rex)))
+      goto InvalidRexPrefix;
+    rex &= ~kX86ByteInvalidRex & 0xFF;
+    writer.emit8If(rex | kX86ByteRex, rex != 0);
+  }
+
+  // Emit override prefixes.
+  writer.emitSegmentOverride(rmRel->as<Mem>().segmentId());
+  writer.emitAddressOverride((rmInfo & _addressOverrideMask()) != 0);
+
+  // Emit instruction opcodes.
+  writer.emitMMAndOpcode(opcode.v);
+
+  // Emit immediate value.
+  writer.emitImmediate(uint64_t(immValue), immSize);
+  goto EmitDone;
+
+  // --------------------------------------------------------------------------
+  // [Emit - X86 - Opcode /r - register]
+  // --------------------------------------------------------------------------
+
+EmitX86R:
+  // Mandatory instruction prefix.
+  writer.emitPP(opcode.v);
+
+  // Emit REX prefix (64-bit only).
+  {
+    uint32_t rex = opcode.extractRex(options) |
+                   ((opReg & 0x08) >> 1) | // REX.R (0x04).
+                   ((rbReg & 0x08) >> 3) ; // REX.B (0x01).
+
+    if (ASMJIT_UNLIKELY(x86IsRexInvalid(rex)))
+      goto InvalidRexPrefix;
+    rex &= ~kX86ByteInvalidRex & 0xFF;
+    writer.emit8If(rex | kX86ByteRex, rex != 0);
+
+    opReg &= 0x07;
+    rbReg &= 0x07;
+  }
+
+  // Emit instruction opcodes.
+  writer.emitMMAndOpcode(opcode.v);
+
+  // Emit ModR.
+  writer.emit8(x86EncodeMod(3, opReg, rbReg));
+
+  // Emit immediate value.
+  writer.emitImmediate(uint64_t(immValue), immSize);
+  goto EmitDone;
+
+  // --------------------------------------------------------------------------
+  // [Emit - X86 - Opcode /r - memory base]
+  // --------------------------------------------------------------------------
+
+EmitX86RFromM:
+  rmInfo = x86MemInfo[rmRel->as<Mem>().baseAndIndexTypes()];
+  if (ASMJIT_UNLIKELY(rmRel->as<Mem>().hasOffset() || (rmInfo & kX86MemInfo_Index)))
+    goto InvalidInstruction;
+
+  // Emit mandatory instruction prefix.
+  writer.emitPP(opcode.v);
+
+  // Emit REX prefix (64-bit only).
+  {
+    uint32_t rex = opcode.extractRex(options) |
+                   ((opReg & 0x08) >> 1) | // REX.R (0x04).
+                   ((rbReg       ) >> 3) ; // REX.B (0x01).
+
+    if (ASMJIT_UNLIKELY(x86IsRexInvalid(rex)))
+      goto InvalidRexPrefix;
+    rex &= ~kX86ByteInvalidRex & 0xFF;
+    writer.emit8If(rex | kX86ByteRex, rex != 0);
+
+    opReg &= 0x07;
+    rbReg &= 0x07;
+  }
+
+  // Emit override prefixes.
+  writer.emitSegmentOverride(rmRel->as<Mem>().segmentId());
+  writer.emitAddressOverride((rmInfo & _addressOverrideMask()) != 0);
+
+  // Emit instruction opcodes.
+  writer.emitMMAndOpcode(opcode.v);
+
+  // Emit ModR/M.
+  writer.emit8(x86EncodeMod(3, opReg, rbReg));
+
+  // Emit immediate value.
+  writer.emitImmediate(uint64_t(immValue), immSize);
+  goto EmitDone;
+
+  // --------------------------------------------------------------------------
+  // [Emit - X86 - Opcode /r - memory operand]
+  // --------------------------------------------------------------------------
+
+EmitX86M:
+  // `rmRel` operand must be memory.
+  ASMJIT_ASSERT(rmRel != nullptr);
+  ASMJIT_ASSERT(rmRel->opType() == Operand::kOpMem);
+  ASMJIT_ASSERT((opcode & Opcode::kCDSHL_Mask) == 0);
+
+  // Emit override prefixes.
+  rmInfo = x86MemInfo[rmRel->as<Mem>().baseAndIndexTypes()];
+  writer.emitSegmentOverride(rmRel->as<Mem>().segmentId());
+
+  memOpAOMark = writer.cursor();
+  writer.emitAddressOverride((rmInfo & _addressOverrideMask()) != 0);
+
+  // Emit mandatory instruction prefix.
+  writer.emitPP(opcode.v);
+
+  // Emit REX prefix (64-bit only).
+  rbReg = rmRel->as<Mem>().baseId();
+  rxReg = rmRel->as<Mem>().indexId();
+  {
+    uint32_t rex;
+
+    rex  = (rbReg >> 3) & 0x01; // REX.B (0x01).
+    rex |= (rxReg >> 2) & 0x02; // REX.X (0x02).
+    rex |= (opReg >> 1) & 0x04; // REX.R (0x04).
+
+    rex &= rmInfo;
+    rex |= opcode.extractRex(options);
+
+    if (ASMJIT_UNLIKELY(x86IsRexInvalid(rex)))
+      goto InvalidRexPrefix;
+    rex &= ~kX86ByteInvalidRex & 0xFF;
+    writer.emit8If(rex | kX86ByteRex, rex != 0);
+
+    opReg &= 0x07;
+  }
+
+  // Emit instruction opcodes.
+  writer.emitMMAndOpcode(opcode.v);
+
+  // ... Fall through ...
+
+  // --------------------------------------------------------------------------
+  // [Emit - MOD/SIB]
+  // --------------------------------------------------------------------------
+
+EmitModSib:
+  if (!(rmInfo & (kX86MemInfo_Index | kX86MemInfo_67H_X86))) {
+    // ==========|> [BASE + DISP8|DISP32].
+    if (rmInfo & kX86MemInfo_BaseGp) {
+      rbReg &= 0x7;
+      relOffset = rmRel->as<Mem>().offsetLo32();
+
+      uint32_t mod = x86EncodeMod(0, opReg, rbReg);
+      bool forceSIB = commonInfo->isTsibOp();
+
+      if (rbReg == Gp::kIdSp || forceSIB) {
+        // TSIB or [XSP|R12].
+        mod = (mod & 0xF8u) | 0x04u;
+        if (rbReg != Gp::kIdBp && relOffset == 0) {
+          writer.emit8(mod);
+          writer.emit8(x86EncodeSib(0, 4, rbReg));
+        }
+        // TSIB or [XSP|R12 + DISP8|DISP32].
+        else {
+          uint32_t cdShift = (opcode & Opcode::kCDSHL_Mask) >> Opcode::kCDSHL_Shift;
+          int32_t cdOffset = relOffset >> cdShift;
+
+          if (Support::isInt8(cdOffset) && relOffset == int32_t(uint32_t(cdOffset) << cdShift)) {
+            writer.emit8(mod + 0x40); // <- MOD(1, opReg, rbReg).
+            writer.emit8(x86EncodeSib(0, 4, rbReg));
+            writer.emit8(cdOffset & 0xFF);
+          }
+          else {
+            writer.emit8(mod + 0x80); // <- MOD(2, opReg, rbReg).
+            writer.emit8(x86EncodeSib(0, 4, rbReg));
+            writer.emit32uLE(uint32_t(relOffset));
+          }
+        }
+      }
+      else if (rbReg != Gp::kIdBp && relOffset == 0) {
+        // [BASE].
+        writer.emit8(mod);
+      }
+      else {
+        // [BASE + DISP8|DISP32].
+        uint32_t cdShift = (opcode & Opcode::kCDSHL_Mask) >> Opcode::kCDSHL_Shift;
+        int32_t cdOffset = relOffset >> cdShift;
+
+        if (Support::isInt8(cdOffset) && relOffset == int32_t(uint32_t(cdOffset) << cdShift)) {
+          writer.emit8(mod + 0x40);
+          writer.emit8(cdOffset & 0xFF);
+        }
+        else {
+          writer.emit8(mod + 0x80);
+          writer.emit32uLE(uint32_t(relOffset));
+        }
+      }
+    }
+    // ==========|> [ABSOLUTE | DISP32].
+    else if (!(rmInfo & (kX86MemInfo_BaseLabel | kX86MemInfo_BaseRip))) {
+      uint32_t addrType = rmRel->as<Mem>().addrType();
+      relOffset = rmRel->as<Mem>().offsetLo32();
+
+      if (is32Bit()) {
+        // Explicit relative addressing doesn't work in 32-bit mode.
+        if (ASMJIT_UNLIKELY(addrType == BaseMem::kAddrTypeRel))
+          goto InvalidAddress;
+
+        writer.emit8(x86EncodeMod(0, opReg, 5));
+        writer.emit32uLE(uint32_t(relOffset));
+      }
+      else {
+        bool isOffsetI32 = rmRel->as<Mem>().offsetHi32() == (relOffset >> 31);
+        bool isOffsetU32 = rmRel->as<Mem>().offsetHi32() == 0;
+        uint64_t baseAddress = code()->baseAddress();
+
+        // If relative addressing was not explicitly set then we can try to guess.
+        // By guessing we check some properties of the memory operand and try to
+        // base the decision on the segment prefix and the address type.
+        if (addrType == BaseMem::kAddrTypeDefault) {
+          if (baseAddress == Globals::kNoBaseAddress) {
+            // Prefer absolute addressing mode if the offset is 32-bit.
+            addrType = isOffsetI32 || isOffsetU32 ? BaseMem::kAddrTypeAbs
+                                                  : BaseMem::kAddrTypeRel;
+          }
+          else {
+            // Prefer absolute addressing mode if FS|GS segment override is present.
+            bool hasFsGs = rmRel->as<Mem>().segmentId() >= SReg::kIdFs;
+            // Prefer absolute addressing mode if this is LEA with 32-bit immediate.
+            bool isLea32 = (instId == Inst::kIdLea) && (isOffsetI32 || isOffsetU32);
+
+            addrType = hasFsGs || isLea32 ? BaseMem::kAddrTypeAbs
+                                          : BaseMem::kAddrTypeRel;
+          }
+        }
+
+        if (addrType == BaseMem::kAddrTypeRel) {
+          uint32_t kModRel32Size = 5;
+          uint64_t virtualOffset = uint64_t(writer.offsetFrom(_bufferData)) + immSize + kModRel32Size;
+
+          if (baseAddress == Globals::kNoBaseAddress) {
+            // Create a new RelocEntry as we cannot calculate the offset right now.
+            err = _code->newRelocEntry(&re, RelocEntry::kTypeAbsToRel, 4);
+            if (ASMJIT_UNLIKELY(err))
+              goto Failed;
+
+            writer.emit8(x86EncodeMod(0, opReg, 5));
+            writer.emit32uLE(0);
+
+            re->_sourceSectionId = _section->id();
+            re->_sourceOffset = offset();
+            re->_leadingSize = uint8_t(writer.offsetFrom(_bufferPtr) - 4);
+            re->_trailingSize = uint8_t(immSize);
+            re->_payload = uint64_t(rmRel->as<Mem>().offset());
+
+            writer.emitImmediate(uint64_t(immValue), immSize);
+            goto EmitDone;
+          }
+          else {
+            uint64_t rip64 = baseAddress + _section->offset() + virtualOffset;
+            uint64_t rel64 = uint64_t(rmRel->as<Mem>().offset()) - rip64;
+
+            if (Support::isInt32(int64_t(rel64))) {
+              writer.emit8(x86EncodeMod(0, opReg, 5));
+              writer.emit32uLE(uint32_t(rel64 & 0xFFFFFFFFu));
+              writer.emitImmediate(uint64_t(immValue), immSize);
+              goto EmitDone;
+            }
+            else {
+              // We must check the original address type as we have modified
+              // `addrType`. We failed if the original address type is 'rel'.
+              if (ASMJIT_UNLIKELY(rmRel->as<Mem>().isRel()))
+                goto InvalidAddress;
+            }
+          }
+        }
+
+        // Handle unsigned 32-bit address that doesn't work with sign extension.
+        // Consider the following instructions:
+        //
+        //   1. lea rax, [-1]         - Sign extended to 0xFFFFFFFFFFFFFFFF
+        //   2. lea rax, [0xFFFFFFFF] - Zero extended to 0x00000000FFFFFFFF
+        //   3. add rax, [-1]         - Sign extended to 0xFFFFFFFFFFFFFFFF
+        //   4. add rax, [0xFFFFFFFF] - Zero extended to 0x00000000FFFFFFFF
+        //
+        // Sign extension is naturally performed by the CPU so we don't have to
+        // bother, however, zero extension requires address-size override prefix,
+        // which we probably don't have at this moment. So to make the address
+        // valid we need to insert it at `memOpAOMark` if it's not already there.
+        //
+        // If this is 'lea' instruction then it's possible to remove REX.W part
+        // from REX prefix (if it's there), which would be one-byte shorter than
+        // inserting address-size override.
+        //
+        // NOTE: If we don't do this then these instructions are unencodable.
+        if (!isOffsetI32) {
+          // 64-bit absolute address is unencodable.
+          if (ASMJIT_UNLIKELY(!isOffsetU32))
+            goto InvalidAddress64Bit;
+
+          // We only patch the existing code if we don't have address-size override.
+          if (*memOpAOMark != 0x67) {
+            if (instId == Inst::kIdLea) {
+              // LEA: Remove REX.W, if present. This is easy as we know that 'lea'
+              // doesn't use any PP prefix so if REX prefix was emitted it would be
+              // at `memOpAOMark`.
+              uint32_t rex = *memOpAOMark;
+              if (rex & kX86ByteRex) {
+                rex &= (~kX86ByteRexW) & 0xFF;
+                *memOpAOMark = uint8_t(rex);
+
+                // We can remove the REX prefix completely if it was not forced.
+                if (rex == kX86ByteRex && !(options & Inst::kOptionRex))
+                  writer.remove8(memOpAOMark);
+              }
+            }
+            else {
+              // Any other instruction: Insert address-size override prefix.
+              writer.insert8(memOpAOMark, 0x67);
+            }
+          }
+        }
+
+        // Emit 32-bit absolute address.
+        writer.emit8(x86EncodeMod(0, opReg, 4));
+        writer.emit8(x86EncodeSib(0, 4, 5));
+        writer.emit32uLE(uint32_t(relOffset));
+      }
+    }
+    // ==========|> [LABEL|RIP + DISP32]
+    else {
+      writer.emit8(x86EncodeMod(0, opReg, 5));
+
+      if (is32Bit()) {
+EmitModSib_LabelRip_X86:
+        if (ASMJIT_UNLIKELY(_code->_relocations.willGrow(_code->allocator()) != kErrorOk))
+          goto OutOfMemory;
+
+        relOffset = rmRel->as<Mem>().offsetLo32();
+        if (rmInfo & kX86MemInfo_BaseLabel) {
+          // [LABEL->ABS].
+          label = _code->labelEntry(rmRel->as<Mem>().baseId());
+          if (ASMJIT_UNLIKELY(!label))
+            goto InvalidLabel;
+
+          err = _code->newRelocEntry(&re, RelocEntry::kTypeRelToAbs, 4);
+          if (ASMJIT_UNLIKELY(err))
+            goto Failed;
+
+          re->_sourceSectionId = _section->id();
+          re->_sourceOffset = offset();
+          re->_leadingSize = uint8_t(writer.offsetFrom(_bufferPtr));
+          re->_trailingSize = uint8_t(immSize);
+          re->_payload = uint64_t(int64_t(relOffset));
+
+          if (label->isBound()) {
+            // Label bound to the current section.
+            re->_payload += label->offset();
+            re->_targetSectionId = label->section()->id();
+            writer.emit32uLE(0);
+          }
+          else {
+            // Non-bound label or label bound to a different section.
+            relOffset = -4 - immSize;
+            relSize = 4;
+            goto EmitRel;
+          }
+        }
+        else {
+          // [RIP->ABS].
+          err = _code->newRelocEntry(&re, RelocEntry::kTypeRelToAbs, 4);
+          if (ASMJIT_UNLIKELY(err))
+            goto Failed;
+
+          re->_sourceSectionId = _section->id();
+          re->_targetSectionId = _section->id();
+          re->_sourceOffset = offset();
+          re->_leadingSize = uint8_t(writer.offsetFrom(_bufferPtr));
+          re->_trailingSize = uint8_t(immSize);
+          re->_payload = re->_sourceOffset + re->_leadingSize + 4 + re->_trailingSize + uint64_t(int64_t(relOffset));
+
+          writer.emit32uLE(0);
+        }
+      }
+      else {
+        relOffset = rmRel->as<Mem>().offsetLo32();
+        if (rmInfo & kX86MemInfo_BaseLabel) {
+          // [RIP].
+          label = _code->labelEntry(rmRel->as<Mem>().baseId());
+          if (ASMJIT_UNLIKELY(!label))
+            goto InvalidLabel;
+
+          relOffset -= (4 + immSize);
+          if (label->isBoundTo(_section)) {
+            // Label bound to the current section.
+            relOffset += int32_t(label->offset() - writer.offsetFrom(_bufferData));
+            writer.emit32uLE(uint32_t(relOffset));
+          }
+          else {
+            // Non-bound label or label bound to a different section.
+            relSize = 4;
+            goto EmitRel;
+          }
+        }
+        else {
+          // [RIP].
+          writer.emit32uLE(uint32_t(relOffset));
+        }
+      }
+    }
+  }
+  else if (!(rmInfo & kX86MemInfo_67H_X86)) {
+    // ESP|RSP can't be used as INDEX in pure SIB mode, however, VSIB mode
+    // allows XMM4|YMM4|ZMM4 (that's why the check is before the label).
+    if (ASMJIT_UNLIKELY(rxReg == Gp::kIdSp))
+      goto InvalidAddressIndex;
+
+EmitModVSib:
+    rxReg &= 0x7;
+
+    // ==========|> [BASE + INDEX + DISP8|DISP32].
+    if (rmInfo & kX86MemInfo_BaseGp) {
+      rbReg &= 0x7;
+      relOffset = rmRel->as<Mem>().offsetLo32();
+
+      uint32_t mod = x86EncodeMod(0, opReg, 4);
+      uint32_t sib = x86EncodeSib(rmRel->as<Mem>().shift(), rxReg, rbReg);
+
+      if (relOffset == 0 && rbReg != Gp::kIdBp) {
+        // [BASE + INDEX << SHIFT].
+        writer.emit8(mod);
+        writer.emit8(sib);
+      }
+      else {
+        uint32_t cdShift = (opcode & Opcode::kCDSHL_Mask) >> Opcode::kCDSHL_Shift;
+        int32_t cdOffset = relOffset >> cdShift;
+
+        if (Support::isInt8(cdOffset) && relOffset == int32_t(uint32_t(cdOffset) << cdShift)) {
+          // [BASE + INDEX << SHIFT + DISP8].
+          writer.emit8(mod + 0x40); // <- MOD(1, opReg, 4).
+          writer.emit8(sib);
+          writer.emit8(uint32_t(cdOffset));
+        }
+        else {
+          // [BASE + INDEX << SHIFT + DISP32].
+          writer.emit8(mod + 0x80); // <- MOD(2, opReg, 4).
+          writer.emit8(sib);
+          writer.emit32uLE(uint32_t(relOffset));
+        }
+      }
+    }
+    // ==========|> [INDEX + DISP32].
+    else if (!(rmInfo & (kX86MemInfo_BaseLabel | kX86MemInfo_BaseRip))) {
+      // [INDEX << SHIFT + DISP32].
+      writer.emit8(x86EncodeMod(0, opReg, 4));
+      writer.emit8(x86EncodeSib(rmRel->as<Mem>().shift(), rxReg, 5));
+
+      relOffset = rmRel->as<Mem>().offsetLo32();
+      writer.emit32uLE(uint32_t(relOffset));
+    }
+    // ==========|> [LABEL|RIP + INDEX + DISP32].
+    else {
+      if (is32Bit()) {
+        writer.emit8(x86EncodeMod(0, opReg, 4));
+        writer.emit8(x86EncodeSib(rmRel->as<Mem>().shift(), rxReg, 5));
+        goto EmitModSib_LabelRip_X86;
+      }
+      else {
+        // NOTE: This also handles VSIB+RIP, which is not allowed in 64-bit mode.
+        goto InvalidAddress;
+      }
+    }
+  }
+  else {
+    // 16-bit address mode (32-bit mode with 67 override prefix).
+    relOffset = (int32_t(rmRel->as<Mem>().offsetLo32()) << 16) >> 16;
+
+    // NOTE: 16-bit addresses don't use SIB byte and their encoding differs. We
+    // use a table-based approach to calculate the proper MOD byte as it's easier.
+    // Also, not all BASE [+ INDEX] combinations are supported in 16-bit mode, so
+    // this may fail.
+    const uint32_t kBaseGpIdx = (kX86MemInfo_BaseGp | kX86MemInfo_Index);
+
+    if (rmInfo & kBaseGpIdx) {
+      // ==========|> [BASE + INDEX + DISP16].
+      uint32_t mod;
+
+      rbReg &= 0x7;
+      rxReg &= 0x7;
+
+      if ((rmInfo & kBaseGpIdx) == kBaseGpIdx) {
+        uint32_t shf = rmRel->as<Mem>().shift();
+        if (ASMJIT_UNLIKELY(shf != 0))
+          goto InvalidAddress;
+        mod = x86Mod16BaseIndexTable[(rbReg << 3) + rxReg];
+      }
+      else {
+        if (rmInfo & kX86MemInfo_Index)
+          rbReg = rxReg;
+        mod = x86Mod16BaseTable[rbReg];
+      }
+
+      if (ASMJIT_UNLIKELY(mod == 0xFF))
+        goto InvalidAddress;
+
+      mod += opReg << 3;
+      if (relOffset == 0 && mod != 0x06) {
+        writer.emit8(mod);
+      }
+      else if (Support::isInt8(relOffset)) {
+        writer.emit8(mod + 0x40);
+        writer.emit8(uint32_t(relOffset));
+      }
+      else {
+        writer.emit8(mod + 0x80);
+        writer.emit16uLE(uint32_t(relOffset));
+      }
+    }
+    else {
+      // Not supported in 16-bit addresses.
+      if (rmInfo & (kX86MemInfo_BaseRip | kX86MemInfo_BaseLabel))
+        goto InvalidAddress;
+
+      // ==========|> [DISP16].
+      writer.emit8(opReg | 0x06);
+      writer.emit16uLE(uint32_t(relOffset));
+    }
+  }
+
+  writer.emitImmediate(uint64_t(immValue), immSize);
+  goto EmitDone;
+
+  // --------------------------------------------------------------------------
+  // [Emit - FPU]
+  // --------------------------------------------------------------------------
+
+EmitFpuOp:
+  // Mandatory instruction prefix.
+  writer.emitPP(opcode.v);
+
+  // FPU instructions consist of two opcodes.
+  writer.emit8(opcode.v >> Opcode::kFPU_2B_Shift);
+  writer.emit8(opcode.v);
+  goto EmitDone;
+
+  // --------------------------------------------------------------------------
+  // [Emit - VEX|EVEX]
+  // --------------------------------------------------------------------------
+
+EmitVexEvexOp:
+  {
+    // These don't use immediate.
+    ASMJIT_ASSERT(immSize == 0);
+
+    // Only 'vzeroall' and 'vzeroupper' instructions use this encoding, they
+    // don't define 'W' to be '1' so we can just check the 'mmmmm' field. Both
+    // functions can encode by using VEX2 prefix so VEX3 is basically only used
+    // when specified as instruction option.
+    ASMJIT_ASSERT((opcode & Opcode::kW) == 0);
+
+    uint32_t x = ((opcode  & Opcode::kMM_Mask    ) >> (Opcode::kMM_Shift     )) |
+                 ((opcode  & Opcode::kLL_Mask    ) >> (Opcode::kLL_Shift - 10)) |
+                 ((opcode  & Opcode::kPP_VEXMask ) >> (Opcode::kPP_Shift -  8)) |
+                 ((options & Inst::kOptionVex3   ) >> (Opcode::kMM_Shift     )) ;
+    if (x & 0x04u) {
+      x  = (x & (0x4 ^ 0xFFFF)) << 8;                    // [00000000|00000Lpp|0000m0mm|00000000].
+      x ^= (kX86ByteVex3) |                              // [........|00000Lpp|0000m0mm|__VEX3__].
+           (0x07u  << 13) |                              // [........|00000Lpp|1110m0mm|__VEX3__].
+           (0x0Fu  << 19) |                              // [........|01111Lpp|1110m0mm|__VEX3__].
+           (opcode << 24) ;                              // [_OPCODE_|01111Lpp|1110m0mm|__VEX3__].
+
+      writer.emit32uLE(x);
+      goto EmitDone;
+    }
+    else {
+      x = ((x >> 8) ^ x) ^ 0xF9;
+      writer.emit8(kX86ByteVex2);
+      writer.emit8(x);
+      writer.emit8(opcode.v);
+      goto EmitDone;
+    }
+  }
+
+  // --------------------------------------------------------------------------
+  // [Emit - VEX|EVEX - /r (Register)]
+  // --------------------------------------------------------------------------
+
+EmitVexEvexR:
+  {
+    // Construct `x` - a complete EVEX|VEX prefix.
+    uint32_t x = ((opReg << 4) & 0xF980u) |              // [........|........|Vvvvv..R|R.......].
+                 ((rbReg << 2) & 0x0060u) |              // [........|........|........|.BB.....].
+                 (opcode.extractLLMM(options)) |         // [........|.LL.....|Vvvvv..R|RBBmmmmm].
+                 (_extraReg.id() << 16);                 // [........|.LL..aaa|Vvvvv..R|RBBmmmmm].
+    opReg &= 0x7;
+
+    // Handle AVX512 options by a single branch.
+    const uint32_t kAvx512Options = Inst::kOptionZMask | Inst::kOptionER | Inst::kOptionSAE;
+    if (options & kAvx512Options) {
+      uint32_t kBcstMask = 0x1 << 20;
+      uint32_t kLLMask10 = 0x2 << 21;
+      uint32_t kLLMask11 = 0x3 << 21;
+
+      // Designed to be easily encodable so the position must be exact.
+      // The {rz-sae} is encoded as {11}, so it should match the mask.
+      ASMJIT_ASSERT(Inst::kOptionRZ_SAE == kLLMask11);
+
+      x |= options & Inst::kOptionZMask;                 // [........|zLLb.aaa|Vvvvv..R|RBBmmmmm].
+
+      // Support embedded-rounding {er} and suppress-all-exceptions {sae}.
+      if (options & (Inst::kOptionER | Inst::kOptionSAE)) {
+        // Embedded rounding is only encodable if the instruction is either
+        // scalar or it's a 512-bit operation as the {er} rounding predicate
+        // collides with LL part of the instruction.
+        if ((x & kLLMask11) != kLLMask10) {
+          // Ok, so LL is not 10, thus the instruction must be scalar.
+          // Scalar instructions don't support broadcast so if this
+          // instruction supports it {er} nor {sae} would be encodable.
+          if (ASMJIT_UNLIKELY(commonInfo->hasAvx512B()))
+            goto InvalidEROrSAE;
+        }
+
+        if (options & Inst::kOptionER) {
+          if (ASMJIT_UNLIKELY(!commonInfo->hasAvx512ER()))
+            goto InvalidEROrSAE;
+
+          x &=~kLLMask11;                                // [........|.00..aaa|Vvvvv..R|RBBmmmmm].
+          x |= kBcstMask | (options & kLLMask11);        // [........|.LLb.aaa|Vvvvv..R|RBBmmmmm].
+        }
+        else {
+          if (ASMJIT_UNLIKELY(!commonInfo->hasAvx512SAE()))
+            goto InvalidEROrSAE;
+
+          x |= kBcstMask;                                // [........|.LLb.aaa|Vvvvv..R|RBBmmmmm].
+        }
+      }
+    }
+
+    // Check if EVEX is required by checking bits in `x` :  [........|xx.x.xxx|x......x|.x.x....].
+    if (x & 0x00D78150u) {
+      uint32_t y = ((x << 4) & 0x00080000u) |            // [........|...bV...|........|........].
+                   ((x >> 4) & 0x00000010u) ;            // [........|...bV...|........|...R....].
+      x  = (x & 0x00FF78E3u) | y;                        // [........|zLLbVaaa|0vvvv000|RBBR00mm].
+      x  = x << 8;                                       // [zLLbVaaa|0vvvv000|RBBR00mm|00000000].
+      x |= (opcode >> kVSHR_W    ) & 0x00800000u;        // [zLLbVaaa|Wvvvv000|RBBR00mm|00000000].
+      x |= (opcode >> kVSHR_PP_EW) & 0x00830000u;        // [zLLbVaaa|Wvvvv0pp|RBBR00mm|00000000] (added PP and EVEX.W).
+                                                         //      _     ____    ____
+      x ^= 0x087CF000u | kX86ByteEvex;                   // [zLLbVaaa|Wvvvv1pp|RBBR00mm|01100010].
+
+      writer.emit32uLE(x);
+      writer.emit8(opcode.v);
+
+      rbReg &= 0x7;
+      writer.emit8(x86EncodeMod(3, opReg, rbReg));
+      writer.emitImmByteOrDWord(uint64_t(immValue), immSize);
+      goto EmitDone;
+    }
+
+    // Not EVEX, prepare `x` for VEX2 or VEX3:          x = [........|00L00000|0vvvv000|R0B0mmmm].
+    x |= ((opcode >> (kVSHR_W  + 8)) & 0x8000u) |        // [00000000|00L00000|Wvvvv000|R0B0mmmm].
+         ((opcode >> (kVSHR_PP + 8)) & 0x0300u) |        // [00000000|00L00000|0vvvv0pp|R0B0mmmm].
+         ((x      >> 11            ) & 0x0400u) ;        // [00000000|00L00000|WvvvvLpp|R0B0mmmm].
+
+    // Check if VEX3 is required / forced:                  [........|........|x.......|..x..x..].
+    if (x & 0x0008024u) {
+      uint32_t xorMsk = x86VEXPrefix[x & 0xF] | (opcode << 24);
+
+      // Clear 'FORCE-VEX3' bit and all high bits.
+      x  = (x & (0x4 ^ 0xFFFF)) << 8;                    // [00000000|WvvvvLpp|R0B0m0mm|00000000].
+                                                         //            ____    _ _
+      x ^= xorMsk;                                       // [_OPCODE_|WvvvvLpp|R1Bmmmmm|VEX3|XOP].
+      writer.emit32uLE(x);
+
+      rbReg &= 0x7;
+      writer.emit8(x86EncodeMod(3, opReg, rbReg));
+      writer.emitImmByteOrDWord(uint64_t(immValue), immSize);
+      goto EmitDone;
+    }
+    else {
+      // 'mmmmm' must be '00001'.
+      ASMJIT_ASSERT((x & 0x1F) == 0x01);
+
+      x = ((x >> 8) ^ x) ^ 0xF9;
+      writer.emit8(kX86ByteVex2);
+      writer.emit8(x);
+      writer.emit8(opcode.v);
+
+      rbReg &= 0x7;
+      writer.emit8(x86EncodeMod(3, opReg, rbReg));
+      writer.emitImmByteOrDWord(uint64_t(immValue), immSize);
+      goto EmitDone;
+    }
+  }
+
+  // --------------------------------------------------------------------------
+  // [Emit - VEX|EVEX - /r (Memory)]
+  // --------------------------------------------------------------------------
+
+EmitVexEvexM:
+  ASMJIT_ASSERT(rmRel != nullptr);
+  ASMJIT_ASSERT(rmRel->opType() == Operand::kOpMem);
+
+  rmInfo = x86MemInfo[rmRel->as<Mem>().baseAndIndexTypes()];
+  writer.emitSegmentOverride(rmRel->as<Mem>().segmentId());
+
+  memOpAOMark = writer.cursor();
+  writer.emitAddressOverride((rmInfo & _addressOverrideMask()) != 0);
+
+  rbReg = rmRel->as<Mem>().hasBaseReg()  ? rmRel->as<Mem>().baseId()  : uint32_t(0);
+  rxReg = rmRel->as<Mem>().hasIndexReg() ? rmRel->as<Mem>().indexId() : uint32_t(0);
+
+  {
+    uint32_t broadcastBit = uint32_t(rmRel->as<Mem>().hasBroadcast());
+
+    // Construct `x` - a complete EVEX|VEX prefix.
+    uint32_t x = ((opReg <<  4) & 0x0000F980u) |         // [........|........|Vvvvv..R|R.......].
+                 ((rxReg <<  3) & 0x00000040u) |         // [........|........|........|.X......].
+                 ((rxReg << 15) & 0x00080000u) |         // [........|....X...|........|........].
+                 ((rbReg <<  2) & 0x00000020u) |         // [........|........|........|..B.....].
+                 opcode.extractLLMM(options)   |         // [........|.LL.X...|Vvvvv..R|RXBmmmmm].
+                 (_extraReg.id()    << 16)     |         // [........|.LL.Xaaa|Vvvvv..R|RXBmmmmm].
+                 (broadcastBit      << 20)     ;         // [........|.LLbXaaa|Vvvvv..R|RXBmmmmm].
+    opReg &= 0x07u;
+
+    // Mark invalid VEX (force EVEX) case:               // [@.......|.LLbXaaa|Vvvvv..R|RXBmmmmm].
+    x |= (~commonInfo->flags() & InstDB::kFlagVex) << (31 - Support::constCtz(InstDB::kFlagVex));
+
+    // Handle AVX512 options by a single branch.
+    const uint32_t kAvx512Options = Inst::kOptionZMask   |
+                                    Inst::kOptionER      |
+                                    Inst::kOptionSAE     ;
+    if (options & kAvx512Options) {
+      // {er} and {sae} are both invalid if memory operand is used.
+      if (ASMJIT_UNLIKELY(options & (Inst::kOptionER | Inst::kOptionSAE)))
+        goto InvalidEROrSAE;
+
+      x |= options & (Inst::kOptionZMask);               // [@.......|zLLbXaaa|Vvvvv..R|RXBmmmmm].
+    }
+
+    // Check if EVEX is required by checking bits in `x` :  [@.......|xx.xxxxx|x......x|...x....].
+    if (x & 0x80DF8110u) {
+      uint32_t y = ((x << 4) & 0x00080000u) |            // [@.......|....V...|........|........].
+                   ((x >> 4) & 0x00000010u) ;            // [@.......|....V...|........|...R....].
+      x  = (x & 0x00FF78E3u) | y;                        // [........|zLLbVaaa|0vvvv000|RXBR00mm].
+      x  = x << 8;                                       // [zLLbVaaa|0vvvv000|RBBR00mm|00000000].
+      x |= (opcode >> kVSHR_W    ) & 0x00800000u;        // [zLLbVaaa|Wvvvv000|RBBR00mm|00000000].
+      x |= (opcode >> kVSHR_PP_EW) & 0x00830000u;        // [zLLbVaaa|Wvvvv0pp|RBBR00mm|00000000] (added PP and EVEX.W).
+                                                         //      _     ____    ____
+      x ^= 0x087CF000u | kX86ByteEvex;                   // [zLLbVaaa|Wvvvv1pp|RBBR00mm|01100010].
+
+      writer.emit32uLE(x);
+      writer.emit8(opcode.v);
+
+      if (x & 0x10000000u) {
+        // Broadcast, change the compressed displacement scale to either x4 (SHL 2) or x8 (SHL 3)
+        // depending on instruction's W. If 'W' is 1 'SHL' must be 3, otherwise it must be 2.
+        opcode &=~uint32_t(Opcode::kCDSHL_Mask);
+        opcode |= ((x & 0x00800000u) ? 3u : 2u) << Opcode::kCDSHL_Shift;
+      }
+      else {
+        // Add the compressed displacement 'SHF' to the opcode based on 'TTWLL'.
+        // The index to `x86CDisp8SHL` is composed as `CDTT[4:3] | W[2] | LL[1:0]`.
+        uint32_t TTWLL = ((opcode >> (Opcode::kCDTT_Shift - 3)) & 0x18) +
+                         ((opcode >> (Opcode::kW_Shift    - 2)) & 0x04) +
+                         ((x >> 29) & 0x3);
+        opcode += x86CDisp8SHL[TTWLL];
+      }
+    }
+    else {
+      // Not EVEX, prepare `x` for VEX2 or VEX3:        x = [........|00L00000|0vvvv000|RXB0mmmm].
+      x |= ((opcode >> (kVSHR_W  + 8)) & 0x8000u) |      // [00000000|00L00000|Wvvvv000|RXB0mmmm].
+           ((opcode >> (kVSHR_PP + 8)) & 0x0300u) |      // [00000000|00L00000|Wvvvv0pp|RXB0mmmm].
+           ((x      >> 11            ) & 0x0400u) ;      // [00000000|00L00000|WvvvvLpp|RXB0mmmm].
+
+      // Clear a possible CDisp specified by EVEX.
+      opcode &= ~Opcode::kCDSHL_Mask;
+
+      // Check if VEX3 is required / forced:                [........|........|x.......|.xx..x..].
+      if (x & 0x0008064u) {
+        uint32_t xorMsk = x86VEXPrefix[x & 0xF] | (opcode << 24);
+
+        // Clear 'FORCE-VEX3' bit and all high bits.
+        x  = (x & (0x4 ^ 0xFFFF)) << 8;                  // [00000000|WvvvvLpp|RXB0m0mm|00000000].
+                                                         //            ____    ___
+        x ^= xorMsk;                                     // [_OPCODE_|WvvvvLpp|RXBmmmmm|VEX3_XOP].
+        writer.emit32uLE(x);
+      }
+      else {
+        // 'mmmmm' must be '00001'.
+        ASMJIT_ASSERT((x & 0x1F) == 0x01);
+
+        x = ((x >> 8) ^ x) ^ 0xF9;
+        writer.emit8(kX86ByteVex2);
+        writer.emit8(x);
+        writer.emit8(opcode.v);
+      }
+    }
+  }
+
+  // MOD|SIB address.
+  if (!commonInfo->hasFlag(InstDB::kFlagVsib))
+    goto EmitModSib;
+
+  // MOD|VSIB address without INDEX is invalid.
+  if (rmInfo & kX86MemInfo_Index)
+    goto EmitModVSib;
+  goto InvalidInstruction;
+
+  // --------------------------------------------------------------------------
+  // [Emit - Jmp/Jcc/Call]
+  // --------------------------------------------------------------------------
+
+EmitJmpCall:
+  {
+    // Emit REX prefix if asked for (64-bit only).
+    uint32_t rex = opcode.extractRex(options);
+    if (ASMJIT_UNLIKELY(x86IsRexInvalid(rex)))
+      goto InvalidRexPrefix;
+    rex &= ~kX86ByteInvalidRex & 0xFF;
+    writer.emit8If(rex | kX86ByteRex, rex != 0);
+
+    uint64_t ip = uint64_t(writer.offsetFrom(_bufferData));
+    uint32_t rel32 = 0;
+    uint32_t opCode8 = x86AltOpcodeOf(instInfo);
+
+    uint32_t inst8Size  = 1 + 1; //          OPCODE + REL8 .
+    uint32_t inst32Size = 1 + 4; // [PREFIX] OPCODE + REL32.
+
+    // Jcc instructions with 32-bit displacement use 0x0F prefix,
+    // other instructions don't. No other prefixes are used by X86.
+    ASMJIT_ASSERT((opCode8 & Opcode::kMM_Mask) == 0);
+    ASMJIT_ASSERT((opcode  & Opcode::kMM_Mask) == 0 ||
+                  (opcode  & Opcode::kMM_Mask) == Opcode::kMM_0F);
+
+    // Only one of these should be used at the same time.
+    inst32Size += uint32_t(opReg != 0);
+    inst32Size += uint32_t((opcode & Opcode::kMM_Mask) == Opcode::kMM_0F);
+
+    if (rmRel->isLabel()) {
+      label = _code->labelEntry(rmRel->as<Label>());
+      if (ASMJIT_UNLIKELY(!label))
+        goto InvalidLabel;
+
+      if (label->isBoundTo(_section)) {
+        // Label bound to the current section.
+        rel32 = uint32_t((label->offset() - ip - inst32Size) & 0xFFFFFFFFu);
+        goto EmitJmpCallRel;
+      }
+      else {
+        // Non-bound label or label bound to a different section.
+        if (opCode8 && (!opcode.v || (options & Inst::kOptionShortForm))) {
+          writer.emit8(opCode8);
+
+          // Record DISP8 (non-bound label).
+          relOffset = -1;
+          relSize = 1;
+          goto EmitRel;
+        }
+        else {
+          // Refuse also 'short' prefix, if specified.
+          if (ASMJIT_UNLIKELY(!opcode.v || (options & Inst::kOptionShortForm) != 0))
+            goto InvalidDisplacement;
+
+          writer.emit8If(0x0F, (opcode & Opcode::kMM_Mask) != 0);// Emit 0F prefix.
+          writer.emit8(opcode.v);                                // Emit opcode.
+          writer.emit8If(x86EncodeMod(3, opReg, 0), opReg != 0); // Emit MOD.
+
+          // Record DISP32 (non-bound label).
+          relOffset = -4;
+          relSize = 4;
+          goto EmitRel;
+        }
+      }
+    }
+
+    if (rmRel->isImm()) {
+      uint64_t baseAddress = code()->baseAddress();
+      uint64_t jumpAddress = rmRel->as<Imm>().valueAs<uint64_t>();
+
+      // If the base-address is known calculate a relative displacement and
+      // check if it fits in 32 bits (which is always true in 32-bit mode).
+      // Emit relative displacement as it was a bound label if all checks are ok.
+      if (baseAddress != Globals::kNoBaseAddress) {
+        uint64_t rel64 = jumpAddress - (ip + baseAddress) - inst32Size;
+        if (Environment::is32Bit(arch()) || Support::isInt32(int64_t(rel64))) {
+          rel32 = uint32_t(rel64 & 0xFFFFFFFFu);
+          goto EmitJmpCallRel;
+        }
+        else {
+          // Relative displacement exceeds 32-bits - relocator can only
+          // insert trampoline for jmp/call, but not for jcc/jecxz.
+          if (ASMJIT_UNLIKELY(!x86IsJmpOrCall(instId)))
+            goto InvalidDisplacement;
+        }
+      }
+
+      err = _code->newRelocEntry(&re, RelocEntry::kTypeAbsToRel, 0);
+      if (ASMJIT_UNLIKELY(err))
+        goto Failed;
+
+      re->_sourceOffset = offset();
+      re->_sourceSectionId = _section->id();
+      re->_payload = jumpAddress;
+
+      if (ASMJIT_LIKELY(opcode.v)) {
+        // 64-bit: Emit REX prefix so the instruction can be patched later.
+        // REX prefix does nothing if not patched, but allows to patch the
+        // instruction to use MOD/M and to point to a memory where the final
+        // 64-bit address is stored.
+        if (Environment::is64Bit(arch()) && x86IsJmpOrCall(instId)) {
+          if (!rex)
+            writer.emit8(kX86ByteRex);
+
+          err = _code->addAddressToAddressTable(jumpAddress);
+          if (ASMJIT_UNLIKELY(err))
+            goto Failed;
+
+          re->_relocType = RelocEntry::kTypeX64AddressEntry;
+        }
+
+        writer.emit8If(0x0F, (opcode & Opcode::kMM_Mask) != 0);  // Emit 0F prefix.
+        writer.emit8(opcode.v);                                  // Emit opcode.
+        writer.emit8If(x86EncodeMod(3, opReg, 0), opReg != 0);   // Emit MOD.
+        writer.emit32uLE(0);                                     // Emit DISP32.
+
+        re->_valueSize = 4;
+        re->_leadingSize = uint8_t(writer.offsetFrom(_bufferPtr) - 4);
+        re->_trailingSize = uint8_t(immSize);
+      }
+      else {
+        writer.emit8(opCode8);                                   // Emit opcode.
+        writer.emit8(0);                                         // Emit DISP8 (zero).
+
+        re->_valueSize = 1;
+        re->_leadingSize = uint8_t(writer.offsetFrom(_bufferPtr) - 1);
+        re->_trailingSize = uint8_t(immSize);
+      }
+      goto EmitDone;
+    }
+
+    // Not Label|Imm -> Invalid.
+    goto InvalidInstruction;
+
+    // Emit jmp/call with relative displacement known at assembly-time. Decide
+    // between 8-bit and 32-bit displacement encoding. Some instructions only
+    // allow either 8-bit or 32-bit encoding, others allow both encodings.
+EmitJmpCallRel:
+    if (Support::isInt8(int32_t(rel32 + inst32Size - inst8Size)) && opCode8 && !(options & Inst::kOptionLongForm)) {
+      options |= Inst::kOptionShortForm;
+      writer.emit8(opCode8);                                     // Emit opcode
+      writer.emit8(rel32 + inst32Size - inst8Size);              // Emit DISP8.
+      goto EmitDone;
+    }
+    else {
+      if (ASMJIT_UNLIKELY(!opcode.v || (options & Inst::kOptionShortForm) != 0))
+        goto InvalidDisplacement;
+
+      options &= ~Inst::kOptionShortForm;
+      writer.emit8If(0x0F, (opcode & Opcode::kMM_Mask) != 0);    // Emit 0x0F prefix.
+      writer.emit8(opcode.v);                                    // Emit Opcode.
+      writer.emit8If(x86EncodeMod(3, opReg, 0), opReg != 0);     // Emit MOD.
+      writer.emit32uLE(rel32);                                   // Emit DISP32.
+      goto EmitDone;
+    }
+  }
+
+  // --------------------------------------------------------------------------
+  // [Emit - Relative]
+  // --------------------------------------------------------------------------
+
+EmitRel:
+  {
+    ASMJIT_ASSERT(relSize == 1 || relSize == 4);
+
+    // Chain with label.
+    size_t offset = size_t(writer.offsetFrom(_bufferData));
+    LabelLink* link = _code->newLabelLink(label, _section->id(), offset, relOffset);
+
+    if (ASMJIT_UNLIKELY(!link))
+      goto OutOfMemory;
+
+    if (re)
+      link->relocId = re->id();
+
+    // Emit label size as dummy data.
+    if (relSize == 1)
+      writer.emit8(0x01);
+    else // if (relSize == 4)
+      writer.emit32uLE(0x04040404);
+  }
+  writer.emitImmediate(uint64_t(immValue), immSize);
+
+  // --------------------------------------------------------------------------
+  // [Done]
+  // --------------------------------------------------------------------------
+
+EmitDone:
+  if (ASMJIT_UNLIKELY(options & Inst::kOptionReserved)) {
+#ifndef ASMJIT_NO_LOGGING
+    if (_logger)
+      EmitterUtils::logInstructionEmitted(this, instId, options, o0, o1, o2, opExt, relSize, immSize, writer.cursor());
+#endif
+  }
+
+  resetExtraReg();
+  resetInstOptions();
+  resetInlineComment();
+
+  writer.done(this);
+  return kErrorOk;
+
+  // --------------------------------------------------------------------------
+  // [Error Cases]
+  // --------------------------------------------------------------------------
+
+  #define ERROR_HANDLER(ERROR)                  \
+    ERROR:                                      \
+      err = DebugUtils::errored(kError##ERROR); \
+      goto Failed;
+
+  ERROR_HANDLER(OutOfMemory)
+  ERROR_HANDLER(InvalidLabel)
+  ERROR_HANDLER(InvalidInstruction)
+  ERROR_HANDLER(InvalidLockPrefix)
+  ERROR_HANDLER(InvalidXAcquirePrefix)
+  ERROR_HANDLER(InvalidXReleasePrefix)
+  ERROR_HANDLER(InvalidRepPrefix)
+  ERROR_HANDLER(InvalidRexPrefix)
+  ERROR_HANDLER(InvalidEROrSAE)
+  ERROR_HANDLER(InvalidAddress)
+  ERROR_HANDLER(InvalidAddressIndex)
+  ERROR_HANDLER(InvalidAddress64Bit)
+  ERROR_HANDLER(InvalidDisplacement)
+  ERROR_HANDLER(InvalidPhysId)
+  ERROR_HANDLER(InvalidSegment)
+  ERROR_HANDLER(InvalidImmediate)
+  ERROR_HANDLER(OperandSizeMismatch)
+  ERROR_HANDLER(AmbiguousOperandSize)
+  ERROR_HANDLER(NotConsecutiveRegs)
+
+  #undef ERROR_HANDLER
+
+Failed:
+#ifndef ASMJIT_NO_LOGGING
+  return EmitterUtils::logInstructionFailed(this, err, instId, options, o0, o1, o2, opExt);
+#else
+  resetExtraReg();
+  resetInstOptions();
+  resetInlineComment();
+  return reportError(err);
+#endif
+}
+
+// ============================================================================
+// [asmjit::x86::Assembler - Align]
+// ============================================================================
+
+Error Assembler::align(uint32_t alignMode, uint32_t alignment) {
+  if (ASMJIT_UNLIKELY(!_code))
+    return reportError(DebugUtils::errored(kErrorNotInitialized));
+
+  if (ASMJIT_UNLIKELY(alignMode >= kAlignCount))
+    return reportError(DebugUtils::errored(kErrorInvalidArgument));
+
+  if (alignment <= 1)
+    return kErrorOk;
+
+  if (ASMJIT_UNLIKELY(!Support::isPowerOf2(alignment) || alignment > Globals::kMaxAlignment))
+    return reportError(DebugUtils::errored(kErrorInvalidArgument));
+
+  uint32_t i = uint32_t(Support::alignUpDiff<size_t>(offset(), alignment));
+  if (i > 0) {
+    CodeBufferWriter writer(this);
+    ASMJIT_PROPAGATE(writer.ensureSpace(this, i));
+
+    uint8_t pattern = 0x00;
+    switch (alignMode) {
+      case kAlignCode: {
+        if (hasEncodingOption(kEncodingOptionOptimizedAlign)) {
+          // Intel 64 and IA-32 Architectures Software Developer's Manual - Volume 2B (NOP).
+          enum { kMaxNopSize = 9 };
+
+          static const uint8_t nopData[kMaxNopSize][kMaxNopSize] = {
+            { 0x90 },
+            { 0x66, 0x90 },
+            { 0x0F, 0x1F, 0x00 },
+            { 0x0F, 0x1F, 0x40, 0x00 },
+            { 0x0F, 0x1F, 0x44, 0x00, 0x00 },
+            { 0x66, 0x0F, 0x1F, 0x44, 0x00, 0x00 },
+            { 0x0F, 0x1F, 0x80, 0x00, 0x00, 0x00, 0x00 },
+            { 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 },
+            { 0x66, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 }
+          };
+
+          do {
+            uint32_t n = Support::min<uint32_t>(i, kMaxNopSize);
+            const uint8_t* src = nopData[n - 1];
+
+            i -= n;
+            do {
+              writer.emit8(*src++);
+            } while (--n);
+          } while (i);
+        }
+
+        pattern = 0x90;
+        break;
+      }
+
+      case kAlignData:
+        pattern = 0xCC;
+        break;
+
+      case kAlignZero:
+        // Pattern already set to zero.
+        break;
+    }
+
+    while (i) {
+      writer.emit8(pattern);
+      i--;
+    }
+
+    writer.done(this);
+  }
+
+#ifndef ASMJIT_NO_LOGGING
+  if (_logger) {
+    StringTmp<128> sb;
+    sb.appendChars(' ', _logger->indentation(FormatOptions::kIndentationCode));
+    sb.appendFormat("align %u\n", alignment);
+    _logger->log(sb);
+  }
+#endif
+
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::x86::Assembler - Events]
+// ============================================================================
+
+Error Assembler::onAttach(CodeHolder* code) noexcept {
+  uint32_t arch = code->arch();
+  if (!Environment::isFamilyX86(arch))
+    return DebugUtils::errored(kErrorInvalidArch);
+
+  ASMJIT_PROPAGATE(Base::onAttach(code));
+
+  if (Environment::is32Bit(arch)) {
+    // 32 bit architecture - X86.
+    _gpRegInfo.setSignature(Gpd::kSignature);
+    _forcedInstOptions |= Inst::_kOptionInvalidRex;
+    _setAddressOverrideMask(kX86MemInfo_67H_X86);
+  }
+  else {
+    // 64 bit architecture - X64.
+    _gpRegInfo.setSignature(Gpq::kSignature);
+    _forcedInstOptions &= ~Inst::_kOptionInvalidRex;
+    _setAddressOverrideMask(kX86MemInfo_67H_X64);
+  }
+
+  return kErrorOk;
+}
+
+Error Assembler::onDetach(CodeHolder* code) noexcept {
+  _forcedInstOptions &= ~Inst::_kOptionInvalidRex;
+  _setAddressOverrideMask(0);
+
+  return Base::onDetach(code);
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86
diff --git a/client/asmjit/x86/x86assembler.h b/client/asmjit/x86/x86assembler.h
new file mode 100644
index 0000000..8cd1014
--- /dev/null
+++ b/client/asmjit/x86/x86assembler.h
@@ -0,0 +1,743 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86ASSEMBLER_H_INCLUDED
+#define ASMJIT_X86_X86ASSEMBLER_H_INCLUDED
+
+#include "../core/assembler.h"
+#include "../x86/x86emitter.h"
+#include "../x86/x86operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::Assembler]
+// ============================================================================
+
+//! X86/X64 assembler implementation.
+//!
+//! x86::Assembler is a code emitter that emits machine code directly into the
+//! \ref CodeBuffer. The assembler is capable of targeting both 32-bit and 64-bit
+//! instruction sets, the instruction set can be configured through \ref CodeHolder.
+//!
+//! ### Basics
+//!
+//! The following example shows a basic use of `x86::Assembler`, how to generate
+//! a function that works in both 32-bit and 64-bit modes, and how to connect
+//! \ref JitRuntime, \ref CodeHolder, and `x86::Assembler`.
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! #include <stdio.h>
+//!
+//! using namespace asmjit;
+//!
+//! // Signature of the generated function.
+//! typedef int (*SumFunc)(const int* arr, size_t count);
+//!
+//! int main() {
+//!   JitRuntime rt;                    // Create a runtime specialized for JIT.
+//!   CodeHolder code;                  // Create a CodeHolder.
+//!
+//!   code.init(rt.environment());      // Initialize code to match the JIT environment.
+//!   x86::Assembler a(&code);          // Create and attach x86::Assembler to code.
+//!
+//!   // Decide between 32-bit CDECL, WIN64, and SysV64 calling conventions:
+//!   //   32-BIT - passed all arguments by stack.
+//!   //   WIN64  - passes first 4 arguments by RCX, RDX, R8, and R9.
+//!   //   UNIX64 - passes first 6 arguments by RDI, RSI, RCX, RDX, R8, and R9.
+//!   x86::Gp arr, cnt;
+//!   x86::Gp sum = x86::eax;           // Use EAX as 'sum' as it's a return register.
+//!
+//!   if (ASMJIT_ARCH_BITS == 64) {
+//!   #if defined(_WIN32)
+//!     arr = x86::rcx;                 // First argument (array ptr).
+//!     cnt = x86::rdx;                 // Second argument (number of elements)
+//!   #else
+//!     arr = x86::rdi;                 // First argument (array ptr).
+//!     cnt = x86::rsi;                 // Second argument (number of elements)
+//!   #endif
+//!   }
+//!   else {
+//!     arr = x86::edx;                 // Use EDX to hold the array pointer.
+//!     cnt = x86::ecx;                 // Use ECX to hold the counter.
+//!     // Fetch first and second arguments from [ESP + 4] and [ESP + 8].
+//!     a.mov(arr, x86::ptr(x86::esp, 4));
+//!     a.mov(cnt, x86::ptr(x86::esp, 8));
+//!   }
+//!
+//!   Label Loop = a.newLabel();        // To construct the loop, we need some labels.
+//!   Label Exit = a.newLabel();
+//!
+//!   a.xor_(sum, sum);                 // Clear 'sum' register (shorter than 'mov').
+//!   a.test(cnt, cnt);                 // Border case:
+//!   a.jz(Exit);                       //   If 'cnt' is zero jump to 'Exit' now.
+//!
+//!   a.bind(Loop);                     // Start of a loop iteration.
+//!   a.add(sum, x86::dword_ptr(arr));  // Add int at [arr] to 'sum'.
+//!   a.add(arr, 4);                    // Increment 'arr' pointer.
+//!   a.dec(cnt);                       // Decrease 'cnt'.
+//!   a.jnz(Loop);                      // If not zero jump to 'Loop'.
+//!
+//!   a.bind(Exit);                     // Exit to handle the border case.
+//!   a.ret();                          // Return from function ('sum' == 'eax').
+//!   // ----> x86::Assembler is no longer needed from here and can be destroyed <----
+//!
+//!   SumFunc fn;
+//!   Error err = rt.add(&fn, &code);   // Add the generated code to the runtime.
+//!
+//!   if (err) return 1;                // Handle a possible error returned by AsmJit.
+//!   // ----> CodeHolder is no longer needed from here and can be destroyed <----
+//!
+//!   static const int array[6] = { 4, 8, 15, 16, 23, 42 };
+//!
+//!   int result = fn(array, 6);        // Execute the generated code.
+//!   printf("%d\n", result);           // Print sum of array (108).
+//!
+//!   rt.release(fn);                   // Explicitly remove the function from the runtime
+//!   return 0;                         // Everything successful...
+//! }
+//! ```
+//!
+//! The example should be self-explanatory. It shows how to work with labels,
+//! how to use operands, and how to emit instructions that can use different
+//! registers based on runtime selection. It implements 32-bit CDECL, WIN64,
+//! and SysV64 caling conventions and will work on most X86/X64 environments.
+//!
+//! Although functions prologs / epilogs can be implemented manually, AsmJit
+//! provides utilities that can be used to create function prologs and epilogs
+//! automatically, see \ref asmjit_function for more details.
+//!
+//! ### Instruction Validation
+//!
+//! Assembler prefers speed over strictness by default. The implementation checks
+//! the type of operands and fails if the signature of types is invalid, however,
+//! it does only basic checks regarding registers and their groups used in
+//! instructions. It's possible to pass operands that don't form any valid
+//! signature to the implementation and succeed. This is usually not a problem
+//! as Assembler provides typed API so operand types are normally checked by C++
+//! compiler at compile time, however, Assembler is fully dynamic and its \ref
+//! emit() function can be called with any instruction id, options, and operands.
+//! Moreover, it's also possible to form instructions that will be accepted by
+//! the typed API, for example by calling `mov(x86::eax, x86::al)` - the C++
+//! compiler won't see a problem as both EAX and AL are \ref Gp registers.
+//!
+//! To help with common mistakes AsmJit allows to activate instruction validation.
+//! This feature instruments the Assembler to call \ref InstAPI::validate() before
+//! it attempts to encode any instruction.
+//!
+//! The example below illustrates how validation can be turned on:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! #include <stdio.h>
+//!
+//! using namespace asmjit;
+//!
+//! int main(int argc, char* argv[]) {
+//!   JitRuntime rt;                    // Create a runtime specialized for JIT.
+//!   CodeHolder code;                  // Create a CodeHolder.
+//!
+//!   code.init(rt.environment());      // Initialize code to match the JIT environment.
+//!   x86::Assembler a(&code);          // Create and attach x86::Assembler to code.
+//!
+//!   // Enable strict validation.
+//!   a.addValidationOptions(BaseEmitter::kValidationOptionAssembler);
+//!
+//!   // Try to encode invalid or ill-formed instructions.
+//!   Error err;
+//!
+//!   // Invalid instruction.
+//!   err = a.mov(x86::eax, x86::al);
+//!   printf("Status: %s\n", DebugUtils::errorAsString(err));
+//!
+//!   // Invalid instruction.
+//!   err = a.emit(x86::Inst::kIdMovss, x86::eax, x86::xmm0);
+//!   printf("Status: %s\n", DebugUtils::errorAsString(err));
+//!
+//!   // Ambiguous operand size - the pointer requires size.
+//!   err = a.inc(x86::ptr(x86::rax), 1);
+//!   printf("Status: %s\n", DebugUtils::errorAsString(err));
+//!
+//!   return 0;
+//! }
+//! ```
+//!
+//! ### Native Registers
+//!
+//! All emitters provide functions to construct machine-size registers depending
+//! on the target. This feature is for users that want to write code targeting
+//! both 32-bit and 64-bit architectures at the same time. In AsmJit terminology
+//! such registers have prefix `z`, so for example on X86 architecture the
+//! following native registers are provided:
+//!
+//!   - `zax` - mapped to either `eax` or `rax`
+//!   - `zbx` - mapped to either `ebx` or `rbx`
+//!   - `zcx` - mapped to either `ecx` or `rcx`
+//!   - `zdx` - mapped to either `edx` or `rdx`
+//!   - `zsp` - mapped to either `esp` or `rsp`
+//!   - `zbp` - mapped to either `ebp` or `rbp`
+//!   - `zsi` - mapped to either `esi` or `rsi`
+//!   - `zdi` - mapped to either `edi` or `rdi`
+//!
+//! They are accessible through \ref x86::Assembler, \ref x86::Builder, and
+//! \ref x86::Compiler. The example below illustrates how to use this feature:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! #include <stdio.h>
+//!
+//! using namespace asmjit;
+//!
+//! typedef int (*Func)(void);
+//!
+//! int main(int argc, char* argv[]) {
+//!   JitRuntime rt;                    // Create a runtime specialized for JIT.
+//!   CodeHolder code;                  // Create a CodeHolder.
+//!
+//!   code.init(rt.environment());      // Initialize code to match the JIT environment.
+//!   x86::Assembler a(&code);          // Create and attach x86::Assembler to code.
+//!
+//!   // Let's get these registers from x86::Assembler.
+//!   x86::Gp zbp = a.zbp();
+//!   x86::Gp zsp = a.zsp();
+//!
+//!   int stackSize = 32;
+//!
+//!   // Function prolog.
+//!   a.push(zbp);
+//!   a.mov(zbp, zsp);
+//!   a.sub(zsp, stackSize);
+//!
+//!   // ... emit some code (this just sets return value to zero) ...
+//!   a.xor_(x86::eax, x86::eax);
+//!
+//!   // Function epilog and return.
+//!   a.mov(zsp, zbp);
+//!   a.pop(zbp);
+//!   a.ret();
+//!
+//!   // To make the example complete let's call it.
+//!   Func fn;
+//!   Error err = rt.add(&fn, &code);   // Add the generated code to the runtime.
+//!   if (err) return 1;                // Handle a possible error returned by AsmJit.
+//!
+//!   int result = fn();                // Execute the generated code.
+//!   printf("%d\n", result);           // Print the resulting "0".
+//!
+//!   rt.release(fn);                   // Remove the function from the runtime.
+//!   return 0;
+//! }
+//! ```
+//!
+//! The example just returns `0`, but the function generated contains a standard
+//! prolog and epilog sequence and the function itself reserves 32 bytes of local
+//! stack. The advantage is clear - a single code-base can handle multiple targets
+//! easily. If you want to create a register of native size dynamically by
+//! specifying its id it's also possible:
+//!
+//! ```
+//! void example(x86::Assembler& a) {
+//!   x86::Gp zax = a.gpz(x86::Gp::kIdAx);
+//!   x86::Gp zbx = a.gpz(x86::Gp::kIdBx);
+//!   x86::Gp zcx = a.gpz(x86::Gp::kIdCx);
+//!   x86::Gp zdx = a.gpz(x86::Gp::kIdDx);
+//!
+//!   // You can also change register's id easily.
+//!   x86::Gp zsp = zax;
+//!   zsp.setId(4); // or x86::Gp::kIdSp.
+//! }
+//! ```
+//!
+//! ### Data Embedding
+//!
+//! x86::Assembler extends the standard \ref BaseAssembler with X86/X64 specific
+//! conventions that are often used by assemblers to embed data next to the code.
+//! The following functions can be used to embed data:
+//!
+//!   - \ref x86::Assembler::db() - embeds byte (8 bits) (x86 naming).
+//!   - \ref x86::Assembler::dw() - embeds word (16 bits) (x86 naming).
+//!   - \ref x86::Assembler::dd() - embeds dword (32 bits) (x86 naming).
+//!   - \ref x86::Assembler::dq() - embeds qword (64 bits) (x86 naming).
+//!
+//!   - \ref BaseAssembler::embedInt8() - embeds int8_t (portable naming).
+//!   - \ref BaseAssembler::embedUInt8() - embeds uint8_t (portable naming).
+//!   - \ref BaseAssembler::embedInt16() - embeds int16_t (portable naming).
+//!   - \ref BaseAssembler::embedUInt16() - embeds uint16_t (portable naming).
+//!   - \ref BaseAssembler::embedInt32() - embeds int32_t (portable naming).
+//!   - \ref BaseAssembler::embedUInt32() - embeds uint32_t (portable naming).
+//!   - \ref BaseAssembler::embedInt64() - embeds int64_t (portable naming).
+//!   - \ref BaseAssembler::embedUInt64() - embeds uint64_t (portable naming).
+//!   - \ref BaseAssembler::embedFloat() - embeds float (portable naming).
+//!   - \ref BaseAssembler::embedDouble() - embeds double (portable naming).
+//!
+//! The following example illustrates how embed works:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! using namespace asmjit;
+//!
+//! void embedData(x86::Assembler& a) {
+//!   a.db(0xFF);         // Embeds 0xFF byte.
+//!   a.dw(0xFF00);       // Embeds 0xFF00 word (little-endian).
+//!   a.dd(0xFF000000);   // Embeds 0xFF000000 dword (little-endian).
+//!   a.embedFloat(0.4f); // Embeds 0.4f (32-bit float, little-endian).
+//! }
+//! ```
+//!
+//! Sometimes it's required to read the data that is embedded after code, for
+//! example. This can be done through \ref Label as shown below:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! using namespace asmjit;
+//!
+//! void embedData(x86::Assembler& a, const Label& L_Data) {
+//!   x86::Gp addr = a.zax();  // EAX or RAX.
+//!   x86::Gp val = x86::edi;  // Where to store some value...
+//!
+//!   // Approach 1 - Load the address to register through LEA. This approach
+//!   //              is flexible as the address can be then manipulated, for
+//!   //              example if you have a data array, which would need index.
+//!   a.lea(addr, L_Data);     // Loads the address of the label to EAX or RAX.
+//!   a.mov(val, dword_ptr(addr));
+//!
+//!   // Approach 2 - Load the data directly by using L_Data in address. It's
+//!   //              worth noting that this doesn't work with indexes in X64
+//!   //              mode. It will use absolute address in 32-bit mode and
+//!   //              relative address (RIP) in 64-bit mode.
+//!   a.mov(val, dword_ptr(L_Data));
+//! }
+//! ```
+//!
+//! ### Label Embedding
+//!
+//! It's also possible to embed labels. In general AsmJit provides the following
+//! options:
+//!
+//!   - \ref BaseEmitter::embedLabel() - Embeds absolute address of a label.
+//!     This is target dependent and would embed either 32-bit or 64-bit data
+//!     that embeds absolute label address. This kind of embedding cannot be
+//!     used in a position independent code.
+//!
+//!   - \ref BaseEmitter::embedLabelDelta() - Embeds a difference between two
+//!     labels. The size of the difference can be specified so it's possible to
+//!     embed 8-bit, 16-bit, 32-bit, and 64-bit difference, which is sufficient
+//!     for most purposes.
+//!
+//! The following example demonstrates how to embed labels and their differences:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! using namespace asmjit;
+//!
+//! void embedLabel(x86::Assembler& a, const Label& L_Data) {
+//!   // [1] Embed L_Data - the size of the data will be dependent on the target.
+//!   a.embedLabel(L_Data);
+//!
+//!   // [2] Embed a 32-bit difference of two labels.
+//!   Label L_Here = a.newLabel();
+//!   a.bind(L_Here);
+//!   // Embeds int32_t(L_Data - L_Here).
+//!   a.embedLabelDelta(L_Data, L_Here, 4);
+//! }
+//! ```
+//!
+//! ### Using FuncFrame and FuncDetail with x86::Assembler
+//!
+//! The example below demonstrates how \ref FuncFrame and \ref FuncDetail can be
+//! used together with \ref x86::Assembler to generate a function that will use
+//! platform dependent calling conventions automatically depending on the target:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! #include <stdio.h>
+//!
+//! using namespace asmjit;
+//!
+//! typedef void (*SumIntsFunc)(int* dst, const int* a, const int* b);
+//!
+//! int main(int argc, char* argv[]) {
+//!   JitRuntime rt;                    // Create JIT Runtime.
+//!   CodeHolder code;                  // Create a CodeHolder.
+//!
+//!   code.init(rt.environment());      // Initialize code to match the JIT environment.
+//!   x86::Assembler a(&code);          // Create and attach x86::Assembler to code.
+//!
+//!   // Decide which registers will be mapped to function arguments. Try changing
+//!   // registers of dst, src_a, and src_b and see what happens in function's
+//!   // prolog and epilog.
+//!   x86::Gp dst   = a.zax();
+//!   x86::Gp src_a = a.zcx();
+//!   x86::Gp src_b = a.zdx();
+//!
+//!   X86::Xmm vec0 = x86::xmm0;
+//!   X86::Xmm vec1 = x86::xmm1;
+//!
+//!   // Create/initialize FuncDetail and FuncFrame.
+//!   FuncDetail func;
+//!   func.init(FuncSignatureT<void, int*, const int*, const int*>(CallConv::kIdHost));
+//!
+//!   FuncFrame frame;
+//!   frame.init(func);
+//!
+//!   // Make XMM0 and XMM1 dirty - kGroupVec describes XMM|YMM|ZMM registers.
+//!   frame.setDirtyRegs(x86::Reg::kGroupVec, IntUtils::mask(0, 1));
+//!
+//!   // Alternatively, if you don't want to use register masks you can pass BaseReg
+//!   // to addDirtyRegs(). The following code would add both xmm0 and xmm1.
+//!   frame.addDirtyRegs(x86::xmm0, x86::xmm1);
+//!
+//!   FuncArgsAssignment args(&func);   // Create arguments assignment context.
+//!   args.assignAll(dst, src_a, src_b);// Assign our registers to arguments.
+//!   args.updateFrameInfo(frame);      // Reflect our args in FuncFrame.
+//!   frame.finalize();                 // Finalize the FuncFrame (updates it).
+//!
+//!   a.emitProlog(frame);              // Emit function prolog.
+//!   a.emitArgsAssignment(frame, args);// Assign arguments to registers.
+//!   a.movdqu(vec0, x86::ptr(src_a));  // Load 4 ints from [src_a] to XMM0.
+//!   a.movdqu(vec1, x86::ptr(src_b));  // Load 4 ints from [src_b] to XMM1.
+//!   a.paddd(vec0, vec1);              // Add 4 ints in XMM1 to XMM0.
+//!   a.movdqu(x86::ptr(dst), vec0);    // Store the result to [dst].
+//!   a.emitEpilog(frame);              // Emit function epilog and return.
+//!
+//!   SumIntsFunc fn;
+//!   Error err = rt.add(&fn, &code);   // Add the generated code to the runtime.
+//!   if (err) return 1;                // Handle a possible error case.
+//!
+//!   // Execute the generated function.
+//!   int inA[4] = { 4, 3, 2, 1 };
+//!   int inB[4] = { 1, 5, 2, 8 };
+//!   int out[4];
+//!   fn(out, inA, inB);
+//!
+//!   // Prints {5 8 4 9}
+//!   printf("{%d %d %d %d}\n", out[0], out[1], out[2], out[3]);
+//!
+//!   rt.release(fn);
+//!   return 0;
+//! }
+//! ```
+//!
+//! ### Using x86::Assembler as Code-Patcher
+//!
+//! This is an advanced topic that is sometimes unavoidable. AsmJit by default
+//! appends machine code it generates into a \ref CodeBuffer, however, it also
+//! allows to set the offset in \ref CodeBuffer explicitly and to overwrite its
+//! content. This technique is extremely dangerous as X86 instructions have
+//! variable length (see below), so you should in general only patch code to
+//! change instruction's immediate values or some other details not known the
+//! at a time the instruction was emitted. A typical scenario that requires
+//! code-patching is when you start emitting function and you don't know how
+//! much stack you want to reserve for it.
+//!
+//! Before we go further it's important to introduce instruction options, because
+//! they can help with code-patching (and not only patching, but that will be
+//! explained in AVX-512 section):
+//!
+//!   - Many general-purpose instructions (especially arithmetic ones) on X86
+//!     have multiple encodings - in AsmJit this is usually called 'short form'
+//!     and 'long form'.
+//!   - AsmJit always tries to use 'short form' as it makes the resulting
+//!     machine-code smaller, which is always good - this decision is used
+//!     by majority of assemblers out there.
+//!   - AsmJit allows to override the default decision by using `short_()`
+//!     and `long_()` instruction options to force short or long form,
+//!     respectively. The most useful is `long_()` as it basically forces
+//!     AsmJit to always emit the longest form. The `short_()` is not that
+//!     useful as it's automatic (except jumps to non-bound labels). Note that
+//!     the underscore after each function name avoids collision with built-in
+//!     C++ types.
+//!
+//! To illustrate what short form and long form means in binary let's assume
+//! we want to emit "add esp, 16" instruction, which has two possible binary
+//! encodings:
+//!
+//!   - `83C410` - This is a short form aka `short add esp, 16` - You can see
+//!     opcode byte (0x8C), MOD/RM byte (0xC4) and an 8-bit immediate value
+//!     representing `16`.
+//!   - `81C410000000` - This is a long form aka `long add esp, 16` - You can
+//!     see a different opcode byte (0x81), the same Mod/RM byte (0xC4) and a
+//!     32-bit immediate in little-endian representing `16`.
+//!
+//! It should be obvious that patching an existing instruction into an instruction
+//! having a different size may create various problems. So it's recommended to be
+//! careful and to only patch instructions into instructions having the same size.
+//! The example below demonstrates how instruction options can be used to guarantee
+//! the size of an instruction by forcing the assembler to use long-form encoding:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! #include <stdio.h>
+//!
+//! using namespace asmjit;
+//!
+//! typedef int (*Func)(void);
+//!
+//! int main(int argc, char* argv[]) {
+//!   JitRuntime rt;                    // Create a runtime specialized for JIT.
+//!   CodeHolder code;                  // Create a CodeHolder.
+//!
+//!   code.init(rt.environment());      // Initialize code to match the JIT environment.
+//!   x86::Assembler a(&code);          // Create and attach x86::Assembler to code.
+//!
+//!   // Let's get these registers from x86::Assembler.
+//!   x86::Gp zbp = a.zbp();
+//!   x86::Gp zsp = a.zsp();
+//!
+//!   // Function prolog.
+//!   a.push(zbp);
+//!   a.mov(zbp, zsp);
+//!
+//!   // This is where we are gonna patch the code later, so let's get the offset
+//!   // (the current location) from the beginning of the code-buffer.
+//!   size_t patchOffset = a.offset();
+//!   // Let's just emit 'sub zsp, 0' for now, but don't forget to use LONG form.
+//!   a.long_().sub(zsp, 0);
+//!
+//!   // ... emit some code (this just sets return value to zero) ...
+//!   a.xor_(x86::eax, x86::eax);
+//!
+//!   // Function epilog and return.
+//!   a.mov(zsp, zbp);
+//!   a.pop(zbp);
+//!   a.ret();
+//!
+//!   // Now we know how much stack size we want to reserve. I have chosen 128
+//!   // bytes on purpose as it's encodable only in long form that we have used.
+//!
+//!   int stackSize = 128;              // Number of bytes to reserve on the stack.
+//!   a.setOffset(patchOffset);         // Move the current cursor to `patchOffset`.
+//!   a.long_().sub(zsp, stackSize);    // Patch the code; don't forget to use LONG form.
+//!
+//!   // Now the code is ready to be called
+//!   Func fn;
+//!   Error err = rt.add(&fn, &code);   // Add the generated code to the runtime.
+//!   if (err) return 1;                // Handle a possible error returned by AsmJit.
+//!
+//!   int result = fn();                // Execute the generated code.
+//!   printf("%d\n", result);           // Print the resulting "0".
+//!
+//!   rt.release(fn);                   // Remove the function from the runtime.
+//!   return 0;
+//! }
+//! ```
+//!
+//! If you run the example it will just work, because both instructions have
+//! the same size. As an experiment you can try removing `long_()` form to
+//! see what happens when wrong code is generated.
+//!
+//! ### Code Patching and REX Prefix
+//!
+//! In 64-bit mode there is one more thing to worry about when patching code:
+//! REX prefix. It's a single byte prefix designed to address registers with
+//! ids from 9 to 15 and to override the default width of operation from 32
+//! to 64 bits. AsmJit, like other assemblers, only emits REX prefix when it's
+//! necessary. If the patched code only changes the immediate value as shown
+//! in the previous example then there is nothing to worry about as it doesn't
+//! change the logic behind emitting REX prefix, however, if the patched code
+//! changes register id or overrides the operation width then it's important
+//! to take care of REX prefix as well.
+//!
+//! AsmJit contains another instruction option that controls (forces) REX
+//! prefix - `rex()`. If you use it the instruction emitted will always use
+//! REX prefix even when it's encodable without it. The following list contains
+//! some instructions and their binary representations to illustrate when it's
+//! emitted:
+//!
+//!   - `__83C410` - `add esp, 16`     - 32-bit operation in 64-bit mode doesn't require REX prefix.
+//!   - `4083C410` - `rex add esp, 16` - 32-bit operation in 64-bit mode with forced REX prefix (0x40).
+//!   - `4883C410` - `add rsp, 16`     - 64-bit operation in 64-bit mode requires REX prefix (0x48).
+//!   - `4183C410` - `add r12d, 16`    - 32-bit operation in 64-bit mode using R12D requires REX prefix (0x41).
+//!   - `4983C410` - `add r12, 16`     - 64-bit operation in 64-bit mode using R12 requires REX prefix (0x49).
+//!
+//! ### More Prefixes
+//!
+//! X86 architecture is known for its prefixes. AsmJit supports all prefixes
+//! that can affect how the instruction is encoded:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//!
+//! using namespace asmjit;
+//!
+//! void prefixesExample(x86::Assembler& a) {
+//!   // Lock prefix for implementing atomics:
+//!   //   lock add dword ptr [dst], 1
+//!   a.lock().add(x86::dword_ptr(dst), 1);
+//!
+//!   // Similarly, XAcquire/XRelease prefixes are also available:
+//!   //   xacquire add dword ptr [dst], 1
+//!   a.xacquire().add(x86::dword_ptr(dst), 1);
+//!
+//!   // Rep prefix (see also repe/repz and repne/repnz):
+//!   //   rep movs byte ptr [dst], byte ptr [src]
+//!   a.rep().movs(x86::byte_ptr(dst), x86::byte_ptr(src));
+//!
+//!   // Forcing REX prefix in 64-bit mode.
+//!   //   rex mov eax, 1
+//!   a.rex().mov(x86::eax, 1);
+//!
+//!   // AVX instruction without forced prefix uses the shortest encoding:
+//!   //   vaddpd xmm0, xmm1, xmm2 -> [C5|F1|58|C2]
+//!   a.vaddpd(x86::xmm0, x86::xmm1, x86::xmm2);
+//!
+//!   // Forcing VEX3 prefix (AVX):
+//!   //   vex3 vaddpd xmm0, xmm1, xmm2 -> [C4|E1|71|58|C2]
+//!   a.vex3().vaddpd(x86::xmm0, x86::xmm1, x86::xmm2);
+//!
+//!   // Forcing EVEX prefix (AVX512):
+//!   //   evex vaddpd xmm0, xmm1, xmm2 -> [62|F1|F5|08|58|C2]
+//!   a.evex().vaddpd(x86::xmm0, x86::xmm1, x86::xmm2);
+//!
+//!   // Some instructions accept prefixes not originally intended to:
+//!   //   rep ret
+//!   a.rep().ret();
+//! }
+//! ```
+//!
+//! It's important to understand that prefixes are part of instruction options.
+//! When a member function that involves adding a prefix is called the prefix
+//! is combined with existing instruction options, which will affect the next
+//! instruction generated.
+//!
+//! ### Generating AVX512 code.
+//!
+//! x86::Assembler can generate AVX512+ code including the use of opmask
+//! registers. Opmask can be specified through \ref x86::Assembler::k()
+//! function, which stores it as an extra register, which will be used
+//! by the next instruction. AsmJit uses such concept for manipulating
+//! instruction options as well.
+//!
+//! The following AVX512 features are supported:
+//!
+//!   - Opmask selector {k} and zeroing {z}.
+//!   - Rounding modes {rn|rd|ru|rz} and suppress-all-exceptions {sae} option.
+//!   - AVX512 broadcasts {1toN}.
+//!
+//! The following example demonstrates how AVX512 features can be used:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//!
+//! using namespace asmjit;
+//!
+//! void generateAVX512Code(x86::Assembler& a) {
+//!   using namespace x86;
+//!
+//!   // Opmask Selectors
+//!   // ----------------
+//!   //
+//!   //   - Opmask / zeroing is part of the instruction options / extraReg.
+//!   //   - k(reg) is like {kreg} in Intel syntax.
+//!   //   - z() is like {z} in Intel syntax.
+//!
+//!   // vaddpd zmm {k1} {z}, zmm1, zmm2
+//!   a.k(k1).z().vaddpd(zmm0, zmm1, zmm2);
+//!
+//!   // Memory Broadcasts
+//!   // -----------------
+//!   //
+//!   //   - Broadcast data is part of memory operand.
+//!   //   - Use x86::Mem::_1toN(), which returns a new x86::Mem operand.
+//!
+//!   // vaddpd zmm0 {k1} {z}, zmm1, [rcx] {1to8}
+//!   a.k(k1).z().vaddpd(zmm0, zmm1, x86::mem(rcx)._1to8());
+//!
+//!   // Embedded Rounding & Suppress-All-Exceptoins
+//!   // -------------------------------------------
+//!   //
+//!   //   - Rounding mode and {sae} are part of instruction options.
+//!   //   - Use sae() to enable exception suppression.
+//!   //   - Use rn_sae(), rd_sae(), ru_sae(), and rz_sae() - to enable rounding.
+//!   //   - Embedded rounding implicitly sets {sae} as well, that's why the API
+//!   //     also has sae() suffix, to make it clear.
+//!
+//!   // vcmppd k1, zmm1, zmm2, 0x00 {sae}
+//!   a.sae().vcmppd(k1, zmm1, zmm2, 0);
+//!
+//!   // vaddpd zmm0, zmm1, zmm2 {rz}
+//!   a.rz_sae().vaddpd(zmm0, zmm1, zmm2);
+//! }
+//! ```
+class ASMJIT_VIRTAPI Assembler
+  : public BaseAssembler,
+    public EmitterImplicitT<Assembler> {
+public:
+  ASMJIT_NONCOPYABLE(Assembler)
+  typedef BaseAssembler Base;
+
+  //! \name Construction & Destruction
+  //! \{
+
+  ASMJIT_API explicit Assembler(CodeHolder* code = nullptr) noexcept;
+  ASMJIT_API virtual ~Assembler() noexcept;
+
+  //! \}
+
+  //! \cond INTERNAL
+  //! \name Internal
+  //! \{
+
+  // NOTE: x86::Assembler uses _privateData to store 'address-override' bit that
+  // is used to decide whether to emit address-override (67H) prefix based on
+  // the memory BASE+INDEX registers. It's either `kX86MemInfo_67H_X86` or
+  // `kX86MemInfo_67H_X64`.
+  inline uint32_t _addressOverrideMask() const noexcept { return _privateData; }
+  inline void _setAddressOverrideMask(uint32_t m) noexcept { _privateData = m; }
+
+  //! \}
+  //! \endcond
+
+  //! \name Emit
+  //! \{
+
+  ASMJIT_API Error _emit(uint32_t instId, const Operand_& o0, const Operand_& o1, const Operand_& o2, const Operand_* opExt) override;
+
+  //! \}
+  //! \endcond
+
+  //! \name Align
+  //! \{
+
+  ASMJIT_API Error align(uint32_t alignMode, uint32_t alignment) override;
+
+  //! \}
+
+  //! \name Events
+  //! \{
+
+  ASMJIT_API Error onAttach(CodeHolder* code) noexcept override;
+  ASMJIT_API Error onDetach(CodeHolder* code) noexcept override;
+
+  //! \}
+};
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86ASSEMBLER_H_INCLUDED
diff --git a/client/asmjit/x86/x86builder.cpp b/client/asmjit/x86/x86builder.cpp
new file mode 100644
index 0000000..8f9c63c
--- /dev/null
+++ b/client/asmjit/x86/x86builder.cpp
@@ -0,0 +1,71 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#include "../core/api-build_p.h"
+#if defined(ASMJIT_BUILD_X86) && !defined(ASMJIT_NO_BUILDER)
+
+#include "../x86/x86assembler.h"
+#include "../x86/x86builder.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::x86::Builder - Construction / Destruction]
+// ============================================================================
+
+Builder::Builder(CodeHolder* code) noexcept : BaseBuilder() {
+  if (code)
+    code->attach(this);
+}
+Builder::~Builder() noexcept {}
+
+// ============================================================================
+// [asmjit::x86::Builder - Finalize]
+// ============================================================================
+
+Error Builder::finalize() {
+  ASMJIT_PROPAGATE(runPasses());
+  Assembler a(_code);
+  a.addEncodingOptions(encodingOptions());
+  a.addValidationOptions(validationOptions());
+  return serializeTo(&a);
+}
+
+// ============================================================================
+// [asmjit::x86::Builder - Events]
+// ============================================================================
+
+Error Builder::onAttach(CodeHolder* code) noexcept {
+  uint32_t arch = code->arch();
+  if (!Environment::isFamilyX86(arch))
+    return DebugUtils::errored(kErrorInvalidArch);
+
+  ASMJIT_PROPAGATE(Base::onAttach(code));
+
+  _gpRegInfo.setSignature(Environment::is32Bit(arch) ? uint32_t(Gpd::kSignature) : uint32_t(Gpq::kSignature));
+  return kErrorOk;
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86 && !ASMJIT_NO_BUILDER
diff --git a/client/asmjit/x86/x86builder.h b/client/asmjit/x86/x86builder.h
new file mode 100644
index 0000000..256bc9e
--- /dev/null
+++ b/client/asmjit/x86/x86builder.h
@@ -0,0 +1,387 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86BUILDER_H_INCLUDED
+#define ASMJIT_X86_X86BUILDER_H_INCLUDED
+
+#include "../core/api-config.h"
+#ifndef ASMJIT_NO_BUILDER
+
+#include "../core/builder.h"
+#include "../core/datatypes.h"
+#include "../x86/x86emitter.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::x86::Builder]
+// ============================================================================
+
+//! X86/X64 builder implementation.
+//!
+//! The code representation used by \ref BaseBuilder is compatible with everything
+//! AsmJit provides. Each instruction is stored as \ref InstNode, which contains
+//! instruction id, options, and operands. Each instruction emitted will create
+//! a new \ref InstNode instance and add it to the current cursor in the double-linked
+//! list of nodes. Since the instruction stream used by \ref BaseBuilder can be
+//! manipulated, we can rewrite the SumInts example from \ref asmjit_assembler
+//! into the following:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! #include <stdio.h>
+//!
+//! using namespace asmjit;
+//!
+//! typedef void (*SumIntsFunc)(int* dst, const int* a, const int* b);
+//!
+//! // Small helper function to print the current content of `cb`.
+//! static void dumpCode(BaseBuilder& builder, const char* phase) {
+//!   String sb;
+//!   builder.dump(sb);
+//!   printf("%s:\n%s\n", phase, sb.data());
+//! }
+//!
+//! int main() {
+//!   JitRuntime rt;                    // Create JIT Runtime.
+//!   CodeHolder code;                  // Create a CodeHolder.
+//!
+//!   code.init(rt.environment());      // Initialize code to match the JIT environment.
+//!   x86::Builder cb(&code);           // Create and attach x86::Builder to `code`.
+//!
+//!   // Decide which registers will be mapped to function arguments. Try changing
+//!   // registers of `dst`, `srcA`, and `srcB` and see what happens in function's
+//!   // prolog and epilog.
+//!   x86::Gp dst = cb.zax();
+//!   x86::Gp srcA = cb.zcx();
+//!   x86::Gp srcB = cb.zdx();
+//!
+//!   X86::Xmm vec0 = x86::xmm0;
+//!   X86::Xmm vec1 = x86::xmm1;
+//!
+//!   // Create and initialize `FuncDetail`.
+//!   FuncDetail func;
+//!   func.init(FuncSignatureT<void, int*, const int*, const int*>(CallConv::kIdHost));
+//!
+//!   // Remember prolog insertion point.
+//!   BaseNode* prologInsertionPoint = cb.cursor();
+//!
+//!   // Emit function body:
+//!   cb.movdqu(vec0, x86::ptr(srcA));  // Load 4 ints from [srcA] to XMM0.
+//!   cb.movdqu(vec1, x86::ptr(srcB));  // Load 4 ints from [srcB] to XMM1.
+//!   cb.paddd(vec0, vec1);             // Add 4 ints in XMM1 to XMM0.
+//!   cb.movdqu(x86::ptr(dst), vec0);   // Store the result to [dst].
+//!
+//!   // Remember epilog insertion point.
+//!   BaseNode* epilogInsertionPoint = cb.cursor();
+//!
+//!   // Let's see what we have now.
+//!   dumpCode(cb, "Raw Function");
+//!
+//!   // Now, after we emitted the function body, we can insert the prolog, arguments
+//!   // allocation, and epilog. This is not possible with using pure x86::Assembler.
+//!   FuncFrame frame;
+//!   frame.init(func);
+//!
+//!   // Make XMM0 and XMM1 dirty; `kGroupVec` describes XMM|YMM|ZMM registers.
+//!   frame.setDirtyRegs(x86::Reg::kGroupVec, IntUtils::mask(0, 1));
+//!
+//!   FuncArgsAssignment args(&func);   // Create arguments assignment context.
+//!   args.assignAll(dst, srcA, srcB);  // Assign our registers to arguments.
+//!   args.updateFrame(frame);          // Reflect our args in FuncFrame.
+//!   frame.finalize();                 // Finalize the FuncFrame (updates it).
+//!
+//!   // Insert function prolog and allocate arguments to registers.
+//!   cb.setCursor(prologInsertionPoint);
+//!   cb.emitProlog(frame);
+//!   cb.emitArgsAssignment(frame, args);
+//!
+//!   // Insert function epilog.
+//!   cb.setCursor(epilogInsertionPoint);
+//!   cb.emitEpilog(frame);
+//!
+//!   // Let's see how the function's prolog and epilog looks.
+//!   dumpCode(cb, "Prolog & Epilog");
+//!
+//!   // IMPORTANT: Builder requires finalize() to be called to serialize its
+//!   // code to the Assembler (it automatically creates one if not attached).
+//!   cb.finalize();
+//!
+//!   SumIntsFunc fn;
+//!   Error err = rt.add(&fn, &code);   // Add the generated code to the runtime.
+//!   if (err) return 1;                // Handle a possible error case.
+//!
+//!   // Execute the generated function.
+//!   int inA[4] = { 4, 3, 2, 1 };
+//!   int inB[4] = { 1, 5, 2, 8 };
+//!   int out[4];
+//!   fn(out, inA, inB);
+//!
+//!   // Prints {5 8 4 9}
+//!   printf("{%d %d %d %d}\n", out[0], out[1], out[2], out[3]);
+//!
+//!   rt.release(fn);                   // Explicitly remove the function from the runtime.
+//!   return 0;
+//! }
+//! ```
+//!
+//! When the example is executed it should output the following (this one using
+//! AMD64-SystemV ABI):
+//!
+//! ```
+//! Raw Function:
+//! movdqu xmm0, [rcx]
+//! movdqu xmm1, [rdx]
+//! paddd xmm0, xmm1
+//! movdqu [rax], xmm0
+//!
+//! Prolog & Epilog:
+//! mov rax, rdi
+//! mov rcx, rsi
+//! movdqu xmm0, [rcx]
+//! movdqu xmm1, [rdx]
+//! paddd xmm0, xmm1
+//! movdqu [rax], xmm0
+//! ret
+//!
+//! {5 8 4 9}
+//! ```
+//!
+//! The number of use-cases of \ref BaseBuilder is not limited and highly depends
+//! on your creativity and experience. The previous example can be easily improved
+//! to collect all dirty registers inside the function programmatically and to pass
+//! them to \ref FuncFrame::setDirtyRegs().
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//!
+//! using namespace asmjit;
+//!
+//! // NOTE: This function doesn't cover all possible constructs. It ignores
+//! // instructions that write to implicit registers that are not part of the
+//! // operand list. It also counts read-only registers. Real implementation
+//! // would be a bit more complicated, but still relatively easy to implement.
+//! static void collectDirtyRegs(const BaseNode* first,
+//!                              const BaseNode* last,
+//!                              uint32_t regMask[BaseReg::kGroupVirt]) {
+//!   const BaseNode* node = first;
+//!   while (node) {
+//!     if (node->actsAsInst()) {
+//!       const InstNode* inst = node->as<InstNode>();
+//!       const Operand* opArray = inst->operands();
+//!
+//!       for (uint32_t i = 0, opCount = inst->opCount(); i < opCount; i++) {
+//!         const Operand& op = opArray[i];
+//!         if (op.isReg()) {
+//!           const x86::Reg& reg = op.as<x86::Reg>();
+//!           if (reg.group() < BaseReg::kGroupVirt) {
+//!             regMask[reg.group()] |= 1u << reg.id();
+//!           }
+//!         }
+//!       }
+//!     }
+//!
+//!     if (node == last)
+//!       break;
+//!     node = node->next();
+//!   }
+//! }
+//!
+//! static void setDirtyRegsOfFuncFrame(const x86::Builder& builder, FuncFrame& frame) {
+//!   uint32_t regMask[BaseReg::kGroupVirt] {};
+//!   collectDirtyRegs(builder.firstNode(), builder.lastNode(), regMask);
+//!
+//!   // X86/X64 ABIs only require to save GP/XMM registers:
+//!   frame.setDirtyRegs(x86::Reg::kGroupGp , regMask[x86::Reg::kGroupGp ]);
+//!   frame.setDirtyRegs(x86::Reg::kGroupVec, regMask[x86::Reg::kGroupVec]);
+//! }
+//! ```
+//!
+//! ### Casting Between Various Emitters
+//!
+//! Even when \ref BaseAssembler and \ref BaseBuilder provide the same interface
+//! as defined by \ref BaseEmitter their platform dependent variants like \ref
+//! x86::Assembler and \ref x86::Builder cannot be interchanged or casted
+//! to each other by using a C++ `static_cast<>`. The main reason is the
+//! inheritance graph of these classes is different and cast-incompatible, as
+//! illustrated below:
+//!
+//! ```
+//!                                             +--------------+      +=========================+
+//!                    +----------------------->| x86::Emitter |<--+--# x86::EmitterImplicitT<> #<--+
+//!                    |                        +--------------+   |  +=========================+   |
+//!                    |                           (abstract)      |           (mixin)              |
+//!                    |   +--------------+     +~~~~~~~~~~~~~~+   |                                |
+//!                    +-->| BaseAssembler|---->|x86::Assembler|<--+                                |
+//!                    |   +--------------+     +~~~~~~~~~~~~~~+   |                                |
+//!                    |      (abstract)            (final)        |                                |
+//! +===============+  |   +--------------+     +~~~~~~~~~~~~~~+   |                                |
+//! #  BaseEmitter  #--+-->|  BaseBuilder |--+->| x86::Builder |<--+                                |
+//! +===============+      +--------------+  |  +~~~~~~~~~~~~~~+                                    |
+//!    (abstract)             (abstract)     |      (final)                                         |
+//!                    +---------------------+                                                      |
+//!                    |                                                                            |
+//!                    |   +--------------+     +~~~~~~~~~~~~~~+      +=========================+   |
+//!                    +-->| BaseCompiler |---->| x86::Compiler|<-----# x86::EmitterExplicitT<> #---+
+//!                        +--------------+     +~~~~~~~~~~~~~~+      +=========================+
+//!                           (abstract)            (final)                   (mixin)
+//! ```
+//!
+//! The graph basically shows that it's not possible to cast between \ref
+//! x86::Assembler and \ref x86::Builder. However, since both share the
+//! base interface (\ref BaseEmitter) it's possible to cast them to a class
+//! that cannot be instantiated, but defines the same interface - the class
+//! is called \ref x86::Emitter and was introduced to make it possible to
+//! write a function that can emit to both \ref x86::Assembler and \ref
+//! x86::Builder. Note that \ref x86::Emitter cannot be created, it's abstract
+//! and has private constructors and destructors; it was only designed to be
+//! casted to and used as an interface.
+//!
+//! Each architecture-specific emitter implements a member function called
+//! `as<arch::Emitter>()`, which casts the instance to the architecture
+//! specific emitter as illustrated below:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//!
+//! using namespace asmjit;
+//!
+//! static void emitSomething(x86::Emitter* e) {
+//!   e->mov(x86::eax, x86::ebx);
+//! }
+//!
+//! static void assemble(CodeHolder& code, bool useAsm) {
+//!   if (useAsm) {
+//!     x86::Assembler assembler(&code);
+//!     emitSomething(assembler.as<x86::Emitter>());
+//!   }
+//!   else {
+//!     x86::Builder builder(&code);
+//!     emitSomething(builder.as<x86::Emitter>());
+//!
+//!     // NOTE: Builder requires `finalize()` to be called to serialize its
+//!     // content to Assembler (it automatically creates one if not attached).
+//!     builder.finalize();
+//!   }
+//! }
+//! ```
+//!
+//! The example above shows how to create a function that can emit code to
+//! either \ref x86::Assembler or \ref x86::Builder through \ref x86::Emitter,
+//! which provides emitter-neutral functionality. \ref x86::Emitter, however,
+//! doesn't provide any emitter-specific functionality like `setCursor()`.
+//!
+//! ### Code Injection and Manipulation
+//!
+//! \ref BaseBuilder emitter stores its nodes in a double-linked list, which
+//! makes it easy to manipulate that list during the code generation or
+//! afterwards. Each node is always emitted next to the current cursor and the
+//! cursor is advanced to that newly emitted node. The cursor can be retrieved
+//! and changed by \ref BaseBuilder::cursor() and \ref BaseBuilder::setCursor(),
+//! respectively.
+//!
+//! The example below demonstrates how to remember a node and inject something
+//! next to it.
+//!
+//! ```
+//! static void example(x86::Builder& builder) {
+//!   // Emit something, after it returns the cursor would point at the last
+//!   // emitted node.
+//!   builder.mov(x86::rax, x86::rdx); // [1]
+//!
+//!   // We can retrieve the node.
+//!   BaseNode* node = builder.cursor();
+//!
+//!   // Change the instruction we just emitted, just for fun...
+//!   if (node->isInst()) {
+//!     InstNode* inst = node->as<InstNode>();
+//!     // Changes the operands at index [1] to RCX.
+//!     inst->setOp(1, x86::rcx);
+//!   }
+//!
+//!   // ------------------------- Generate Some Code -------------------------
+//!   builder.add(x86::rax, x86::rdx); // [2]
+//!   builder.shr(x86::rax, 3);        // [3]
+//!   // ----------------------------------------------------------------------
+//!
+//!   // Now, we know where our node is, and we can simply change the cursor
+//!   // and start emitting something after it. The setCursor() function
+//!   // returns the previous cursor, and it's always a good practice to remember
+//!   // it, because you never know if you are not already injecting the code
+//!   // somewhere else...
+//!   BaseNode* oldCursor = builder.setCursor(node);
+//!
+//!   builder.mul(x86::rax, 8);        // [4]
+//!
+//!   // Restore the cursor
+//!   builder.setCursor(oldCursor);
+//! }
+//! ```
+//!
+//! The function above would actually emit the following:
+//!
+//! ```
+//! mov rax, rcx ; [1] Patched at the beginning.
+//! mul rax, 8   ; [4] Injected.
+//! add rax, rdx ; [2] Followed [1] initially.
+//! shr rax, 3   ; [3] Follows [2].
+//! ```
+class ASMJIT_VIRTAPI Builder
+  : public BaseBuilder,
+    public EmitterImplicitT<Builder> {
+public:
+  ASMJIT_NONCOPYABLE(Builder)
+  typedef BaseBuilder Base;
+
+  //! \name Construction & Destruction
+  //! \{
+
+  ASMJIT_API explicit Builder(CodeHolder* code = nullptr) noexcept;
+  ASMJIT_API virtual ~Builder() noexcept;
+
+  //! \}
+
+  //! \name Finalize
+  //! \{
+
+  ASMJIT_API Error finalize() override;
+
+  //! \}
+
+  //! \name Events
+  //! \{
+
+  ASMJIT_API Error onAttach(CodeHolder* code) noexcept override;
+
+  //! \}
+};
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_BUILDER
+#endif // ASMJIT_X86_X86BUILDER_H_INCLUDED
diff --git a/client/asmjit/x86/x86callconv.cpp b/client/asmjit/x86/x86callconv.cpp
new file mode 100644
index 0000000..e0a3f21
--- /dev/null
+++ b/client/asmjit/x86/x86callconv.cpp
@@ -0,0 +1,238 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#include "../core/api-build_p.h"
+#ifdef ASMJIT_BUILD_X86
+
+#include "../x86/x86callconv_p.h"
+#include "../x86/x86operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::x86::CallConvInternal - Init]
+// ============================================================================
+
+namespace CallConvInternal {
+
+static inline bool shouldThreatAsCDeclIn64BitMode(uint32_t ccId) noexcept {
+  return ccId == CallConv::kIdCDecl ||
+         ccId == CallConv::kIdStdCall ||
+         ccId == CallConv::kIdThisCall ||
+         ccId == CallConv::kIdFastCall ||
+         ccId == CallConv::kIdRegParm1 ||
+         ccId == CallConv::kIdRegParm2 ||
+         ccId == CallConv::kIdRegParm3;
+}
+
+ASMJIT_FAVOR_SIZE Error init(CallConv& cc, uint32_t ccId, const Environment& environment) noexcept {
+  constexpr uint32_t kGroupGp   = Reg::kGroupGp;
+  constexpr uint32_t kGroupVec  = Reg::kGroupVec;
+  constexpr uint32_t kGroupMm   = Reg::kGroupMm;
+  constexpr uint32_t kGroupKReg = Reg::kGroupKReg;
+
+  constexpr uint32_t kZax = Gp::kIdAx;
+  constexpr uint32_t kZbx = Gp::kIdBx;
+  constexpr uint32_t kZcx = Gp::kIdCx;
+  constexpr uint32_t kZdx = Gp::kIdDx;
+  constexpr uint32_t kZsp = Gp::kIdSp;
+  constexpr uint32_t kZbp = Gp::kIdBp;
+  constexpr uint32_t kZsi = Gp::kIdSi;
+  constexpr uint32_t kZdi = Gp::kIdDi;
+
+  bool winABI = environment.isPlatformWindows() || environment.isAbiMSVC();
+
+  cc.setArch(environment.arch());
+
+  if (environment.is32Bit()) {
+    bool isStandardCallConv = true;
+
+    cc.setPreservedRegs(Reg::kGroupGp, Support::bitMask(Gp::kIdBx, Gp::kIdSp, Gp::kIdBp, Gp::kIdSi, Gp::kIdDi));
+    cc.setNaturalStackAlignment(4);
+
+    switch (ccId) {
+      case CallConv::kIdCDecl:
+        break;
+
+      case CallConv::kIdStdCall:
+        cc.setFlags(CallConv::kFlagCalleePopsStack);
+        break;
+
+      case CallConv::kIdFastCall:
+        cc.setFlags(CallConv::kFlagCalleePopsStack);
+        cc.setPassedOrder(kGroupGp, kZcx, kZdx);
+        break;
+
+      case CallConv::kIdVectorCall:
+        cc.setFlags(CallConv::kFlagCalleePopsStack);
+        cc.setPassedOrder(kGroupGp, kZcx, kZdx);
+        cc.setPassedOrder(kGroupVec, 0, 1, 2, 3, 4, 5);
+        break;
+
+      case CallConv::kIdThisCall:
+        // NOTE: Even MINGW (starting with GCC 4.7.0) now uses __thiscall on MS Windows,
+        // so we won't bail to any other calling convention if __thiscall was specified.
+        if (winABI) {
+          cc.setFlags(CallConv::kFlagCalleePopsStack);
+          cc.setPassedOrder(kGroupGp, kZcx);
+        }
+        else {
+          ccId = CallConv::kIdCDecl;
+        }
+        break;
+
+      case CallConv::kIdRegParm1:
+        cc.setPassedOrder(kGroupGp, kZax);
+        break;
+
+      case CallConv::kIdRegParm2:
+        cc.setPassedOrder(kGroupGp, kZax, kZdx);
+        break;
+
+      case CallConv::kIdRegParm3:
+        cc.setPassedOrder(kGroupGp, kZax, kZdx, kZcx);
+        break;
+
+      case CallConv::kIdLightCall2:
+      case CallConv::kIdLightCall3:
+      case CallConv::kIdLightCall4: {
+        uint32_t n = (ccId - CallConv::kIdLightCall2) + 2;
+
+        cc.setFlags(CallConv::kFlagPassFloatsByVec);
+        cc.setPassedOrder(kGroupGp, kZax, kZdx, kZcx, kZsi, kZdi);
+        cc.setPassedOrder(kGroupMm, 0, 1, 2, 3, 4, 5, 6, 7);
+        cc.setPassedOrder(kGroupVec, 0, 1, 2, 3, 4, 5, 6, 7);
+        cc.setPassedOrder(kGroupKReg, 0, 1, 2, 3, 4, 5, 6, 7);
+        cc.setPreservedRegs(kGroupGp, Support::lsbMask<uint32_t>(8));
+        cc.setPreservedRegs(kGroupVec, Support::lsbMask<uint32_t>(8) & ~Support::lsbMask<uint32_t>(n));
+
+        cc.setNaturalStackAlignment(16);
+        isStandardCallConv = false;
+        break;
+      }
+
+      default:
+        return DebugUtils::errored(kErrorInvalidArgument);
+    }
+
+    if (isStandardCallConv) {
+      // MMX arguments is something where compiler vendors disagree. For example
+      // GCC and MSVC would pass first three via registers and the rest via stack,
+      // however Clang passes all via stack. Returning MMX registers is even more
+      // fun, where GCC uses MM0, but Clang uses EAX:EDX pair. I'm not sure it's
+      // something we should be worried about as MMX is deprecated anyway.
+      cc.setPassedOrder(kGroupMm, 0, 1, 2);
+
+      // Vector arguments (XMM|YMM|ZMM) are passed via registers. However, if the
+      // function is variadic then they have to be passed via stack.
+      cc.setPassedOrder(kGroupVec, 0, 1, 2);
+
+      // Functions with variable arguments always use stack for MM and vector
+      // arguments.
+      cc.addFlags(CallConv::kFlagPassVecByStackIfVA);
+    }
+
+    if (ccId == CallConv::kIdCDecl) {
+      cc.addFlags(CallConv::kFlagVarArgCompatible);
+    }
+  }
+  else {
+    // Preprocess the calling convention into a common id as many conventions
+    // are normally ignored even by C/C++ compilers and treated as `__cdecl`.
+    if (shouldThreatAsCDeclIn64BitMode(ccId))
+      ccId = winABI ? CallConv::kIdX64Windows : CallConv::kIdX64SystemV;
+
+    switch (ccId) {
+      case CallConv::kIdX64SystemV: {
+        cc.setFlags(CallConv::kFlagPassFloatsByVec |
+                    CallConv::kFlagPassMmxByXmm    |
+                    CallConv::kFlagVarArgCompatible);
+        cc.setNaturalStackAlignment(16);
+        cc.setRedZoneSize(128);
+        cc.setPassedOrder(kGroupGp, kZdi, kZsi, kZdx, kZcx, 8, 9);
+        cc.setPassedOrder(kGroupVec, 0, 1, 2, 3, 4, 5, 6, 7);
+        cc.setPreservedRegs(kGroupGp, Support::bitMask(kZbx, kZsp, kZbp, 12, 13, 14, 15));
+        break;
+      }
+
+      case CallConv::kIdX64Windows: {
+        cc.setStrategy(CallConv::kStrategyX64Windows);
+        cc.setFlags(CallConv::kFlagPassFloatsByVec |
+                    CallConv::kFlagIndirectVecArgs |
+                    CallConv::kFlagPassMmxByGp     |
+                    CallConv::kFlagVarArgCompatible);
+        cc.setNaturalStackAlignment(16);
+        // Maximum 4 arguments in registers, each adds 8 bytes to the spill zone.
+        cc.setSpillZoneSize(4 * 8);
+        cc.setPassedOrder(kGroupGp, kZcx, kZdx, 8, 9);
+        cc.setPassedOrder(kGroupVec, 0, 1, 2, 3);
+        cc.setPreservedRegs(kGroupGp, Support::bitMask(kZbx, kZsp, kZbp, kZsi, kZdi, 12, 13, 14, 15));
+        cc.setPreservedRegs(kGroupVec, Support::bitMask(6, 7, 8, 9, 10, 11, 12, 13, 14, 15));
+        break;
+      }
+
+      case CallConv::kIdVectorCall: {
+        cc.setStrategy(CallConv::kStrategyX64VectorCall);
+        cc.setFlags(CallConv::kFlagPassFloatsByVec |
+                    CallConv::kFlagPassMmxByGp     );
+        cc.setNaturalStackAlignment(16);
+        // Maximum 6 arguments in registers, each adds 8 bytes to the spill zone.
+        cc.setSpillZoneSize(6 * 8);
+        cc.setPassedOrder(kGroupGp, kZcx, kZdx, 8, 9);
+        cc.setPassedOrder(kGroupVec, 0, 1, 2, 3, 4, 5);
+        cc.setPreservedRegs(kGroupGp, Support::bitMask(kZbx, kZsp, kZbp, kZsi, kZdi, 12, 13, 14, 15));
+        cc.setPreservedRegs(kGroupVec, Support::bitMask(6, 7, 8, 9, 10, 11, 12, 13, 14, 15));
+        break;
+      }
+
+      case CallConv::kIdLightCall2:
+      case CallConv::kIdLightCall3:
+      case CallConv::kIdLightCall4: {
+        uint32_t n = (ccId - CallConv::kIdLightCall2) + 2;
+
+        cc.setFlags(CallConv::kFlagPassFloatsByVec);
+        cc.setNaturalStackAlignment(16);
+        cc.setPassedOrder(kGroupGp, kZax, kZdx, kZcx, kZsi, kZdi);
+        cc.setPassedOrder(kGroupMm, 0, 1, 2, 3, 4, 5, 6, 7);
+        cc.setPassedOrder(kGroupVec, 0, 1, 2, 3, 4, 5, 6, 7);
+        cc.setPassedOrder(kGroupKReg, 0, 1, 2, 3, 4, 5, 6, 7);
+
+        cc.setPreservedRegs(kGroupGp, Support::lsbMask<uint32_t>(16));
+        cc.setPreservedRegs(kGroupVec, ~Support::lsbMask<uint32_t>(n));
+        break;
+      }
+
+      default:
+        return DebugUtils::errored(kErrorInvalidArgument);
+    }
+  }
+
+  cc.setId(ccId);
+  return kErrorOk;
+}
+
+} // {CallConvInternal}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86
diff --git a/client/asmjit/x86/x86callconv_p.h b/client/asmjit/x86/x86callconv_p.h
new file mode 100644
index 0000000..1607ea2
--- /dev/null
+++ b/client/asmjit/x86/x86callconv_p.h
@@ -0,0 +1,52 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86CALLCONV_P_H_INCLUDED
+#define ASMJIT_X86_X86CALLCONV_P_H_INCLUDED
+
+#include "../core/callconv.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::x86::CallConvInternal]
+// ============================================================================
+
+//! X86-specific function API (calling conventions and other utilities).
+namespace CallConvInternal {
+
+//! Initialize `CallConv` structure (X86 specific).
+Error init(CallConv& cc, uint32_t ccId, const Environment& environment) noexcept;
+
+} // {CallConvInternal}
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86CALLCONV_P_H_INCLUDED
diff --git a/client/asmjit/x86/x86compiler.cpp b/client/asmjit/x86/x86compiler.cpp
new file mode 100644
index 0000000..c087548
--- /dev/null
+++ b/client/asmjit/x86/x86compiler.cpp
@@ -0,0 +1,80 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#include "../core/api-build_p.h"
+#if defined(ASMJIT_BUILD_X86) && !defined(ASMJIT_NO_COMPILER)
+
+#include "../x86/x86assembler.h"
+#include "../x86/x86compiler.h"
+#include "../x86/x86rapass_p.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::x86::Compiler - Construction / Destruction]
+// ============================================================================
+
+Compiler::Compiler(CodeHolder* code) noexcept : BaseCompiler() {
+  if (code)
+    code->attach(this);
+}
+Compiler::~Compiler() noexcept {}
+
+// ============================================================================
+// [asmjit::x86::Compiler - Finalize]
+// ============================================================================
+
+Error Compiler::finalize() {
+  ASMJIT_PROPAGATE(runPasses());
+  Assembler a(_code);
+  a.addEncodingOptions(encodingOptions());
+  a.addValidationOptions(validationOptions());
+  return serializeTo(&a);
+}
+// ============================================================================
+// [asmjit::x86::Compiler - Events]
+// ============================================================================
+
+Error Compiler::onAttach(CodeHolder* code) noexcept {
+  uint32_t arch = code->arch();
+  if (!Environment::isFamilyX86(arch))
+    return DebugUtils::errored(kErrorInvalidArch);
+
+  ASMJIT_PROPAGATE(Base::onAttach(code));
+
+  bool is32Bit = Environment::is32Bit(arch);
+  _gpRegInfo.setSignature(is32Bit ? uint32_t(Gpd::kSignature)
+                                  : uint32_t(Gpq::kSignature));
+
+  Error err = addPassT<X86RAPass>();
+  if (ASMJIT_UNLIKELY(err)) {
+    onDetach(code);
+    return err;
+  }
+
+  return kErrorOk;
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86 && !ASMJIT_NO_COMPILER
diff --git a/client/asmjit/x86/x86compiler.h b/client/asmjit/x86/x86compiler.h
new file mode 100644
index 0000000..4c64b3b
--- /dev/null
+++ b/client/asmjit/x86/x86compiler.h
@@ -0,0 +1,721 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86COMPILER_H_INCLUDED
+#define ASMJIT_X86_X86COMPILER_H_INCLUDED
+
+#include "../core/api-config.h"
+#ifndef ASMJIT_NO_COMPILER
+
+#include "../core/compiler.h"
+#include "../core/datatypes.h"
+#include "../core/type.h"
+#include "../x86/x86emitter.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::x86::Compiler]
+// ============================================================================
+
+//! X86/X64 compiler implementation.
+//!
+//! ### Compiler Basics
+//!
+//! The first \ref x86::Compiler example shows how to generate a function that
+//! simply returns an integer value. It's an analogy to the first Assembler example:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! #include <stdio.h>
+//!
+//! using namespace asmjit;
+//!
+//! // Signature of the generated function.
+//! typedef int (*Func)(void);
+//!
+//! int main() {
+//!   JitRuntime rt;                    // Runtime specialized for JIT code execution.
+//!   CodeHolder code;                  // Holds code and relocation information.
+//!
+//!   code.init(rt.environment());      // Initialize code to match the JIT environment.
+//!   x86::Compiler cc(&code);          // Create and attach x86::Compiler to code.
+//!
+//!   cc.addFunc(FuncSignatureT<int>());// Begin a function of `int fn(void)` signature.
+//!
+//!   x86::Gp vReg = cc.newGpd();       // Create a 32-bit general purpose register.
+//!   cc.mov(vReg, 1);                  // Move one to our virtual register `vReg`.
+//!   cc.ret(vReg);                     // Return `vReg` from the function.
+//!
+//!   cc.endFunc();                     // End of the function body.
+//!   cc.finalize();                    // Translate and assemble the whole 'cc' content.
+//!   // ----> x86::Compiler is no longer needed from here and can be destroyed <----
+//!
+//!   Func fn;
+//!   Error err = rt.add(&fn, &code);   // Add the generated code to the runtime.
+//!   if (err) return 1;                // Handle a possible error returned by AsmJit.
+//!   // ----> CodeHolder is no longer needed from here and can be destroyed <----
+//!
+//!   int result = fn();                // Execute the generated code.
+//!   printf("%d\n", result);           // Print the resulting "1".
+//!
+//!   rt.release(fn);                   // Explicitly remove the function from the runtime.
+//!   return 0;
+//! }
+//! ```
+//!
+//! The \ref BaseCompiler::addFunc() and \ref BaseCompiler::endFunc() functions
+//! are used to define the function and its end. Both must be called per function,
+//! but the body doesn't have to be generated in sequence. An example of generating
+//! two functions will be shown later. The next example shows more complicated code
+//! that contain a loop and generates a simple memory copy function that uses
+//! `uint32_t` items:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! #include <stdio.h>
+//!
+//! using namespace asmjit;
+//!
+//! // Signature of the generated function.
+//! typedef void (*MemCpy32)(uint32_t* dst, const uint32_t* src, size_t count);
+//!
+//! int main() {
+//!   JitRuntime rt;                    // Runtime specialized for JIT code execution.
+//!   CodeHolder code;                  // Holds code and relocation information.
+//!
+//!   code.init(rt.environment());      // Initialize code to match the JIT environment.
+//!   x86::Compiler cc(&code);          // Create and attach x86::Compiler to code.
+//!
+//!   cc.addFunc(                       // Begin the function of the following signature:
+//!     FuncSignatureT<void,            //   Return value - void      (no return value).
+//!       uint32_t*,                    //   1st argument - uint32_t* (machine reg-size).
+//!       const uint32_t*,              //   2nd argument - uint32_t* (machine reg-size).
+//!       size_t>());                   //   3rd argument - size_t    (machine reg-size).
+//!
+//!   Label L_Loop = cc.newLabel();     // Start of the loop.
+//!   Label L_Exit = cc.newLabel();     // Used to exit early.
+//!
+//!   x86::Gp dst = cc.newIntPtr("dst");// Create `dst` register (destination pointer).
+//!   x86::Gp src = cc.newIntPtr("src");// Create `src` register (source pointer).
+//!   x86::Gp i = cc.newUIntPtr("i");   // Create `i` register (loop counter).
+//!
+//!   cc.setArg(0, dst);                // Assign `dst` argument.
+//!   cc.setArg(1, src);                // Assign `src` argument.
+//!   cc.setArg(2, i);                  // Assign `i` argument.
+//!
+//!   cc.test(i, i);                    // Early exit if length is zero.
+//!   cc.jz(L_Exit);
+//!
+//!   cc.bind(L_Loop);                  // Bind the beginning of the loop here.
+//!
+//!   x86::Gp tmp = cc.newInt32("tmp"); // Copy a single dword (4 bytes).
+//!   cc.mov(tmp, x86::dword_ptr(src)); // Load DWORD from [src] address.
+//!   cc.mov(x86::dword_ptr(dst), tmp); // Store DWORD to [dst] address.
+//!
+//!   cc.add(src, 4);                   // Increment `src`.
+//!   cc.add(dst, 4);                   // Increment `dst`.
+//!
+//!   cc.dec(i);                        // Loop until `i` is non-zero.
+//!   cc.jnz(L_Loop);
+//!
+//!   cc.bind(L_Exit);                  // Label used by early exit.
+//!   cc.endFunc();                     // End of the function body.
+//!
+//!   cc.finalize();                    // Translate and assemble the whole 'cc' content.
+//!   // ----> x86::Compiler is no longer needed from here and can be destroyed <----
+//!
+//!   // Add the generated code to the runtime.
+//!   MemCpy32 memcpy32;
+//!   Error err = rt.add(&memcpy32, &code);
+//!
+//!   // Handle a possible error returned by AsmJit.
+//!   if (err)
+//!     return 1;
+//!   // ----> CodeHolder is no longer needed from here and can be destroyed <----
+//!
+//!   // Test the generated code.
+//!   uint32_t input[6] = { 1, 2, 3, 5, 8, 13 };
+//!   uint32_t output[6];
+//!   memcpy32(output, input, 6);
+//!
+//!   for (uint32_t i = 0; i < 6; i++)
+//!     printf("%d\n", output[i]);
+//!
+//!   rt.release(memcpy32);
+//!   return 0;
+//! }
+//! ```
+//!
+//! ### Recursive Functions
+//!
+//! It's possible to create more functions by using the same \ref x86::Compiler
+//! instance and make links between them. In such case it's important to keep
+//! the pointer to \ref FuncNode.
+//!
+//! The example below creates a simple Fibonacci function that calls itself recursively:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! #include <stdio.h>
+//!
+//! using namespace asmjit;
+//!
+//! // Signature of the generated function.
+//! typedef uint32_t (*Fibonacci)(uint32_t x);
+//!
+//! int main() {
+//!   JitRuntime rt;                    // Runtime specialized for JIT code execution.
+//!   CodeHolder code;                  // Holds code and relocation information.
+//!
+//!   code.init(rt.environment());      // Initialize code to match the JIT environment.
+//!   x86::Compiler cc(&code);          // Create and attach x86::Compiler to code.
+//!
+//!   FuncNode* func = cc.addFunc(      // Begin of the Fibonacci function, addFunc()
+//!     FuncSignatureT<int, int>());    // Returns a pointer to the FuncNode node.
+//!
+//!   Label L_Exit = cc.newLabel()      // Exit label.
+//!   x86::Gp x = cc.newU32();          // Function x argument.
+//!   x86::Gp y = cc.newU32();          // Temporary.
+//!
+//!   cc.setArg(0, x);
+//!
+//!   cc.cmp(x, 3);                     // Return x if less than 3.
+//!   cc.jb(L_Exit);
+//!
+//!   cc.mov(y, x);                     // Make copy of the original x.
+//!   cc.dec(x);                        // Decrease x.
+//!
+//!   InvokeNode* invokeNode;           // Function invocation:
+//!   cc.invoke(&invokeNode,            //   - InvokeNode (output).
+//!     func->label(),                  //   - Function address or Label.
+//!     FuncSignatureT<int, int>());    //   - Function signature.
+//!
+//!   invokeNode->setArg(0, x);         // Assign x as the first argument.
+//!   invokeNode->setRet(0, x);         // Assign x as a return value as well.
+//!
+//!   cc.add(x, y);                     // Combine the return value with y.
+//!
+//!   cc.bind(L_Exit);
+//!   cc.ret(x);                        // Return x.
+//!   cc.endFunc();                     // End of the function body.
+//!
+//!   cc.finalize();                    // Translate and assemble the whole 'cc' content.
+//!   // ----> x86::Compiler is no longer needed from here and can be destroyed <----
+//!
+//!   Fibonacci fib;
+//!   Error err = rt.add(&fib, &code);  // Add the generated code to the runtime.
+//!   if (err) return 1;                // Handle a possible error returned by AsmJit.
+//!   // ----> CodeHolder is no longer needed from here and can be destroyed <----
+//!
+//!   // Test the generated code.
+//!   printf("Fib(%u) -> %u\n", 8, fib(8));
+//!
+//!   rt.release(fib);
+//!   return 0;
+//! }
+//! ```
+//!
+//! ### Stack Management
+//!
+//! Function's stack-frame is managed automatically, which is used by the register allocator to spill virtual registers. It also provides an interface to allocate user-defined block of the stack, which can be used as a temporary storage by the generated function. In the following example a stack of 256 bytes size is allocated, filled by bytes starting from 0 to 255 and then iterated again to sum all the values.
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//! #include <stdio.h>
+//!
+//! using namespace asmjit;
+//!
+//! // Signature of the generated function.
+//! typedef int (*Func)(void);
+//!
+//! int main() {
+//!   JitRuntime rt;                    // Runtime specialized for JIT code execution.
+//!   CodeHolder code;                  // Holds code and relocation information.
+//!
+//!   code.init(rt.environment());      // Initialize code to match the JIT environment.
+//!   x86::Compiler cc(&code);          // Create and attach x86::Compiler to code.
+//!
+//!   cc.addFunc(FuncSignatureT<int>());// Create a function that returns int.
+//!
+//!   x86::Gp p = cc.newIntPtr("p");
+//!   x86::Gp i = cc.newIntPtr("i");
+//!
+//!   // Allocate 256 bytes on the stack aligned to 4 bytes.
+//!   x86::Mem stack = cc.newStack(256, 4);
+//!
+//!   x86::Mem stackIdx(stack);         // Copy of stack with i added.
+//!   stackIdx.setIndex(i);             // stackIdx <- stack[i].
+//!   stackIdx.setSize(1);              // stackIdx <- byte ptr stack[i].
+//!
+//!   // Load a stack address to `p`. This step is purely optional and shows
+//!   // that `lea` is useful to load a memory operands address (even absolute)
+//!   // to a general purpose register.
+//!   cc.lea(p, stack);
+//!
+//!   // Clear i (xor is a C++ keyword, hence 'xor_' is used instead).
+//!   cc.xor_(i, i);
+//!
+//!   Label L1 = cc.newLabel();
+//!   Label L2 = cc.newLabel();
+//!
+//!   cc.bind(L1);                      // First loop, fill the stack.
+//!   cc.mov(stackIdx, i.r8());         // stack[i] = uint8_t(i).
+//!
+//!   cc.inc(i);                        // i++;
+//!   cc.cmp(i, 256);                   // if (i < 256)
+//!   cc.jb(L1);                        //   goto L1;
+//!
+//!   // Second loop, sum all bytes stored in `stack`.
+//!   x86::Gp sum = cc.newI32("sum");
+//!   x86::Gp val = cc.newI32("val");
+//!
+//!   cc.xor_(i, i);
+//!   cc.xor_(sum, sum);
+//!
+//!   cc.bind(L2);
+//!
+//!   cc.movzx(val, stackIdx);          // val = uint32_t(stack[i]);
+//!   cc.add(sum, val);                 // sum += val;
+//!
+//!   cc.inc(i);                        // i++;
+//!   cc.cmp(i, 256);                   // if (i < 256)
+//!   cc.jb(L2);                        //   goto L2;
+//!
+//!   cc.ret(sum);                      // Return the `sum` of all values.
+//!   cc.endFunc();                     // End of the function body.
+//!
+//!   cc.finalize();                    // Translate and assemble the whole 'cc' content.
+//!   // ----> x86::Compiler is no longer needed from here and can be destroyed <----
+//!
+//!   Func func;
+//!   Error err = rt.add(&func, &code); // Add the generated code to the runtime.
+//!   if (err) return 1;                // Handle a possible error returned by AsmJit.
+//!   // ----> CodeHolder is no longer needed from here and can be destroyed <----
+//!
+//!   printf("Func() -> %d\n", func()); // Test the generated code.
+//!
+//!   rt.release(func);
+//!   return 0;
+//! }
+//! ```
+//!
+//! ### Constant Pool
+//!
+//! Compiler provides two constant pools for a general purpose code generation:
+//!
+//!   - Local constant pool - Part of \ref FuncNode, can be only used by a
+//!     single function and added after the function epilog sequence (after
+//!     `ret` instruction).
+//!
+//!   - Global constant pool - Part of \ref BaseCompiler, flushed at the end
+//!     of the generated code by \ref BaseEmitter::finalize().
+//!
+//! The example below illustrates how a built-in constant pool can be used:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//!
+//! using namespace asmjit;
+//!
+//! static void exampleUseOfConstPool(x86::Compiler& cc) {
+//!   cc.addFunc(FuncSignatureT<int>());
+//!
+//!   x86::Gp v0 = cc.newGpd("v0");
+//!   x86::Gp v1 = cc.newGpd("v1");
+//!
+//!   x86::Mem c0 = cc.newInt32Const(ConstPool::kScopeLocal, 200);
+//!   x86::Mem c1 = cc.newInt32Const(ConstPool::kScopeLocal, 33);
+//!
+//!   cc.mov(v0, c0);
+//!   cc.mov(v1, c1);
+//!   cc.add(v0, v1);
+//!
+//!   cc.ret(v0);
+//!   cc.endFunc();
+//! }
+//! ```
+//!
+//! ### Jump Tables
+//!
+//! x86::Compiler supports `jmp` instruction with reg/mem operand, which is a
+//! commonly used pattern to implement indirect jumps within a function, for
+//! example to implement `switch()` statement in a programming languages. By
+//! default AsmJit assumes that every basic block can be a possible jump
+//! target as it's unable to deduce targets from instruction's operands. This
+//! is a very pessimistic default that should be avoided if possible as it's
+//! costly and very unfriendly to liveness analysis and register allocation.
+//!
+//! Instead of relying on such pessimistic default behavior, let's use \ref
+//! JumpAnnotation to annotate a jump where all targets are known:
+//!
+//! ```
+//! #include <asmjit/x86.h>
+//!
+//! using namespace asmjit;
+//!
+//! static void exampleUseOfIndirectJump(x86::Compiler& cc) {
+//!   cc.addFunc(FuncSignatureT<float, float, float, uint32_t>(CallConv::kIdHost));
+//!
+//!   // Function arguments
+//!   x86::Xmm a = cc.newXmmSs("a");
+//!   x86::Xmm b = cc.newXmmSs("b");
+//!   x86::Gp op = cc.newUInt32("op");
+//!
+//!   x86::Gp target = cc.newIntPtr("target");
+//!   x86::Gp offset = cc.newIntPtr("offset");
+//!
+//!   Label L_Table = cc.newLabel();
+//!   Label L_Add = cc.newLabel();
+//!   Label L_Sub = cc.newLabel();
+//!   Label L_Mul = cc.newLabel();
+//!   Label L_Div = cc.newLabel();
+//!   Label L_End = cc.newLabel();
+//!
+//!   cc.setArg(0, a);
+//!   cc.setArg(1, b);
+//!   cc.setArg(2, op);
+//!
+//!   // Jump annotation is a building block that allows to annotate all
+//!   // possible targets where `jmp()` can jump. It then drives the CFG
+//!   // contruction and liveness analysis, which impacts register allocation.
+//!   JumpAnnotation* annotation = cc.newJumpAnnotation();
+//!   annotation->addLabel(L_Add);
+//!   annotation->addLabel(L_Sub);
+//!   annotation->addLabel(L_Mul);
+//!   annotation->addLabel(L_Div);
+//!
+//!   // Most likely not the common indirect jump approach, but it
+//!   // doesn't really matter how final address is calculated. The
+//!   // most important path using JumpAnnotation with `jmp()`.
+//!   cc.lea(offset, x86::ptr(L_Table));
+//!   if (cc.is64Bit())
+//!     cc.movsxd(target, x86::dword_ptr(offset, op.cloneAs(offset), 2));
+//!   else
+//!     cc.mov(target, x86::dword_ptr(offset, op.cloneAs(offset), 2));
+//!   cc.add(target, offset);
+//!   cc.jmp(target, annotation);
+//!
+//!   // Acts like a switch() statement in C.
+//!   cc.bind(L_Add);
+//!   cc.addss(a, b);
+//!   cc.jmp(L_End);
+//!
+//!   cc.bind(L_Sub);
+//!   cc.subss(a, b);
+//!   cc.jmp(L_End);
+//!
+//!   cc.bind(L_Mul);
+//!   cc.mulss(a, b);
+//!   cc.jmp(L_End);
+//!
+//!   cc.bind(L_Div);
+//!   cc.divss(a, b);
+//!
+//!   cc.bind(L_End);
+//!   cc.ret(a);
+//!
+//!   cc.endFunc();
+//!
+//!   // Relative int32_t offsets of `L_XXX - L_Table`.
+//!   cc.bind(L_Table);
+//!   cc.embedLabelDelta(L_Add, L_Table, 4);
+//!   cc.embedLabelDelta(L_Sub, L_Table, 4);
+//!   cc.embedLabelDelta(L_Mul, L_Table, 4);
+//!   cc.embedLabelDelta(L_Div, L_Table, 4);
+//! }
+//! ```
+class ASMJIT_VIRTAPI Compiler
+  : public BaseCompiler,
+    public EmitterExplicitT<Compiler> {
+public:
+  ASMJIT_NONCOPYABLE(Compiler)
+  typedef BaseCompiler Base;
+
+  //! \name Construction & Destruction
+  //! \{
+
+  ASMJIT_API explicit Compiler(CodeHolder* code = nullptr) noexcept;
+  ASMJIT_API virtual ~Compiler() noexcept;
+
+  //! \}
+
+  //! \name Virtual Registers
+  //! \{
+
+#ifndef ASMJIT_NO_LOGGING
+# define ASMJIT_NEW_REG_FMT(OUT, PARAM, FORMAT, ARGS)                         \
+    _newRegFmt(&OUT, PARAM, FORMAT, ARGS)
+#else
+# define ASMJIT_NEW_REG_FMT(OUT, PARAM, FORMAT, ARGS)                         \
+    DebugUtils::unused(FORMAT);                                               \
+    DebugUtils::unused(std::forward<Args>(args)...);                          \
+    _newReg(&OUT, PARAM)
+#endif
+
+#define ASMJIT_NEW_REG_CUSTOM(FUNC, REG)                                      \
+    inline REG FUNC(uint32_t typeId) {                                        \
+      REG reg(Globals::NoInit);                                               \
+      _newReg(&reg, typeId);                                                  \
+      return reg;                                                             \
+    }                                                                         \
+                                                                              \
+    template<typename... Args>                                                \
+    inline REG FUNC(uint32_t typeId, const char* fmt, Args&&... args) {       \
+      REG reg(Globals::NoInit);                                               \
+      ASMJIT_NEW_REG_FMT(reg, typeId, fmt, std::forward<Args>(args)...);      \
+      return reg;                                                             \
+    }
+
+#define ASMJIT_NEW_REG_TYPED(FUNC, REG, TYPE_ID)                              \
+    inline REG FUNC() {                                                       \
+      REG reg(Globals::NoInit);                                               \
+      _newReg(&reg, TYPE_ID);                                                 \
+      return reg;                                                             \
+    }                                                                         \
+                                                                              \
+    template<typename... Args>                                                \
+    inline REG FUNC(const char* fmt, Args&&... args) {                        \
+      REG reg(Globals::NoInit);                                               \
+      ASMJIT_NEW_REG_FMT(reg, TYPE_ID, fmt, std::forward<Args>(args)...);     \
+      return reg;                                                             \
+    }
+
+  template<typename RegT>
+  inline RegT newSimilarReg(const RegT& ref) {
+    RegT reg(Globals::NoInit);
+    _newReg(reg, ref);
+    return reg;
+  }
+
+  template<typename RegT, typename... Args>
+  inline RegT newSimilarReg(const RegT& ref, const char* fmt, Args&&... args) {
+    RegT reg(Globals::NoInit);
+    ASMJIT_NEW_REG_FMT(reg, ref, fmt, std::forward<Args>(args)...);
+    return reg;
+  }
+
+  ASMJIT_NEW_REG_CUSTOM(newReg    , Reg )
+  ASMJIT_NEW_REG_CUSTOM(newGp     , Gp  )
+  ASMJIT_NEW_REG_CUSTOM(newVec    , Vec )
+  ASMJIT_NEW_REG_CUSTOM(newK      , KReg)
+
+  ASMJIT_NEW_REG_TYPED(newI8     , Gp  , Type::kIdI8     )
+  ASMJIT_NEW_REG_TYPED(newU8     , Gp  , Type::kIdU8     )
+  ASMJIT_NEW_REG_TYPED(newI16    , Gp  , Type::kIdI16    )
+  ASMJIT_NEW_REG_TYPED(newU16    , Gp  , Type::kIdU16    )
+  ASMJIT_NEW_REG_TYPED(newI32    , Gp  , Type::kIdI32    )
+  ASMJIT_NEW_REG_TYPED(newU32    , Gp  , Type::kIdU32    )
+  ASMJIT_NEW_REG_TYPED(newI64    , Gp  , Type::kIdI64    )
+  ASMJIT_NEW_REG_TYPED(newU64    , Gp  , Type::kIdU64    )
+  ASMJIT_NEW_REG_TYPED(newInt8   , Gp  , Type::kIdI8     )
+  ASMJIT_NEW_REG_TYPED(newUInt8  , Gp  , Type::kIdU8     )
+  ASMJIT_NEW_REG_TYPED(newInt16  , Gp  , Type::kIdI16    )
+  ASMJIT_NEW_REG_TYPED(newUInt16 , Gp  , Type::kIdU16    )
+  ASMJIT_NEW_REG_TYPED(newInt32  , Gp  , Type::kIdI32    )
+  ASMJIT_NEW_REG_TYPED(newUInt32 , Gp  , Type::kIdU32    )
+  ASMJIT_NEW_REG_TYPED(newInt64  , Gp  , Type::kIdI64    )
+  ASMJIT_NEW_REG_TYPED(newUInt64 , Gp  , Type::kIdU64    )
+  ASMJIT_NEW_REG_TYPED(newIntPtr , Gp  , Type::kIdIntPtr )
+  ASMJIT_NEW_REG_TYPED(newUIntPtr, Gp  , Type::kIdUIntPtr)
+
+  ASMJIT_NEW_REG_TYPED(newGpb    , Gp  , Type::kIdU8     )
+  ASMJIT_NEW_REG_TYPED(newGpw    , Gp  , Type::kIdU16    )
+  ASMJIT_NEW_REG_TYPED(newGpd    , Gp  , Type::kIdU32    )
+  ASMJIT_NEW_REG_TYPED(newGpq    , Gp  , Type::kIdU64    )
+  ASMJIT_NEW_REG_TYPED(newGpz    , Gp  , Type::kIdUIntPtr)
+  ASMJIT_NEW_REG_TYPED(newXmm    , Xmm , Type::kIdI32x4  )
+  ASMJIT_NEW_REG_TYPED(newXmmSs  , Xmm , Type::kIdF32x1  )
+  ASMJIT_NEW_REG_TYPED(newXmmSd  , Xmm , Type::kIdF64x1  )
+  ASMJIT_NEW_REG_TYPED(newXmmPs  , Xmm , Type::kIdF32x4  )
+  ASMJIT_NEW_REG_TYPED(newXmmPd  , Xmm , Type::kIdF64x2  )
+  ASMJIT_NEW_REG_TYPED(newYmm    , Ymm , Type::kIdI32x8  )
+  ASMJIT_NEW_REG_TYPED(newYmmPs  , Ymm , Type::kIdF32x8  )
+  ASMJIT_NEW_REG_TYPED(newYmmPd  , Ymm , Type::kIdF64x4  )
+  ASMJIT_NEW_REG_TYPED(newZmm    , Zmm , Type::kIdI32x16 )
+  ASMJIT_NEW_REG_TYPED(newZmmPs  , Zmm , Type::kIdF32x16 )
+  ASMJIT_NEW_REG_TYPED(newZmmPd  , Zmm , Type::kIdF64x8  )
+  ASMJIT_NEW_REG_TYPED(newMm     , Mm  , Type::kIdMmx64  )
+  ASMJIT_NEW_REG_TYPED(newKb     , KReg, Type::kIdMask8  )
+  ASMJIT_NEW_REG_TYPED(newKw     , KReg, Type::kIdMask16 )
+  ASMJIT_NEW_REG_TYPED(newKd     , KReg, Type::kIdMask32 )
+  ASMJIT_NEW_REG_TYPED(newKq     , KReg, Type::kIdMask64 )
+
+#undef ASMJIT_NEW_REG_TYPED
+#undef ASMJIT_NEW_REG_CUSTOM
+#undef ASMJIT_NEW_REG_FMT
+
+  //! \}
+
+  //! \name Stack
+  //! \{
+
+  //! Creates a new memory chunk allocated on the current function's stack.
+  inline Mem newStack(uint32_t size, uint32_t alignment, const char* name = nullptr) {
+    Mem m(Globals::NoInit);
+    _newStack(&m, size, alignment, name);
+    return m;
+  }
+
+  //! \}
+
+  //! \name Constants
+  //! \{
+
+  //! Put data to a constant-pool and get a memory reference to it.
+  inline Mem newConst(uint32_t scope, const void* data, size_t size) {
+    Mem m(Globals::NoInit);
+    _newConst(&m, scope, data, size);
+    return m;
+  }
+
+  //! Put a BYTE `val` to a constant-pool.
+  inline Mem newByteConst(uint32_t scope, uint8_t val) noexcept { return newConst(scope, &val, 1); }
+  //! Put a WORD `val` to a constant-pool.
+  inline Mem newWordConst(uint32_t scope, uint16_t val) noexcept { return newConst(scope, &val, 2); }
+  //! Put a DWORD `val` to a constant-pool.
+  inline Mem newDWordConst(uint32_t scope, uint32_t val) noexcept { return newConst(scope, &val, 4); }
+  //! Put a QWORD `val` to a constant-pool.
+  inline Mem newQWordConst(uint32_t scope, uint64_t val) noexcept { return newConst(scope, &val, 8); }
+
+  //! Put a WORD `val` to a constant-pool.
+  inline Mem newInt16Const(uint32_t scope, int16_t val) noexcept { return newConst(scope, &val, 2); }
+  //! Put a WORD `val` to a constant-pool.
+  inline Mem newUInt16Const(uint32_t scope, uint16_t val) noexcept { return newConst(scope, &val, 2); }
+  //! Put a DWORD `val` to a constant-pool.
+  inline Mem newInt32Const(uint32_t scope, int32_t val) noexcept { return newConst(scope, &val, 4); }
+  //! Put a DWORD `val` to a constant-pool.
+  inline Mem newUInt32Const(uint32_t scope, uint32_t val) noexcept { return newConst(scope, &val, 4); }
+  //! Put a QWORD `val` to a constant-pool.
+  inline Mem newInt64Const(uint32_t scope, int64_t val) noexcept { return newConst(scope, &val, 8); }
+  //! Put a QWORD `val` to a constant-pool.
+  inline Mem newUInt64Const(uint32_t scope, uint64_t val) noexcept { return newConst(scope, &val, 8); }
+
+  //! Put a SP-FP `val` to a constant-pool.
+  inline Mem newFloatConst(uint32_t scope, float val) noexcept { return newConst(scope, &val, 4); }
+  //! Put a DP-FP `val` to a constant-pool.
+  inline Mem newDoubleConst(uint32_t scope, double val) noexcept { return newConst(scope, &val, 8); }
+
+#ifndef ASMJIT_NO_DEPRECATED
+  ASMJIT_DEPRECATED("newMmConst() uses a deprecated Data64, use newConst() with your own data instead")
+  inline Mem newMmConst(uint32_t scope, const Data64& val) noexcept { return newConst(scope, &val, 8); }
+
+  ASMJIT_DEPRECATED("newXmmConst() uses a deprecated Data128, use newConst() with your own data instead")
+  inline Mem newXmmConst(uint32_t scope, const Data128& val) noexcept { return newConst(scope, &val, 16); }
+
+  ASMJIT_DEPRECATED("newYmmConst() uses a deprecated Data256, use newConst() with your own data instead")
+  inline Mem newYmmConst(uint32_t scope, const Data256& val) noexcept { return newConst(scope, &val, 32); }
+#endif // !ASMJIT_NO_DEPRECATED
+
+  //! \}
+
+  //! \name Instruction Options
+  //! \{
+
+  //! Force the compiler to not follow the conditional or unconditional jump.
+  inline Compiler& unfollow() noexcept { _instOptions |= Inst::kOptionUnfollow; return *this; }
+  //! Tell the compiler that the destination variable will be overwritten.
+  inline Compiler& overwrite() noexcept { _instOptions |= Inst::kOptionOverwrite; return *this; }
+
+  //! \}
+
+  //! \name Function Call & Ret Intrinsics
+  //! \{
+
+  //! Invoke a function call without `target` type enforcement.
+  inline Error invoke_(InvokeNode** out, const Operand_& target, const FuncSignature& signature) {
+    return _addInvokeNode(out, Inst::kIdCall, target, signature);
+  }
+
+  //! Invoke a function call of the given `target` and `signature` and store
+  //! the added node to `out`.
+  //!
+  //! Creates a new \ref InvokeNode, initializes all the necessary members to
+  //! match the given function `signature`, adds the node to the compiler, and
+  //! stores its pointer to `out`. The operation is atomic, if anything fails
+  //! nullptr is stored in `out` and error code is returned.
+  inline Error invoke(InvokeNode** out, const Gp& target, const FuncSignature& signature) { return invoke_(out, target, signature); }
+  //! \overload
+  inline Error invoke(InvokeNode** out, const Mem& target, const FuncSignature& signature) { return invoke_(out, target, signature); }
+  //! \overload
+  inline Error invoke(InvokeNode** out, const Label& target, const FuncSignature& signature) { return invoke_(out, target, signature); }
+  //! \overload
+  inline Error invoke(InvokeNode** out, const Imm& target, const FuncSignature& signature) { return invoke_(out, target, signature); }
+  //! \overload
+  inline Error invoke(InvokeNode** out, uint64_t target, const FuncSignature& signature) { return invoke_(out, Imm(int64_t(target)), signature); }
+
+#ifndef _DOXYGEN
+  template<typename Target>
+  ASMJIT_DEPRECATED("Use invoke() instead of call()")
+  inline InvokeNode* call(const Target& target, const FuncSignature& signature) {
+    InvokeNode* invokeNode;
+    invoke(&invokeNode, target, signature);
+    return invokeNode;
+  }
+#endif
+
+  //! Return.
+  inline FuncRetNode* ret() { return addRet(Operand(), Operand()); }
+  //! \overload
+  inline FuncRetNode* ret(const BaseReg& o0) { return addRet(o0, Operand()); }
+  //! \overload
+  inline FuncRetNode* ret(const BaseReg& o0, const BaseReg& o1) { return addRet(o0, o1); }
+
+  //! \}
+
+  //! \name Jump Tables Support
+  //! \{
+
+  using EmitterExplicitT<Compiler>::jmp;
+
+  //! Adds a jump to the given `target` with the provided jump `annotation`.
+  inline Error jmp(const BaseReg& target, JumpAnnotation* annotation) { return emitAnnotatedJump(Inst::kIdJmp, target, annotation); }
+  //! \overload
+  inline Error jmp(const BaseMem& target, JumpAnnotation* annotation) { return emitAnnotatedJump(Inst::kIdJmp, target, annotation); }
+
+  //! \}
+
+  //! \name Finalize
+  //! \{
+
+  ASMJIT_API Error finalize() override;
+
+  //! \}
+
+  //! \name Events
+  //! \{
+
+  ASMJIT_API Error onAttach(CodeHolder* code) noexcept override;
+
+  //! \}
+};
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_COMPILER
+#endif // ASMJIT_X86_X86COMPILER_H_INCLUDED
diff --git a/client/asmjit/x86/x86emitter.h b/client/asmjit/x86/x86emitter.h
new file mode 100644
index 0000000..9764c83
--- /dev/null
+++ b/client/asmjit/x86/x86emitter.h
@@ -0,0 +1,4159 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86EMITTER_H_INCLUDED
+#define ASMJIT_X86_X86EMITTER_H_INCLUDED
+
+#include "../core/emitter.h"
+#include "../core/support.h"
+#include "../x86/x86globals.h"
+#include "../x86/x86operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+#define ASMJIT_INST_0x(NAME, ID) \
+  inline Error NAME() { return _emitter()->emit(Inst::kId##ID); }
+
+#define ASMJIT_INST_1x(NAME, ID, T0) \
+  inline Error NAME(const T0& o0) { return _emitter()->emit(Inst::kId##ID, o0); }
+
+#define ASMJIT_INST_1i(NAME, ID, T0) \
+  inline Error NAME(const T0& o0) { return _emitter()->emit(Inst::kId##ID, o0); } \
+  /** \cond */ \
+  inline Error NAME(int o0) { return _emitter()->emit(Inst::kId##ID, Support::asInt(o0)); } \
+  inline Error NAME(unsigned int o0) { return _emitter()->emit(Inst::kId##ID, Support::asInt(o0)); } \
+  inline Error NAME(int64_t o0) { return _emitter()->emit(Inst::kId##ID, Support::asInt(o0)); } \
+  inline Error NAME(uint64_t o0) { return _emitter()->emit(Inst::kId##ID, Support::asInt(o0)); } \
+  /** \endcond */
+
+#define ASMJIT_INST_1c(NAME, ID, CONV, T0) \
+  inline Error NAME(uint32_t cc, const T0& o0) { return _emitter()->emit(CONV(cc), o0); } \
+  inline Error NAME##a(const T0& o0) { return _emitter()->emit(Inst::kId##ID##a, o0); } \
+  inline Error NAME##ae(const T0& o0) { return _emitter()->emit(Inst::kId##ID##ae, o0); } \
+  inline Error NAME##b(const T0& o0) { return _emitter()->emit(Inst::kId##ID##b, o0); } \
+  inline Error NAME##be(const T0& o0) { return _emitter()->emit(Inst::kId##ID##be, o0); } \
+  inline Error NAME##c(const T0& o0) { return _emitter()->emit(Inst::kId##ID##c, o0); } \
+  inline Error NAME##e(const T0& o0) { return _emitter()->emit(Inst::kId##ID##e, o0); } \
+  inline Error NAME##g(const T0& o0) { return _emitter()->emit(Inst::kId##ID##g, o0); } \
+  inline Error NAME##ge(const T0& o0) { return _emitter()->emit(Inst::kId##ID##ge, o0); } \
+  inline Error NAME##l(const T0& o0) { return _emitter()->emit(Inst::kId##ID##l, o0); } \
+  inline Error NAME##le(const T0& o0) { return _emitter()->emit(Inst::kId##ID##le, o0); } \
+  inline Error NAME##na(const T0& o0) { return _emitter()->emit(Inst::kId##ID##na, o0); } \
+  inline Error NAME##nae(const T0& o0) { return _emitter()->emit(Inst::kId##ID##nae, o0); } \
+  inline Error NAME##nb(const T0& o0) { return _emitter()->emit(Inst::kId##ID##nb, o0); } \
+  inline Error NAME##nbe(const T0& o0) { return _emitter()->emit(Inst::kId##ID##nbe, o0); } \
+  inline Error NAME##nc(const T0& o0) { return _emitter()->emit(Inst::kId##ID##nc, o0); } \
+  inline Error NAME##ne(const T0& o0) { return _emitter()->emit(Inst::kId##ID##ne, o0); } \
+  inline Error NAME##ng(const T0& o0) { return _emitter()->emit(Inst::kId##ID##ng, o0); } \
+  inline Error NAME##nge(const T0& o0) { return _emitter()->emit(Inst::kId##ID##nge, o0); } \
+  inline Error NAME##nl(const T0& o0) { return _emitter()->emit(Inst::kId##ID##nl, o0); } \
+  inline Error NAME##nle(const T0& o0) { return _emitter()->emit(Inst::kId##ID##nle, o0); } \
+  inline Error NAME##no(const T0& o0) { return _emitter()->emit(Inst::kId##ID##no, o0); } \
+  inline Error NAME##np(const T0& o0) { return _emitter()->emit(Inst::kId##ID##np, o0); } \
+  inline Error NAME##ns(const T0& o0) { return _emitter()->emit(Inst::kId##ID##ns, o0); } \
+  inline Error NAME##nz(const T0& o0) { return _emitter()->emit(Inst::kId##ID##nz, o0); } \
+  inline Error NAME##o(const T0& o0) { return _emitter()->emit(Inst::kId##ID##o, o0); } \
+  inline Error NAME##p(const T0& o0) { return _emitter()->emit(Inst::kId##ID##p, o0); } \
+  inline Error NAME##pe(const T0& o0) { return _emitter()->emit(Inst::kId##ID##pe, o0); } \
+  inline Error NAME##po(const T0& o0) { return _emitter()->emit(Inst::kId##ID##po, o0); } \
+  inline Error NAME##s(const T0& o0) { return _emitter()->emit(Inst::kId##ID##s, o0); } \
+  inline Error NAME##z(const T0& o0) { return _emitter()->emit(Inst::kId##ID##z, o0); }
+
+#define ASMJIT_INST_2x(NAME, ID, T0, T1) \
+  inline Error NAME(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID, o0, o1); }
+
+#define ASMJIT_INST_2i(NAME, ID, T0, T1) \
+  inline Error NAME(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID, o0, o1); } \
+  /** \cond */ \
+  inline Error NAME(const T0& o0, int o1) { return _emitter()->emit(Inst::kId##ID, o0, Support::asInt(o1)); } \
+  inline Error NAME(const T0& o0, unsigned int o1) { return _emitter()->emit(Inst::kId##ID, o0, Support::asInt(o1)); } \
+  inline Error NAME(const T0& o0, int64_t o1) { return _emitter()->emit(Inst::kId##ID, o0, Support::asInt(o1)); } \
+  inline Error NAME(const T0& o0, uint64_t o1) { return _emitter()->emit(Inst::kId##ID, o0, Support::asInt(o1)); } \
+  /** \endcond */
+
+#define ASMJIT_INST_2c(NAME, ID, CONV, T0, T1) \
+  inline Error NAME(uint32_t cc, const T0& o0, const T1& o1) { return _emitter()->emit(CONV(cc), o0, o1); } \
+  inline Error NAME##a(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##a, o0, o1); } \
+  inline Error NAME##ae(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##ae, o0, o1); } \
+  inline Error NAME##b(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##b, o0, o1); } \
+  inline Error NAME##be(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##be, o0, o1); } \
+  inline Error NAME##c(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##c, o0, o1); } \
+  inline Error NAME##e(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##e, o0, o1); } \
+  inline Error NAME##g(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##g, o0, o1); } \
+  inline Error NAME##ge(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##ge, o0, o1); } \
+  inline Error NAME##l(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##l, o0, o1); } \
+  inline Error NAME##le(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##le, o0, o1); } \
+  inline Error NAME##na(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##na, o0, o1); } \
+  inline Error NAME##nae(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##nae, o0, o1); } \
+  inline Error NAME##nb(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##nb, o0, o1); } \
+  inline Error NAME##nbe(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##nbe, o0, o1); } \
+  inline Error NAME##nc(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##nc, o0, o1); } \
+  inline Error NAME##ne(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##ne, o0, o1); } \
+  inline Error NAME##ng(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##ng, o0, o1); } \
+  inline Error NAME##nge(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##nge, o0, o1); } \
+  inline Error NAME##nl(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##nl, o0, o1); } \
+  inline Error NAME##nle(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##nle, o0, o1); } \
+  inline Error NAME##no(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##no, o0, o1); } \
+  inline Error NAME##np(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##np, o0, o1); } \
+  inline Error NAME##ns(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##ns, o0, o1); } \
+  inline Error NAME##nz(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##nz, o0, o1); } \
+  inline Error NAME##o(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##o, o0, o1); } \
+  inline Error NAME##p(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##p, o0, o1); } \
+  inline Error NAME##pe(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##pe, o0, o1); } \
+  inline Error NAME##po(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##po, o0, o1); } \
+  inline Error NAME##s(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##s, o0, o1); } \
+  inline Error NAME##z(const T0& o0, const T1& o1) { return _emitter()->emit(Inst::kId##ID##z, o0, o1); }
+
+#define ASMJIT_INST_3x(NAME, ID, T0, T1, T2) \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2); }
+
+#define ASMJIT_INST_3i(NAME, ID, T0, T1, T2) \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2); } \
+  /** \cond */ \
+  inline Error NAME(const T0& o0, const T1& o1, int o2) { return _emitter()->emit(Inst::kId##ID, o0, o1, Support::asInt(o2)); } \
+  inline Error NAME(const T0& o0, const T1& o1, unsigned int o2) { return _emitter()->emit(Inst::kId##ID, o0, o1, Support::asInt(o2)); } \
+  inline Error NAME(const T0& o0, const T1& o1, int64_t o2) { return _emitter()->emit(Inst::kId##ID, o0, o1, Support::asInt(o2)); } \
+  inline Error NAME(const T0& o0, const T1& o1, uint64_t o2) { return _emitter()->emit(Inst::kId##ID, o0, o1, Support::asInt(o2)); } \
+  /** \endcond */
+
+#define ASMJIT_INST_3ii(NAME, ID, T0, T1, T2) \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2); } \
+  inline Error NAME(const T0& o0, int o1, int o2) { return _emitter()->emit(Inst::kId##ID, o0, Imm(o1), Support::asInt(o2)); }
+
+#define ASMJIT_INST_4x(NAME, ID, T0, T1, T2, T3) \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, o3); }
+
+#define ASMJIT_INST_4i(NAME, ID, T0, T1, T2, T3) \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, o3); } \
+  /** \cond */ \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, int o3) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, Support::asInt(o3)); } \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, unsigned int o3) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, Support::asInt(o3)); } \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, int64_t o3) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, Support::asInt(o3)); } \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, uint64_t o3) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, Support::asInt(o3)); } \
+  /** \endcond */
+
+#define ASMJIT_INST_4ii(NAME, ID, T0, T1, T2, T3) \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, o3); } \
+  inline Error NAME(const T0& o0, const T1& o1, int o2, int o3) { return _emitter()->emit(Inst::kId##ID, o0, o1, Imm(o2), Support::asInt(o3)); }
+
+#define ASMJIT_INST_5x(NAME, ID, T0, T1, T2, T3, T4) \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, const T4& o4) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, o3, o4); }
+
+#define ASMJIT_INST_5i(NAME, ID, T0, T1, T2, T3, T4) \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, const T4& o4) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, o3, o4); } \
+  /** \cond */ \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, int o4) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, o3, Support::asInt(o4)); } \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, unsigned int o4) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, o3, Support::asInt(o4)); } \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, int64_t o4) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, o3, Support::asInt(o4)); } \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, uint64_t o4) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, o3, Support::asInt(o4)); } \
+  /** \endcond */
+
+#define ASMJIT_INST_6x(NAME, ID, T0, T1, T2, T3, T4, T5) \
+  inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, const T4& o4, const T5& o5) { return _emitter()->emit(Inst::kId##ID, o0, o1, o2, o3, o4, o5); }
+
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::x86::EmitterExplicitT]
+// ============================================================================
+
+//! Emitter (X86 - explicit).
+template<typename This>
+struct EmitterExplicitT {
+  //! \cond
+
+  // These typedefs are used to describe implicit operands passed explicitly.
+  typedef Gp AL;
+  typedef Gp AH;
+  typedef Gp CL;
+  typedef Gp AX;
+  typedef Gp DX;
+
+  typedef Gp EAX;
+  typedef Gp EBX;
+  typedef Gp ECX;
+  typedef Gp EDX;
+
+  typedef Gp RAX;
+  typedef Gp RBX;
+  typedef Gp RCX;
+  typedef Gp RDX;
+
+  typedef Gp ZAX;
+  typedef Gp ZBX;
+  typedef Gp ZCX;
+  typedef Gp ZDX;
+
+  typedef Mem DS_ZAX; // ds:[zax]
+  typedef Mem DS_ZDI; // ds:[zdi]
+  typedef Mem ES_ZDI; // es:[zdi]
+  typedef Mem DS_ZSI; // ds:[zsi]
+
+  typedef Xmm XMM0;
+
+  // These two are unfortunately reported by the sanitizer. We know what we do,
+  // however, the sanitizer doesn't. I have tried to use reinterpret_cast instead,
+  // but that would generate bad code when compiled by MSC.
+  ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF inline This* _emitter() noexcept { return static_cast<This*>(this); }
+  ASMJIT_ATTRIBUTE_NO_SANITIZE_UNDEF inline const This* _emitter() const noexcept { return static_cast<const This*>(this); }
+
+  //! \endcond
+
+  //! \name Native Registers
+  //! \{
+
+  //! Returns either GPD or GPQ register of the given `id` depending on the emitter's architecture.
+  inline Gp gpz(uint32_t id) const noexcept { return Gp(_emitter()->_gpRegInfo.signature(), id); }
+
+  inline Gp zax() const noexcept { return Gp(_emitter()->_gpRegInfo.signature(), Gp::kIdAx); }
+  inline Gp zcx() const noexcept { return Gp(_emitter()->_gpRegInfo.signature(), Gp::kIdCx); }
+  inline Gp zdx() const noexcept { return Gp(_emitter()->_gpRegInfo.signature(), Gp::kIdDx); }
+  inline Gp zbx() const noexcept { return Gp(_emitter()->_gpRegInfo.signature(), Gp::kIdBx); }
+  inline Gp zsp() const noexcept { return Gp(_emitter()->_gpRegInfo.signature(), Gp::kIdSp); }
+  inline Gp zbp() const noexcept { return Gp(_emitter()->_gpRegInfo.signature(), Gp::kIdBp); }
+  inline Gp zsi() const noexcept { return Gp(_emitter()->_gpRegInfo.signature(), Gp::kIdSi); }
+  inline Gp zdi() const noexcept { return Gp(_emitter()->_gpRegInfo.signature(), Gp::kIdDi); }
+
+  //! \}
+
+  //! \name Native Pointers
+  //! \{
+
+  //! Creates a target dependent pointer of which base register's id is `baseId`.
+  inline Mem ptr_base(uint32_t baseId, int32_t off = 0, uint32_t size = 0) const noexcept {
+    return Mem(Mem::Decomposed { _emitter()->_gpRegInfo.type(), baseId, 0, 0, off, size, 0 });
+  }
+
+  inline Mem ptr_zax(int32_t off = 0, uint32_t size = 0) const noexcept { return ptr_base(Gp::kIdAx, off, size); }
+  inline Mem ptr_zcx(int32_t off = 0, uint32_t size = 0) const noexcept { return ptr_base(Gp::kIdCx, off, size); }
+  inline Mem ptr_zdx(int32_t off = 0, uint32_t size = 0) const noexcept { return ptr_base(Gp::kIdDx, off, size); }
+  inline Mem ptr_zbx(int32_t off = 0, uint32_t size = 0) const noexcept { return ptr_base(Gp::kIdBx, off, size); }
+  inline Mem ptr_zsp(int32_t off = 0, uint32_t size = 0) const noexcept { return ptr_base(Gp::kIdSp, off, size); }
+  inline Mem ptr_zbp(int32_t off = 0, uint32_t size = 0) const noexcept { return ptr_base(Gp::kIdBp, off, size); }
+  inline Mem ptr_zsi(int32_t off = 0, uint32_t size = 0) const noexcept { return ptr_base(Gp::kIdSi, off, size); }
+  inline Mem ptr_zdi(int32_t off = 0, uint32_t size = 0) const noexcept { return ptr_base(Gp::kIdDi, off, size); }
+
+  //! Creates an `intptr_t` memory operand depending on the current architecture.
+  inline Mem intptr_ptr(const Gp& base, int32_t offset = 0) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(base, offset, nativeGpSize);
+  }
+  //! \overload
+  inline Mem intptr_ptr(const Gp& base, const Gp& index, uint32_t shift = 0, int32_t offset = 0) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(base, index, shift, offset, nativeGpSize);
+  }
+  //! \overload
+  inline Mem intptr_ptr(const Gp& base, const Vec& index, uint32_t shift = 0, int32_t offset = 0) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(base, index, shift, offset, nativeGpSize);
+  }
+  //! \overload
+  inline Mem intptr_ptr(const Label& base, int32_t offset = 0) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(base, offset, nativeGpSize);
+  }
+  //! \overload
+  inline Mem intptr_ptr(const Label& base, const Gp& index, uint32_t shift, int32_t offset = 0) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(base, index, shift, offset, nativeGpSize);
+  }
+  //! \overload
+  inline Mem intptr_ptr(const Label& base, const Vec& index, uint32_t shift, int32_t offset = 0) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(base, index, shift, offset, nativeGpSize);
+  }
+  //! \overload
+  inline Mem intptr_ptr(const Rip& rip, int32_t offset = 0) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(rip, offset, nativeGpSize);
+  }
+  //! \overload
+  inline Mem intptr_ptr(uint64_t base) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(base, nativeGpSize);
+  }
+  //! \overload
+  inline Mem intptr_ptr(uint64_t base, const Gp& index, uint32_t shift = 0) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(base, index, shift, nativeGpSize);
+  }
+  //! \overload
+  inline Mem intptr_ptr_abs(uint64_t base) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(base, nativeGpSize, BaseMem::kSignatureMemAbs);
+  }
+  //! \overload
+  inline Mem intptr_ptr_abs(uint64_t base, const Gp& index, uint32_t shift = 0) const noexcept {
+    uint32_t nativeGpSize = _emitter()->registerSize();
+    return Mem(base, index, shift, nativeGpSize, BaseMem::kSignatureMemAbs);
+  }
+
+  //! \}
+
+  //! \name Embed
+  //! \{
+
+  //! Embeds 8-bit integer data.
+  inline Error db(uint8_t x, size_t repeatCount = 1) { return _emitter()->embedUInt8(x, repeatCount); }
+  //! Embeds 16-bit integer data.
+  inline Error dw(uint16_t x, size_t repeatCount = 1) { return _emitter()->embedUInt16(x, repeatCount); }
+  //! Embeds 32-bit integer data.
+  inline Error dd(uint32_t x, size_t repeatCount = 1) { return _emitter()->embedUInt32(x, repeatCount); }
+  //! Embeds 64-bit integer data.
+  inline Error dq(uint64_t x, size_t repeatCount = 1) { return _emitter()->embedUInt64(x, repeatCount); }
+
+#ifndef ASMJIT_NO_DEPRECATED
+  ASMJIT_DEPRECATED("Use embedInt8() instead of dint8()")
+  inline Error dint8(int8_t x) { return _emitter()->embed(&x, sizeof(int8_t)); }
+
+  ASMJIT_DEPRECATED("Use embedUInt8() instead of duint8()")
+  inline Error duint8(uint8_t x) { return _emitter()->embed(&x, sizeof(uint8_t)); }
+
+  ASMJIT_DEPRECATED("Use embedInt16() instead of dint16()")
+  inline Error dint16(int16_t x) { return _emitter()->embed(&x, sizeof(int16_t)); }
+
+  ASMJIT_DEPRECATED("Use embedUInt16() instead of duint16()")
+  inline Error duint16(uint16_t x) { return _emitter()->embed(&x, sizeof(uint16_t)); }
+
+  ASMJIT_DEPRECATED("Use embedInt32() instead of dint32()")
+  inline Error dint32(int32_t x) { return _emitter()->embed(&x, sizeof(int32_t)); }
+
+  ASMJIT_DEPRECATED("Use embedUInt32() instead of duint32()")
+  inline Error duint32(uint32_t x) { return _emitter()->embed(&x, sizeof(uint32_t)); }
+
+  ASMJIT_DEPRECATED("Use embedInt64() instead of dint64()")
+  inline Error dint64(int64_t x) { return _emitter()->embed(&x, sizeof(int64_t)); }
+
+  ASMJIT_DEPRECATED("Use embedUInt64() instead of duint64()")
+  inline Error duint64(uint64_t x) { return _emitter()->embed(&x, sizeof(uint64_t)); }
+
+  ASMJIT_DEPRECATED("Use embedFloat() instead of float()")
+  inline Error dfloat(float x) { return _emitter()->embed(&x, sizeof(float)); }
+
+  ASMJIT_DEPRECATED("Use embedDouble() instead of ddouble()")
+  inline Error ddouble(double x) { return _emitter()->embed(&x, sizeof(double)); }
+
+  ASMJIT_DEPRECATED("Use embed[U]IntN() or embed[Float|Double]() instead of dmm()")
+  inline Error dmm(const Data64& x) { return _emitter()->embed(&x, 8); }
+
+  ASMJIT_DEPRECATED("Use embed[U]IntN() or embed[Float|Double]() instead of dxmm()")
+  inline Error dxmm(const Data128& x) { return _emitter()->embed(&x, 16); }
+
+  ASMJIT_DEPRECATED("Use embed[U]IntN() or embed[Float|Double]() instead of dymm()")
+  inline Error dymm(const Data256& x) { return _emitter()->embed(&x, 32); }
+#endif // !ASMJIT_NO_DEPRECATED
+
+  //! Adds data in a given structure instance to the CodeBuffer.
+  template<typename T>
+  inline Error dstruct(const T& x) { return _emitter()->embed(&x, uint32_t(sizeof(T))); }
+
+  //! \}
+
+protected:
+  //! \cond
+  inline This& _addInstOptions(uint32_t options) noexcept {
+    _emitter()->addInstOptions(options);
+    return *_emitter();
+  }
+  //! \endcond
+
+public:
+  //! \name Short/Long Form Options
+  //! \{
+
+  //! Force short form of jmp/jcc instruction.
+  inline This& short_() noexcept { return _addInstOptions(Inst::kOptionShortForm); }
+  //! Force long form of jmp/jcc instruction.
+  inline This& long_() noexcept { return _addInstOptions(Inst::kOptionLongForm); }
+
+  //! \}
+
+  //! \name Encoding Options
+  //! \{
+
+  //! Prefer MOD_MR encoding over MOD_RM (the default) when encoding instruction
+  //! that allows both. This option is only applicable to instructions where both
+  //! operands are registers.
+  inline This& mod_mr() noexcept { return _addInstOptions(Inst::kOptionModMR); }
+
+  //! \}
+
+  //! \name Prefix Options
+  //! \{
+
+  //! Condition is likely to be taken (has only benefit on P4).
+  inline This& taken() noexcept { return _addInstOptions(Inst::kOptionTaken); }
+  //! Condition is unlikely to be taken (has only benefit on P4).
+  inline This& notTaken() noexcept { return _addInstOptions(Inst::kOptionNotTaken); }
+
+  //! Use LOCK prefix.
+  inline This& lock() noexcept { return _addInstOptions(Inst::kOptionLock); }
+  //! Use XACQUIRE prefix.
+  inline This& xacquire() noexcept { return _addInstOptions(Inst::kOptionXAcquire); }
+  //! Use XRELEASE prefix.
+  inline This& xrelease() noexcept { return _addInstOptions(Inst::kOptionXRelease); }
+
+  //! Use BND/REPNE prefix.
+  //!
+  //! \note This is the same as using `repne()` or `repnz()` prefix.
+  inline This& bnd() noexcept { return _addInstOptions(Inst::kOptionRepne); }
+
+  //! Use REP/REPZ prefix.
+  //!
+  //! \note This is the same as using `repe()` or `repz()` prefix.
+  inline This& rep(const Gp& zcx) noexcept {
+    _emitter()->_extraReg.init(zcx);
+    return _addInstOptions(Inst::kOptionRep);
+  }
+
+  //! Use REP/REPE prefix.
+  //!
+  //! \note This is the same as using `rep()` or `repz()` prefix.
+  inline This& repe(const Gp& zcx) noexcept { return rep(zcx); }
+
+  //! Use REP/REPE prefix.
+  //!
+  //! \note This is the same as using `rep()` or `repe()` prefix.
+  inline This& repz(const Gp& zcx) noexcept { return rep(zcx); }
+
+  //! Use REPNE prefix.
+  //!
+  //! \note This is the same as using `bnd()` or `repnz()` prefix.
+  inline This& repne(const Gp& zcx) noexcept {
+    _emitter()->_extraReg.init(zcx);
+    return _addInstOptions(Inst::kOptionRepne);
+  }
+
+  //! Use REPNE prefix.
+  //!
+  //! \note This is the same as using `bnd()` or `repne()` prefix.
+  inline This& repnz(const Gp& zcx) noexcept { return repne(zcx); }
+
+  //! \}
+
+  //! \name REX Options
+  //! \{
+
+  //! Force REX prefix to be emitted even when it's not needed (X86_64).
+  //!
+  //! \note Don't use when using high 8-bit registers as REX prefix makes them
+  //! inaccessible and `x86::Assembler` would fail to encode such instruction.
+  inline This& rex() noexcept { return _addInstOptions(Inst::kOptionRex); }
+
+  //! Force REX.B prefix (X64) [It exists for special purposes only].
+  inline This& rex_b() noexcept { return _addInstOptions(Inst::kOptionOpCodeB); }
+  //! Force REX.X prefix (X64) [It exists for special purposes only].
+  inline This& rex_x() noexcept { return _addInstOptions(Inst::kOptionOpCodeX); }
+  //! Force REX.R prefix (X64) [It exists for special purposes only].
+  inline This& rex_r() noexcept { return _addInstOptions(Inst::kOptionOpCodeR); }
+  //! Force REX.W prefix (X64) [It exists for special purposes only].
+  inline This& rex_w() noexcept { return _addInstOptions(Inst::kOptionOpCodeW); }
+
+  //! \}
+
+  //! \name VEX and EVEX Options
+  //! \{
+
+  //! Force 3-byte VEX prefix (AVX+).
+  inline This& vex3() noexcept { return _addInstOptions(Inst::kOptionVex3); }
+  //! Force 4-byte EVEX prefix (AVX512+).
+  inline This& evex() noexcept { return _addInstOptions(Inst::kOptionEvex); }
+
+  //! \}
+
+  //! \name AVX-512 Options & Masking
+  //! \{
+
+  //! Use masking {k} (AVX512+).
+  inline This& k(const KReg& kreg) noexcept {
+    _emitter()->_extraReg.init(kreg);
+    return *_emitter();
+  }
+
+  //! Use zeroing instead of merging (AVX512+).
+  inline This& z() noexcept { return _addInstOptions(Inst::kOptionZMask); }
+
+  //! Suppress all exceptions (AVX512+).
+  inline This& sae() noexcept { return _addInstOptions(Inst::kOptionSAE); }
+  //! Static rounding mode {rn} (round-to-nearest even) and {sae} (AVX512+).
+  inline This& rn_sae() noexcept { return _addInstOptions(Inst::kOptionER | Inst::kOptionRN_SAE); }
+  //! Static rounding mode {rd} (round-down, toward -inf) and {sae} (AVX512+).
+  inline This& rd_sae() noexcept { return _addInstOptions(Inst::kOptionER | Inst::kOptionRD_SAE); }
+  //! Static rounding mode {ru} (round-up, toward +inf) and {sae} (AVX512+).
+  inline This& ru_sae() noexcept { return _addInstOptions(Inst::kOptionER | Inst::kOptionRU_SAE); }
+  //! Static rounding mode {rz} (round-toward-zero, truncate) and {sae} (AVX512+).
+  inline This& rz_sae() noexcept { return _addInstOptions(Inst::kOptionER | Inst::kOptionRZ_SAE); }
+
+  //! \}
+
+  //! \name Core Instructions
+  //! \{
+
+  ASMJIT_INST_2x(adc, Adc, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(adc, Adc, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2i(adc, Adc, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2x(adc, Adc, Mem, Gp)                                    // ANY
+  ASMJIT_INST_2i(adc, Adc, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(add, Add, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(add, Add, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2i(add, Add, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2x(add, Add, Mem, Gp)                                    // ANY
+  ASMJIT_INST_2i(add, Add, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(and_, And, Gp, Gp)                                    // ANY
+  ASMJIT_INST_2x(and_, And, Gp, Mem)                                   // ANY
+  ASMJIT_INST_2i(and_, And, Gp, Imm)                                   // ANY
+  ASMJIT_INST_2x(and_, And, Mem, Gp)                                   // ANY
+  ASMJIT_INST_2i(and_, And, Mem, Imm)                                  // ANY
+  ASMJIT_INST_2x(bound, Bound, Gp, Mem)                                // X86
+  ASMJIT_INST_2x(bsf, Bsf, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(bsf, Bsf, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2x(bsr, Bsr, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(bsr, Bsr, Gp, Mem)                                    // ANY
+  ASMJIT_INST_1x(bswap, Bswap, Gp)                                     // ANY
+  ASMJIT_INST_2x(bt, Bt, Gp, Gp)                                       // ANY
+  ASMJIT_INST_2i(bt, Bt, Gp, Imm)                                      // ANY
+  ASMJIT_INST_2x(bt, Bt, Mem, Gp)                                      // ANY
+  ASMJIT_INST_2i(bt, Bt, Mem, Imm)                                     // ANY
+  ASMJIT_INST_2x(btc, Btc, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2i(btc, Btc, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2x(btc, Btc, Mem, Gp)                                    // ANY
+  ASMJIT_INST_2i(btc, Btc, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(btr, Btr, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2i(btr, Btr, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2x(btr, Btr, Mem, Gp)                                    // ANY
+  ASMJIT_INST_2i(btr, Btr, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(bts, Bts, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2i(bts, Bts, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2x(bts, Bts, Mem, Gp)                                    // ANY
+  ASMJIT_INST_2i(bts, Bts, Mem, Imm)                                   // ANY
+  ASMJIT_INST_1x(cbw, Cbw, AX)                                         // ANY [EXPLICIT] AX      <- Sign Extend AL
+  ASMJIT_INST_2x(cdq, Cdq, EDX, EAX)                                   // ANY [EXPLICIT] EDX:EAX <- Sign Extend EAX
+  ASMJIT_INST_1x(cdqe, Cdqe, EAX)                                      // X64 [EXPLICIT] RAX     <- Sign Extend EAX
+  ASMJIT_INST_2x(cqo, Cqo, RDX, RAX)                                   // X64 [EXPLICIT] RDX:RAX <- Sign Extend RAX
+  ASMJIT_INST_2x(cwd, Cwd, DX, AX)                                     // ANY [EXPLICIT] DX:AX   <- Sign Extend AX
+  ASMJIT_INST_1x(cwde, Cwde, EAX)                                      // ANY [EXPLICIT] EAX     <- Sign Extend AX
+  ASMJIT_INST_1x(call, Call, Gp)                                       // ANY
+  ASMJIT_INST_1x(call, Call, Mem)                                      // ANY
+  ASMJIT_INST_1x(call, Call, Label)                                    // ANY
+  ASMJIT_INST_1i(call, Call, Imm)                                      // ANY
+  ASMJIT_INST_2c(cmov, Cmov, Condition::toCmovcc, Gp, Gp)              // CMOV
+  ASMJIT_INST_2c(cmov, Cmov, Condition::toCmovcc, Gp, Mem)             // CMOV
+  ASMJIT_INST_2x(cmp, Cmp, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(cmp, Cmp, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2i(cmp, Cmp, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2x(cmp, Cmp, Mem, Gp)                                    // ANY
+  ASMJIT_INST_2i(cmp, Cmp, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(cmps, Cmps, DS_ZSI, ES_ZDI)                           // ANY [EXPLICIT]
+  ASMJIT_INST_3x(cmpxchg, Cmpxchg, Gp, Gp, ZAX)                        // I486 [EXPLICIT]
+  ASMJIT_INST_3x(cmpxchg, Cmpxchg, Mem, Gp, ZAX)                       // I486 [EXPLICIT]
+  ASMJIT_INST_5x(cmpxchg16b, Cmpxchg16b, Mem, RDX, RAX, RCX, RBX);     // CMPXCHG16B [EXPLICIT] m == EDX:EAX ? m <- ECX:EBX
+  ASMJIT_INST_5x(cmpxchg8b, Cmpxchg8b, Mem, EDX, EAX, ECX, EBX);       // CMPXCHG8B [EXPLICIT] m == RDX:RAX ? m <- RCX:RBX
+  ASMJIT_INST_1x(dec, Dec, Gp)                                         // ANY
+  ASMJIT_INST_1x(dec, Dec, Mem)                                        // ANY
+  ASMJIT_INST_2x(div, Div, Gp, Gp)                                     // ANY [EXPLICIT]  AH[Rem]: AL[Quot] <- AX / r8
+  ASMJIT_INST_2x(div, Div, Gp, Mem)                                    // ANY [EXPLICIT]  AH[Rem]: AL[Quot] <- AX / m8
+  ASMJIT_INST_3x(div, Div, Gp, Gp, Gp)                                 // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / r16|r32|r64
+  ASMJIT_INST_3x(div, Div, Gp, Gp, Mem)                                // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / m16|m32|m64
+  ASMJIT_INST_2x(idiv, Idiv, Gp, Gp)                                   // ANY [EXPLICIT]  AH[Rem]: AL[Quot] <- AX / r8
+  ASMJIT_INST_2x(idiv, Idiv, Gp, Mem)                                  // ANY [EXPLICIT]  AH[Rem]: AL[Quot] <- AX / m8
+  ASMJIT_INST_3x(idiv, Idiv, Gp, Gp, Gp)                               // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / r16|r32|r64
+  ASMJIT_INST_3x(idiv, Idiv, Gp, Gp, Mem)                              // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / m16|m32|m64
+  ASMJIT_INST_2x(imul, Imul, Gp, Gp)                                   // ANY [EXPLICIT] AX <- AL * r8 | ra <- ra * rb
+  ASMJIT_INST_2x(imul, Imul, Gp, Mem)                                  // ANY [EXPLICIT] AX <- AL * m8 | ra <- ra * m16|m32|m64
+  ASMJIT_INST_2i(imul, Imul, Gp, Imm)                                  // ANY
+  ASMJIT_INST_3i(imul, Imul, Gp, Gp, Imm)                              // ANY
+  ASMJIT_INST_3i(imul, Imul, Gp, Mem, Imm)                             // ANY
+  ASMJIT_INST_3x(imul, Imul, Gp, Gp, Gp)                               // ANY [EXPLICIT] xDX:xAX <- xAX * r16|r32|r64
+  ASMJIT_INST_3x(imul, Imul, Gp, Gp, Mem)                              // ANY [EXPLICIT] xDX:xAX <- xAX * m16|m32|m64
+  ASMJIT_INST_1x(inc, Inc, Gp)                                         // ANY
+  ASMJIT_INST_1x(inc, Inc, Mem)                                        // ANY
+  ASMJIT_INST_1c(j, J, Condition::toJcc, Label)                        // ANY
+  ASMJIT_INST_1c(j, J, Condition::toJcc, Imm)                          // ANY
+  ASMJIT_INST_1c(j, J, Condition::toJcc, uint64_t)                     // ANY
+  ASMJIT_INST_2x(jecxz, Jecxz, Gp, Label)                              // ANY [EXPLICIT] Short jump if CX/ECX/RCX is zero.
+  ASMJIT_INST_2x(jecxz, Jecxz, Gp, Imm)                                // ANY [EXPLICIT] Short jump if CX/ECX/RCX is zero.
+  ASMJIT_INST_2x(jecxz, Jecxz, Gp, uint64_t)                           // ANY [EXPLICIT] Short jump if CX/ECX/RCX is zero.
+  ASMJIT_INST_1x(jmp, Jmp, Gp)                                         // ANY
+  ASMJIT_INST_1x(jmp, Jmp, Mem)                                        // ANY
+  ASMJIT_INST_1x(jmp, Jmp, Label)                                      // ANY
+  ASMJIT_INST_1x(jmp, Jmp, Imm)                                        // ANY
+  ASMJIT_INST_1x(jmp, Jmp, uint64_t)                                   // ANY
+  ASMJIT_INST_2x(lea, Lea, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2x(lods, Lods, ZAX, DS_ZSI)                              // ANY [EXPLICIT]
+  ASMJIT_INST_2x(loop, Loop, ZCX, Label)                               // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0.
+  ASMJIT_INST_2x(loop, Loop, ZCX, Imm)                                 // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0.
+  ASMJIT_INST_2x(loop, Loop, ZCX, uint64_t)                            // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0.
+  ASMJIT_INST_2x(loope, Loope, ZCX, Label)                             // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
+  ASMJIT_INST_2x(loope, Loope, ZCX, Imm)                               // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
+  ASMJIT_INST_2x(loope, Loope, ZCX, uint64_t)                          // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
+  ASMJIT_INST_2x(loopne, Loopne, ZCX, Label)                           // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
+  ASMJIT_INST_2x(loopne, Loopne, ZCX, Imm)                             // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
+  ASMJIT_INST_2x(loopne, Loopne, ZCX, uint64_t)                        // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
+  ASMJIT_INST_2x(mov, Mov, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(mov, Mov, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2i(mov, Mov, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2x(mov, Mov, Mem, Gp)                                    // ANY
+  ASMJIT_INST_2i(mov, Mov, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(mov, Mov, Gp, CReg)                                   // ANY
+  ASMJIT_INST_2x(mov, Mov, CReg, Gp)                                   // ANY
+  ASMJIT_INST_2x(mov, Mov, Gp, DReg)                                   // ANY
+  ASMJIT_INST_2x(mov, Mov, DReg, Gp)                                   // ANY
+  ASMJIT_INST_2x(mov, Mov, Gp, SReg)                                   // ANY
+  ASMJIT_INST_2x(mov, Mov, Mem, SReg)                                  // ANY
+  ASMJIT_INST_2x(mov, Mov, SReg, Gp)                                   // ANY
+  ASMJIT_INST_2x(mov, Mov, SReg, Mem)                                  // ANY
+  ASMJIT_INST_2x(movnti, Movnti, Mem, Gp)                              // SSE2
+  ASMJIT_INST_2x(movs, Movs, ES_ZDI, DS_ZSI)                           // ANY [EXPLICIT]
+  ASMJIT_INST_2x(movsx, Movsx, Gp, Gp)                                 // ANY
+  ASMJIT_INST_2x(movsx, Movsx, Gp, Mem)                                // ANY
+  ASMJIT_INST_2x(movsxd, Movsxd, Gp, Gp)                               // X64
+  ASMJIT_INST_2x(movsxd, Movsxd, Gp, Mem)                              // X64
+  ASMJIT_INST_2x(movzx, Movzx, Gp, Gp)                                 // ANY
+  ASMJIT_INST_2x(movzx, Movzx, Gp, Mem)                                // ANY
+  ASMJIT_INST_2x(mul, Mul, AX, Gp)                                     // ANY [EXPLICIT] AX      <-  AL * r8
+  ASMJIT_INST_2x(mul, Mul, AX, Mem)                                    // ANY [EXPLICIT] AX      <-  AL * m8
+  ASMJIT_INST_3x(mul, Mul, ZDX, ZAX, Gp)                               // ANY [EXPLICIT] xDX:xAX <- xAX * r16|r32|r64
+  ASMJIT_INST_3x(mul, Mul, ZDX, ZAX, Mem)                              // ANY [EXPLICIT] xDX:xAX <- xAX * m16|m32|m64
+  ASMJIT_INST_1x(neg, Neg, Gp)                                         // ANY
+  ASMJIT_INST_1x(neg, Neg, Mem)                                        // ANY
+  ASMJIT_INST_0x(nop, Nop)                                             // ANY
+  ASMJIT_INST_1x(nop, Nop, Gp)                                         // ANY
+  ASMJIT_INST_1x(nop, Nop, Mem)                                        // ANY
+  ASMJIT_INST_2x(nop, Nop, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(nop, Nop, Mem, Gp)                                    // ANY
+  ASMJIT_INST_1x(not_, Not, Gp)                                        // ANY
+  ASMJIT_INST_1x(not_, Not, Mem)                                       // ANY
+  ASMJIT_INST_2x(or_, Or, Gp, Gp)                                      // ANY
+  ASMJIT_INST_2x(or_, Or, Gp, Mem)                                     // ANY
+  ASMJIT_INST_2i(or_, Or, Gp, Imm)                                     // ANY
+  ASMJIT_INST_2x(or_, Or, Mem, Gp)                                     // ANY
+  ASMJIT_INST_2i(or_, Or, Mem, Imm)                                    // ANY
+  ASMJIT_INST_1x(pop, Pop, Gp)                                         // ANY
+  ASMJIT_INST_1x(pop, Pop, Mem)                                        // ANY
+  ASMJIT_INST_1x(pop, Pop, SReg);                                      // ANY
+  ASMJIT_INST_0x(popa, Popa)                                           // X86
+  ASMJIT_INST_0x(popad, Popad)                                         // X86
+  ASMJIT_INST_0x(popf, Popf)                                           // ANY
+  ASMJIT_INST_0x(popfd, Popfd)                                         // X86
+  ASMJIT_INST_0x(popfq, Popfq)                                         // X64
+  ASMJIT_INST_1x(push, Push, Gp)                                       // ANY
+  ASMJIT_INST_1x(push, Push, Mem)                                      // ANY
+  ASMJIT_INST_1x(push, Push, SReg)                                     // ANY
+  ASMJIT_INST_1i(push, Push, Imm)                                      // ANY
+  ASMJIT_INST_0x(pusha, Pusha)                                         // X86
+  ASMJIT_INST_0x(pushad, Pushad)                                       // X86
+  ASMJIT_INST_0x(pushf, Pushf)                                         // ANY
+  ASMJIT_INST_0x(pushfd, Pushfd)                                       // X86
+  ASMJIT_INST_0x(pushfq, Pushfq)                                       // X64
+  ASMJIT_INST_2x(rcl, Rcl, Gp, CL)                                     // ANY
+  ASMJIT_INST_2x(rcl, Rcl, Mem, CL)                                    // ANY
+  ASMJIT_INST_2i(rcl, Rcl, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2i(rcl, Rcl, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(rcr, Rcr, Gp, CL)                                     // ANY
+  ASMJIT_INST_2x(rcr, Rcr, Mem, CL)                                    // ANY
+  ASMJIT_INST_2i(rcr, Rcr, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2i(rcr, Rcr, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(rol, Rol, Gp, CL)                                     // ANY
+  ASMJIT_INST_2x(rol, Rol, Mem, CL)                                    // ANY
+  ASMJIT_INST_2i(rol, Rol, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2i(rol, Rol, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(ror, Ror, Gp, CL)                                     // ANY
+  ASMJIT_INST_2x(ror, Ror, Mem, CL)                                    // ANY
+  ASMJIT_INST_2i(ror, Ror, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2i(ror, Ror, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(sbb, Sbb, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(sbb, Sbb, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2i(sbb, Sbb, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2x(sbb, Sbb, Mem, Gp)                                    // ANY
+  ASMJIT_INST_2i(sbb, Sbb, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(sal, Sal, Gp, CL)                                     // ANY
+  ASMJIT_INST_2x(sal, Sal, Mem, CL)                                    // ANY
+  ASMJIT_INST_2i(sal, Sal, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2i(sal, Sal, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(sar, Sar, Gp, CL)                                     // ANY
+  ASMJIT_INST_2x(sar, Sar, Mem, CL)                                    // ANY
+  ASMJIT_INST_2i(sar, Sar, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2i(sar, Sar, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(scas, Scas, ZAX, ES_ZDI)                              // ANY [EXPLICIT]
+  ASMJIT_INST_1c(set, Set, Condition::toSetcc, Gp)                     // ANY
+  ASMJIT_INST_1c(set, Set, Condition::toSetcc, Mem)                    // ANY
+  ASMJIT_INST_2x(shl, Shl, Gp, CL)                                     // ANY
+  ASMJIT_INST_2x(shl, Shl, Mem, CL)                                    // ANY
+  ASMJIT_INST_2i(shl, Shl, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2i(shl, Shl, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(shr, Shr, Gp, CL)                                     // ANY
+  ASMJIT_INST_2x(shr, Shr, Mem, CL)                                    // ANY
+  ASMJIT_INST_2i(shr, Shr, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2i(shr, Shr, Mem, Imm)                                   // ANY
+  ASMJIT_INST_3x(shld, Shld, Gp, Gp, CL)                               // ANY
+  ASMJIT_INST_3x(shld, Shld, Mem, Gp, CL)                              // ANY
+  ASMJIT_INST_3i(shld, Shld, Gp, Gp, Imm)                              // ANY
+  ASMJIT_INST_3i(shld, Shld, Mem, Gp, Imm)                             // ANY
+  ASMJIT_INST_3x(shrd, Shrd, Gp, Gp, CL)                               // ANY
+  ASMJIT_INST_3x(shrd, Shrd, Mem, Gp, CL)                              // ANY
+  ASMJIT_INST_3i(shrd, Shrd, Gp, Gp, Imm)                              // ANY
+  ASMJIT_INST_3i(shrd, Shrd, Mem, Gp, Imm)                             // ANY
+  ASMJIT_INST_2x(stos, Stos, ES_ZDI, ZAX)                              // ANY [EXPLICIT]
+  ASMJIT_INST_2x(sub, Sub, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(sub, Sub, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2i(sub, Sub, Gp, Imm)                                    // ANY
+  ASMJIT_INST_2x(sub, Sub, Mem, Gp)                                    // ANY
+  ASMJIT_INST_2i(sub, Sub, Mem, Imm)                                   // ANY
+  ASMJIT_INST_2x(test, Test, Gp, Gp)                                   // ANY
+  ASMJIT_INST_2i(test, Test, Gp, Imm)                                  // ANY
+  ASMJIT_INST_2x(test, Test, Mem, Gp)                                  // ANY
+  ASMJIT_INST_2i(test, Test, Mem, Imm)                                 // ANY
+  ASMJIT_INST_1x(ud0, Ud0, Reg)                                        // ANY
+  ASMJIT_INST_1x(ud0, Ud0, Mem)                                        // ANY
+  ASMJIT_INST_1x(ud1, Ud1, Reg)                                        // ANY
+  ASMJIT_INST_1x(ud1, Ud1, Mem)                                        // ANY
+  ASMJIT_INST_0x(ud2, Ud2)                                             // ANY
+  ASMJIT_INST_2x(xadd, Xadd, Gp, Gp)                                   // ANY
+  ASMJIT_INST_2x(xadd, Xadd, Mem, Gp)                                  // ANY
+  ASMJIT_INST_2x(xchg, Xchg, Gp, Gp)                                   // ANY
+  ASMJIT_INST_2x(xchg, Xchg, Mem, Gp)                                  // ANY
+  ASMJIT_INST_2x(xchg, Xchg, Gp, Mem)                                  // ANY
+  ASMJIT_INST_2x(xor_, Xor, Gp, Gp)                                    // ANY
+  ASMJIT_INST_2x(xor_, Xor, Gp, Mem)                                   // ANY
+  ASMJIT_INST_2i(xor_, Xor, Gp, Imm)                                   // ANY
+  ASMJIT_INST_2x(xor_, Xor, Mem, Gp)                                   // ANY
+  ASMJIT_INST_2i(xor_, Xor, Mem, Imm)                                  // ANY
+
+  //! \}
+
+  //! \name Deprecated 32-bit Instructions
+  //! \{
+
+  ASMJIT_INST_1x(aaa, Aaa, Gp)                                         // X86 [EXPLICIT]
+  ASMJIT_INST_2i(aad, Aad, Gp, Imm)                                    // X86 [EXPLICIT]
+  ASMJIT_INST_2i(aam, Aam, Gp, Imm)                                    // X86 [EXPLICIT]
+  ASMJIT_INST_1x(aas, Aas, Gp)                                         // X86 [EXPLICIT]
+  ASMJIT_INST_1x(daa, Daa, Gp)                                         // X86 [EXPLICIT]
+  ASMJIT_INST_1x(das, Das, Gp)                                         // X86 [EXPLICIT]
+
+  //! \}
+
+  //! \name ENTER/LEAVE Instructions
+  //! \{
+
+  ASMJIT_INST_2x(enter, Enter, Imm, Imm)                               // ANY
+  ASMJIT_INST_0x(leave, Leave)                                         // ANY
+
+  //! \}
+
+  //! \name IN/OUT Instructions
+  //! \{
+
+  // NOTE: For some reason Doxygen is messed up here and thinks we are in cond.
+  //! \endcond
+
+  ASMJIT_INST_2i(in, In, ZAX, Imm)                                     // ANY
+  ASMJIT_INST_2x(in, In, ZAX, DX)                                      // ANY
+  ASMJIT_INST_2x(ins, Ins, ES_ZDI, DX)                                 // ANY
+  ASMJIT_INST_2x(out, Out, Imm, ZAX)                                   // ANY
+  ASMJIT_INST_2i(out, Out, DX, ZAX)                                    // ANY
+  ASMJIT_INST_2i(outs, Outs, DX, DS_ZSI)                               // ANY
+
+  //! \}
+
+  //! \name Clear/Set CF/DF Instructions
+  //! \{
+
+  ASMJIT_INST_0x(clc, Clc)                                             // ANY
+  ASMJIT_INST_0x(cld, Cld)                                             // ANY
+  ASMJIT_INST_0x(cmc, Cmc)                                             // ANY
+  ASMJIT_INST_0x(stc, Stc)                                             // ANY
+  ASMJIT_INST_0x(std, Std)                                             // ANY
+
+  //! \}
+
+  //! \name LAHF/SAHF Instructions
+  //! \{
+
+  ASMJIT_INST_1x(lahf, Lahf, AH)                                       // LAHFSAHF [EXPLICIT] AH <- EFL
+  ASMJIT_INST_1x(sahf, Sahf, AH)                                       // LAHFSAHF [EXPLICIT] EFL <- AH
+
+  //! \}
+
+  //! \name ADX Instructions
+  //! \{
+
+  ASMJIT_INST_2x(adcx, Adcx, Gp, Gp)                                   // ADX
+  ASMJIT_INST_2x(adcx, Adcx, Gp, Mem)                                  // ADX
+  ASMJIT_INST_2x(adox, Adox, Gp, Gp)                                   // ADX
+  ASMJIT_INST_2x(adox, Adox, Gp, Mem)                                  // ADX
+
+  //! \}
+
+  //! \name LZCNT/POPCNT Instructions
+  //! \{
+
+  ASMJIT_INST_2x(lzcnt, Lzcnt, Gp, Gp)                                 // LZCNT
+  ASMJIT_INST_2x(lzcnt, Lzcnt, Gp, Mem)                                // LZCNT
+  ASMJIT_INST_2x(popcnt, Popcnt, Gp, Gp)                               // POPCNT
+  ASMJIT_INST_2x(popcnt, Popcnt, Gp, Mem)                              // POPCNT
+
+  //! \}
+
+  //! \name BMI Instructions
+  //! \{
+
+  ASMJIT_INST_3x(andn, Andn, Gp, Gp, Gp)                               // BMI
+  ASMJIT_INST_3x(andn, Andn, Gp, Gp, Mem)                              // BMI
+  ASMJIT_INST_3x(bextr, Bextr, Gp, Gp, Gp)                             // BMI
+  ASMJIT_INST_3x(bextr, Bextr, Gp, Mem, Gp)                            // BMI
+  ASMJIT_INST_2x(blsi, Blsi, Gp, Gp)                                   // BMI
+  ASMJIT_INST_2x(blsi, Blsi, Gp, Mem)                                  // BMI
+  ASMJIT_INST_2x(blsmsk, Blsmsk, Gp, Gp)                               // BMI
+  ASMJIT_INST_2x(blsmsk, Blsmsk, Gp, Mem)                              // BMI
+  ASMJIT_INST_2x(blsr, Blsr, Gp, Gp)                                   // BMI
+  ASMJIT_INST_2x(blsr, Blsr, Gp, Mem)                                  // BMI
+  ASMJIT_INST_2x(tzcnt, Tzcnt, Gp, Gp)                                 // BMI
+  ASMJIT_INST_2x(tzcnt, Tzcnt, Gp, Mem)                                // BMI
+
+  //! \}
+
+  //! \name BMI2 Instructions
+  //! \{
+
+  ASMJIT_INST_3x(bzhi, Bzhi, Gp, Gp, Gp)                               // BMI2
+  ASMJIT_INST_3x(bzhi, Bzhi, Gp, Mem, Gp)                              // BMI2
+  ASMJIT_INST_4x(mulx, Mulx, Gp, Gp, Gp, ZDX)                          // BMI2      [EXPLICIT]
+  ASMJIT_INST_4x(mulx, Mulx, Gp, Gp, Mem, ZDX)                         // BMI2      [EXPLICIT]
+  ASMJIT_INST_3x(pdep, Pdep, Gp, Gp, Gp)                               // BMI2
+  ASMJIT_INST_3x(pdep, Pdep, Gp, Gp, Mem)                              // BMI2
+  ASMJIT_INST_3x(pext, Pext, Gp, Gp, Gp)                               // BMI2
+  ASMJIT_INST_3x(pext, Pext, Gp, Gp, Mem)                              // BMI2
+  ASMJIT_INST_3i(rorx, Rorx, Gp, Gp, Imm)                              // BMI2
+  ASMJIT_INST_3i(rorx, Rorx, Gp, Mem, Imm)                             // BMI2
+  ASMJIT_INST_3x(sarx, Sarx, Gp, Gp, Gp)                               // BMI2
+  ASMJIT_INST_3x(sarx, Sarx, Gp, Mem, Gp)                              // BMI2
+  ASMJIT_INST_3x(shlx, Shlx, Gp, Gp, Gp)                               // BMI2
+  ASMJIT_INST_3x(shlx, Shlx, Gp, Mem, Gp)                              // BMI2
+  ASMJIT_INST_3x(shrx, Shrx, Gp, Gp, Gp)                               // BMI2
+  ASMJIT_INST_3x(shrx, Shrx, Gp, Mem, Gp)                              // BMI2
+
+  //! \}
+
+  //! \name TBM Instructions
+  //! \{
+
+  ASMJIT_INST_2x(blcfill, Blcfill, Gp, Gp)                             // TBM
+  ASMJIT_INST_2x(blcfill, Blcfill, Gp, Mem)                            // TBM
+  ASMJIT_INST_2x(blci, Blci, Gp, Gp)                                   // TBM
+  ASMJIT_INST_2x(blci, Blci, Gp, Mem)                                  // TBM
+  ASMJIT_INST_2x(blcic, Blcic, Gp, Gp)                                 // TBM
+  ASMJIT_INST_2x(blcic, Blcic, Gp, Mem)                                // TBM
+  ASMJIT_INST_2x(blcmsk, Blcmsk, Gp, Gp)                               // TBM
+  ASMJIT_INST_2x(blcmsk, Blcmsk, Gp, Mem)                              // TBM
+  ASMJIT_INST_2x(blcs, Blcs, Gp, Gp)                                   // TBM
+  ASMJIT_INST_2x(blcs, Blcs, Gp, Mem)                                  // TBM
+  ASMJIT_INST_2x(blsfill, Blsfill, Gp, Gp)                             // TBM
+  ASMJIT_INST_2x(blsfill, Blsfill, Gp, Mem)                            // TBM
+  ASMJIT_INST_2x(blsic, Blsic, Gp, Gp)                                 // TBM
+  ASMJIT_INST_2x(blsic, Blsic, Gp, Mem)                                // TBM
+  ASMJIT_INST_2x(t1mskc, T1mskc, Gp, Gp)                               // TBM
+  ASMJIT_INST_2x(t1mskc, T1mskc, Gp, Mem)                              // TBM
+  ASMJIT_INST_2x(tzmsk, Tzmsk, Gp, Gp)                                 // TBM
+  ASMJIT_INST_2x(tzmsk, Tzmsk, Gp, Mem)                                // TBM
+
+  //! \}
+
+  //! \name CRC32 Instructions (SSE4.2)
+  //! \{
+
+  ASMJIT_INST_2x(crc32, Crc32, Gp, Gp)                                 // SSE4_2
+  ASMJIT_INST_2x(crc32, Crc32, Gp, Mem)                                // SSE4_2
+
+  //! \}
+
+  //! \name MOVBE Instructions
+  //! \{
+
+  ASMJIT_INST_2x(movbe, Movbe, Gp, Mem)                                // MOVBE
+  ASMJIT_INST_2x(movbe, Movbe, Mem, Gp)                                // MOVBE
+
+  //! \}
+
+  //! \name MOVDIRI & MOVDIR64B Instructions
+  //! \{
+
+  ASMJIT_INST_2x(movdiri, Movdiri, Mem, Gp)                            // MOVDIRI
+  ASMJIT_INST_2x(movdir64b, Movdir64b, Mem, Mem)                       // MOVDIR64B
+
+  //! \}
+
+  //! \name MXCSR Instructions (SSE)
+  //! \{
+
+  ASMJIT_INST_1x(ldmxcsr, Ldmxcsr, Mem)                                // SSE
+  ASMJIT_INST_1x(stmxcsr, Stmxcsr, Mem)                                // SSE
+
+  //! \}
+
+  //! \name FENCE Instructions (SSE and SSE2)
+  //! \{
+
+  ASMJIT_INST_0x(lfence, Lfence)                                       // SSE2
+  ASMJIT_INST_0x(mfence, Mfence)                                       // SSE2
+  ASMJIT_INST_0x(sfence, Sfence)                                       // SSE
+
+  //! \}
+
+  //! \name PREFETCH Instructions
+  //! \{
+
+  ASMJIT_INST_1x(prefetch, Prefetch, Mem)                              // 3DNOW
+  ASMJIT_INST_1x(prefetchnta, Prefetchnta, Mem)                        // SSE
+  ASMJIT_INST_1x(prefetcht0, Prefetcht0, Mem)                          // SSE
+  ASMJIT_INST_1x(prefetcht1, Prefetcht1, Mem)                          // SSE
+  ASMJIT_INST_1x(prefetcht2, Prefetcht2, Mem)                          // SSE
+  ASMJIT_INST_1x(prefetchw, Prefetchw, Mem)                            // PREFETCHW
+  ASMJIT_INST_1x(prefetchwt1, Prefetchwt1, Mem)                        // PREFETCHW1
+
+  //! \}
+
+  //! \name CPUID Instruction
+  //! \{
+
+  ASMJIT_INST_4x(cpuid, Cpuid, EAX, EBX, ECX, EDX)                     // I486 [EXPLICIT] EAX:EBX:ECX:EDX <- CPUID[EAX:ECX]
+
+  //! \}
+
+  //! \name CacheLine Instructions
+  //! \{
+
+  ASMJIT_INST_1x(cldemote, Cldemote, Mem)                              // CLDEMOTE
+  ASMJIT_INST_1x(clflush, Clflush, Mem)                                // CLFLUSH
+  ASMJIT_INST_1x(clflushopt, Clflushopt, Mem)                          // CLFLUSH_OPT
+  ASMJIT_INST_1x(clwb, Clwb, Mem)                                      // CLWB
+  ASMJIT_INST_1x(clzero, Clzero, DS_ZAX)                               // CLZERO [EXPLICIT]
+
+  //! \}
+
+  //! \name SERIALIZE Instruction
+  //! \{
+
+  ASMJIT_INST_0x(serialize, Serialize)                                 // SERIALIZE
+
+  //! \}
+
+  //! \name RDPID Instruction
+  //! \{
+
+  ASMJIT_INST_1x(rdpid, Rdpid, Gp)                                     // RDPID
+
+  //! \}
+
+  //! \name RDPRU/RDPKRU Instructions
+  //! \{
+
+  ASMJIT_INST_3x(rdpru, Rdpru, EDX, EAX, ECX)                          // RDPRU     [EXPLICIT] EDX:EAX <- PRU[ECX]
+  ASMJIT_INST_3x(rdpkru, Rdpkru, EDX, EAX, ECX)                        // RDPKRU    [EXPLICIT] EDX:EAX <- PKRU[ECX]
+
+  //! \}
+
+  //! \name RDTSC/RDTSCP Instructions
+  //! \{
+
+  ASMJIT_INST_2x(rdtsc, Rdtsc, EDX, EAX)                               // RDTSC     [EXPLICIT] EDX:EAX     <- Counter
+  ASMJIT_INST_3x(rdtscp, Rdtscp, EDX, EAX, ECX)                        // RDTSCP    [EXPLICIT] EDX:EAX:EXC <- Counter
+
+  //! \}
+
+  //! \name Other User-Mode Instructions
+  //! \{
+
+  ASMJIT_INST_2x(arpl, Arpl, Gp, Gp)                                   // X86
+  ASMJIT_INST_2x(arpl, Arpl, Mem, Gp)                                  // X86
+  ASMJIT_INST_0x(cli, Cli)                                             // ANY
+  ASMJIT_INST_0x(getsec, Getsec)                                       // SMX
+  ASMJIT_INST_1i(int_, Int, Imm)                                       // ANY
+  ASMJIT_INST_0x(int3, Int3)                                           // ANY
+  ASMJIT_INST_0x(into, Into)                                           // ANY
+  ASMJIT_INST_2x(lar, Lar, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(lar, Lar, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2x(lds, Lds, Gp, Mem)                                    // X86
+  ASMJIT_INST_2x(les, Les, Gp, Mem)                                    // X86
+  ASMJIT_INST_2x(lfs, Lfs, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2x(lgs, Lgs, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2x(lsl, Lsl, Gp, Gp)                                     // ANY
+  ASMJIT_INST_2x(lsl, Lsl, Gp, Mem)                                    // ANY
+  ASMJIT_INST_2x(lss, Lss, Gp, Mem)                                    // ANY
+  ASMJIT_INST_0x(pause, Pause)                                         // SSE2
+  ASMJIT_INST_0x(rsm, Rsm)                                             // X86
+  ASMJIT_INST_1x(sgdt, Sgdt, Mem)                                      // ANY
+  ASMJIT_INST_1x(sidt, Sidt, Mem)                                      // ANY
+  ASMJIT_INST_1x(sldt, Sldt, Gp)                                       // ANY
+  ASMJIT_INST_1x(sldt, Sldt, Mem)                                      // ANY
+  ASMJIT_INST_1x(smsw, Smsw, Gp)                                       // ANY
+  ASMJIT_INST_1x(smsw, Smsw, Mem)                                      // ANY
+  ASMJIT_INST_0x(sti, Sti)                                             // ANY
+  ASMJIT_INST_1x(str, Str, Gp)                                         // ANY
+  ASMJIT_INST_1x(str, Str, Mem)                                        // ANY
+  ASMJIT_INST_1x(verr, Verr, Gp)                                       // ANY
+  ASMJIT_INST_1x(verr, Verr, Mem)                                      // ANY
+  ASMJIT_INST_1x(verw, Verw, Gp)                                       // ANY
+  ASMJIT_INST_1x(verw, Verw, Mem)                                      // ANY
+
+  //! \}
+
+  //! \name FSGSBASE Instructions
+  //! \{
+
+  ASMJIT_INST_1x(rdfsbase, Rdfsbase, Gp)                               // FSGSBASE
+  ASMJIT_INST_1x(rdgsbase, Rdgsbase, Gp)                               // FSGSBASE
+  ASMJIT_INST_1x(wrfsbase, Wrfsbase, Gp)                               // FSGSBASE
+  ASMJIT_INST_1x(wrgsbase, Wrgsbase, Gp)                               // FSGSBASE
+
+  //! \}
+
+  //! \name FXSR Instructions
+  //! \{
+
+  ASMJIT_INST_1x(fxrstor, Fxrstor, Mem)                                // FXSR
+  ASMJIT_INST_1x(fxrstor64, Fxrstor64, Mem)                            // FXSR
+  ASMJIT_INST_1x(fxsave, Fxsave, Mem)                                  // FXSR
+  ASMJIT_INST_1x(fxsave64, Fxsave64, Mem)                              // FXSR
+
+  //! \}
+
+  //! \name XSAVE Instructions
+  //! \{
+
+  ASMJIT_INST_3x(xgetbv, Xgetbv, EDX, EAX, ECX)                        // XSAVE [EXPLICIT] EDX:EAX <- XCR[ECX]
+
+  //! \}
+
+  //! \name MPX Extensions
+  //! \{
+
+  ASMJIT_INST_2x(bndcl, Bndcl, Bnd, Gp)                                // MPX
+  ASMJIT_INST_2x(bndcl, Bndcl, Bnd, Mem)                               // MPX
+  ASMJIT_INST_2x(bndcn, Bndcn, Bnd, Gp)                                // MPX
+  ASMJIT_INST_2x(bndcn, Bndcn, Bnd, Mem)                               // MPX
+  ASMJIT_INST_2x(bndcu, Bndcu, Bnd, Gp)                                // MPX
+  ASMJIT_INST_2x(bndcu, Bndcu, Bnd, Mem)                               // MPX
+  ASMJIT_INST_2x(bndldx, Bndldx, Bnd, Mem)                             // MPX
+  ASMJIT_INST_2x(bndmk, Bndmk, Bnd, Mem)                               // MPX
+  ASMJIT_INST_2x(bndmov, Bndmov, Bnd, Bnd)                             // MPX
+  ASMJIT_INST_2x(bndmov, Bndmov, Bnd, Mem)                             // MPX
+  ASMJIT_INST_2x(bndmov, Bndmov, Mem, Bnd)                             // MPX
+  ASMJIT_INST_2x(bndstx, Bndstx, Mem, Bnd)                             // MPX
+
+  //! \}
+
+  //! \name MONITORX Instructions
+  //! \{
+
+  ASMJIT_INST_3x(monitorx, Monitorx, Mem, Gp, Gp)
+  ASMJIT_INST_3x(mwaitx, Mwaitx, Gp, Gp, Gp)
+
+  //! \}
+
+  //! \name MCOMMIT Instruction
+  //! \{
+
+  ASMJIT_INST_0x(mcommit, Mcommit)                                     // MCOMMIT
+
+  //! \}
+
+  //! \name PTWRITE Instruction
+  //! \{
+
+  ASMJIT_INST_1x(ptwrite, Ptwrite, Gp)                                 // PTWRITE
+  ASMJIT_INST_1x(ptwrite, Ptwrite, Mem)                                // PTWRITE
+
+  //! \}
+
+  //! \name ENQCMD Instructions
+  //! \{
+
+  ASMJIT_INST_2x(enqcmd, Enqcmd, Mem, Mem)                             // ENQCMD
+  ASMJIT_INST_2x(enqcmds, Enqcmds, Mem, Mem)                           // ENQCMD
+
+  //! \}
+
+  //! \name WAITPKG Instructions
+  //! \{
+
+  ASMJIT_INST_3x(tpause, Tpause, Gp, Gp, Gp)
+  ASMJIT_INST_1x(umonitor, Umonitor, Mem)
+  ASMJIT_INST_3x(umwait, Umwait, Gp, Gp, Gp)
+
+  //! \}
+
+  //! \name RDRAND & RDSEED Instructions
+  //! \{
+
+  ASMJIT_INST_1x(rdrand, Rdrand, Gp)                                   // RDRAND
+  ASMJIT_INST_1x(rdseed, Rdseed, Gp)                                   // RDSEED
+
+  //! \}
+
+  //! \name LWP Instructions
+  //! \{
+
+  ASMJIT_INST_1x(llwpcb, Llwpcb, Gp)                                   // LWP
+  ASMJIT_INST_3i(lwpins, Lwpins, Gp, Gp, Imm)                          // LWP
+  ASMJIT_INST_3i(lwpins, Lwpins, Gp, Mem, Imm)                         // LWP
+  ASMJIT_INST_3i(lwpval, Lwpval, Gp, Gp, Imm)                          // LWP
+  ASMJIT_INST_3i(lwpval, Lwpval, Gp, Mem, Imm)                         // LWP
+  ASMJIT_INST_1x(slwpcb, Slwpcb, Gp)                                   // LWP
+
+  //! \}
+
+  //! \name RTM & TSX Instructions
+  //! \{
+
+  ASMJIT_INST_0x(xabort, Xabort)                                       // RTM
+  ASMJIT_INST_1x(xbegin, Xbegin, Label)                                // RTM
+  ASMJIT_INST_1x(xbegin, Xbegin, Imm)                                  // RTM
+  ASMJIT_INST_1x(xbegin, Xbegin, uint64_t)                             // RTM
+  ASMJIT_INST_0x(xend, Xend)                                           // RTM
+  ASMJIT_INST_0x(xtest, Xtest)                                         // TSX
+
+  //! \}
+
+  //! \name TSXLDTRK Instructions
+  //! \{
+
+  ASMJIT_INST_0x(xresldtrk, Xresldtrk)
+  ASMJIT_INST_0x(xsusldtrk, Xsusldtrk)
+
+  //! \}
+
+  //! \name CET-IBT Instructions
+  //! \{
+
+  ASMJIT_INST_0x(endbr32, Endbr32)
+  ASMJIT_INST_0x(endbr64, Endbr64)
+
+  //! \}
+
+  //! \name CET-SS Instructions
+  //! \{
+
+  ASMJIT_INST_1x(clrssbsy, Clrssbsy, Mem)
+  ASMJIT_INST_0x(setssbsy, Setssbsy)
+
+  ASMJIT_INST_1x(rstorssp, Rstorssp, Mem)
+  ASMJIT_INST_0x(saveprevssp, Saveprevssp)
+
+  ASMJIT_INST_1x(incsspd, Incsspd, Gp)
+  ASMJIT_INST_1x(incsspq, Incsspq, Gp)
+  ASMJIT_INST_1x(rdsspd, Rdsspd, Gp)
+  ASMJIT_INST_1x(rdsspq, Rdsspq, Gp)
+  ASMJIT_INST_2x(wrssd, Wrssd, Mem, Gp)
+  ASMJIT_INST_2x(wrssq, Wrssq, Mem, Gp)
+  ASMJIT_INST_2x(wrussd, Wrussd, Mem, Gp)
+  ASMJIT_INST_2x(wrussq, Wrussq, Mem, Gp)
+
+  //! \}
+
+  //! \name Core Privileged Instructions
+  //! \{
+
+  ASMJIT_INST_0x(clts, Clts)                                           // ANY
+  ASMJIT_INST_0x(hlt, Hlt)                                             // ANY
+  ASMJIT_INST_0x(invd, Invd)                                           // ANY
+  ASMJIT_INST_1x(invlpg, Invlpg, Mem)                                  // ANY
+  ASMJIT_INST_2x(invpcid, Invpcid, Gp, Mem)                            // ANY
+  ASMJIT_INST_1x(lgdt, Lgdt, Mem)                                      // ANY
+  ASMJIT_INST_1x(lidt, Lidt, Mem)                                      // ANY
+  ASMJIT_INST_1x(lldt, Lldt, Gp)                                       // ANY
+  ASMJIT_INST_1x(lldt, Lldt, Mem)                                      // ANY
+  ASMJIT_INST_1x(lmsw, Lmsw, Gp)                                       // ANY
+  ASMJIT_INST_1x(lmsw, Lmsw, Mem)                                      // ANY
+  ASMJIT_INST_1x(ltr, Ltr, Gp)                                         // ANY
+  ASMJIT_INST_1x(ltr, Ltr, Mem)                                        // ANY
+  ASMJIT_INST_3x(rdmsr, Rdmsr, EDX, EAX, ECX)                          // MSR       [EXPLICIT] RDX:EAX     <- MSR[ECX]
+  ASMJIT_INST_3x(rdpmc, Rdpmc, EDX, EAX, ECX)                          // ANY       [EXPLICIT] RDX:EAX     <- PMC[ECX]
+  ASMJIT_INST_0x(swapgs, Swapgs)                                       // X64
+  ASMJIT_INST_0x(wbinvd, Wbinvd)                                       // ANY
+  ASMJIT_INST_0x(wbnoinvd, Wbnoinvd)                                   // WBNOINVD
+  ASMJIT_INST_3x(wrmsr, Wrmsr, EDX, EAX, ECX)                          // MSR       [EXPLICIT] RDX:EAX     -> MSR[ECX]
+  ASMJIT_INST_3x(xsetbv, Xsetbv, EDX, EAX, ECX)                        // XSAVE     [EXPLICIT] XCR[ECX] <- EDX:EAX
+
+  //! \}
+
+  //! \name MONITOR Instructions (Privileged)
+  //! \{
+
+  ASMJIT_INST_3x(monitor, Monitor, Mem, Gp, Gp)                        // MONITOR
+  ASMJIT_INST_2x(mwait, Mwait, Gp, Gp)                                 // MONITOR
+
+  //! \}
+
+  //! \name SMAP Instructions (Privileged)
+  //! \{
+
+  ASMJIT_INST_0x(clac, Clac)                                           // SMAP
+  ASMJIT_INST_0x(stac, Stac)                                           // SMAP
+
+  //! \}
+
+  //! \name SKINIT Instructions (Privileged)
+  //! \{
+
+  ASMJIT_INST_1x(skinit, Skinit, Gp)                                   // SKINIT    [EXPLICIT] <eax>
+  ASMJIT_INST_0x(stgi, Stgi)                                           // SKINIT
+
+  //! \}
+
+  //! \name SNP Instructions (Privileged)
+  //! \{
+
+  ASMJIT_INST_0x(psmash, Psmash)                                       // SNP
+  ASMJIT_INST_0x(pvalidate, Pvalidate)                                 // SNP
+  ASMJIT_INST_0x(rmpadjust, Rmpadjust)                                 // SNP
+  ASMJIT_INST_0x(rmpupdate, Rmpupdate)                                 // SNP
+
+  //! \}
+
+  //! \name VMX Instructions (All privileged except vmfunc)
+  //! \{
+
+  ASMJIT_INST_2x(invept, Invept, Gp, Mem)                              // VMX
+  ASMJIT_INST_2x(invvpid, Invvpid, Gp, Mem)                            // VMX
+  ASMJIT_INST_0x(vmcall, Vmcall)                                       // VMX
+  ASMJIT_INST_1x(vmclear, Vmclear, Mem)                                // VMX
+  ASMJIT_INST_0x(vmfunc, Vmfunc)                                       // VMX
+  ASMJIT_INST_0x(vmlaunch, Vmlaunch)                                   // VMX
+  ASMJIT_INST_1x(vmptrld, Vmptrld, Mem)                                // VMX
+  ASMJIT_INST_1x(vmptrst, Vmptrst, Mem)                                // VMX
+  ASMJIT_INST_2x(vmread, Vmread, Mem, Gp)                              // VMX
+  ASMJIT_INST_0x(vmresume, Vmresume)                                   // VMX
+  ASMJIT_INST_2x(vmwrite, Vmwrite, Gp, Mem)                            // VMX
+  ASMJIT_INST_1x(vmxon, Vmxon, Mem)                                    // VMX
+
+  //! \}
+
+  //! \name SVM Instructions (All privileged except vmmcall)
+  //! \{
+
+  ASMJIT_INST_0x(clgi, Clgi)                                           // SVM
+  ASMJIT_INST_2x(invlpga, Invlpga, Gp, Gp)                             // SVM       [EXPLICIT] <eax|rax, ecx>
+  ASMJIT_INST_1x(vmload, Vmload, Gp)                                   // SVM       [EXPLICIT] <zax>
+  ASMJIT_INST_0x(vmmcall, Vmmcall)                                     // SVM
+  ASMJIT_INST_1x(vmrun, Vmrun, Gp)                                     // SVM       [EXPLICIT] <zax>
+  ASMJIT_INST_1x(vmsave, Vmsave, Gp)                                   // SVM       [EXPLICIT] <zax>
+
+  //! \}
+
+  //! \name FPU Instructions
+  //! \{
+
+  ASMJIT_INST_0x(f2xm1, F2xm1)                                         // FPU
+  ASMJIT_INST_0x(fabs, Fabs)                                           // FPU
+  ASMJIT_INST_2x(fadd, Fadd, St, St)                                   // FPU
+  ASMJIT_INST_1x(fadd, Fadd, Mem)                                      // FPU
+  ASMJIT_INST_1x(faddp, Faddp, St)                                     // FPU
+  ASMJIT_INST_0x(faddp, Faddp)                                         // FPU
+  ASMJIT_INST_1x(fbld, Fbld, Mem)                                      // FPU
+  ASMJIT_INST_1x(fbstp, Fbstp, Mem)                                    // FPU
+  ASMJIT_INST_0x(fchs, Fchs)                                           // FPU
+  ASMJIT_INST_0x(fclex, Fclex)                                         // FPU
+  ASMJIT_INST_1x(fcmovb, Fcmovb, St)                                   // FPU
+  ASMJIT_INST_1x(fcmovbe, Fcmovbe, St)                                 // FPU
+  ASMJIT_INST_1x(fcmove, Fcmove, St)                                   // FPU
+  ASMJIT_INST_1x(fcmovnb, Fcmovnb, St)                                 // FPU
+  ASMJIT_INST_1x(fcmovnbe, Fcmovnbe, St)                               // FPU
+  ASMJIT_INST_1x(fcmovne, Fcmovne, St)                                 // FPU
+  ASMJIT_INST_1x(fcmovnu, Fcmovnu, St)                                 // FPU
+  ASMJIT_INST_1x(fcmovu, Fcmovu, St)                                   // FPU
+  ASMJIT_INST_1x(fcom, Fcom, St)                                       // FPU
+  ASMJIT_INST_0x(fcom, Fcom)                                           // FPU
+  ASMJIT_INST_1x(fcom, Fcom, Mem)                                      // FPU
+  ASMJIT_INST_1x(fcomp, Fcomp, St)                                     // FPU
+  ASMJIT_INST_0x(fcomp, Fcomp)                                         // FPU
+  ASMJIT_INST_1x(fcomp, Fcomp, Mem)                                    // FPU
+  ASMJIT_INST_0x(fcompp, Fcompp)                                       // FPU
+  ASMJIT_INST_1x(fcomi, Fcomi, St)                                     // FPU
+  ASMJIT_INST_1x(fcomip, Fcomip, St)                                   // FPU
+  ASMJIT_INST_0x(fcos, Fcos)                                           // FPU
+  ASMJIT_INST_0x(fdecstp, Fdecstp)                                     // FPU
+  ASMJIT_INST_2x(fdiv, Fdiv, St, St)                                   // FPU
+  ASMJIT_INST_1x(fdiv, Fdiv, Mem)                                      // FPU
+  ASMJIT_INST_1x(fdivp, Fdivp, St)                                     // FPU
+  ASMJIT_INST_0x(fdivp, Fdivp)                                         // FPU
+  ASMJIT_INST_2x(fdivr, Fdivr, St, St)                                 // FPU
+  ASMJIT_INST_1x(fdivr, Fdivr, Mem)                                    // FPU
+  ASMJIT_INST_1x(fdivrp, Fdivrp, St)                                   // FPU
+  ASMJIT_INST_0x(fdivrp, Fdivrp)                                       // FPU
+  ASMJIT_INST_1x(ffree, Ffree, St)                                     // FPU
+  ASMJIT_INST_1x(fiadd, Fiadd, Mem)                                    // FPU
+  ASMJIT_INST_1x(ficom, Ficom, Mem)                                    // FPU
+  ASMJIT_INST_1x(ficomp, Ficomp, Mem)                                  // FPU
+  ASMJIT_INST_1x(fidiv, Fidiv, Mem)                                    // FPU
+  ASMJIT_INST_1x(fidivr, Fidivr, Mem)                                  // FPU
+  ASMJIT_INST_1x(fild, Fild, Mem)                                      // FPU
+  ASMJIT_INST_1x(fimul, Fimul, Mem)                                    // FPU
+  ASMJIT_INST_0x(fincstp, Fincstp)                                     // FPU
+  ASMJIT_INST_0x(finit, Finit)                                         // FPU
+  ASMJIT_INST_1x(fisub, Fisub, Mem)                                    // FPU
+  ASMJIT_INST_1x(fisubr, Fisubr, Mem)                                  // FPU
+  ASMJIT_INST_0x(fninit, Fninit)                                       // FPU
+  ASMJIT_INST_1x(fist, Fist, Mem)                                      // FPU
+  ASMJIT_INST_1x(fistp, Fistp, Mem)                                    // FPU
+  ASMJIT_INST_1x(fisttp, Fisttp, Mem)                                  // FPU+SSE3
+  ASMJIT_INST_1x(fld, Fld, Mem)                                        // FPU
+  ASMJIT_INST_1x(fld, Fld, St)                                         // FPU
+  ASMJIT_INST_0x(fld1, Fld1)                                           // FPU
+  ASMJIT_INST_0x(fldl2t, Fldl2t)                                       // FPU
+  ASMJIT_INST_0x(fldl2e, Fldl2e)                                       // FPU
+  ASMJIT_INST_0x(fldpi, Fldpi)                                         // FPU
+  ASMJIT_INST_0x(fldlg2, Fldlg2)                                       // FPU
+  ASMJIT_INST_0x(fldln2, Fldln2)                                       // FPU
+  ASMJIT_INST_0x(fldz, Fldz)                                           // FPU
+  ASMJIT_INST_1x(fldcw, Fldcw, Mem)                                    // FPU
+  ASMJIT_INST_1x(fldenv, Fldenv, Mem)                                  // FPU
+  ASMJIT_INST_2x(fmul, Fmul, St, St)                                   // FPU
+  ASMJIT_INST_1x(fmul, Fmul, Mem)                                      // FPU
+  ASMJIT_INST_1x(fmulp, Fmulp, St)                                     // FPU
+  ASMJIT_INST_0x(fmulp, Fmulp)                                         // FPU
+  ASMJIT_INST_0x(fnclex, Fnclex)                                       // FPU
+  ASMJIT_INST_0x(fnop, Fnop)                                           // FPU
+  ASMJIT_INST_1x(fnsave, Fnsave, Mem)                                  // FPU
+  ASMJIT_INST_1x(fnstenv, Fnstenv, Mem)                                // FPU
+  ASMJIT_INST_1x(fnstcw, Fnstcw, Mem)                                  // FPU
+  ASMJIT_INST_0x(fpatan, Fpatan)                                       // FPU
+  ASMJIT_INST_0x(fprem, Fprem)                                         // FPU
+  ASMJIT_INST_0x(fprem1, Fprem1)                                       // FPU
+  ASMJIT_INST_0x(fptan, Fptan)                                         // FPU
+  ASMJIT_INST_0x(frndint, Frndint)                                     // FPU
+  ASMJIT_INST_1x(frstor, Frstor, Mem)                                  // FPU
+  ASMJIT_INST_1x(fsave, Fsave, Mem)                                    // FPU
+  ASMJIT_INST_0x(fscale, Fscale)                                       // FPU
+  ASMJIT_INST_0x(fsin, Fsin)                                           // FPU
+  ASMJIT_INST_0x(fsincos, Fsincos)                                     // FPU
+  ASMJIT_INST_0x(fsqrt, Fsqrt)                                         // FPU
+  ASMJIT_INST_1x(fst, Fst, Mem)                                        // FPU
+  ASMJIT_INST_1x(fst, Fst, St)                                         // FPU
+  ASMJIT_INST_1x(fstp, Fstp, Mem)                                      // FPU
+  ASMJIT_INST_1x(fstp, Fstp, St)                                       // FPU
+  ASMJIT_INST_1x(fstcw, Fstcw, Mem)                                    // FPU
+  ASMJIT_INST_1x(fstenv, Fstenv, Mem)                                  // FPU
+  ASMJIT_INST_2x(fsub, Fsub, St, St)                                   // FPU
+  ASMJIT_INST_1x(fsub, Fsub, Mem)                                      // FPU
+  ASMJIT_INST_1x(fsubp, Fsubp, St)                                     // FPU
+  ASMJIT_INST_0x(fsubp, Fsubp)                                         // FPU
+  ASMJIT_INST_2x(fsubr, Fsubr, St, St)                                 // FPU
+  ASMJIT_INST_1x(fsubr, Fsubr, Mem)                                    // FPU
+  ASMJIT_INST_1x(fsubrp, Fsubrp, St)                                   // FPU
+  ASMJIT_INST_0x(fsubrp, Fsubrp)                                       // FPU
+  ASMJIT_INST_0x(ftst, Ftst)                                           // FPU
+  ASMJIT_INST_1x(fucom, Fucom, St)                                     // FPU
+  ASMJIT_INST_0x(fucom, Fucom)                                         // FPU
+  ASMJIT_INST_1x(fucomi, Fucomi, St)                                   // FPU
+  ASMJIT_INST_1x(fucomip, Fucomip, St)                                 // FPU
+  ASMJIT_INST_1x(fucomp, Fucomp, St)                                   // FPU
+  ASMJIT_INST_0x(fucomp, Fucomp)                                       // FPU
+  ASMJIT_INST_0x(fucompp, Fucompp)                                     // FPU
+  ASMJIT_INST_0x(fwait, Fwait)                                         // FPU
+  ASMJIT_INST_0x(fxam, Fxam)                                           // FPU
+  ASMJIT_INST_1x(fxch, Fxch, St)                                       // FPU
+  ASMJIT_INST_0x(fxtract, Fxtract)                                     // FPU
+  ASMJIT_INST_0x(fyl2x, Fyl2x)                                         // FPU
+  ASMJIT_INST_0x(fyl2xp1, Fyl2xp1)                                     // FPU
+  ASMJIT_INST_1x(fstsw, Fstsw, Gp)                                     // FPU
+  ASMJIT_INST_1x(fstsw, Fstsw, Mem)                                    // FPU
+  ASMJIT_INST_1x(fnstsw, Fnstsw, Gp)                                   // FPU
+  ASMJIT_INST_1x(fnstsw, Fnstsw, Mem)                                  // FPU
+
+  //! \}
+
+  //! \name MMX & SSE+ Instructions
+  //! \{
+
+  ASMJIT_INST_2x(addpd, Addpd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(addpd, Addpd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(addps, Addps, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(addps, Addps, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(addsd, Addsd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(addsd, Addsd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(addss, Addss, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(addss, Addss, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(addsubpd, Addsubpd, Xmm, Xmm)                         // SSE3
+  ASMJIT_INST_2x(addsubpd, Addsubpd, Xmm, Mem)                         // SSE3
+  ASMJIT_INST_2x(addsubps, Addsubps, Xmm, Xmm)                         // SSE3
+  ASMJIT_INST_2x(addsubps, Addsubps, Xmm, Mem)                         // SSE3
+  ASMJIT_INST_2x(andnpd, Andnpd, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(andnpd, Andnpd, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(andnps, Andnps, Xmm, Xmm)                             // SSE
+  ASMJIT_INST_2x(andnps, Andnps, Xmm, Mem)                             // SSE
+  ASMJIT_INST_2x(andpd, Andpd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(andpd, Andpd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(andps, Andps, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(andps, Andps, Xmm, Mem)                               // SSE
+  ASMJIT_INST_3i(blendpd, Blendpd, Xmm, Xmm, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(blendpd, Blendpd, Xmm, Mem, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(blendps, Blendps, Xmm, Xmm, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(blendps, Blendps, Xmm, Mem, Imm)                      // SSE4_1
+  ASMJIT_INST_3x(blendvpd, Blendvpd, Xmm, Xmm, XMM0)                   // SSE4_1 [EXPLICIT]
+  ASMJIT_INST_3x(blendvpd, Blendvpd, Xmm, Mem, XMM0)                   // SSE4_1 [EXPLICIT]
+  ASMJIT_INST_3x(blendvps, Blendvps, Xmm, Xmm, XMM0)                   // SSE4_1 [EXPLICIT]
+  ASMJIT_INST_3x(blendvps, Blendvps, Xmm, Mem, XMM0)                   // SSE4_1 [EXPLICIT]
+  ASMJIT_INST_3i(cmppd, Cmppd, Xmm, Xmm, Imm)                          // SSE2
+  ASMJIT_INST_3i(cmppd, Cmppd, Xmm, Mem, Imm)                          // SSE2
+  ASMJIT_INST_3i(cmpps, Cmpps, Xmm, Xmm, Imm)                          // SSE
+  ASMJIT_INST_3i(cmpps, Cmpps, Xmm, Mem, Imm)                          // SSE
+  ASMJIT_INST_3i(cmpsd, Cmpsd, Xmm, Xmm, Imm)                          // SSE2
+  ASMJIT_INST_3i(cmpsd, Cmpsd, Xmm, Mem, Imm)                          // SSE2
+  ASMJIT_INST_3i(cmpss, Cmpss, Xmm, Xmm, Imm)                          // SSE
+  ASMJIT_INST_3i(cmpss, Cmpss, Xmm, Mem, Imm)                          // SSE
+  ASMJIT_INST_2x(comisd, Comisd, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(comisd, Comisd, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(comiss, Comiss, Xmm, Xmm)                             // SSE
+  ASMJIT_INST_2x(comiss, Comiss, Xmm, Mem)                             // SSE
+  ASMJIT_INST_2x(cvtdq2pd, Cvtdq2pd, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(cvtdq2pd, Cvtdq2pd, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(cvtdq2ps, Cvtdq2ps, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(cvtdq2ps, Cvtdq2ps, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(cvtpd2dq, Cvtpd2dq, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(cvtpd2dq, Cvtpd2dq, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(cvtpd2pi, Cvtpd2pi, Mm, Xmm)                          // SSE2
+  ASMJIT_INST_2x(cvtpd2pi, Cvtpd2pi, Mm, Mem)                          // SSE2
+  ASMJIT_INST_2x(cvtpd2ps, Cvtpd2ps, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(cvtpd2ps, Cvtpd2ps, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(cvtpi2pd, Cvtpi2pd, Xmm, Mm)                          // SSE2
+  ASMJIT_INST_2x(cvtpi2pd, Cvtpi2pd, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(cvtpi2ps, Cvtpi2ps, Xmm, Mm)                          // SSE
+  ASMJIT_INST_2x(cvtpi2ps, Cvtpi2ps, Xmm, Mem)                         // SSE
+  ASMJIT_INST_2x(cvtps2dq, Cvtps2dq, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(cvtps2dq, Cvtps2dq, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(cvtps2pd, Cvtps2pd, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(cvtps2pd, Cvtps2pd, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(cvtps2pi, Cvtps2pi, Mm, Xmm)                          // SSE
+  ASMJIT_INST_2x(cvtps2pi, Cvtps2pi, Mm, Mem)                          // SSE
+  ASMJIT_INST_2x(cvtsd2si, Cvtsd2si, Gp, Xmm)                          // SSE2
+  ASMJIT_INST_2x(cvtsd2si, Cvtsd2si, Gp, Mem)                          // SSE2
+  ASMJIT_INST_2x(cvtsd2ss, Cvtsd2ss, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(cvtsd2ss, Cvtsd2ss, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(cvtsi2sd, Cvtsi2sd, Xmm, Gp)                          // SSE2
+  ASMJIT_INST_2x(cvtsi2sd, Cvtsi2sd, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(cvtsi2ss, Cvtsi2ss, Xmm, Gp)                          // SSE
+  ASMJIT_INST_2x(cvtsi2ss, Cvtsi2ss, Xmm, Mem)                         // SSE
+  ASMJIT_INST_2x(cvtss2sd, Cvtss2sd, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(cvtss2sd, Cvtss2sd, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(cvtss2si, Cvtss2si, Gp, Xmm)                          // SSE
+  ASMJIT_INST_2x(cvtss2si, Cvtss2si, Gp, Mem)                          // SSE
+  ASMJIT_INST_2x(cvttpd2pi, Cvttpd2pi, Mm, Xmm)                        // SSE2
+  ASMJIT_INST_2x(cvttpd2pi, Cvttpd2pi, Mm, Mem)                        // SSE2
+  ASMJIT_INST_2x(cvttpd2dq, Cvttpd2dq, Xmm, Xmm)                       // SSE2
+  ASMJIT_INST_2x(cvttpd2dq, Cvttpd2dq, Xmm, Mem)                       // SSE2
+  ASMJIT_INST_2x(cvttps2dq, Cvttps2dq, Xmm, Xmm)                       // SSE2
+  ASMJIT_INST_2x(cvttps2dq, Cvttps2dq, Xmm, Mem)                       // SSE2
+  ASMJIT_INST_2x(cvttps2pi, Cvttps2pi, Mm, Xmm)                        // SSE
+  ASMJIT_INST_2x(cvttps2pi, Cvttps2pi, Mm, Mem)                        // SSE
+  ASMJIT_INST_2x(cvttsd2si, Cvttsd2si, Gp, Xmm)                        // SSE2
+  ASMJIT_INST_2x(cvttsd2si, Cvttsd2si, Gp, Mem)                        // SSE2
+  ASMJIT_INST_2x(cvttss2si, Cvttss2si, Gp, Xmm)                        // SSE
+  ASMJIT_INST_2x(cvttss2si, Cvttss2si, Gp, Mem)                        // SSE
+  ASMJIT_INST_2x(divpd, Divpd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(divpd, Divpd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(divps, Divps, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(divps, Divps, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(divsd, Divsd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(divsd, Divsd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(divss, Divss, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(divss, Divss, Xmm, Mem)                               // SSE
+  ASMJIT_INST_3i(dppd, Dppd, Xmm, Xmm, Imm)                            // SSE4_1
+  ASMJIT_INST_3i(dppd, Dppd, Xmm, Mem, Imm)                            // SSE4_1
+  ASMJIT_INST_3i(dpps, Dpps, Xmm, Xmm, Imm)                            // SSE4_1
+  ASMJIT_INST_3i(dpps, Dpps, Xmm, Mem, Imm)                            // SSE4_1
+  ASMJIT_INST_3i(extractps, Extractps, Gp, Xmm, Imm)                   // SSE4_1
+  ASMJIT_INST_3i(extractps, Extractps, Mem, Xmm, Imm)                  // SSE4_1
+  ASMJIT_INST_2x(extrq, Extrq, Xmm, Xmm)                               // SSE4A
+  ASMJIT_INST_3ii(extrq, Extrq, Xmm, Imm, Imm)                         // SSE4A
+  ASMJIT_INST_2x(haddpd, Haddpd, Xmm, Xmm)                             // SSE3
+  ASMJIT_INST_2x(haddpd, Haddpd, Xmm, Mem)                             // SSE3
+  ASMJIT_INST_2x(haddps, Haddps, Xmm, Xmm)                             // SSE3
+  ASMJIT_INST_2x(haddps, Haddps, Xmm, Mem)                             // SSE3
+  ASMJIT_INST_2x(hsubpd, Hsubpd, Xmm, Xmm)                             // SSE3
+  ASMJIT_INST_2x(hsubpd, Hsubpd, Xmm, Mem)                             // SSE3
+  ASMJIT_INST_2x(hsubps, Hsubps, Xmm, Xmm)                             // SSE3
+  ASMJIT_INST_2x(hsubps, Hsubps, Xmm, Mem)                             // SSE3
+  ASMJIT_INST_3i(insertps, Insertps, Xmm, Xmm, Imm)                    // SSE4_1
+  ASMJIT_INST_3i(insertps, Insertps, Xmm, Mem, Imm)                    // SSE4_1
+  ASMJIT_INST_2x(insertq, Insertq, Xmm, Xmm)                           // SSE4A
+  ASMJIT_INST_4ii(insertq, Insertq, Xmm, Xmm, Imm, Imm)                // SSE4A
+  ASMJIT_INST_2x(lddqu, Lddqu, Xmm, Mem)                               // SSE3
+  ASMJIT_INST_3x(maskmovq, Maskmovq, Mm, Mm, DS_ZDI)                   // SSE  [EXPLICIT]
+  ASMJIT_INST_3x(maskmovdqu, Maskmovdqu, Xmm, Xmm, DS_ZDI)             // SSE2 [EXPLICIT]
+  ASMJIT_INST_2x(maxpd, Maxpd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(maxpd, Maxpd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(maxps, Maxps, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(maxps, Maxps, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(maxsd, Maxsd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(maxsd, Maxsd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(maxss, Maxss, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(maxss, Maxss, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(minpd, Minpd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(minpd, Minpd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(minps, Minps, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(minps, Minps, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(minsd, Minsd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(minsd, Minsd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(minss, Minss, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(minss, Minss, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(movapd, Movapd, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(movapd, Movapd, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(movapd, Movapd, Mem, Xmm)                             // SSE2
+  ASMJIT_INST_2x(movaps, Movaps, Xmm, Xmm)                             // SSE
+  ASMJIT_INST_2x(movaps, Movaps, Xmm, Mem)                             // SSE
+  ASMJIT_INST_2x(movaps, Movaps, Mem, Xmm)                             // SSE
+  ASMJIT_INST_2x(movd, Movd, Mem, Mm)                                  // MMX
+  ASMJIT_INST_2x(movd, Movd, Mem, Xmm)                                 // SSE
+  ASMJIT_INST_2x(movd, Movd, Gp, Mm)                                   // MMX
+  ASMJIT_INST_2x(movd, Movd, Gp, Xmm)                                  // SSE
+  ASMJIT_INST_2x(movd, Movd, Mm, Mem)                                  // MMX
+  ASMJIT_INST_2x(movd, Movd, Xmm, Mem)                                 // SSE
+  ASMJIT_INST_2x(movd, Movd, Mm, Gp)                                   // MMX
+  ASMJIT_INST_2x(movd, Movd, Xmm, Gp)                                  // SSE
+  ASMJIT_INST_2x(movddup, Movddup, Xmm, Xmm)                           // SSE3
+  ASMJIT_INST_2x(movddup, Movddup, Xmm, Mem)                           // SSE3
+  ASMJIT_INST_2x(movdq2q, Movdq2q, Mm, Xmm)                            // SSE2
+  ASMJIT_INST_2x(movdqa, Movdqa, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(movdqa, Movdqa, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(movdqa, Movdqa, Mem, Xmm)                             // SSE2
+  ASMJIT_INST_2x(movdqu, Movdqu, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(movdqu, Movdqu, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(movdqu, Movdqu, Mem, Xmm)                             // SSE2
+  ASMJIT_INST_2x(movhlps, Movhlps, Xmm, Xmm)                           // SSE
+  ASMJIT_INST_2x(movhpd, Movhpd, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(movhpd, Movhpd, Mem, Xmm)                             // SSE2
+  ASMJIT_INST_2x(movhps, Movhps, Xmm, Mem)                             // SSE
+  ASMJIT_INST_2x(movhps, Movhps, Mem, Xmm)                             // SSE
+  ASMJIT_INST_2x(movlhps, Movlhps, Xmm, Xmm)                           // SSE
+  ASMJIT_INST_2x(movlpd, Movlpd, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(movlpd, Movlpd, Mem, Xmm)                             // SSE2
+  ASMJIT_INST_2x(movlps, Movlps, Xmm, Mem)                             // SSE
+  ASMJIT_INST_2x(movlps, Movlps, Mem, Xmm)                             // SSE
+  ASMJIT_INST_2x(movmskps, Movmskps, Gp, Xmm)                          // SSE2
+  ASMJIT_INST_2x(movmskpd, Movmskpd, Gp, Xmm)                          // SSE2
+  ASMJIT_INST_2x(movntdq, Movntdq, Mem, Xmm)                           // SSE2
+  ASMJIT_INST_2x(movntdqa, Movntdqa, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(movntpd, Movntpd, Mem, Xmm)                           // SSE2
+  ASMJIT_INST_2x(movntps, Movntps, Mem, Xmm)                           // SSE
+  ASMJIT_INST_2x(movntsd, Movntsd, Mem, Xmm)                           // SSE4A
+  ASMJIT_INST_2x(movntss, Movntss, Mem, Xmm)                           // SSE4A
+  ASMJIT_INST_2x(movntq, Movntq, Mem, Mm)                              // SSE
+  ASMJIT_INST_2x(movq, Movq, Mm, Mm)                                   // MMX
+  ASMJIT_INST_2x(movq, Movq, Xmm, Xmm)                                 // SSE
+  ASMJIT_INST_2x(movq, Movq, Mem, Mm)                                  // MMX
+  ASMJIT_INST_2x(movq, Movq, Mem, Xmm)                                 // SSE
+  ASMJIT_INST_2x(movq, Movq, Mm, Mem)                                  // MMX
+  ASMJIT_INST_2x(movq, Movq, Xmm, Mem)                                 // SSE
+  ASMJIT_INST_2x(movq, Movq, Gp, Mm)                                   // MMX
+  ASMJIT_INST_2x(movq, Movq, Gp, Xmm)                                  // SSE+X64.
+  ASMJIT_INST_2x(movq, Movq, Mm, Gp)                                   // MMX
+  ASMJIT_INST_2x(movq, Movq, Xmm, Gp)                                  // SSE+X64.
+  ASMJIT_INST_2x(movq2dq, Movq2dq, Xmm, Mm)                            // SSE2
+  ASMJIT_INST_2x(movsd, Movsd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(movsd, Movsd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(movsd, Movsd, Mem, Xmm)                               // SSE2
+  ASMJIT_INST_2x(movshdup, Movshdup, Xmm, Xmm)                         // SSE3
+  ASMJIT_INST_2x(movshdup, Movshdup, Xmm, Mem)                         // SSE3
+  ASMJIT_INST_2x(movsldup, Movsldup, Xmm, Xmm)                         // SSE3
+  ASMJIT_INST_2x(movsldup, Movsldup, Xmm, Mem)                         // SSE3
+  ASMJIT_INST_2x(movss, Movss, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(movss, Movss, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(movss, Movss, Mem, Xmm)                               // SSE
+  ASMJIT_INST_2x(movupd, Movupd, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(movupd, Movupd, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(movupd, Movupd, Mem, Xmm)                             // SSE2
+  ASMJIT_INST_2x(movups, Movups, Xmm, Xmm)                             // SSE
+  ASMJIT_INST_2x(movups, Movups, Xmm, Mem)                             // SSE
+  ASMJIT_INST_2x(movups, Movups, Mem, Xmm)                             // SSE
+  ASMJIT_INST_3i(mpsadbw, Mpsadbw, Xmm, Xmm, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(mpsadbw, Mpsadbw, Xmm, Mem, Imm)                      // SSE4_1
+  ASMJIT_INST_2x(mulpd, Mulpd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(mulpd, Mulpd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(mulps, Mulps, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(mulps, Mulps, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(mulsd, Mulsd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(mulsd, Mulsd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(mulss, Mulss, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(mulss, Mulss, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(orpd, Orpd, Xmm, Xmm)                                 // SSE2
+  ASMJIT_INST_2x(orpd, Orpd, Xmm, Mem)                                 // SSE2
+  ASMJIT_INST_2x(orps, Orps, Xmm, Xmm)                                 // SSE
+  ASMJIT_INST_2x(orps, Orps, Xmm, Mem)                                 // SSE
+  ASMJIT_INST_2x(packssdw, Packssdw, Mm, Mm)                           // MMX
+  ASMJIT_INST_2x(packssdw, Packssdw, Mm, Mem)                          // MMX
+  ASMJIT_INST_2x(packssdw, Packssdw, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(packssdw, Packssdw, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(packsswb, Packsswb, Mm, Mm)                           // MMX
+  ASMJIT_INST_2x(packsswb, Packsswb, Mm, Mem)                          // MMX
+  ASMJIT_INST_2x(packsswb, Packsswb, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(packsswb, Packsswb, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(packusdw, Packusdw, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(packusdw, Packusdw, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(packuswb, Packuswb, Mm, Mm)                           // MMX
+  ASMJIT_INST_2x(packuswb, Packuswb, Mm, Mem)                          // MMX
+  ASMJIT_INST_2x(packuswb, Packuswb, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(packuswb, Packuswb, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(pabsb, Pabsb, Mm, Mm)                                 // SSSE3
+  ASMJIT_INST_2x(pabsb, Pabsb, Mm, Mem)                                // SSSE3
+  ASMJIT_INST_2x(pabsb, Pabsb, Xmm, Xmm)                               // SSSE3
+  ASMJIT_INST_2x(pabsb, Pabsb, Xmm, Mem)                               // SSSE3
+  ASMJIT_INST_2x(pabsd, Pabsd, Mm, Mm)                                 // SSSE3
+  ASMJIT_INST_2x(pabsd, Pabsd, Mm, Mem)                                // SSSE3
+  ASMJIT_INST_2x(pabsd, Pabsd, Xmm, Xmm)                               // SSSE3
+  ASMJIT_INST_2x(pabsd, Pabsd, Xmm, Mem)                               // SSSE3
+  ASMJIT_INST_2x(pabsw, Pabsw, Mm, Mm)                                 // SSSE3
+  ASMJIT_INST_2x(pabsw, Pabsw, Mm, Mem)                                // SSSE3
+  ASMJIT_INST_2x(pabsw, Pabsw, Xmm, Xmm)                               // SSSE3
+  ASMJIT_INST_2x(pabsw, Pabsw, Xmm, Mem)                               // SSSE3
+  ASMJIT_INST_2x(paddb, Paddb, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(paddb, Paddb, Mm, Mem)                                // MMX
+  ASMJIT_INST_2x(paddb, Paddb, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(paddb, Paddb, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(paddd, Paddd, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(paddd, Paddd, Mm, Mem)                                // MMX
+  ASMJIT_INST_2x(paddd, Paddd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(paddd, Paddd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(paddq, Paddq, Mm, Mm)                                 // SSE2
+  ASMJIT_INST_2x(paddq, Paddq, Mm, Mem)                                // SSE2
+  ASMJIT_INST_2x(paddq, Paddq, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(paddq, Paddq, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(paddsb, Paddsb, Mm, Mm)                               // MMX
+  ASMJIT_INST_2x(paddsb, Paddsb, Mm, Mem)                              // MMX
+  ASMJIT_INST_2x(paddsb, Paddsb, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(paddsb, Paddsb, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(paddsw, Paddsw, Mm, Mm)                               // MMX
+  ASMJIT_INST_2x(paddsw, Paddsw, Mm, Mem)                              // MMX
+  ASMJIT_INST_2x(paddsw, Paddsw, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(paddsw, Paddsw, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(paddusb, Paddusb, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(paddusb, Paddusb, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(paddusb, Paddusb, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(paddusb, Paddusb, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(paddusw, Paddusw, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(paddusw, Paddusw, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(paddusw, Paddusw, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(paddusw, Paddusw, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(paddw, Paddw, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(paddw, Paddw, Mm, Mem)                                // MMX
+  ASMJIT_INST_2x(paddw, Paddw, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(paddw, Paddw, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_3i(palignr, Palignr, Mm, Mm, Imm)                        // SSSE3
+  ASMJIT_INST_3i(palignr, Palignr, Mm, Mem, Imm)                       // SSSE3
+  ASMJIT_INST_3i(palignr, Palignr, Xmm, Xmm, Imm)                      // SSSE3
+  ASMJIT_INST_3i(palignr, Palignr, Xmm, Mem, Imm)                      // SSSE3
+  ASMJIT_INST_2x(pand, Pand, Mm, Mm)                                   // MMX
+  ASMJIT_INST_2x(pand, Pand, Mm, Mem)                                  // MMX
+  ASMJIT_INST_2x(pand, Pand, Xmm, Xmm)                                 // SSE2
+  ASMJIT_INST_2x(pand, Pand, Xmm, Mem)                                 // SSE2
+  ASMJIT_INST_2x(pandn, Pandn, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(pandn, Pandn, Mm, Mem)                                // MMX
+  ASMJIT_INST_2x(pandn, Pandn, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(pandn, Pandn, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(pavgb, Pavgb, Mm, Mm)                                 // SSE
+  ASMJIT_INST_2x(pavgb, Pavgb, Mm, Mem)                                // SSE
+  ASMJIT_INST_2x(pavgb, Pavgb, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(pavgb, Pavgb, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(pavgw, Pavgw, Mm, Mm)                                 // SSE
+  ASMJIT_INST_2x(pavgw, Pavgw, Mm, Mem)                                // SSE
+  ASMJIT_INST_2x(pavgw, Pavgw, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(pavgw, Pavgw, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_3x(pblendvb, Pblendvb, Xmm, Xmm, XMM0)                   // SSE4_1 [EXPLICIT]
+  ASMJIT_INST_3x(pblendvb, Pblendvb, Xmm, Mem, XMM0)                   // SSE4_1 [EXPLICIT]
+  ASMJIT_INST_3i(pblendw, Pblendw, Xmm, Xmm, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(pblendw, Pblendw, Xmm, Mem, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(pclmulqdq, Pclmulqdq, Xmm, Xmm, Imm)                  // PCLMULQDQ.
+  ASMJIT_INST_3i(pclmulqdq, Pclmulqdq, Xmm, Mem, Imm)                  // PCLMULQDQ.
+  ASMJIT_INST_6x(pcmpestri, Pcmpestri, Xmm, Xmm, Imm, ECX, EAX, EDX)   // SSE4_2 [EXPLICIT]
+  ASMJIT_INST_6x(pcmpestri, Pcmpestri, Xmm, Mem, Imm, ECX, EAX, EDX)   // SSE4_2 [EXPLICIT]
+  ASMJIT_INST_6x(pcmpestrm, Pcmpestrm, Xmm, Xmm, Imm, XMM0, EAX, EDX)  // SSE4_2 [EXPLICIT]
+  ASMJIT_INST_6x(pcmpestrm, Pcmpestrm, Xmm, Mem, Imm, XMM0, EAX, EDX)  // SSE4_2 [EXPLICIT]
+  ASMJIT_INST_2x(pcmpeqb, Pcmpeqb, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(pcmpeqb, Pcmpeqb, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(pcmpeqb, Pcmpeqb, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(pcmpeqb, Pcmpeqb, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(pcmpeqd, Pcmpeqd, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(pcmpeqd, Pcmpeqd, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(pcmpeqd, Pcmpeqd, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(pcmpeqd, Pcmpeqd, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(pcmpeqq, Pcmpeqq, Xmm, Xmm)                           // SSE4_1
+  ASMJIT_INST_2x(pcmpeqq, Pcmpeqq, Xmm, Mem)                           // SSE4_1
+  ASMJIT_INST_2x(pcmpeqw, Pcmpeqw, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(pcmpeqw, Pcmpeqw, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(pcmpeqw, Pcmpeqw, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(pcmpeqw, Pcmpeqw, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(pcmpgtb, Pcmpgtb, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(pcmpgtb, Pcmpgtb, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(pcmpgtb, Pcmpgtb, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(pcmpgtb, Pcmpgtb, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(pcmpgtd, Pcmpgtd, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(pcmpgtd, Pcmpgtd, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(pcmpgtd, Pcmpgtd, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(pcmpgtd, Pcmpgtd, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(pcmpgtq, Pcmpgtq, Xmm, Xmm)                           // SSE4_2.
+  ASMJIT_INST_2x(pcmpgtq, Pcmpgtq, Xmm, Mem)                           // SSE4_2.
+  ASMJIT_INST_2x(pcmpgtw, Pcmpgtw, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(pcmpgtw, Pcmpgtw, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(pcmpgtw, Pcmpgtw, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(pcmpgtw, Pcmpgtw, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_4x(pcmpistri, Pcmpistri, Xmm, Xmm, Imm, ECX)             // SSE4_2 [EXPLICIT]
+  ASMJIT_INST_4x(pcmpistri, Pcmpistri, Xmm, Mem, Imm, ECX)             // SSE4_2 [EXPLICIT]
+  ASMJIT_INST_4x(pcmpistrm, Pcmpistrm, Xmm, Xmm, Imm, XMM0)            // SSE4_2 [EXPLICIT]
+  ASMJIT_INST_4x(pcmpistrm, Pcmpistrm, Xmm, Mem, Imm, XMM0)            // SSE4_2 [EXPLICIT]
+  ASMJIT_INST_3i(pextrb, Pextrb, Gp, Xmm, Imm)                         // SSE4_1
+  ASMJIT_INST_3i(pextrb, Pextrb, Mem, Xmm, Imm)                        // SSE4_1
+  ASMJIT_INST_3i(pextrd, Pextrd, Gp, Xmm, Imm)                         // SSE4_1
+  ASMJIT_INST_3i(pextrd, Pextrd, Mem, Xmm, Imm)                        // SSE4_1
+  ASMJIT_INST_3i(pextrq, Pextrq, Gp, Xmm, Imm)                         // SSE4_1
+  ASMJIT_INST_3i(pextrq, Pextrq, Mem, Xmm, Imm)                        // SSE4_1
+  ASMJIT_INST_3i(pextrw, Pextrw, Gp, Mm, Imm)                          // SSE
+  ASMJIT_INST_3i(pextrw, Pextrw, Gp, Xmm, Imm)                         // SSE2
+  ASMJIT_INST_3i(pextrw, Pextrw, Mem, Xmm, Imm)                        // SSE4_1
+  ASMJIT_INST_2x(phaddd, Phaddd, Mm, Mm)                               // SSSE3
+  ASMJIT_INST_2x(phaddd, Phaddd, Mm, Mem)                              // SSSE3
+  ASMJIT_INST_2x(phaddd, Phaddd, Xmm, Xmm)                             // SSSE3
+  ASMJIT_INST_2x(phaddd, Phaddd, Xmm, Mem)                             // SSSE3
+  ASMJIT_INST_2x(phaddsw, Phaddsw, Mm, Mm)                             // SSSE3
+  ASMJIT_INST_2x(phaddsw, Phaddsw, Mm, Mem)                            // SSSE3
+  ASMJIT_INST_2x(phaddsw, Phaddsw, Xmm, Xmm)                           // SSSE3
+  ASMJIT_INST_2x(phaddsw, Phaddsw, Xmm, Mem)                           // SSSE3
+  ASMJIT_INST_2x(phaddw, Phaddw, Mm, Mm)                               // SSSE3
+  ASMJIT_INST_2x(phaddw, Phaddw, Mm, Mem)                              // SSSE3
+  ASMJIT_INST_2x(phaddw, Phaddw, Xmm, Xmm)                             // SSSE3
+  ASMJIT_INST_2x(phaddw, Phaddw, Xmm, Mem)                             // SSSE3
+  ASMJIT_INST_2x(phminposuw, Phminposuw, Xmm, Xmm)                     // SSE4_1
+  ASMJIT_INST_2x(phminposuw, Phminposuw, Xmm, Mem)                     // SSE4_1
+  ASMJIT_INST_2x(phsubd, Phsubd, Mm, Mm)                               // SSSE3
+  ASMJIT_INST_2x(phsubd, Phsubd, Mm, Mem)                              // SSSE3
+  ASMJIT_INST_2x(phsubd, Phsubd, Xmm, Xmm)                             // SSSE3
+  ASMJIT_INST_2x(phsubd, Phsubd, Xmm, Mem)                             // SSSE3
+  ASMJIT_INST_2x(phsubsw, Phsubsw, Mm, Mm)                             // SSSE3
+  ASMJIT_INST_2x(phsubsw, Phsubsw, Mm, Mem)                            // SSSE3
+  ASMJIT_INST_2x(phsubsw, Phsubsw, Xmm, Xmm)                           // SSSE3
+  ASMJIT_INST_2x(phsubsw, Phsubsw, Xmm, Mem)                           // SSSE3
+  ASMJIT_INST_2x(phsubw, Phsubw, Mm, Mm)                               // SSSE3
+  ASMJIT_INST_2x(phsubw, Phsubw, Mm, Mem)                              // SSSE3
+  ASMJIT_INST_2x(phsubw, Phsubw, Xmm, Xmm)                             // SSSE3
+  ASMJIT_INST_2x(phsubw, Phsubw, Xmm, Mem)                             // SSSE3
+  ASMJIT_INST_3i(pinsrb, Pinsrb, Xmm, Gp, Imm)                         // SSE4_1
+  ASMJIT_INST_3i(pinsrb, Pinsrb, Xmm, Mem, Imm)                        // SSE4_1
+  ASMJIT_INST_3i(pinsrd, Pinsrd, Xmm, Gp, Imm)                         // SSE4_1
+  ASMJIT_INST_3i(pinsrd, Pinsrd, Xmm, Mem, Imm)                        // SSE4_1
+  ASMJIT_INST_3i(pinsrq, Pinsrq, Xmm, Gp, Imm)                         // SSE4_1
+  ASMJIT_INST_3i(pinsrq, Pinsrq, Xmm, Mem, Imm)                        // SSE4_1
+  ASMJIT_INST_3i(pinsrw, Pinsrw, Mm, Gp, Imm)                          // SSE
+  ASMJIT_INST_3i(pinsrw, Pinsrw, Mm, Mem, Imm)                         // SSE
+  ASMJIT_INST_3i(pinsrw, Pinsrw, Xmm, Gp, Imm)                         // SSE2
+  ASMJIT_INST_3i(pinsrw, Pinsrw, Xmm, Mem, Imm)                        // SSE2
+  ASMJIT_INST_2x(pmaddubsw, Pmaddubsw, Mm, Mm)                         // SSSE3
+  ASMJIT_INST_2x(pmaddubsw, Pmaddubsw, Mm, Mem)                        // SSSE3
+  ASMJIT_INST_2x(pmaddubsw, Pmaddubsw, Xmm, Xmm)                       // SSSE3
+  ASMJIT_INST_2x(pmaddubsw, Pmaddubsw, Xmm, Mem)                       // SSSE3
+  ASMJIT_INST_2x(pmaddwd, Pmaddwd, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(pmaddwd, Pmaddwd, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(pmaddwd, Pmaddwd, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(pmaddwd, Pmaddwd, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(pmaxsb, Pmaxsb, Xmm, Xmm)                             // SSE4_1
+  ASMJIT_INST_2x(pmaxsb, Pmaxsb, Xmm, Mem)                             // SSE4_1
+  ASMJIT_INST_2x(pmaxsd, Pmaxsd, Xmm, Xmm)                             // SSE4_1
+  ASMJIT_INST_2x(pmaxsd, Pmaxsd, Xmm, Mem)                             // SSE4_1
+  ASMJIT_INST_2x(pmaxsw, Pmaxsw, Mm, Mm)                               // SSE
+  ASMJIT_INST_2x(pmaxsw, Pmaxsw, Mm, Mem)                              // SSE
+  ASMJIT_INST_2x(pmaxsw, Pmaxsw, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(pmaxsw, Pmaxsw, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(pmaxub, Pmaxub, Mm, Mm)                               // SSE
+  ASMJIT_INST_2x(pmaxub, Pmaxub, Mm, Mem)                              // SSE
+  ASMJIT_INST_2x(pmaxub, Pmaxub, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(pmaxub, Pmaxub, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(pmaxud, Pmaxud, Xmm, Xmm)                             // SSE4_1
+  ASMJIT_INST_2x(pmaxud, Pmaxud, Xmm, Mem)                             // SSE4_1
+  ASMJIT_INST_2x(pmaxuw, Pmaxuw, Xmm, Xmm)                             // SSE4_1
+  ASMJIT_INST_2x(pmaxuw, Pmaxuw, Xmm, Mem)                             // SSE4_1
+  ASMJIT_INST_2x(pminsb, Pminsb, Xmm, Xmm)                             // SSE4_1
+  ASMJIT_INST_2x(pminsb, Pminsb, Xmm, Mem)                             // SSE4_1
+  ASMJIT_INST_2x(pminsd, Pminsd, Xmm, Xmm)                             // SSE4_1
+  ASMJIT_INST_2x(pminsd, Pminsd, Xmm, Mem)                             // SSE4_1
+  ASMJIT_INST_2x(pminsw, Pminsw, Mm, Mm)                               // SSE
+  ASMJIT_INST_2x(pminsw, Pminsw, Mm, Mem)                              // SSE
+  ASMJIT_INST_2x(pminsw, Pminsw, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(pminsw, Pminsw, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(pminub, Pminub, Mm, Mm)                               // SSE
+  ASMJIT_INST_2x(pminub, Pminub, Mm, Mem)                              // SSE
+  ASMJIT_INST_2x(pminub, Pminub, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(pminub, Pminub, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(pminud, Pminud, Xmm, Xmm)                             // SSE4_1
+  ASMJIT_INST_2x(pminud, Pminud, Xmm, Mem)                             // SSE4_1
+  ASMJIT_INST_2x(pminuw, Pminuw, Xmm, Xmm)                             // SSE4_1
+  ASMJIT_INST_2x(pminuw, Pminuw, Xmm, Mem)                             // SSE4_1
+  ASMJIT_INST_2x(pmovmskb, Pmovmskb, Gp, Mm)                           // SSE
+  ASMJIT_INST_2x(pmovmskb, Pmovmskb, Gp, Xmm)                          // SSE2
+  ASMJIT_INST_2x(pmovsxbd, Pmovsxbd, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxbd, Pmovsxbd, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxbq, Pmovsxbq, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxbq, Pmovsxbq, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxbw, Pmovsxbw, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxbw, Pmovsxbw, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxdq, Pmovsxdq, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxdq, Pmovsxdq, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxwd, Pmovsxwd, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxwd, Pmovsxwd, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxwq, Pmovsxwq, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovsxwq, Pmovsxwq, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxbd, Pmovzxbd, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxbd, Pmovzxbd, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxbq, Pmovzxbq, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxbq, Pmovzxbq, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxbw, Pmovzxbw, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxbw, Pmovzxbw, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxdq, Pmovzxdq, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxdq, Pmovzxdq, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxwd, Pmovzxwd, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxwd, Pmovzxwd, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxwq, Pmovzxwq, Xmm, Xmm)                         // SSE4_1
+  ASMJIT_INST_2x(pmovzxwq, Pmovzxwq, Xmm, Mem)                         // SSE4_1
+  ASMJIT_INST_2x(pmuldq, Pmuldq, Xmm, Xmm)                             // SSE4_1
+  ASMJIT_INST_2x(pmuldq, Pmuldq, Xmm, Mem)                             // SSE4_1
+  ASMJIT_INST_2x(pmulhrsw, Pmulhrsw, Mm, Mm)                           // SSSE3
+  ASMJIT_INST_2x(pmulhrsw, Pmulhrsw, Mm, Mem)                          // SSSE3
+  ASMJIT_INST_2x(pmulhrsw, Pmulhrsw, Xmm, Xmm)                         // SSSE3
+  ASMJIT_INST_2x(pmulhrsw, Pmulhrsw, Xmm, Mem)                         // SSSE3
+  ASMJIT_INST_2x(pmulhw, Pmulhw, Mm, Mm)                               // MMX
+  ASMJIT_INST_2x(pmulhw, Pmulhw, Mm, Mem)                              // MMX
+  ASMJIT_INST_2x(pmulhw, Pmulhw, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(pmulhw, Pmulhw, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(pmulhuw, Pmulhuw, Mm, Mm)                             // SSE
+  ASMJIT_INST_2x(pmulhuw, Pmulhuw, Mm, Mem)                            // SSE
+  ASMJIT_INST_2x(pmulhuw, Pmulhuw, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(pmulhuw, Pmulhuw, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(pmulld, Pmulld, Xmm, Xmm)                             // SSE4_1
+  ASMJIT_INST_2x(pmulld, Pmulld, Xmm, Mem)                             // SSE4_1
+  ASMJIT_INST_2x(pmullw, Pmullw, Mm, Mm)                               // MMX
+  ASMJIT_INST_2x(pmullw, Pmullw, Mm, Mem)                              // MMX
+  ASMJIT_INST_2x(pmullw, Pmullw, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(pmullw, Pmullw, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(pmuludq, Pmuludq, Mm, Mm)                             // SSE2
+  ASMJIT_INST_2x(pmuludq, Pmuludq, Mm, Mem)                            // SSE2
+  ASMJIT_INST_2x(pmuludq, Pmuludq, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(pmuludq, Pmuludq, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(por, Por, Mm, Mm)                                     // MMX
+  ASMJIT_INST_2x(por, Por, Mm, Mem)                                    // MMX
+  ASMJIT_INST_2x(por, Por, Xmm, Xmm)                                   // SSE2
+  ASMJIT_INST_2x(por, Por, Xmm, Mem)                                   // SSE2
+  ASMJIT_INST_2x(psadbw, Psadbw, Mm, Mm)                               // SSE
+  ASMJIT_INST_2x(psadbw, Psadbw, Mm, Mem)                              // SSE
+  ASMJIT_INST_2x(psadbw, Psadbw, Xmm, Xmm)                             // SSE
+  ASMJIT_INST_2x(psadbw, Psadbw, Xmm, Mem)                             // SSE
+  ASMJIT_INST_2x(pslld, Pslld, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(pslld, Pslld, Mm, Mem)                                // MMX
+  ASMJIT_INST_2i(pslld, Pslld, Mm, Imm)                                // MMX
+  ASMJIT_INST_2x(pslld, Pslld, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(pslld, Pslld, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2i(pslld, Pslld, Xmm, Imm)                               // SSE2
+  ASMJIT_INST_2i(pslldq, Pslldq, Xmm, Imm)                             // SSE2
+  ASMJIT_INST_2x(psllq, Psllq, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(psllq, Psllq, Mm, Mem)                                // MMX
+  ASMJIT_INST_2i(psllq, Psllq, Mm, Imm)                                // MMX
+  ASMJIT_INST_2x(psllq, Psllq, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psllq, Psllq, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2i(psllq, Psllq, Xmm, Imm)                               // SSE2
+  ASMJIT_INST_2x(psllw, Psllw, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(psllw, Psllw, Mm, Mem)                                // MMX
+  ASMJIT_INST_2i(psllw, Psllw, Mm, Imm)                                // MMX
+  ASMJIT_INST_2x(psllw, Psllw, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psllw, Psllw, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2i(psllw, Psllw, Xmm, Imm)                               // SSE2
+  ASMJIT_INST_2x(psrad, Psrad, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(psrad, Psrad, Mm, Mem)                                // MMX
+  ASMJIT_INST_2i(psrad, Psrad, Mm, Imm)                                // MMX
+  ASMJIT_INST_2x(psrad, Psrad, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psrad, Psrad, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2i(psrad, Psrad, Xmm, Imm)                               // SSE2
+  ASMJIT_INST_2x(psraw, Psraw, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(psraw, Psraw, Mm, Mem)                                // MMX
+  ASMJIT_INST_2i(psraw, Psraw, Mm, Imm)                                // MMX
+  ASMJIT_INST_2x(psraw, Psraw, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psraw, Psraw, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2i(psraw, Psraw, Xmm, Imm)                               // SSE2
+  ASMJIT_INST_2x(pshufb, Pshufb, Mm, Mm)                               // SSSE3
+  ASMJIT_INST_2x(pshufb, Pshufb, Mm, Mem)                              // SSSE3
+  ASMJIT_INST_2x(pshufb, Pshufb, Xmm, Xmm)                             // SSSE3
+  ASMJIT_INST_2x(pshufb, Pshufb, Xmm, Mem)                             // SSSE3
+  ASMJIT_INST_3i(pshufd, Pshufd, Xmm, Xmm, Imm)                        // SSE2
+  ASMJIT_INST_3i(pshufd, Pshufd, Xmm, Mem, Imm)                        // SSE2
+  ASMJIT_INST_3i(pshufhw, Pshufhw, Xmm, Xmm, Imm)                      // SSE2
+  ASMJIT_INST_3i(pshufhw, Pshufhw, Xmm, Mem, Imm)                      // SSE2
+  ASMJIT_INST_3i(pshuflw, Pshuflw, Xmm, Xmm, Imm)                      // SSE2
+  ASMJIT_INST_3i(pshuflw, Pshuflw, Xmm, Mem, Imm)                      // SSE2
+  ASMJIT_INST_3i(pshufw, Pshufw, Mm, Mm, Imm)                          // SSE
+  ASMJIT_INST_3i(pshufw, Pshufw, Mm, Mem, Imm)                         // SSE
+  ASMJIT_INST_2x(psignb, Psignb, Mm, Mm)                               // SSSE3
+  ASMJIT_INST_2x(psignb, Psignb, Mm, Mem)                              // SSSE3
+  ASMJIT_INST_2x(psignb, Psignb, Xmm, Xmm)                             // SSSE3
+  ASMJIT_INST_2x(psignb, Psignb, Xmm, Mem)                             // SSSE3
+  ASMJIT_INST_2x(psignd, Psignd, Mm, Mm)                               // SSSE3
+  ASMJIT_INST_2x(psignd, Psignd, Mm, Mem)                              // SSSE3
+  ASMJIT_INST_2x(psignd, Psignd, Xmm, Xmm)                             // SSSE3
+  ASMJIT_INST_2x(psignd, Psignd, Xmm, Mem)                             // SSSE3
+  ASMJIT_INST_2x(psignw, Psignw, Mm, Mm)                               // SSSE3
+  ASMJIT_INST_2x(psignw, Psignw, Mm, Mem)                              // SSSE3
+  ASMJIT_INST_2x(psignw, Psignw, Xmm, Xmm)                             // SSSE3
+  ASMJIT_INST_2x(psignw, Psignw, Xmm, Mem)                             // SSSE3
+  ASMJIT_INST_2x(psrld, Psrld, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(psrld, Psrld, Mm, Mem)                                // MMX
+  ASMJIT_INST_2i(psrld, Psrld, Mm, Imm)                                // MMX
+  ASMJIT_INST_2x(psrld, Psrld, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psrld, Psrld, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2i(psrld, Psrld, Xmm, Imm)                               // SSE2
+  ASMJIT_INST_2i(psrldq, Psrldq, Xmm, Imm)                             // SSE2
+  ASMJIT_INST_2x(psrlq, Psrlq, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(psrlq, Psrlq, Mm, Mem)                                // MMX
+  ASMJIT_INST_2i(psrlq, Psrlq, Mm, Imm)                                // MMX
+  ASMJIT_INST_2x(psrlq, Psrlq, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psrlq, Psrlq, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2i(psrlq, Psrlq, Xmm, Imm)                               // SSE2
+  ASMJIT_INST_2x(psrlw, Psrlw, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(psrlw, Psrlw, Mm, Mem)                                // MMX
+  ASMJIT_INST_2i(psrlw, Psrlw, Mm, Imm)                                // MMX
+  ASMJIT_INST_2x(psrlw, Psrlw, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psrlw, Psrlw, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2i(psrlw, Psrlw, Xmm, Imm)                               // SSE2
+  ASMJIT_INST_2x(psubb, Psubb, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(psubb, Psubb, Mm, Mem)                                // MMX
+  ASMJIT_INST_2x(psubb, Psubb, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psubb, Psubb, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(psubd, Psubd, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(psubd, Psubd, Mm, Mem)                                // MMX
+  ASMJIT_INST_2x(psubd, Psubd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psubd, Psubd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(psubq, Psubq, Mm, Mm)                                 // SSE2
+  ASMJIT_INST_2x(psubq, Psubq, Mm, Mem)                                // SSE2
+  ASMJIT_INST_2x(psubq, Psubq, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psubq, Psubq, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(psubsb, Psubsb, Mm, Mm)                               // MMX
+  ASMJIT_INST_2x(psubsb, Psubsb, Mm, Mem)                              // MMX
+  ASMJIT_INST_2x(psubsb, Psubsb, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(psubsb, Psubsb, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(psubsw, Psubsw, Mm, Mm)                               // MMX
+  ASMJIT_INST_2x(psubsw, Psubsw, Mm, Mem)                              // MMX
+  ASMJIT_INST_2x(psubsw, Psubsw, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(psubsw, Psubsw, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(psubusb, Psubusb, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(psubusb, Psubusb, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(psubusb, Psubusb, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(psubusb, Psubusb, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(psubusw, Psubusw, Mm, Mm)                             // MMX
+  ASMJIT_INST_2x(psubusw, Psubusw, Mm, Mem)                            // MMX
+  ASMJIT_INST_2x(psubusw, Psubusw, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(psubusw, Psubusw, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(psubw, Psubw, Mm, Mm)                                 // MMX
+  ASMJIT_INST_2x(psubw, Psubw, Mm, Mem)                                // MMX
+  ASMJIT_INST_2x(psubw, Psubw, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(psubw, Psubw, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(ptest, Ptest, Xmm, Xmm)                               // SSE4_1
+  ASMJIT_INST_2x(ptest, Ptest, Xmm, Mem)                               // SSE4_1
+  ASMJIT_INST_2x(punpckhbw, Punpckhbw, Mm, Mm)                         // MMX
+  ASMJIT_INST_2x(punpckhbw, Punpckhbw, Mm, Mem)                        // MMX
+  ASMJIT_INST_2x(punpckhbw, Punpckhbw, Xmm, Xmm)                       // SSE2
+  ASMJIT_INST_2x(punpckhbw, Punpckhbw, Xmm, Mem)                       // SSE2
+  ASMJIT_INST_2x(punpckhdq, Punpckhdq, Mm, Mm)                         // MMX
+  ASMJIT_INST_2x(punpckhdq, Punpckhdq, Mm, Mem)                        // MMX
+  ASMJIT_INST_2x(punpckhdq, Punpckhdq, Xmm, Xmm)                       // SSE2
+  ASMJIT_INST_2x(punpckhdq, Punpckhdq, Xmm, Mem)                       // SSE2
+  ASMJIT_INST_2x(punpckhqdq, Punpckhqdq, Xmm, Xmm)                     // SSE2
+  ASMJIT_INST_2x(punpckhqdq, Punpckhqdq, Xmm, Mem)                     // SSE2
+  ASMJIT_INST_2x(punpckhwd, Punpckhwd, Mm, Mm)                         // MMX
+  ASMJIT_INST_2x(punpckhwd, Punpckhwd, Mm, Mem)                        // MMX
+  ASMJIT_INST_2x(punpckhwd, Punpckhwd, Xmm, Xmm)                       // SSE2
+  ASMJIT_INST_2x(punpckhwd, Punpckhwd, Xmm, Mem)                       // SSE2
+  ASMJIT_INST_2x(punpcklbw, Punpcklbw, Mm, Mm)                         // MMX
+  ASMJIT_INST_2x(punpcklbw, Punpcklbw, Mm, Mem)                        // MMX
+  ASMJIT_INST_2x(punpcklbw, Punpcklbw, Xmm, Xmm)                       // SSE2
+  ASMJIT_INST_2x(punpcklbw, Punpcklbw, Xmm, Mem)                       // SSE2
+  ASMJIT_INST_2x(punpckldq, Punpckldq, Mm, Mm)                         // MMX
+  ASMJIT_INST_2x(punpckldq, Punpckldq, Mm, Mem)                        // MMX
+  ASMJIT_INST_2x(punpckldq, Punpckldq, Xmm, Xmm)                       // SSE2
+  ASMJIT_INST_2x(punpckldq, Punpckldq, Xmm, Mem)                       // SSE2
+  ASMJIT_INST_2x(punpcklqdq, Punpcklqdq, Xmm, Xmm)                     // SSE2
+  ASMJIT_INST_2x(punpcklqdq, Punpcklqdq, Xmm, Mem)                     // SSE2
+  ASMJIT_INST_2x(punpcklwd, Punpcklwd, Mm, Mm)                         // MMX
+  ASMJIT_INST_2x(punpcklwd, Punpcklwd, Mm, Mem)                        // MMX
+  ASMJIT_INST_2x(punpcklwd, Punpcklwd, Xmm, Xmm)                       // SSE2
+  ASMJIT_INST_2x(punpcklwd, Punpcklwd, Xmm, Mem)                       // SSE2
+  ASMJIT_INST_2x(pxor, Pxor, Mm, Mm)                                   // MMX
+  ASMJIT_INST_2x(pxor, Pxor, Mm, Mem)                                  // MMX
+  ASMJIT_INST_2x(pxor, Pxor, Xmm, Xmm)                                 // SSE2
+  ASMJIT_INST_2x(pxor, Pxor, Xmm, Mem)                                 // SSE2
+  ASMJIT_INST_2x(rcpps, Rcpps, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(rcpps, Rcpps, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(rcpss, Rcpss, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(rcpss, Rcpss, Xmm, Mem)                               // SSE
+  ASMJIT_INST_3i(roundpd, Roundpd, Xmm, Xmm, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(roundpd, Roundpd, Xmm, Mem, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(roundps, Roundps, Xmm, Xmm, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(roundps, Roundps, Xmm, Mem, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(roundsd, Roundsd, Xmm, Xmm, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(roundsd, Roundsd, Xmm, Mem, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(roundss, Roundss, Xmm, Xmm, Imm)                      // SSE4_1
+  ASMJIT_INST_3i(roundss, Roundss, Xmm, Mem, Imm)                      // SSE4_1
+  ASMJIT_INST_2x(rsqrtps, Rsqrtps, Xmm, Xmm)                           // SSE
+  ASMJIT_INST_2x(rsqrtps, Rsqrtps, Xmm, Mem)                           // SSE
+  ASMJIT_INST_2x(rsqrtss, Rsqrtss, Xmm, Xmm)                           // SSE
+  ASMJIT_INST_2x(rsqrtss, Rsqrtss, Xmm, Mem)                           // SSE
+  ASMJIT_INST_3i(shufpd, Shufpd, Xmm, Xmm, Imm)                        // SSE2
+  ASMJIT_INST_3i(shufpd, Shufpd, Xmm, Mem, Imm)                        // SSE2
+  ASMJIT_INST_3i(shufps, Shufps, Xmm, Xmm, Imm)                        // SSE
+  ASMJIT_INST_3i(shufps, Shufps, Xmm, Mem, Imm)                        // SSE
+  ASMJIT_INST_2x(sqrtpd, Sqrtpd, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(sqrtpd, Sqrtpd, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(sqrtps, Sqrtps, Xmm, Xmm)                             // SSE
+  ASMJIT_INST_2x(sqrtps, Sqrtps, Xmm, Mem)                             // SSE
+  ASMJIT_INST_2x(sqrtsd, Sqrtsd, Xmm, Xmm)                             // SSE2
+  ASMJIT_INST_2x(sqrtsd, Sqrtsd, Xmm, Mem)                             // SSE2
+  ASMJIT_INST_2x(sqrtss, Sqrtss, Xmm, Xmm)                             // SSE
+  ASMJIT_INST_2x(sqrtss, Sqrtss, Xmm, Mem)                             // SSE
+  ASMJIT_INST_2x(subpd, Subpd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(subpd, Subpd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(subps, Subps, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(subps, Subps, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(subsd, Subsd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(subsd, Subsd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(subss, Subss, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(subss, Subss, Xmm, Mem)                               // SSE
+  ASMJIT_INST_2x(ucomisd, Ucomisd, Xmm, Xmm)                           // SSE2
+  ASMJIT_INST_2x(ucomisd, Ucomisd, Xmm, Mem)                           // SSE2
+  ASMJIT_INST_2x(ucomiss, Ucomiss, Xmm, Xmm)                           // SSE
+  ASMJIT_INST_2x(ucomiss, Ucomiss, Xmm, Mem)                           // SSE
+  ASMJIT_INST_2x(unpckhpd, Unpckhpd, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(unpckhpd, Unpckhpd, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(unpckhps, Unpckhps, Xmm, Xmm)                         // SSE
+  ASMJIT_INST_2x(unpckhps, Unpckhps, Xmm, Mem)                         // SSE
+  ASMJIT_INST_2x(unpcklpd, Unpcklpd, Xmm, Xmm)                         // SSE2
+  ASMJIT_INST_2x(unpcklpd, Unpcklpd, Xmm, Mem)                         // SSE2
+  ASMJIT_INST_2x(unpcklps, Unpcklps, Xmm, Xmm)                         // SSE
+  ASMJIT_INST_2x(unpcklps, Unpcklps, Xmm, Mem)                         // SSE
+  ASMJIT_INST_2x(xorpd, Xorpd, Xmm, Xmm)                               // SSE2
+  ASMJIT_INST_2x(xorpd, Xorpd, Xmm, Mem)                               // SSE2
+  ASMJIT_INST_2x(xorps, Xorps, Xmm, Xmm)                               // SSE
+  ASMJIT_INST_2x(xorps, Xorps, Xmm, Mem)                               // SSE
+
+  //! \}
+
+  //! \name 3DNOW and GEODE Instructions (Deprecated)
+  //! \{
+
+  ASMJIT_INST_2x(pavgusb, Pavgusb, Mm, Mm)                             // 3DNOW
+  ASMJIT_INST_2x(pavgusb, Pavgusb, Mm, Mem)                            // 3DNOW
+  ASMJIT_INST_2x(pf2id, Pf2id, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pf2id, Pf2id, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pf2iw, Pf2iw, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pf2iw, Pf2iw, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pfacc, Pfacc, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pfacc, Pfacc, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pfadd, Pfadd, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pfadd, Pfadd, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pfcmpeq, Pfcmpeq, Mm, Mm)                             // 3DNOW
+  ASMJIT_INST_2x(pfcmpeq, Pfcmpeq, Mm, Mem)                            // 3DNOW
+  ASMJIT_INST_2x(pfcmpge, Pfcmpge, Mm, Mm)                             // 3DNOW
+  ASMJIT_INST_2x(pfcmpge, Pfcmpge, Mm, Mem)                            // 3DNOW
+  ASMJIT_INST_2x(pfcmpgt, Pfcmpgt, Mm, Mm)                             // 3DNOW
+  ASMJIT_INST_2x(pfcmpgt, Pfcmpgt, Mm, Mem)                            // 3DNOW
+  ASMJIT_INST_2x(pfmax, Pfmax, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pfmax, Pfmax, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pfmin, Pfmin, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pfmin, Pfmin, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pfmul, Pfmul, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pfmul, Pfmul, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pfnacc, Pfnacc, Mm, Mm)                               // 3DNOW
+  ASMJIT_INST_2x(pfnacc, Pfnacc, Mm, Mem)                              // 3DNOW
+  ASMJIT_INST_2x(pfpnacc, Pfpnacc, Mm, Mm)                             // 3DNOW
+  ASMJIT_INST_2x(pfpnacc, Pfpnacc, Mm, Mem)                            // 3DNOW
+  ASMJIT_INST_2x(pfrcp, Pfrcp, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pfrcp, Pfrcp, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pfrcpit1, Pfrcpit1, Mm, Mm)                           // 3DNOW
+  ASMJIT_INST_2x(pfrcpit1, Pfrcpit1, Mm, Mem)                          // 3DNOW
+  ASMJIT_INST_2x(pfrcpit2, Pfrcpit2, Mm, Mm)                           // 3DNOW
+  ASMJIT_INST_2x(pfrcpit2, Pfrcpit2, Mm, Mem)                          // 3DNOW
+  ASMJIT_INST_2x(pfrcpv, Pfrcpv, Mm, Mm)                               // GEODE
+  ASMJIT_INST_2x(pfrcpv, Pfrcpv, Mm, Mem)                              // GEODE
+  ASMJIT_INST_2x(pfrsqit1, Pfrsqit1, Mm, Mm)                           // 3DNOW
+  ASMJIT_INST_2x(pfrsqit1, Pfrsqit1, Mm, Mem)                          // 3DNOW
+  ASMJIT_INST_2x(pfrsqrt, Pfrsqrt, Mm, Mm)                             // 3DNOW
+  ASMJIT_INST_2x(pfrsqrt, Pfrsqrt, Mm, Mem)                            // 3DNOW
+  ASMJIT_INST_2x(pfrsqrtv, Pfrsqrtv, Mm, Mm)                           // GEODE
+  ASMJIT_INST_2x(pfrsqrtv, Pfrsqrtv, Mm, Mem)                          // GEODE
+  ASMJIT_INST_2x(pfsub, Pfsub, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pfsub, Pfsub, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pfsubr, Pfsubr, Mm, Mm)                               // 3DNOW
+  ASMJIT_INST_2x(pfsubr, Pfsubr, Mm, Mem)                              // 3DNOW
+  ASMJIT_INST_2x(pi2fd, Pi2fd, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pi2fd, Pi2fd, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pi2fw, Pi2fw, Mm, Mm)                                 // 3DNOW
+  ASMJIT_INST_2x(pi2fw, Pi2fw, Mm, Mem)                                // 3DNOW
+  ASMJIT_INST_2x(pmulhrw, Pmulhrw, Mm, Mm)                             // 3DNOW
+  ASMJIT_INST_2x(pmulhrw, Pmulhrw, Mm, Mem)                            // 3DNOW
+  ASMJIT_INST_2x(pswapd, Pswapd, Mm, Mm)                               // 3DNOW
+  ASMJIT_INST_2x(pswapd, Pswapd, Mm, Mem)                              // 3DNOW
+
+  //! \}
+
+  //! \name EMMS/FEMMS Instructions
+  //! \{
+
+  ASMJIT_INST_0x(emms, Emms)                                           // MMX
+  ASMJIT_INST_0x(femms, Femms)                                         // 3DNOW
+
+  //! \}
+
+  //! \name AESNI Instructions
+  //! \{
+
+  ASMJIT_INST_2x(aesdec, Aesdec, Xmm, Xmm)                             // AESNI
+  ASMJIT_INST_2x(aesdec, Aesdec, Xmm, Mem)                             // AESNI
+  ASMJIT_INST_2x(aesdeclast, Aesdeclast, Xmm, Xmm)                     // AESNI
+  ASMJIT_INST_2x(aesdeclast, Aesdeclast, Xmm, Mem)                     // AESNI
+  ASMJIT_INST_2x(aesenc, Aesenc, Xmm, Xmm)                             // AESNI
+  ASMJIT_INST_2x(aesenc, Aesenc, Xmm, Mem)                             // AESNI
+  ASMJIT_INST_2x(aesenclast, Aesenclast, Xmm, Xmm)                     // AESNI
+  ASMJIT_INST_2x(aesenclast, Aesenclast, Xmm, Mem)                     // AESNI
+  ASMJIT_INST_2x(aesimc, Aesimc, Xmm, Xmm)                             // AESNI
+  ASMJIT_INST_2x(aesimc, Aesimc, Xmm, Mem)                             // AESNI
+  ASMJIT_INST_3i(aeskeygenassist, Aeskeygenassist, Xmm, Xmm, Imm)      // AESNI
+  ASMJIT_INST_3i(aeskeygenassist, Aeskeygenassist, Xmm, Mem, Imm)      // AESNI
+
+  //! \}
+
+  //! \name SHA Instructions
+  //! \{
+
+  ASMJIT_INST_2x(sha1msg1, Sha1msg1, Xmm, Xmm)                         // SHA
+  ASMJIT_INST_2x(sha1msg1, Sha1msg1, Xmm, Mem)                         // SHA
+  ASMJIT_INST_2x(sha1msg2, Sha1msg2, Xmm, Xmm)                         // SHA
+  ASMJIT_INST_2x(sha1msg2, Sha1msg2, Xmm, Mem)                         // SHA
+  ASMJIT_INST_2x(sha1nexte, Sha1nexte, Xmm, Xmm)                       // SHA
+  ASMJIT_INST_2x(sha1nexte, Sha1nexte, Xmm, Mem)                       // SHA
+  ASMJIT_INST_3i(sha1rnds4, Sha1rnds4, Xmm, Xmm, Imm)                  // SHA
+  ASMJIT_INST_3i(sha1rnds4, Sha1rnds4, Xmm, Mem, Imm)                  // SHA
+  ASMJIT_INST_2x(sha256msg1, Sha256msg1, Xmm, Xmm)                     // SHA
+  ASMJIT_INST_2x(sha256msg1, Sha256msg1, Xmm, Mem)                     // SHA
+  ASMJIT_INST_2x(sha256msg2, Sha256msg2, Xmm, Xmm)                     // SHA
+  ASMJIT_INST_2x(sha256msg2, Sha256msg2, Xmm, Mem)                     // SHA
+  ASMJIT_INST_3x(sha256rnds2, Sha256rnds2, Xmm, Xmm, XMM0)             // SHA [EXPLICIT]
+  ASMJIT_INST_3x(sha256rnds2, Sha256rnds2, Xmm, Mem, XMM0)             // SHA [EXPLICIT]
+
+  //! \}
+
+  //! \name GFNI Instructions
+  //! \{
+
+  // NOTE: For some reason Doxygen is messed up here and thinks we are in cond.
+  //! \endcond
+
+  ASMJIT_INST_3i(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Xmm, Imm)    // GFNI
+  ASMJIT_INST_3i(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Mem, Imm)    // GFNI
+  ASMJIT_INST_3i(gf2p8affineqb, Gf2p8affineqb, Xmm, Xmm, Imm)          // GFNI
+  ASMJIT_INST_3i(gf2p8affineqb, Gf2p8affineqb, Xmm, Mem, Imm)          // GFNI
+  ASMJIT_INST_2x(gf2p8mulb, Gf2p8mulb, Xmm, Xmm)                       // GFNI
+  ASMJIT_INST_2x(gf2p8mulb, Gf2p8mulb, Xmm, Mem)                       // GFNI
+
+  //! \}
+
+  //! \name AVX, FMA, and AVX512 Instructions
+  //! \{
+
+  ASMJIT_INST_3x(kaddb, Kaddb, KReg, KReg, KReg)                       // AVX512_DQ
+  ASMJIT_INST_3x(kaddd, Kaddd, KReg, KReg, KReg)                       // AVX512_BW
+  ASMJIT_INST_3x(kaddq, Kaddq, KReg, KReg, KReg)                       // AVX512_BW
+  ASMJIT_INST_3x(kaddw, Kaddw, KReg, KReg, KReg)                       // AVX512_DQ
+  ASMJIT_INST_3x(kandb, Kandb, KReg, KReg, KReg)                       // AVX512_DQ
+  ASMJIT_INST_3x(kandd, Kandd, KReg, KReg, KReg)                       // AVX512_BW
+  ASMJIT_INST_3x(kandnb, Kandnb, KReg, KReg, KReg)                     // AVX512_DQ
+  ASMJIT_INST_3x(kandnd, Kandnd, KReg, KReg, KReg)                     // AVX512_BW
+  ASMJIT_INST_3x(kandnq, Kandnq, KReg, KReg, KReg)                     // AVX512_BW
+  ASMJIT_INST_3x(kandnw, Kandnw, KReg, KReg, KReg)                     // AVX512_F
+  ASMJIT_INST_3x(kandq, Kandq, KReg, KReg, KReg)                       // AVX512_BW
+  ASMJIT_INST_3x(kandw, Kandw, KReg, KReg, KReg)                       // AVX512_F
+  ASMJIT_INST_2x(kmovb, Kmovb, KReg, KReg)                             // AVX512_DQ
+  ASMJIT_INST_2x(kmovb, Kmovb, KReg, Mem)                              // AVX512_DQ
+  ASMJIT_INST_2x(kmovb, Kmovb, KReg, Gp)                               // AVX512_DQ
+  ASMJIT_INST_2x(kmovb, Kmovb, Mem, KReg)                              // AVX512_DQ
+  ASMJIT_INST_2x(kmovb, Kmovb, Gp, KReg)                               // AVX512_DQ
+  ASMJIT_INST_2x(kmovd, Kmovd, KReg, KReg)                             // AVX512_BW
+  ASMJIT_INST_2x(kmovd, Kmovd, KReg, Mem)                              // AVX512_BW
+  ASMJIT_INST_2x(kmovd, Kmovd, KReg, Gp)                               // AVX512_BW
+  ASMJIT_INST_2x(kmovd, Kmovd, Mem, KReg)                              // AVX512_BW
+  ASMJIT_INST_2x(kmovd, Kmovd, Gp, KReg)                               // AVX512_BW
+  ASMJIT_INST_2x(kmovq, Kmovq, KReg, KReg)                             // AVX512_BW
+  ASMJIT_INST_2x(kmovq, Kmovq, KReg, Mem)                              // AVX512_BW
+  ASMJIT_INST_2x(kmovq, Kmovq, KReg, Gp)                               // AVX512_BW
+  ASMJIT_INST_2x(kmovq, Kmovq, Mem, KReg)                              // AVX512_BW
+  ASMJIT_INST_2x(kmovq, Kmovq, Gp, KReg)                               // AVX512_BW
+  ASMJIT_INST_2x(kmovw, Kmovw, KReg, KReg)                             // AVX512_F
+  ASMJIT_INST_2x(kmovw, Kmovw, KReg, Mem)                              // AVX512_F
+  ASMJIT_INST_2x(kmovw, Kmovw, KReg, Gp)                               // AVX512_F
+  ASMJIT_INST_2x(kmovw, Kmovw, Mem, KReg)                              // AVX512_F
+  ASMJIT_INST_2x(kmovw, Kmovw, Gp, KReg)                               // AVX512_F
+  ASMJIT_INST_2x(knotb, Knotb, KReg, KReg)                             // AVX512_DQ
+  ASMJIT_INST_2x(knotd, Knotd, KReg, KReg)                             // AVX512_BW
+  ASMJIT_INST_2x(knotq, Knotq, KReg, KReg)                             // AVX512_BW
+  ASMJIT_INST_2x(knotw, Knotw, KReg, KReg)                             // AVX512_F
+  ASMJIT_INST_3x(korb, Korb, KReg, KReg, KReg)                         // AVX512_DQ
+  ASMJIT_INST_3x(kord, Kord, KReg, KReg, KReg)                         // AVX512_BW
+  ASMJIT_INST_3x(korq, Korq, KReg, KReg, KReg)                         // AVX512_BW
+  ASMJIT_INST_2x(kortestb, Kortestb, KReg, KReg)                       // AVX512_DQ
+  ASMJIT_INST_2x(kortestd, Kortestd, KReg, KReg)                       // AVX512_BW
+  ASMJIT_INST_2x(kortestq, Kortestq, KReg, KReg)                       // AVX512_BW
+  ASMJIT_INST_2x(kortestw, Kortestw, KReg, KReg)                       // AVX512_F
+  ASMJIT_INST_3x(korw, Korw, KReg, KReg, KReg)                         // AVX512_F
+  ASMJIT_INST_3i(kshiftlb, Kshiftlb, KReg, KReg, Imm)                  // AVX512_DQ
+  ASMJIT_INST_3i(kshiftld, Kshiftld, KReg, KReg, Imm)                  // AVX512_BW
+  ASMJIT_INST_3i(kshiftlq, Kshiftlq, KReg, KReg, Imm)                  // AVX512_BW
+  ASMJIT_INST_3i(kshiftlw, Kshiftlw, KReg, KReg, Imm)                  // AVX512_F
+  ASMJIT_INST_3i(kshiftrb, Kshiftrb, KReg, KReg, Imm)                  // AVX512_DQ
+  ASMJIT_INST_3i(kshiftrd, Kshiftrd, KReg, KReg, Imm)                  // AVX512_BW
+  ASMJIT_INST_3i(kshiftrq, Kshiftrq, KReg, KReg, Imm)                  // AVX512_BW
+  ASMJIT_INST_3i(kshiftrw, Kshiftrw, KReg, KReg, Imm)                  // AVX512_F
+  ASMJIT_INST_2x(ktestb, Ktestb, KReg, KReg)                           // AVX512_DQ
+  ASMJIT_INST_2x(ktestd, Ktestd, KReg, KReg)                           // AVX512_BW
+  ASMJIT_INST_2x(ktestq, Ktestq, KReg, KReg)                           // AVX512_BW
+  ASMJIT_INST_2x(ktestw, Ktestw, KReg, KReg)                           // AVX512_DQ
+  ASMJIT_INST_3x(kunpckbw, Kunpckbw, KReg, KReg, KReg)                 // AVX512_F
+  ASMJIT_INST_3x(kunpckdq, Kunpckdq, KReg, KReg, KReg)                 // AVX512_BW
+  ASMJIT_INST_3x(kunpckwd, Kunpckwd, KReg, KReg, KReg)                 // AVX512_BW
+  ASMJIT_INST_3x(kxnorb, Kxnorb, KReg, KReg, KReg)                     // AVX512_DQ
+  ASMJIT_INST_3x(kxnord, Kxnord, KReg, KReg, KReg)                     // AVX512_BW
+  ASMJIT_INST_3x(kxnorq, Kxnorq, KReg, KReg, KReg)                     // AVX512_BW
+  ASMJIT_INST_3x(kxnorw, Kxnorw, KReg, KReg, KReg)                     // AVX512_F
+  ASMJIT_INST_3x(kxorb, Kxorb, KReg, KReg, KReg)                       // AVX512_DQ
+  ASMJIT_INST_3x(kxord, Kxord, KReg, KReg, KReg)                       // AVX512_BW
+  ASMJIT_INST_3x(kxorq, Kxorq, KReg, KReg, KReg)                       // AVX512_BW
+  ASMJIT_INST_3x(kxorw, Kxorw, KReg, KReg, KReg)                       // AVX512_F
+  ASMJIT_INST_6x(v4fmaddps, V4fmaddps, Zmm, Zmm, Zmm, Zmm, Zmm, Mem)   // AVX512_4FMAPS{kz}
+  ASMJIT_INST_6x(v4fmaddss, V4fmaddss, Xmm, Xmm, Xmm, Xmm, Xmm, Mem)   // AVX512_4FMAPS{kz}
+  ASMJIT_INST_6x(v4fnmaddps, V4fnmaddps, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz}
+  ASMJIT_INST_6x(v4fnmaddss, V4fnmaddss, Xmm, Xmm, Xmm, Xmm, Xmm, Mem) // AVX512_4FMAPS{kz}
+  ASMJIT_INST_3x(vaddpd, Vaddpd, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vaddpd, Vaddpd, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vaddps, Vaddps, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vaddps, Vaddps, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vaddsd, Vaddsd, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vaddsd, Vaddsd, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vaddss, Vaddss, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vaddss, Vaddss, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vaddsubpd, Vaddsubpd, Vec, Vec, Vec)                  // AVX
+  ASMJIT_INST_3x(vaddsubpd, Vaddsubpd, Vec, Vec, Mem)                  // AVX
+  ASMJIT_INST_3x(vaddsubps, Vaddsubps, Vec, Vec, Vec)                  // AVX
+  ASMJIT_INST_3x(vaddsubps, Vaddsubps, Vec, Vec, Mem)                  // AVX
+  ASMJIT_INST_3x(vaesdec, Vaesdec, Vec, Vec, Vec)                      // AVX+AESNI VAES
+  ASMJIT_INST_3x(vaesdec, Vaesdec, Vec, Vec, Mem)                      // AVX+AESNI VAES
+  ASMJIT_INST_3x(vaesdeclast, Vaesdeclast, Vec, Vec, Vec)              // AVX+AESNI VAES
+  ASMJIT_INST_3x(vaesdeclast, Vaesdeclast, Vec, Vec, Mem)              // AVX+AESNI VAES
+  ASMJIT_INST_3x(vaesenc, Vaesenc, Vec, Vec, Vec)                      // AVX+AESNI VAES
+  ASMJIT_INST_3x(vaesenc, Vaesenc, Vec, Vec, Mem)                      // AVX+AESNI VAES
+  ASMJIT_INST_3x(vaesenclast, Vaesenclast, Vec, Vec, Vec)              // AVX+AESNI VAES
+  ASMJIT_INST_3x(vaesenclast, Vaesenclast, Vec, Vec, Mem)              // AVX+AESNI VAES
+  ASMJIT_INST_2x(vaesimc, Vaesimc, Xmm, Xmm)                           // AVX+AESNI
+  ASMJIT_INST_2x(vaesimc, Vaesimc, Xmm, Mem)                           // AVX+AESNI
+  ASMJIT_INST_3i(vaeskeygenassist, Vaeskeygenassist, Xmm, Xmm, Imm)    // AVX+AESNI
+  ASMJIT_INST_3i(vaeskeygenassist, Vaeskeygenassist, Xmm, Mem, Imm)    // AVX+AESNI
+  ASMJIT_INST_4i(valignd, Valignd, Vec, Vec, Vec, Imm)                 //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(valignd, Valignd, Vec, Vec, Mem, Imm)                 //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(valignq, Valignq, Vec, Vec, Vec, Imm)                 //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(valignq, Valignq, Vec, Vec, Mem, Imm)                 //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vandnpd, Vandnpd, Vec, Vec, Vec)                      // AVX  AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vandnpd, Vandnpd, Vec, Vec, Mem)                      // AVX  AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vandnps, Vandnps, Vec, Vec, Vec)                      // AVX  AVX512_DQ{kz|b32}
+  ASMJIT_INST_3x(vandnps, Vandnps, Vec, Vec, Mem)                      // AVX  AVX512_DQ{kz|b32}
+  ASMJIT_INST_3x(vandpd, Vandpd, Vec, Vec, Vec)                        // AVX  AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vandpd, Vandpd, Vec, Vec, Mem)                        // AVX  AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vandps, Vandps, Vec, Vec, Vec)                        // AVX  AVX512_DQ{kz|b32}
+  ASMJIT_INST_3x(vandps, Vandps, Vec, Vec, Mem)                        // AVX  AVX512_DQ{kz|b32}
+  ASMJIT_INST_3x(vblendmb, Vblendmb, Vec, Vec, Vec)                    //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vblendmb, Vblendmb, Vec, Vec, Mem)                    //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vblendmd, Vblendmd, Vec, Vec, Vec)                    //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vblendmd, Vblendmd, Vec, Vec, Mem)                    //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vblendmpd, Vblendmpd, Vec, Vec, Vec)                  //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vblendmpd, Vblendmpd, Vec, Vec, Mem)                  //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vblendmps, Vblendmps, Vec, Vec, Vec)                  //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vblendmps, Vblendmps, Vec, Vec, Mem)                  //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vblendmq, Vblendmq, Vec, Vec, Vec)                    //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vblendmq, Vblendmq, Vec, Vec, Mem)                    //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vblendmw, Vblendmw, Vec, Vec, Vec)                    //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vblendmw, Vblendmw, Vec, Vec, Mem)                    //      AVX512_BW{kz}
+  ASMJIT_INST_4i(vblendpd, Vblendpd, Vec, Vec, Vec, Imm)               // AVX
+  ASMJIT_INST_4i(vblendpd, Vblendpd, Vec, Vec, Mem, Imm)               // AVX
+  ASMJIT_INST_4i(vblendps, Vblendps, Vec, Vec, Vec, Imm)               // AVX
+  ASMJIT_INST_4i(vblendps, Vblendps, Vec, Vec, Mem, Imm)               // AVX
+  ASMJIT_INST_4x(vblendvpd, Vblendvpd, Vec, Vec, Vec, Vec)             // AVX
+  ASMJIT_INST_4x(vblendvpd, Vblendvpd, Vec, Vec, Mem, Vec)             // AVX
+  ASMJIT_INST_4x(vblendvps, Vblendvps, Vec, Vec, Vec, Vec)             // AVX
+  ASMJIT_INST_4x(vblendvps, Vblendvps, Vec, Vec, Mem, Vec)             // AVX
+  ASMJIT_INST_2x(vbroadcastf128, Vbroadcastf128, Vec, Mem)             // AVX
+  ASMJIT_INST_2x(vbroadcastf32x2, Vbroadcastf32x2, Vec, Vec)           //      AVX512_DQ{kz}
+  ASMJIT_INST_2x(vbroadcastf32x2, Vbroadcastf32x2, Vec, Mem)           //      AVX512_DQ{kz}
+  ASMJIT_INST_2x(vbroadcastf32x4, Vbroadcastf32x4, Vec, Mem)           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vbroadcastf32x8, Vbroadcastf32x8, Vec, Mem)           //      AVX512_DQ{kz}
+  ASMJIT_INST_2x(vbroadcastf64x2, Vbroadcastf64x2, Vec, Mem)           //      AVX512_DQ{kz}
+  ASMJIT_INST_2x(vbroadcastf64x4, Vbroadcastf64x4, Vec, Mem)           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vbroadcasti128, Vbroadcasti128, Vec, Mem)             // AVX2
+  ASMJIT_INST_2x(vbroadcasti32x2, Vbroadcasti32x2, Vec, Vec)           //      AVX512_DQ{kz}
+  ASMJIT_INST_2x(vbroadcasti32x2, Vbroadcasti32x2, Vec, Mem)           //      AVX512_DQ{kz}
+  ASMJIT_INST_2x(vbroadcasti32x4, Vbroadcasti32x4, Vec, Mem)           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vbroadcasti32x8, Vbroadcasti32x8, Vec, Mem)           //      AVX512_DQ{kz}
+  ASMJIT_INST_2x(vbroadcasti64x2, Vbroadcasti64x2, Vec, Vec)           //      AVX512_DQ{kz}
+  ASMJIT_INST_2x(vbroadcasti64x2, Vbroadcasti64x2, Vec, Mem)           //      AVX512_DQ{kz}
+  ASMJIT_INST_2x(vbroadcasti64x4, Vbroadcasti64x4, Vec, Vec)           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vbroadcasti64x4, Vbroadcasti64x4, Vec, Mem)           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vbroadcastsd, Vbroadcastsd, Vec, Mem)                 // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vbroadcastsd, Vbroadcastsd, Vec, Xmm)                 // AVX2 AVX512_F{kz}
+  ASMJIT_INST_2x(vbroadcastss, Vbroadcastss, Vec, Mem)                 // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vbroadcastss, Vbroadcastss, Vec, Xmm)                 // AVX2 AVX512_F{kz}
+  ASMJIT_INST_4i(vcmppd, Vcmppd, Vec, Vec, Vec, Imm)                   // AVX
+  ASMJIT_INST_4i(vcmppd, Vcmppd, Vec, Vec, Mem, Imm)                   // AVX
+  ASMJIT_INST_4i(vcmppd, Vcmppd, KReg, Vec, Vec, Imm)                  //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vcmppd, Vcmppd, KReg, Vec, Mem, Imm)                  //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vcmpps, Vcmpps, Vec, Vec, Vec, Imm)                   // AVX
+  ASMJIT_INST_4i(vcmpps, Vcmpps, Vec, Vec, Mem, Imm)                   // AVX
+  ASMJIT_INST_4i(vcmpps, Vcmpps, KReg, Vec, Vec, Imm)                  //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vcmpps, Vcmpps, KReg, Vec, Mem, Imm)                  //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vcmpsd, Vcmpsd, Xmm, Xmm, Xmm, Imm)                   // AVX
+  ASMJIT_INST_4i(vcmpsd, Vcmpsd, Xmm, Xmm, Mem, Imm)                   // AVX
+  ASMJIT_INST_4i(vcmpsd, Vcmpsd, KReg, Xmm, Xmm, Imm)                  //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vcmpsd, Vcmpsd, KReg, Xmm, Mem, Imm)                  //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vcmpss, Vcmpss, Xmm, Xmm, Xmm, Imm)                   // AVX
+  ASMJIT_INST_4i(vcmpss, Vcmpss, Xmm, Xmm, Mem, Imm)                   // AVX
+  ASMJIT_INST_4i(vcmpss, Vcmpss, KReg, Xmm, Xmm, Imm)                  //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vcmpss, Vcmpss, KReg, Xmm, Mem, Imm)                  //      AVX512_F{kz|sae}
+  ASMJIT_INST_2x(vcomisd, Vcomisd, Xmm, Xmm)                           // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vcomisd, Vcomisd, Xmm, Mem)                           // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vcomiss, Vcomiss, Xmm, Xmm)                           // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vcomiss, Vcomiss, Xmm, Mem)                           // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vcompresspd, Vcompresspd, Vec, Vec)                   //      AVX512_F{kz}
+  ASMJIT_INST_2x(vcompresspd, Vcompresspd, Mem, Vec)                   //      AVX512_F{kz}
+  ASMJIT_INST_2x(vcompressps, Vcompressps, Vec, Vec)                   //      AVX512_F{kz}
+  ASMJIT_INST_2x(vcompressps, Vcompressps, Mem, Vec)                   //      AVX512_F{kz}
+  ASMJIT_INST_2x(vcvtdq2pd, Vcvtdq2pd, Vec, Vec)                       // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtdq2pd, Vcvtdq2pd, Vec, Mem)                       // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtdq2ps, Vcvtdq2ps, Vec, Vec)                       // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtdq2ps, Vcvtdq2ps, Vec, Mem)                       // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vcvtne2ps2bf16, Vcvtne2ps2bf16, Vec, Vec, Vec)        //      AVX512_BF16{kz|b32}
+  ASMJIT_INST_3x(vcvtne2ps2bf16, Vcvtne2ps2bf16, Vec, Vec, Mem)        //      AVX512_BF16{kz|b32}
+  ASMJIT_INST_2x(vcvtneps2bf16, Vcvtneps2bf16, Vec, Vec)               //      AVX512_BF16{kz|b32}
+  ASMJIT_INST_2x(vcvtneps2bf16, Vcvtneps2bf16, Vec, Mem)               //      AVX512_BF16{kz|b32}
+  ASMJIT_INST_2x(vcvtpd2dq, Vcvtpd2dq, Vec, Vec)                       // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvtpd2dq, Vcvtpd2dq, Vec, Mem)                       // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvtpd2ps, Vcvtpd2ps, Vec, Vec)                       // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvtpd2ps, Vcvtpd2ps, Vec, Mem)                       // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvtpd2qq, Vcvtpd2qq, Vec, Vec)                       //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtpd2qq, Vcvtpd2qq, Vec, Mem)                       //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtpd2udq, Vcvtpd2udq, Vec, Vec)                     //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvtpd2udq, Vcvtpd2udq, Vec, Mem)                     //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvtpd2uqq, Vcvtpd2uqq, Vec, Vec)                     //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtpd2uqq, Vcvtpd2uqq, Vec, Mem)                     //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtph2ps, Vcvtph2ps, Vec, Vec)                       // F16C AVX512_F{kz}
+  ASMJIT_INST_2x(vcvtph2ps, Vcvtph2ps, Vec, Mem)                       // F16C AVX512_F{kz}
+  ASMJIT_INST_2x(vcvtps2dq, Vcvtps2dq, Vec, Vec)                       // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtps2dq, Vcvtps2dq, Vec, Mem)                       // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtps2pd, Vcvtps2pd, Vec, Vec)                       // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtps2pd, Vcvtps2pd, Vec, Mem)                       // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vcvtps2ph, Vcvtps2ph, Vec, Vec, Imm)                  // F16C AVX512_F{kz}
+  ASMJIT_INST_3i(vcvtps2ph, Vcvtps2ph, Mem, Vec, Imm)                  // F16C AVX512_F{kz}
+  ASMJIT_INST_2x(vcvtps2qq, Vcvtps2qq, Vec, Vec)                       //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_2x(vcvtps2qq, Vcvtps2qq, Vec, Mem)                       //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_2x(vcvtps2udq, Vcvtps2udq, Vec, Vec)                     //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtps2udq, Vcvtps2udq, Vec, Mem)                     //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtps2uqq, Vcvtps2uqq, Vec, Vec)                     //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_2x(vcvtps2uqq, Vcvtps2uqq, Vec, Mem)                     //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_2x(vcvtqq2pd, Vcvtqq2pd, Vec, Vec)                       //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtqq2pd, Vcvtqq2pd, Vec, Mem)                       //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtqq2ps, Vcvtqq2ps, Vec, Vec)                       //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtqq2ps, Vcvtqq2ps, Vec, Mem)                       //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtsd2si, Vcvtsd2si, Gp, Xmm)                        // AVX  AVX512_F{er}
+  ASMJIT_INST_2x(vcvtsd2si, Vcvtsd2si, Gp, Mem)                        // AVX  AVX512_F{er}
+  ASMJIT_INST_3x(vcvtsd2ss, Vcvtsd2ss, Xmm, Xmm, Xmm)                  // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vcvtsd2ss, Vcvtsd2ss, Xmm, Xmm, Mem)                  // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_2x(vcvtsd2usi, Vcvtsd2usi, Gp, Xmm)                      //      AVX512_F{er}
+  ASMJIT_INST_2x(vcvtsd2usi, Vcvtsd2usi, Gp, Mem)                      //      AVX512_F{er}
+  ASMJIT_INST_3x(vcvtsi2sd, Vcvtsi2sd, Xmm, Xmm, Gp)                   // AVX  AVX512_F{er}
+  ASMJIT_INST_3x(vcvtsi2sd, Vcvtsi2sd, Xmm, Xmm, Mem)                  // AVX  AVX512_F{er}
+  ASMJIT_INST_3x(vcvtsi2ss, Vcvtsi2ss, Xmm, Xmm, Gp)                   // AVX  AVX512_F{er}
+  ASMJIT_INST_3x(vcvtsi2ss, Vcvtsi2ss, Xmm, Xmm, Mem)                  // AVX  AVX512_F{er}
+  ASMJIT_INST_3x(vcvtss2sd, Vcvtss2sd, Xmm, Xmm, Xmm)                  // AVX  AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vcvtss2sd, Vcvtss2sd, Xmm, Xmm, Mem)                  // AVX  AVX512_F{kz|sae}
+  ASMJIT_INST_2x(vcvtss2si, Vcvtss2si, Gp, Xmm)                        // AVX  AVX512_F{er}
+  ASMJIT_INST_2x(vcvtss2si, Vcvtss2si, Gp, Mem)                        // AVX  AVX512_F{er}
+  ASMJIT_INST_2x(vcvtss2usi, Vcvtss2usi, Gp, Xmm)                      //      AVX512_F{er}
+  ASMJIT_INST_2x(vcvtss2usi, Vcvtss2usi, Gp, Mem)                      //      AVX512_F{er}
+  ASMJIT_INST_2x(vcvttpd2dq, Vcvttpd2dq, Vec, Vec)                     // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvttpd2dq, Vcvttpd2dq, Vec, Mem)                     // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvttpd2qq, Vcvttpd2qq, Vec, Vec)                     //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvttpd2qq, Vcvttpd2qq, Vec, Mem)                     //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvttpd2udq, Vcvttpd2udq, Vec, Vec)                   //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvttpd2udq, Vcvttpd2udq, Vec, Mem)                   //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vcvttpd2uqq, Vcvttpd2uqq, Vec, Vec)                   //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvttpd2uqq, Vcvttpd2uqq, Vec, Mem)                   //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvttps2dq, Vcvttps2dq, Vec, Vec)                     // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvttps2dq, Vcvttps2dq, Vec, Mem)                     // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvttps2qq, Vcvttps2qq, Vec, Vec)                     //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_2x(vcvttps2qq, Vcvttps2qq, Vec, Mem)                     //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_2x(vcvttps2udq, Vcvttps2udq, Vec, Vec)                   //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvttps2udq, Vcvttps2udq, Vec, Mem)                   //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvttps2uqq, Vcvttps2uqq, Vec, Vec)                   //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_2x(vcvttps2uqq, Vcvttps2uqq, Vec, Mem)                   //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_2x(vcvttsd2si, Vcvttsd2si, Gp, Xmm)                      // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vcvttsd2si, Vcvttsd2si, Gp, Mem)                      // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vcvttsd2usi, Vcvttsd2usi, Gp, Xmm)                    //      AVX512_F{sae}
+  ASMJIT_INST_2x(vcvttsd2usi, Vcvttsd2usi, Gp, Mem)                    //      AVX512_F{sae}
+  ASMJIT_INST_2x(vcvttss2si, Vcvttss2si, Gp, Xmm)                      // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vcvttss2si, Vcvttss2si, Gp, Mem)                      // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vcvttss2usi, Vcvttss2usi, Gp, Xmm)                    //      AVX512_F{sae}
+  ASMJIT_INST_2x(vcvttss2usi, Vcvttss2usi, Gp, Mem)                    //      AVX512_F{sae}
+  ASMJIT_INST_2x(vcvtudq2pd, Vcvtudq2pd, Vec, Vec)                     //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtudq2pd, Vcvtudq2pd, Vec, Mem)                     //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtudq2ps, Vcvtudq2ps, Vec, Vec)                     //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtudq2ps, Vcvtudq2ps, Vec, Mem)                     //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vcvtuqq2pd, Vcvtuqq2pd, Vec, Vec)                     //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtuqq2pd, Vcvtuqq2pd, Vec, Mem)                     //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtuqq2ps, Vcvtuqq2ps, Vec, Vec)                     //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_2x(vcvtuqq2ps, Vcvtuqq2ps, Vec, Mem)                     //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vcvtusi2sd, Vcvtusi2sd, Xmm, Xmm, Gp)                 //      AVX512_F{er}
+  ASMJIT_INST_3x(vcvtusi2sd, Vcvtusi2sd, Xmm, Xmm, Mem)                //      AVX512_F{er}
+  ASMJIT_INST_3x(vcvtusi2ss, Vcvtusi2ss, Xmm, Xmm, Gp)                 //      AVX512_F{er}
+  ASMJIT_INST_3x(vcvtusi2ss, Vcvtusi2ss, Xmm, Xmm, Mem)                //      AVX512_F{er}
+  ASMJIT_INST_4i(vdbpsadbw, Vdbpsadbw, Vec, Vec, Vec, Imm)             //      AVX512_BW{kz}
+  ASMJIT_INST_4i(vdbpsadbw, Vdbpsadbw, Vec, Vec, Mem, Imm)             //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vdivpd, Vdivpd, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vdivpd, Vdivpd, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vdivps, Vdivps, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vdivps, Vdivps, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vdivsd, Vdivsd, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vdivsd, Vdivsd, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vdivss, Vdivss, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vdivss, Vdivss, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vdpbf16ps, Vdpbf16ps, Vec, Vec, Vec)                  //      AVX512_BF16{kz|b32}
+  ASMJIT_INST_3x(vdpbf16ps, Vdpbf16ps, Vec, Vec, Mem)                  //      AVX512_BF16{kz|b32}
+  ASMJIT_INST_4i(vdppd, Vdppd, Vec, Vec, Vec, Imm)                     // AVX
+  ASMJIT_INST_4i(vdppd, Vdppd, Vec, Vec, Mem, Imm)                     // AVX
+  ASMJIT_INST_4i(vdpps, Vdpps, Vec, Vec, Vec, Imm)                     // AVX
+  ASMJIT_INST_4i(vdpps, Vdpps, Vec, Vec, Mem, Imm)                     // AVX
+  ASMJIT_INST_2x(vexp2pd, Vexp2pd, Vec, Vec)                           //      AVX512_ER{kz|sae|b64}
+  ASMJIT_INST_2x(vexp2pd, Vexp2pd, Vec, Mem)                           //      AVX512_ER{kz|sae|b64}
+  ASMJIT_INST_2x(vexp2ps, Vexp2ps, Vec, Vec)                           //      AVX512_ER{kz|sae|b32}
+  ASMJIT_INST_2x(vexp2ps, Vexp2ps, Vec, Mem)                           //      AVX512_ER{kz|sae|b32}
+  ASMJIT_INST_2x(vexpandpd, Vexpandpd, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vexpandpd, Vexpandpd, Vec, Mem)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vexpandps, Vexpandps, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vexpandps, Vexpandps, Vec, Mem)                       //      AVX512_F{kz}
+  ASMJIT_INST_3i(vextractf128, Vextractf128, Vec, Vec, Imm)            // AVX
+  ASMJIT_INST_3i(vextractf128, Vextractf128, Mem, Vec, Imm)            // AVX
+  ASMJIT_INST_3i(vextractf32x4, Vextractf32x4, Vec, Vec, Imm)          //      AVX512_F{kz}
+  ASMJIT_INST_3i(vextractf32x4, Vextractf32x4, Mem, Vec, Imm)          //      AVX512_F{kz}
+  ASMJIT_INST_3i(vextractf32x8, Vextractf32x8, Vec, Vec, Imm)          //      AVX512_DQ{kz}
+  ASMJIT_INST_3i(vextractf32x8, Vextractf32x8, Mem, Vec, Imm)          //      AVX512_DQ{kz}
+  ASMJIT_INST_3i(vextractf64x2, Vextractf64x2, Vec, Vec, Imm)          //      AVX512_DQ{kz}
+  ASMJIT_INST_3i(vextractf64x2, Vextractf64x2, Mem, Vec, Imm)          //      AVX512_DQ{kz}
+  ASMJIT_INST_3i(vextractf64x4, Vextractf64x4, Vec, Vec, Imm)          //      AVX512_F{kz}
+  ASMJIT_INST_3i(vextractf64x4, Vextractf64x4, Mem, Vec, Imm)          //      AVX512_F{kz}
+  ASMJIT_INST_3i(vextracti128, Vextracti128, Vec, Vec, Imm)            // AVX2
+  ASMJIT_INST_3i(vextracti128, Vextracti128, Mem, Vec, Imm)            // AVX2
+  ASMJIT_INST_3i(vextracti32x4, Vextracti32x4, Vec, Vec, Imm)          //      AVX512_F{kz}
+  ASMJIT_INST_3i(vextracti32x4, Vextracti32x4, Mem, Vec, Imm)          //      AVX512_F{kz}
+  ASMJIT_INST_3i(vextracti32x8, Vextracti32x8, Vec, Vec, Imm)          //      AVX512_DQ{kz}
+  ASMJIT_INST_3i(vextracti32x8, Vextracti32x8, Mem, Vec, Imm)          //      AVX512_DQ{kz}
+  ASMJIT_INST_3i(vextracti64x2, Vextracti64x2, Vec, Vec, Imm)          //      AVX512_DQ{kz}
+  ASMJIT_INST_3i(vextracti64x2, Vextracti64x2, Mem, Vec, Imm)          //      AVX512_DQ{kz}
+  ASMJIT_INST_3i(vextracti64x4, Vextracti64x4, Vec, Vec, Imm)          //      AVX512_F{kz}
+  ASMJIT_INST_3i(vextracti64x4, Vextracti64x4, Mem, Vec, Imm)          //      AVX512_F{kz}
+  ASMJIT_INST_3i(vextractps, Vextractps, Gp, Xmm, Imm)                 // AVX  AVX512_F
+  ASMJIT_INST_3i(vextractps, Vextractps, Mem, Xmm, Imm)                // AVX  AVX512_F
+  ASMJIT_INST_4i(vfixupimmpd, Vfixupimmpd, Vec, Vec, Vec, Imm)         //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vfixupimmpd, Vfixupimmpd, Vec, Vec, Mem, Imm)         //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vfixupimmps, Vfixupimmps, Vec, Vec, Vec, Imm)         //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vfixupimmps, Vfixupimmps, Vec, Vec, Mem, Imm)         //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vfixupimmsd, Vfixupimmsd, Xmm, Xmm, Xmm, Imm)         //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vfixupimmsd, Vfixupimmsd, Xmm, Xmm, Mem, Imm)         //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vfixupimmss, Vfixupimmss, Xmm, Xmm, Xmm, Imm)         //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vfixupimmss, Vfixupimmss, Xmm, Xmm, Mem, Imm)         //      AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vfmadd132pd, Vfmadd132pd, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmadd132pd, Vfmadd132pd, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmadd132ps, Vfmadd132ps, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmadd132ps, Vfmadd132ps, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmadd132sd, Vfmadd132sd, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd132sd, Vfmadd132sd, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd132ss, Vfmadd132ss, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd132ss, Vfmadd132ss, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd213pd, Vfmadd213pd, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmadd213pd, Vfmadd213pd, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmadd213ps, Vfmadd213ps, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmadd213ps, Vfmadd213ps, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmadd213sd, Vfmadd213sd, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd213sd, Vfmadd213sd, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd213ss, Vfmadd213ss, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd213ss, Vfmadd213ss, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd231pd, Vfmadd231pd, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmadd231pd, Vfmadd231pd, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmadd231ps, Vfmadd231ps, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmadd231ps, Vfmadd231ps, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmadd231sd, Vfmadd231sd, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd231sd, Vfmadd231sd, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd231ss, Vfmadd231ss, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmadd231ss, Vfmadd231ss, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmaddsub132pd, Vfmaddsub132pd, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmaddsub132pd, Vfmaddsub132pd, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmaddsub132ps, Vfmaddsub132ps, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmaddsub132ps, Vfmaddsub132ps, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmaddsub213pd, Vfmaddsub213pd, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmaddsub213pd, Vfmaddsub213pd, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmaddsub213ps, Vfmaddsub213ps, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmaddsub213ps, Vfmaddsub213ps, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmaddsub231pd, Vfmaddsub231pd, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmaddsub231pd, Vfmaddsub231pd, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmaddsub231ps, Vfmaddsub231ps, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmaddsub231ps, Vfmaddsub231ps, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsub132pd, Vfmsub132pd, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsub132pd, Vfmsub132pd, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsub132ps, Vfmsub132ps, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsub132ps, Vfmsub132ps, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsub132sd, Vfmsub132sd, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub132sd, Vfmsub132sd, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub132ss, Vfmsub132ss, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub132ss, Vfmsub132ss, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub213pd, Vfmsub213pd, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsub213pd, Vfmsub213pd, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsub213ps, Vfmsub213ps, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsub213ps, Vfmsub213ps, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsub213sd, Vfmsub213sd, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub213sd, Vfmsub213sd, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub213ss, Vfmsub213ss, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub213ss, Vfmsub213ss, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub231pd, Vfmsub231pd, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsub231pd, Vfmsub231pd, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsub231ps, Vfmsub231ps, Vec, Vec, Vec)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsub231ps, Vfmsub231ps, Vec, Vec, Mem)              // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsub231sd, Vfmsub231sd, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub231sd, Vfmsub231sd, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub231ss, Vfmsub231ss, Xmm, Xmm, Xmm)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsub231ss, Vfmsub231ss, Xmm, Xmm, Mem)              // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfmsubadd132pd, Vfmsubadd132pd, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsubadd132pd, Vfmsubadd132pd, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsubadd132ps, Vfmsubadd132ps, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsubadd132ps, Vfmsubadd132ps, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsubadd213pd, Vfmsubadd213pd, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsubadd213pd, Vfmsubadd213pd, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsubadd213ps, Vfmsubadd213ps, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsubadd213ps, Vfmsubadd213ps, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsubadd231pd, Vfmsubadd231pd, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsubadd231pd, Vfmsubadd231pd, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfmsubadd231ps, Vfmsubadd231ps, Vec, Vec, Vec)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfmsubadd231ps, Vfmsubadd231ps, Vec, Vec, Mem)        // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmadd132pd, Vfnmadd132pd, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmadd132pd, Vfnmadd132pd, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmadd132ps, Vfnmadd132ps, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmadd132ps, Vfnmadd132ps, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmadd132sd, Vfnmadd132sd, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd132sd, Vfnmadd132sd, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd132ss, Vfnmadd132ss, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd132ss, Vfnmadd132ss, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd213pd, Vfnmadd213pd, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmadd213pd, Vfnmadd213pd, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmadd213ps, Vfnmadd213ps, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmadd213ps, Vfnmadd213ps, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmadd213sd, Vfnmadd213sd, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd213sd, Vfnmadd213sd, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd213ss, Vfnmadd213ss, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd213ss, Vfnmadd213ss, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd231pd, Vfnmadd231pd, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmadd231pd, Vfnmadd231pd, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmadd231ps, Vfnmadd231ps, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmadd231ps, Vfnmadd231ps, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmadd231sd, Vfnmadd231sd, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd231sd, Vfnmadd231sd, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd231ss, Vfnmadd231ss, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmadd231ss, Vfnmadd231ss, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub132pd, Vfnmsub132pd, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmsub132pd, Vfnmsub132pd, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmsub132ps, Vfnmsub132ps, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmsub132ps, Vfnmsub132ps, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmsub132sd, Vfnmsub132sd, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub132sd, Vfnmsub132sd, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub132ss, Vfnmsub132ss, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub132ss, Vfnmsub132ss, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub213pd, Vfnmsub213pd, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmsub213pd, Vfnmsub213pd, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmsub213ps, Vfnmsub213ps, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmsub213ps, Vfnmsub213ps, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmsub213sd, Vfnmsub213sd, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub213sd, Vfnmsub213sd, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub213ss, Vfnmsub213ss, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub213ss, Vfnmsub213ss, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub231pd, Vfnmsub231pd, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmsub231pd, Vfnmsub231pd, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vfnmsub231ps, Vfnmsub231ps, Vec, Vec, Vec)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmsub231ps, Vfnmsub231ps, Vec, Vec, Mem)            // FMA  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vfnmsub231sd, Vfnmsub231sd, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub231sd, Vfnmsub231sd, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub231ss, Vfnmsub231ss, Xmm, Xmm, Xmm)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vfnmsub231ss, Vfnmsub231ss, Xmm, Xmm, Mem)            // FMA  AVX512_F{kz|er}
+  ASMJIT_INST_3i(vfpclasspd, Vfpclasspd, KReg, Vec, Imm)               //      AVX512_DQ{k|b64}
+  ASMJIT_INST_3i(vfpclasspd, Vfpclasspd, KReg, Mem, Imm)               //      AVX512_DQ{k|b64}
+  ASMJIT_INST_3i(vfpclassps, Vfpclassps, KReg, Vec, Imm)               //      AVX512_DQ{k|b32}
+  ASMJIT_INST_3i(vfpclassps, Vfpclassps, KReg, Mem, Imm)               //      AVX512_DQ{k|b32}
+  ASMJIT_INST_3i(vfpclasssd, Vfpclasssd, KReg, Xmm, Imm)               //      AVX512_DQ{k}
+  ASMJIT_INST_3i(vfpclasssd, Vfpclasssd, KReg, Mem, Imm)               //      AVX512_DQ{k}
+  ASMJIT_INST_3i(vfpclassss, Vfpclassss, KReg, Xmm, Imm)               //      AVX512_DQ{k}
+  ASMJIT_INST_3i(vfpclassss, Vfpclassss, KReg, Mem, Imm)               //      AVX512_DQ{k}
+  ASMJIT_INST_2x(vgatherdpd, Vgatherdpd, Vec, Mem)                     //      AVX512_F{k}
+  ASMJIT_INST_3x(vgatherdpd, Vgatherdpd, Vec, Mem, Vec)                // AVX2
+  ASMJIT_INST_2x(vgatherdps, Vgatherdps, Vec, Mem)                     //      AVX512_F{k}
+  ASMJIT_INST_3x(vgatherdps, Vgatherdps, Vec, Mem, Vec)                // AVX2
+  ASMJIT_INST_1x(vgatherpf0dpd, Vgatherpf0dpd, Mem)                    //      AVX512_PF{k}
+  ASMJIT_INST_1x(vgatherpf0dps, Vgatherpf0dps, Mem)                    //      AVX512_PF{k}
+  ASMJIT_INST_1x(vgatherpf0qpd, Vgatherpf0qpd, Mem)                    //      AVX512_PF{k}
+  ASMJIT_INST_1x(vgatherpf0qps, Vgatherpf0qps, Mem)                    //      AVX512_PF{k}
+  ASMJIT_INST_1x(vgatherpf1dpd, Vgatherpf1dpd, Mem)                    //      AVX512_PF{k}
+  ASMJIT_INST_1x(vgatherpf1dps, Vgatherpf1dps, Mem)                    //      AVX512_PF{k}
+  ASMJIT_INST_1x(vgatherpf1qpd, Vgatherpf1qpd, Mem)                    //      AVX512_PF{k}
+  ASMJIT_INST_1x(vgatherpf1qps, Vgatherpf1qps, Mem)                    //      AVX512_PF{k}
+  ASMJIT_INST_2x(vgatherqpd, Vgatherqpd, Vec, Mem)                     //      AVX512_F{k}
+  ASMJIT_INST_3x(vgatherqpd, Vgatherqpd, Vec, Mem, Vec)                // AVX2
+  ASMJIT_INST_2x(vgatherqps, Vgatherqps, Vec, Mem)                     //      AVX512_F{k}
+  ASMJIT_INST_3x(vgatherqps, Vgatherqps, Vec, Mem, Vec)                // AVX2
+  ASMJIT_INST_2x(vgetexppd, Vgetexppd, Vec, Vec)                       //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vgetexppd, Vgetexppd, Vec, Mem)                       //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vgetexpps, Vgetexpps, Vec, Vec)                       //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vgetexpps, Vgetexpps, Vec, Mem)                       //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vgetexpsd, Vgetexpsd, Xmm, Xmm, Xmm)                  //      AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vgetexpsd, Vgetexpsd, Xmm, Xmm, Mem)                  //      AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vgetexpss, Vgetexpss, Xmm, Xmm, Xmm)                  //      AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vgetexpss, Vgetexpss, Xmm, Xmm, Mem)                  //      AVX512_F{kz|sae}
+  ASMJIT_INST_3i(vgetmantpd, Vgetmantpd, Vec, Vec, Imm)                //      AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vgetmantpd, Vgetmantpd, Vec, Mem, Imm)                //      AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vgetmantps, Vgetmantps, Vec, Vec, Imm)                //      AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vgetmantps, Vgetmantps, Vec, Mem, Imm)                //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vgetmantsd, Vgetmantsd, Xmm, Xmm, Xmm, Imm)           //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vgetmantsd, Vgetmantsd, Xmm, Xmm, Mem, Imm)           //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vgetmantss, Vgetmantss, Xmm, Xmm, Xmm, Imm)           //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vgetmantss, Vgetmantss, Xmm, Xmm, Mem, Imm)           //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vgf2p8affineinvqb, Vgf2p8affineinvqb,Vec,Vec,Vec,Imm) // AVX  AVX512_VL{kz} GFNI
+  ASMJIT_INST_4i(vgf2p8affineinvqb, Vgf2p8affineinvqb,Vec,Vec,Mem,Imm) // AVX  AVX512_VL{kz} GFNI
+  ASMJIT_INST_4i(vgf2p8affineqb, Vgf2p8affineqb, Vec, Vec, Vec, Imm)   // AVX  AVX512_VL{kz} GFNI
+  ASMJIT_INST_4i(vgf2p8affineqb, Vgf2p8affineqb, Vec, Vec, Mem, Imm)   // AVX  AVX512_VL{kz} GFNI
+  ASMJIT_INST_3x(vgf2p8mulb, Vgf2p8mulb, Vec, Vec, Vec)                // AVX  AVX512_VL{kz} GFNI
+  ASMJIT_INST_3x(vgf2p8mulb, Vgf2p8mulb, Vec, Vec, Mem)                // AVX  AVX512_VL{kz} GFNI
+  ASMJIT_INST_3x(vhaddpd, Vhaddpd, Vec, Vec, Vec)                      // AVX
+  ASMJIT_INST_3x(vhaddpd, Vhaddpd, Vec, Vec, Mem)                      // AVX
+  ASMJIT_INST_3x(vhaddps, Vhaddps, Vec, Vec, Vec)                      // AVX
+  ASMJIT_INST_3x(vhaddps, Vhaddps, Vec, Vec, Mem)                      // AVX
+  ASMJIT_INST_3x(vhsubpd, Vhsubpd, Vec, Vec, Vec)                      // AVX
+  ASMJIT_INST_3x(vhsubpd, Vhsubpd, Vec, Vec, Mem)                      // AVX
+  ASMJIT_INST_3x(vhsubps, Vhsubps, Vec, Vec, Vec)                      // AVX
+  ASMJIT_INST_3x(vhsubps, Vhsubps, Vec, Vec, Mem)                      // AVX
+  ASMJIT_INST_4i(vinsertf128, Vinsertf128, Vec, Vec, Vec, Imm)         // AVX
+  ASMJIT_INST_4i(vinsertf128, Vinsertf128, Vec, Vec, Mem, Imm)         // AVX
+  ASMJIT_INST_4i(vinsertf32x4, Vinsertf32x4, Vec, Vec, Vec, Imm)       //      AVX512_F{kz}
+  ASMJIT_INST_4i(vinsertf32x4, Vinsertf32x4, Vec, Vec, Mem, Imm)       //      AVX512_F{kz}
+  ASMJIT_INST_4i(vinsertf32x8, Vinsertf32x8, Vec, Vec, Vec, Imm)       //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vinsertf32x8, Vinsertf32x8, Vec, Vec, Mem, Imm)       //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vinsertf64x2, Vinsertf64x2, Vec, Vec, Vec, Imm)       //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vinsertf64x2, Vinsertf64x2, Vec, Vec, Mem, Imm)       //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vinsertf64x4, Vinsertf64x4, Vec, Vec, Vec, Imm)       //      AVX512_F{kz}
+  ASMJIT_INST_4i(vinsertf64x4, Vinsertf64x4, Vec, Vec, Mem, Imm)       //      AVX512_F{kz}
+  ASMJIT_INST_4i(vinserti128, Vinserti128, Vec, Vec, Vec, Imm)         // AVX2
+  ASMJIT_INST_4i(vinserti128, Vinserti128, Vec, Vec, Mem, Imm)         // AVX2
+  ASMJIT_INST_4i(vinserti32x4, Vinserti32x4, Vec, Vec, Vec, Imm)       //      AVX512_F{kz}
+  ASMJIT_INST_4i(vinserti32x4, Vinserti32x4, Vec, Vec, Mem, Imm)       //      AVX512_F{kz}
+  ASMJIT_INST_4i(vinserti32x8, Vinserti32x8, Vec, Vec, Vec, Imm)       //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vinserti32x8, Vinserti32x8, Vec, Vec, Mem, Imm)       //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vinserti64x2, Vinserti64x2, Vec, Vec, Vec, Imm)       //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vinserti64x2, Vinserti64x2, Vec, Vec, Mem, Imm)       //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vinserti64x4, Vinserti64x4, Vec, Vec, Vec, Imm)       //      AVX512_F{kz}
+  ASMJIT_INST_4i(vinserti64x4, Vinserti64x4, Vec, Vec, Mem, Imm)       //      AVX512_F{kz}
+  ASMJIT_INST_4i(vinsertps, Vinsertps, Xmm, Xmm, Xmm, Imm)             // AVX  AVX512_F
+  ASMJIT_INST_4i(vinsertps, Vinsertps, Xmm, Xmm, Mem, Imm)             // AVX  AVX512_F
+  ASMJIT_INST_2x(vlddqu, Vlddqu, Vec, Mem)                             // AVX
+  ASMJIT_INST_1x(vldmxcsr, Vldmxcsr, Mem)                              // AVX
+  ASMJIT_INST_3x(vmaskmovdqu, Vmaskmovdqu, Vec, Vec, DS_ZDI)           // AVX  [EXPLICIT]
+  ASMJIT_INST_3x(vmaskmovpd, Vmaskmovpd, Mem, Vec, Vec)                // AVX
+  ASMJIT_INST_3x(vmaskmovpd, Vmaskmovpd, Vec, Vec, Mem)                // AVX
+  ASMJIT_INST_3x(vmaskmovps, Vmaskmovps, Mem, Vec, Vec)                // AVX
+  ASMJIT_INST_3x(vmaskmovps, Vmaskmovps, Vec, Vec, Mem)                // AVX
+  ASMJIT_INST_3x(vmaxpd, Vmaxpd, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vmaxpd, Vmaxpd, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vmaxps, Vmaxps, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vmaxps, Vmaxps, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vmaxsd, Vmaxsd, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vmaxsd, Vmaxsd, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vmaxss, Vmaxss, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vmaxss, Vmaxss, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vminpd, Vminpd, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vminpd, Vminpd, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vminps, Vminps, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vminps, Vminps, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vminsd, Vminsd, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vminsd, Vminsd, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vminss, Vminss, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|sae}
+  ASMJIT_INST_3x(vminss, Vminss, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|sae}
+  ASMJIT_INST_2x(vmovapd, Vmovapd, Vec, Vec)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovapd, Vmovapd, Vec, Mem)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovapd, Vmovapd, Mem, Vec)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovaps, Vmovaps, Vec, Vec)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovaps, Vmovaps, Vec, Mem)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovaps, Vmovaps, Mem, Vec)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovd, Vmovd, Gp, Xmm)                                // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovd, Vmovd, Mem, Xmm)                               // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovd, Vmovd, Xmm, Gp)                                // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovd, Vmovd, Xmm, Mem)                               // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovddup, Vmovddup, Vec, Vec)                         // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovddup, Vmovddup, Vec, Mem)                         // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqa, Vmovdqa, Vec, Vec)                           // AVX
+  ASMJIT_INST_2x(vmovdqa, Vmovdqa, Vec, Mem)                           // AVX
+  ASMJIT_INST_2x(vmovdqa, Vmovdqa, Mem, Vec)                           // AVX
+  ASMJIT_INST_2x(vmovdqa32, Vmovdqa32, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqa32, Vmovdqa32, Vec, Mem)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqa32, Vmovdqa32, Mem, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqa64, Vmovdqa64, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqa64, Vmovdqa64, Vec, Mem)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqa64, Vmovdqa64, Mem, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqu, Vmovdqu, Vec, Vec)                           // AVX
+  ASMJIT_INST_2x(vmovdqu, Vmovdqu, Vec, Mem)                           // AVX
+  ASMJIT_INST_2x(vmovdqu, Vmovdqu, Mem, Vec)                           // AVX
+  ASMJIT_INST_2x(vmovdqu16, Vmovdqu16, Vec, Vec)                       //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vmovdqu16, Vmovdqu16, Vec, Mem)                       //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vmovdqu16, Vmovdqu16, Mem, Vec)                       //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vmovdqu32, Vmovdqu32, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqu32, Vmovdqu32, Vec, Mem)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqu32, Vmovdqu32, Mem, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqu64, Vmovdqu64, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqu64, Vmovdqu64, Vec, Mem)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqu64, Vmovdqu64, Mem, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vmovdqu8, Vmovdqu8, Vec, Vec)                         //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vmovdqu8, Vmovdqu8, Vec, Mem)                         //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vmovdqu8, Vmovdqu8, Mem, Vec)                         //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vmovhlps, Vmovhlps, Xmm, Xmm, Xmm)                    // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovhpd, Vmovhpd, Mem, Xmm)                           // AVX  AVX512_F
+  ASMJIT_INST_3x(vmovhpd, Vmovhpd, Xmm, Xmm, Mem)                      // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovhps, Vmovhps, Mem, Xmm)                           // AVX  AVX512_F
+  ASMJIT_INST_3x(vmovhps, Vmovhps, Xmm, Xmm, Mem)                      // AVX  AVX512_F
+  ASMJIT_INST_3x(vmovlhps, Vmovlhps, Xmm, Xmm, Xmm)                    // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovlpd, Vmovlpd, Mem, Xmm)                           // AVX  AVX512_F
+  ASMJIT_INST_3x(vmovlpd, Vmovlpd, Xmm, Xmm, Mem)                      // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovlps, Vmovlps, Mem, Xmm)                           // AVX  AVX512_F
+  ASMJIT_INST_3x(vmovlps, Vmovlps, Xmm, Xmm, Mem)                      // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovmskpd, Vmovmskpd, Gp, Vec)                        // AVX
+  ASMJIT_INST_2x(vmovmskps, Vmovmskps, Gp, Vec)                        // AVX
+  ASMJIT_INST_2x(vmovntdq, Vmovntdq, Mem, Vec)                         // AVX+ AVX512_F
+  ASMJIT_INST_2x(vmovntdqa, Vmovntdqa, Vec, Mem)                       // AVX+ AVX512_F
+  ASMJIT_INST_2x(vmovntpd, Vmovntpd, Mem, Vec)                         // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovntps, Vmovntps, Mem, Vec)                         // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovq, Vmovq, Gp, Xmm)                                // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovq, Vmovq, Mem, Xmm)                               // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovq, Vmovq, Xmm, Mem)                               // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovq, Vmovq, Xmm, Gp)                                // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovq, Vmovq, Xmm, Xmm)                               // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovsd, Vmovsd, Mem, Xmm)                             // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovsd, Vmovsd, Xmm, Mem)                             // AVX  AVX512_F{kz}
+  ASMJIT_INST_3x(vmovsd, Vmovsd, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovshdup, Vmovshdup, Vec, Vec)                       // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovshdup, Vmovshdup, Vec, Mem)                       // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovsldup, Vmovsldup, Vec, Vec)                       // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovsldup, Vmovsldup, Vec, Mem)                       // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovss, Vmovss, Mem, Xmm)                             // AVX  AVX512_F
+  ASMJIT_INST_2x(vmovss, Vmovss, Xmm, Mem)                             // AVX  AVX512_F{kz}
+  ASMJIT_INST_3x(vmovss, Vmovss, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovupd, Vmovupd, Vec, Vec)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovupd, Vmovupd, Vec, Mem)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovupd, Vmovupd, Mem, Vec)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovups, Vmovups, Vec, Vec)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovups, Vmovups, Vec, Mem)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_2x(vmovups, Vmovups, Mem, Vec)                           // AVX  AVX512_F{kz}
+  ASMJIT_INST_4i(vmpsadbw, Vmpsadbw, Vec, Vec, Vec, Imm)               // AVX+
+  ASMJIT_INST_4i(vmpsadbw, Vmpsadbw, Vec, Vec, Mem, Imm)               // AVX+
+  ASMJIT_INST_3x(vmulpd, Vmulpd, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vmulpd, Vmulpd, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vmulps, Vmulps, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vmulps, Vmulps, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vmulsd, Vmulsd, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vmulsd, Vmulsd, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vmulss, Vmulss, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vmulss, Vmulss, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vorpd, Vorpd, Vec, Vec, Vec)                          // AVX  AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vorpd, Vorpd, Vec, Vec, Mem)                          // AVX  AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vorps, Vorps, Vec, Vec, Vec)                          // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vorps, Vorps, Vec, Vec, Mem)                          // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_4x(vp2intersectd, Vp2intersectd, KReg, KReg, Vec, Vec)   //      AVX512_VP2INTERSECT{kz}
+  ASMJIT_INST_4x(vp2intersectd, Vp2intersectd, KReg, KReg, Vec, Mem)   //      AVX512_VP2INTERSECT{kz}
+  ASMJIT_INST_4x(vp2intersectq, Vp2intersectq, KReg, KReg, Vec, Vec)   //      AVX512_VP2INTERSECT{kz}
+  ASMJIT_INST_4x(vp2intersectq, Vp2intersectq, KReg, KReg, Vec, Mem)   //      AVX512_VP2INTERSECT{kz}
+  ASMJIT_INST_6x(vp4dpwssd, Vp4dpwssd, Zmm, Zmm, Zmm, Zmm, Zmm, Mem)   //      AVX512_4FMAPS{kz}
+  ASMJIT_INST_6x(vp4dpwssds, Vp4dpwssds, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) //      AVX512_4FMAPS{kz}
+  ASMJIT_INST_2x(vpabsb, Vpabsb, Vec, Vec)                             // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_2x(vpabsb, Vpabsb, Vec, Mem)                             // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_2x(vpabsd, Vpabsd, Vec, Vec)                             // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpabsd, Vpabsd, Vec, Mem)                             // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpabsq, Vpabsq, Vec, Vec)                             //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpabsq, Vpabsq, Vec, Mem)                             //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpabsw, Vpabsw, Vec, Vec)                             // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_2x(vpabsw, Vpabsw, Vec, Mem)                             // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpackssdw, Vpackssdw, Vec, Vec, Vec)                  // AVX+ AVX512_BW{kz|b32}
+  ASMJIT_INST_3x(vpackssdw, Vpackssdw, Vec, Vec, Mem)                  // AVX+ AVX512_BW{kz|b32}
+  ASMJIT_INST_3x(vpacksswb, Vpacksswb, Vec, Vec, Vec)                  // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpacksswb, Vpacksswb, Vec, Vec, Mem)                  // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpackusdw, Vpackusdw, Vec, Vec, Vec)                  // AVX+ AVX512_BW{kz|b32}
+  ASMJIT_INST_3x(vpackusdw, Vpackusdw, Vec, Vec, Mem)                  // AVX+ AVX512_BW{kz|b32}
+  ASMJIT_INST_3x(vpackuswb, Vpackuswb, Vec, Vec, Vec)                  // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpackuswb, Vpackuswb, Vec, Vec, Mem)                  // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddb, Vpaddb, Vec, Vec, Vec)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddb, Vpaddb, Vec, Vec, Mem)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddd, Vpaddd, Vec, Vec, Vec)                        // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpaddd, Vpaddd, Vec, Vec, Mem)                        // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpaddq, Vpaddq, Vec, Vec, Vec)                        // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpaddq, Vpaddq, Vec, Vec, Mem)                        // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpaddsb, Vpaddsb, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddsb, Vpaddsb, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddsw, Vpaddsw, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddsw, Vpaddsw, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddusb, Vpaddusb, Vec, Vec, Vec)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddusb, Vpaddusb, Vec, Vec, Mem)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddusw, Vpaddusw, Vec, Vec, Vec)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddusw, Vpaddusw, Vec, Vec, Mem)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddw, Vpaddw, Vec, Vec, Vec)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpaddw, Vpaddw, Vec, Vec, Mem)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_4i(vpalignr, Vpalignr, Vec, Vec, Vec, Imm)               // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_4i(vpalignr, Vpalignr, Vec, Vec, Mem, Imm)               // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpand, Vpand, Vec, Vec, Vec)                          // AVX+
+  ASMJIT_INST_3x(vpand, Vpand, Vec, Vec, Mem)                          // AVX+
+  ASMJIT_INST_3x(vpandd, Vpandd, Vec, Vec, Vec)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpandd, Vpandd, Vec, Vec, Mem)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpandn, Vpandn, Vec, Vec, Vec)                        // AV+
+  ASMJIT_INST_3x(vpandn, Vpandn, Vec, Vec, Mem)                        // AVX+
+  ASMJIT_INST_3x(vpandnd, Vpandnd, Vec, Vec, Vec)                      //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpandnd, Vpandnd, Vec, Vec, Mem)                      //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpandnq, Vpandnq, Vec, Vec, Vec)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpandnq, Vpandnq, Vec, Vec, Mem)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpandq, Vpandq, Vec, Vec, Vec)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpandq, Vpandq, Vec, Vec, Mem)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpavgb, Vpavgb, Vec, Vec, Vec)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpavgb, Vpavgb, Vec, Vec, Mem)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpavgw, Vpavgw, Vec, Vec, Vec)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpavgw, Vpavgw, Vec, Vec, Mem)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_4i(vpblendd, Vpblendd, Vec, Vec, Vec, Imm)               // AVX2
+  ASMJIT_INST_4i(vpblendd, Vpblendd, Vec, Vec, Mem, Imm)               // AVX2
+  ASMJIT_INST_4x(vpblendvb, Vpblendvb, Vec, Vec, Vec, Vec)             // AVX+
+  ASMJIT_INST_4x(vpblendvb, Vpblendvb, Vec, Vec, Mem, Vec)             // AVX+
+  ASMJIT_INST_4i(vpblendw, Vpblendw, Vec, Vec, Vec, Imm)               // AVX+
+  ASMJIT_INST_4i(vpblendw, Vpblendw, Vec, Vec, Mem, Imm)               // AVX+
+  ASMJIT_INST_2x(vpbroadcastb, Vpbroadcastb, Vec, Vec)                 // AVX2 AVX512_BW{kz}
+  ASMJIT_INST_2x(vpbroadcastb, Vpbroadcastb, Vec, Mem)                 // AVX2 AVX512_BW{kz}
+  ASMJIT_INST_2x(vpbroadcastb, Vpbroadcastb, Vec, Gp)                  //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vpbroadcastd, Vpbroadcastd, Vec, Vec)                 // AVX2 AVX512_F{kz}
+  ASMJIT_INST_2x(vpbroadcastd, Vpbroadcastd, Vec, Mem)                 // AVX2 AVX512_F{kz}
+  ASMJIT_INST_2x(vpbroadcastd, Vpbroadcastd, Vec, Gp)                  //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpbroadcastmb2d, Vpbroadcastmb2d, Vec, KReg)          //      AVX512_CD
+  ASMJIT_INST_2x(vpbroadcastmb2q, Vpbroadcastmb2q, Vec, KReg)          //      AVX512_CD
+  ASMJIT_INST_2x(vpbroadcastq, Vpbroadcastq, Vec, Vec)                 // AVX2 AVX512_F{kz}
+  ASMJIT_INST_2x(vpbroadcastq, Vpbroadcastq, Vec, Mem)                 // AVX2 AVX512_F{kz}
+  ASMJIT_INST_2x(vpbroadcastq, Vpbroadcastq, Vec, Gp)                  //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpbroadcastw, Vpbroadcastw, Vec, Vec)                 // AVX2 AVX512_BW{kz}
+  ASMJIT_INST_2x(vpbroadcastw, Vpbroadcastw, Vec, Mem)                 // AVX2 AVX512_BW{kz}
+  ASMJIT_INST_2x(vpbroadcastw, Vpbroadcastw, Vec, Gp)                  //      AVX512_BW{kz}
+  ASMJIT_INST_4i(vpclmulqdq, Vpclmulqdq, Vec, Vec, Vec, Imm)           // AVX  VPCLMULQDQ AVX512_F
+  ASMJIT_INST_4i(vpclmulqdq, Vpclmulqdq, Vec, Vec, Mem, Imm)           // AVX  VPCLMULQDQ AVX512_F
+  ASMJIT_INST_4i(vpcmpb, Vpcmpb, KReg, Vec, Vec, Imm)                  //      AVX512_BW{k}
+  ASMJIT_INST_4i(vpcmpb, Vpcmpb, KReg, Vec, Mem, Imm)                  //      AVX512_BW{k}
+  ASMJIT_INST_4i(vpcmpd, Vpcmpd, KReg, Vec, Vec, Imm)                  //      AVX512_F{k|b32}
+  ASMJIT_INST_4i(vpcmpd, Vpcmpd, KReg, Vec, Mem, Imm)                  //      AVX512_F{k|b32}
+  ASMJIT_INST_3x(vpcmpeqb, Vpcmpeqb, Vec, Vec, Vec)                    // AVX+
+  ASMJIT_INST_3x(vpcmpeqb, Vpcmpeqb, Vec, Vec, Mem)                    // AVX+
+  ASMJIT_INST_3x(vpcmpeqb, Vpcmpeqb, KReg, Vec, Vec)                   //      AVX512_BW{k}
+  ASMJIT_INST_3x(vpcmpeqb, Vpcmpeqb, KReg, Vec, Mem)                   //      AVX512_BW{k}
+  ASMJIT_INST_3x(vpcmpeqd, Vpcmpeqd, Vec, Vec, Vec)                    // AVX+
+  ASMJIT_INST_3x(vpcmpeqd, Vpcmpeqd, Vec, Vec, Mem)                    // AVX+
+  ASMJIT_INST_3x(vpcmpeqd, Vpcmpeqd, KReg, Vec, Vec)                   //      AVX512_F{k|b32}
+  ASMJIT_INST_3x(vpcmpeqd, Vpcmpeqd, KReg, Vec, Mem)                   //      AVX512_F{k|b32}
+  ASMJIT_INST_3x(vpcmpeqq, Vpcmpeqq, Vec, Vec, Vec)                    // AVX+
+  ASMJIT_INST_3x(vpcmpeqq, Vpcmpeqq, Vec, Vec, Mem)                    // AVX+
+  ASMJIT_INST_3x(vpcmpeqq, Vpcmpeqq, KReg, Vec, Vec)                   //      AVX512_F{k|b64}
+  ASMJIT_INST_3x(vpcmpeqq, Vpcmpeqq, KReg, Vec, Mem)                   //      AVX512_F{k|b64}
+  ASMJIT_INST_3x(vpcmpeqw, Vpcmpeqw, Vec, Vec, Vec)                    // AVX+
+  ASMJIT_INST_3x(vpcmpeqw, Vpcmpeqw, Vec, Vec, Mem)                    // AVX+
+  ASMJIT_INST_3x(vpcmpeqw, Vpcmpeqw, KReg, Vec, Vec)                   //      AVX512_BW{k}
+  ASMJIT_INST_3x(vpcmpeqw, Vpcmpeqw, KReg, Vec, Mem)                   //      AVX512_BW{k}
+  ASMJIT_INST_6x(vpcmpestri, Vpcmpestri, Vec, Vec, Imm, ECX, EAX, EDX) // AVX  [EXPLICIT]
+  ASMJIT_INST_6x(vpcmpestri, Vpcmpestri, Vec, Mem, Imm, ECX, EAX, EDX) // AVX  [EXPLICIT]
+  ASMJIT_INST_6x(vpcmpestrm, Vpcmpestrm, Vec, Vec, Imm, XMM0, EAX, EDX)// AVX  [EXPLICIT]
+  ASMJIT_INST_6x(vpcmpestrm, Vpcmpestrm, Vec, Mem, Imm, XMM0, EAX, EDX)// AVX  [EXPLICIT]
+  ASMJIT_INST_3x(vpcmpgtb, Vpcmpgtb, Vec, Vec, Vec)                    // AVX+
+  ASMJIT_INST_3x(vpcmpgtb, Vpcmpgtb, Vec, Vec, Mem)                    // AVX+
+  ASMJIT_INST_3x(vpcmpgtb, Vpcmpgtb, KReg, Vec, Vec)                   //      AVX512_BW{k}
+  ASMJIT_INST_3x(vpcmpgtb, Vpcmpgtb, KReg, Vec, Mem)                   //      AVX512_BW{k}
+  ASMJIT_INST_3x(vpcmpgtd, Vpcmpgtd, Vec, Vec, Vec)                    // AVX+
+  ASMJIT_INST_3x(vpcmpgtd, Vpcmpgtd, Vec, Vec, Mem)                    // AVX+
+  ASMJIT_INST_3x(vpcmpgtd, Vpcmpgtd, KReg, Vec, Vec)                   //      AVX512_F{k|b32}
+  ASMJIT_INST_3x(vpcmpgtd, Vpcmpgtd, KReg, Vec, Mem)                   //      AVX512_F{k|b32}
+  ASMJIT_INST_3x(vpcmpgtq, Vpcmpgtq, Vec, Vec, Vec)                    // AVX+
+  ASMJIT_INST_3x(vpcmpgtq, Vpcmpgtq, Vec, Vec, Mem)                    // AVX+
+  ASMJIT_INST_3x(vpcmpgtq, Vpcmpgtq, KReg, Vec, Vec)                   //      AVX512_F{k|b64}
+  ASMJIT_INST_3x(vpcmpgtq, Vpcmpgtq, KReg, Vec, Mem)                   //      AVX512_F{k|b64}
+  ASMJIT_INST_3x(vpcmpgtw, Vpcmpgtw, Vec, Vec, Vec)                    // AVX+
+  ASMJIT_INST_3x(vpcmpgtw, Vpcmpgtw, Vec, Vec, Mem)                    // AVX+
+  ASMJIT_INST_3x(vpcmpgtw, Vpcmpgtw, KReg, Vec, Vec)                   //      AVX512_BW{k}
+  ASMJIT_INST_3x(vpcmpgtw, Vpcmpgtw, KReg, Vec, Mem)                   //      AVX512_BW{k}
+  ASMJIT_INST_4x(vpcmpistri, Vpcmpistri, Vec, Vec, Imm, ECX)           // AVX  [EXPLICIT]
+  ASMJIT_INST_4x(vpcmpistri, Vpcmpistri, Vec, Mem, Imm, ECX)           // AVX  [EXPLICIT]
+  ASMJIT_INST_4x(vpcmpistrm, Vpcmpistrm, Vec, Vec, Imm, XMM0)          // AVX  [EXPLICIT]
+  ASMJIT_INST_4x(vpcmpistrm, Vpcmpistrm, Vec, Mem, Imm, XMM0)          // AVX  [EXPLICIT]
+  ASMJIT_INST_4i(vpcmpq, Vpcmpq, KReg, Vec, Vec, Imm)                  //      AVX512_F{k|b64}
+  ASMJIT_INST_4i(vpcmpq, Vpcmpq, KReg, Vec, Mem, Imm)                  //      AVX512_F{k|b64}
+  ASMJIT_INST_4i(vpcmpub, Vpcmpub, KReg, Vec, Vec, Imm)                //      AVX512_BW{k}
+  ASMJIT_INST_4i(vpcmpub, Vpcmpub, KReg, Vec, Mem, Imm)                //      AVX512_BW{k}
+  ASMJIT_INST_4i(vpcmpud, Vpcmpud, KReg, Vec, Vec, Imm)                //      AVX512_F{k|b32}
+  ASMJIT_INST_4i(vpcmpud, Vpcmpud, KReg, Vec, Mem, Imm)                //      AVX512_F{k|b32}
+  ASMJIT_INST_4i(vpcmpuq, Vpcmpuq, KReg, Vec, Vec, Imm)                //      AVX512_F{k|b64}
+  ASMJIT_INST_4i(vpcmpuq, Vpcmpuq, KReg, Vec, Mem, Imm)                //      AVX512_F{k|b64}
+  ASMJIT_INST_4i(vpcmpuw, Vpcmpuw, KReg, Vec, Vec, Imm)                //      AVX512_BW{k|b64}
+  ASMJIT_INST_4i(vpcmpuw, Vpcmpuw, KReg, Vec, Mem, Imm)                //      AVX512_BW{k|b64}
+  ASMJIT_INST_4i(vpcmpw, Vpcmpw, KReg, Vec, Vec, Imm)                  //      AVX512_BW{k|b64}
+  ASMJIT_INST_4i(vpcmpw, Vpcmpw, KReg, Vec, Mem, Imm)                  //      AVX512_BW{k|b64}
+  ASMJIT_INST_2x(vpcompressb, Vpcompressb, Vec, Vec)                   //      AVX512_VBMI2{kz}
+  ASMJIT_INST_2x(vpcompressb, Vpcompressb, Mem, Vec)                   //      AVX512_VBMI2{kz}
+  ASMJIT_INST_2x(vpcompressd, Vpcompressd, Vec, Vec)                   //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpcompressd, Vpcompressd, Mem, Vec)                   //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpcompressq, Vpcompressq, Vec, Vec)                   //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpcompressq, Vpcompressq, Mem, Vec)                   //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpcompressw, Vpcompressw, Vec, Vec)                   //      AVX512_VBMI2{kz}
+  ASMJIT_INST_2x(vpcompressw, Vpcompressw, Mem, Vec)                   //      AVX512_VBMI2{kz}
+  ASMJIT_INST_2x(vpconflictd, Vpconflictd, Vec, Vec)                   //      AVX512_CD{kz|b32}
+  ASMJIT_INST_2x(vpconflictd, Vpconflictd, Vec, Mem)                   //      AVX512_CD{kz|b32}
+  ASMJIT_INST_2x(vpconflictq, Vpconflictq, Vec, Vec)                   //      AVX512_CD{kz|b32}
+  ASMJIT_INST_2x(vpconflictq, Vpconflictq, Vec, Mem)                   //      AVX512_CD{kz|b32}
+  ASMJIT_INST_3x(vpdpbusd, Vpdpbusd, Vec, Vec, Vec)                    //      AVX512_VNNI{kz|b32}
+  ASMJIT_INST_3x(vpdpbusd, Vpdpbusd, Vec, Vec, Mem)                    //      AVX512_VNNI{kz|b32}
+  ASMJIT_INST_3x(vpdpbusds, Vpdpbusds, Vec, Vec, Vec)                  //      AVX512_VNNI{kz|b32}
+  ASMJIT_INST_3x(vpdpbusds, Vpdpbusds, Vec, Vec, Mem)                  //      AVX512_VNNI{kz|b32}
+  ASMJIT_INST_3x(vpdpwssd, Vpdpwssd, Vec, Vec, Vec)                    //      AVX512_VNNI{kz|b32}
+  ASMJIT_INST_3x(vpdpwssd, Vpdpwssd, Vec, Vec, Mem)                    //      AVX512_VNNI{kz|b32}
+  ASMJIT_INST_3x(vpdpwssds, Vpdpwssds, Vec, Vec, Vec)                  //      AVX512_VNNI{kz|b32}
+  ASMJIT_INST_3x(vpdpwssds, Vpdpwssds, Vec, Vec, Mem)                  //      AVX512_VNNI{kz|b32}
+  ASMJIT_INST_4i(vperm2f128, Vperm2f128, Vec, Vec, Vec, Imm)           // AVX
+  ASMJIT_INST_4i(vperm2f128, Vperm2f128, Vec, Vec, Mem, Imm)           // AVX
+  ASMJIT_INST_4i(vperm2i128, Vperm2i128, Vec, Vec, Vec, Imm)           // AVX2
+  ASMJIT_INST_4i(vperm2i128, Vperm2i128, Vec, Vec, Mem, Imm)           // AVX2
+  ASMJIT_INST_3x(vpermb, Vpermb, Vec, Vec, Vec)                        //      AVX512_VBMI{kz}
+  ASMJIT_INST_3x(vpermb, Vpermb, Vec, Vec, Mem)                        //      AVX512_VBMI{kz}
+  ASMJIT_INST_3x(vpermd, Vpermd, Vec, Vec, Vec)                        // AVX2 AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpermd, Vpermd, Vec, Vec, Mem)                        // AVX2 AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpermi2b, Vpermi2b, Vec, Vec, Vec)                    //      AVX512_VBMI{kz}
+  ASMJIT_INST_3x(vpermi2b, Vpermi2b, Vec, Vec, Mem)                    //      AVX512_VBMI{kz}
+  ASMJIT_INST_3x(vpermi2d, Vpermi2d, Vec, Vec, Vec)                    //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpermi2d, Vpermi2d, Vec, Vec, Mem)                    //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpermi2pd, Vpermi2pd, Vec, Vec, Vec)                  //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermi2pd, Vpermi2pd, Vec, Vec, Mem)                  //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermi2ps, Vpermi2ps, Vec, Vec, Vec)                  //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpermi2ps, Vpermi2ps, Vec, Vec, Mem)                  //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpermi2q, Vpermi2q, Vec, Vec, Vec)                    //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermi2q, Vpermi2q, Vec, Vec, Mem)                    //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermi2w, Vpermi2w, Vec, Vec, Vec)                    //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vpermi2w, Vpermi2w, Vec, Vec, Mem)                    //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vpermilpd, Vpermilpd, Vec, Vec, Vec)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermilpd, Vpermilpd, Vec, Vec, Mem)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vpermilpd, Vpermilpd, Vec, Vec, Imm)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vpermilpd, Vpermilpd, Vec, Mem, Imm)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermilps, Vpermilps, Vec, Vec, Vec)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermilps, Vpermilps, Vec, Vec, Mem)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vpermilps, Vpermilps, Vec, Vec, Imm)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vpermilps, Vpermilps, Vec, Mem, Imm)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vpermpd, Vpermpd, Vec, Vec, Imm)                      // AVX2
+  ASMJIT_INST_3i(vpermpd, Vpermpd, Vec, Mem, Imm)                      // AVX2
+  ASMJIT_INST_3x(vpermps, Vpermps, Vec, Vec, Vec)                      // AVX2
+  ASMJIT_INST_3x(vpermps, Vpermps, Vec, Vec, Mem)                      // AVX2
+  ASMJIT_INST_3i(vpermq, Vpermq, Vec, Vec, Imm)                        // AVX2 AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vpermq, Vpermq, Vec, Mem, Imm)                        // AVX2 AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermq, Vpermq, Vec, Vec, Vec)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermq, Vpermq, Vec, Vec, Mem)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermt2b, Vpermt2b, Vec, Vec, Vec)                    //      AVX512_VBMI{kz}
+  ASMJIT_INST_3x(vpermt2b, Vpermt2b, Vec, Vec, Mem)                    //      AVX512_VBMI{kz}
+  ASMJIT_INST_3x(vpermt2d, Vpermt2d, Vec, Vec, Vec)                    //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpermt2d, Vpermt2d, Vec, Vec, Mem)                    //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpermt2pd, Vpermt2pd, Vec, Vec, Vec)                  //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermt2pd, Vpermt2pd, Vec, Vec, Mem)                  //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermt2ps, Vpermt2ps, Vec, Vec, Vec)                  //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpermt2ps, Vpermt2ps, Vec, Vec, Mem)                  //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpermt2q, Vpermt2q, Vec, Vec, Vec)                    //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermt2q, Vpermt2q, Vec, Vec, Mem)                    //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpermt2w, Vpermt2w, Vec, Vec, Vec)                    //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vpermt2w, Vpermt2w, Vec, Vec, Mem)                    //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vpermw, Vpermw, Vec, Vec, Vec)                        //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vpermw, Vpermw, Vec, Vec, Mem)                        //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vpexpandb, Vpexpandb, Vec, Vec)                       //      AVX512_VBMI2{kz}
+  ASMJIT_INST_2x(vpexpandb, Vpexpandb, Vec, Mem)                       //      AVX512_VBMI2{kz}
+  ASMJIT_INST_2x(vpexpandd, Vpexpandd, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpexpandd, Vpexpandd, Vec, Mem)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpexpandq, Vpexpandq, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpexpandq, Vpexpandq, Vec, Mem)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpexpandw, Vpexpandw, Vec, Vec)                       //      AVX512_VBMI2{kz}
+  ASMJIT_INST_2x(vpexpandw, Vpexpandw, Vec, Mem)                       //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3i(vpextrb, Vpextrb, Gp, Xmm, Imm)                       // AVX  AVX512_BW
+  ASMJIT_INST_3i(vpextrb, Vpextrb, Mem, Xmm, Imm)                      // AVX  AVX512_BW
+  ASMJIT_INST_3i(vpextrd, Vpextrd, Gp, Xmm, Imm)                       // AVX  AVX512_DQ
+  ASMJIT_INST_3i(vpextrd, Vpextrd, Mem, Xmm, Imm)                      // AVX  AVX512_DQ
+  ASMJIT_INST_3i(vpextrq, Vpextrq, Gp, Xmm, Imm)                       // AVX  AVX512_DQ
+  ASMJIT_INST_3i(vpextrq, Vpextrq, Mem, Xmm, Imm)                      // AVX  AVX512_DQ
+  ASMJIT_INST_3i(vpextrw, Vpextrw, Gp, Xmm, Imm)                       // AVX  AVX512_BW
+  ASMJIT_INST_3i(vpextrw, Vpextrw, Mem, Xmm, Imm)                      // AVX  AVX512_BW
+  ASMJIT_INST_2x(vpgatherdd, Vpgatherdd, Vec, Mem)                     //      AVX512_F{k}
+  ASMJIT_INST_3x(vpgatherdd, Vpgatherdd, Vec, Mem, Vec)                // AVX2
+  ASMJIT_INST_2x(vpgatherdq, Vpgatherdq, Vec, Mem)                     //      AVX512_F{k}
+  ASMJIT_INST_3x(vpgatherdq, Vpgatherdq, Vec, Mem, Vec)                // AVX2
+  ASMJIT_INST_2x(vpgatherqd, Vpgatherqd, Vec, Mem)                     //      AVX512_F{k}
+  ASMJIT_INST_3x(vpgatherqd, Vpgatherqd, Vec, Mem, Vec)                // AVX2
+  ASMJIT_INST_2x(vpgatherqq, Vpgatherqq, Vec, Mem)                     //      AVX512_F{k}
+  ASMJIT_INST_3x(vpgatherqq, Vpgatherqq, Vec, Mem, Vec)                // AVX2
+  ASMJIT_INST_3x(vphaddd, Vphaddd, Vec, Vec, Vec)                      // AVX+
+  ASMJIT_INST_3x(vphaddd, Vphaddd, Vec, Vec, Mem)                      // AVX+
+  ASMJIT_INST_3x(vphaddsw, Vphaddsw, Vec, Vec, Vec)                    // AVX+
+  ASMJIT_INST_3x(vphaddsw, Vphaddsw, Vec, Vec, Mem)                    // AVX+
+  ASMJIT_INST_3x(vphaddw, Vphaddw, Vec, Vec, Vec)                      // AVX+
+  ASMJIT_INST_3x(vphaddw, Vphaddw, Vec, Vec, Mem)                      // AVX+
+  ASMJIT_INST_2x(vphminposuw, Vphminposuw, Vec, Vec)                   // AVX
+  ASMJIT_INST_2x(vphminposuw, Vphminposuw, Vec, Mem)                   // AVX
+  ASMJIT_INST_3x(vphsubd, Vphsubd, Vec, Vec, Vec)                      // AVX+
+  ASMJIT_INST_3x(vphsubd, Vphsubd, Vec, Vec, Mem)                      // AVX+
+  ASMJIT_INST_3x(vphsubsw, Vphsubsw, Vec, Vec, Vec)                    // AVX+
+  ASMJIT_INST_3x(vphsubsw, Vphsubsw, Vec, Vec, Mem)                    // AVX+
+  ASMJIT_INST_3x(vphsubw, Vphsubw, Vec, Vec, Vec)                      // AVX+
+  ASMJIT_INST_3x(vphsubw, Vphsubw, Vec, Vec, Mem)                      // AVX+
+  ASMJIT_INST_4i(vpinsrb, Vpinsrb, Xmm, Xmm, Gp, Imm)                  // AVX  AVX512_BW{kz}
+  ASMJIT_INST_4i(vpinsrb, Vpinsrb, Xmm, Xmm, Mem, Imm)                 // AVX  AVX512_BW{kz}
+  ASMJIT_INST_4i(vpinsrd, Vpinsrd, Xmm, Xmm, Gp, Imm)                  // AVX  AVX512_DQ{kz}
+  ASMJIT_INST_4i(vpinsrd, Vpinsrd, Xmm, Xmm, Mem, Imm)                 // AVX  AVX512_DQ{kz}
+  ASMJIT_INST_4i(vpinsrq, Vpinsrq, Xmm, Xmm, Gp, Imm)                  // AVX  AVX512_DQ{kz}
+  ASMJIT_INST_4i(vpinsrq, Vpinsrq, Xmm, Xmm, Mem, Imm)                 // AVX  AVX512_DQ{kz}
+  ASMJIT_INST_4i(vpinsrw, Vpinsrw, Xmm, Xmm, Gp, Imm)                  // AVX  AVX512_BW{kz}
+  ASMJIT_INST_4i(vpinsrw, Vpinsrw, Xmm, Xmm, Mem, Imm)                 // AVX  AVX512_BW{kz}
+  ASMJIT_INST_2x(vplzcntd, Vplzcntd, Vec, Vec)                         //      AVX512_CD{kz|b32}
+  ASMJIT_INST_2x(vplzcntd, Vplzcntd, Vec, Mem)                         //      AVX512_CD{kz|b32}
+  ASMJIT_INST_2x(vplzcntq, Vplzcntq, Vec, Vec)                         //      AVX512_CD{kz|b64}
+  ASMJIT_INST_2x(vplzcntq, Vplzcntq, Vec, Mem)                         //      AVX512_CD{kz|b64}
+  ASMJIT_INST_3x(vpmadd52huq, Vpmadd52huq, Vec, Vec, Vec)              //      AVX512_IFMA{kz|b64}
+  ASMJIT_INST_3x(vpmadd52huq, Vpmadd52huq, Vec, Vec, Mem)              //      AVX512_IFMA{kz|b64}
+  ASMJIT_INST_3x(vpmadd52luq, Vpmadd52luq, Vec, Vec, Vec)              //      AVX512_IFMA{kz|b64}
+  ASMJIT_INST_3x(vpmadd52luq, Vpmadd52luq, Vec, Vec, Mem)              //      AVX512_IFMA{kz|b64}
+  ASMJIT_INST_3x(vpmaddubsw, Vpmaddubsw, Vec, Vec, Vec)                // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaddubsw, Vpmaddubsw, Vec, Vec, Mem)                // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaddwd, Vpmaddwd, Vec, Vec, Vec)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaddwd, Vpmaddwd, Vec, Vec, Mem)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaskmovd, Vpmaskmovd, Mem, Vec, Vec)                // AVX2
+  ASMJIT_INST_3x(vpmaskmovd, Vpmaskmovd, Vec, Vec, Mem)                // AVX2
+  ASMJIT_INST_3x(vpmaskmovq, Vpmaskmovq, Mem, Vec, Vec)                // AVX2
+  ASMJIT_INST_3x(vpmaskmovq, Vpmaskmovq, Vec, Vec, Mem)                // AVX2
+  ASMJIT_INST_3x(vpmaxsb, Vpmaxsb, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaxsb, Vpmaxsb, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaxsd, Vpmaxsd, Vec, Vec, Vec)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpmaxsd, Vpmaxsd, Vec, Vec, Mem)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpmaxsq, Vpmaxsq, Vec, Vec, Vec)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpmaxsq, Vpmaxsq, Vec, Vec, Mem)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpmaxsw, Vpmaxsw, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaxsw, Vpmaxsw, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaxub, Vpmaxub, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaxub, Vpmaxub, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaxud, Vpmaxud, Vec, Vec, Vec)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpmaxud, Vpmaxud, Vec, Vec, Mem)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpmaxuq, Vpmaxuq, Vec, Vec, Vec)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpmaxuq, Vpmaxuq, Vec, Vec, Mem)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpmaxuw, Vpmaxuw, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmaxuw, Vpmaxuw, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpminsb, Vpminsb, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpminsb, Vpminsb, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpminsd, Vpminsd, Vec, Vec, Vec)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpminsd, Vpminsd, Vec, Vec, Mem)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpminsq, Vpminsq, Vec, Vec, Vec)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpminsq, Vpminsq, Vec, Vec, Mem)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpminsw, Vpminsw, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpminsw, Vpminsw, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpminub, Vpminub, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpminub, Vpminub, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpminud, Vpminud, Vec, Vec, Vec)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpminud, Vpminud, Vec, Vec, Mem)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpminuq, Vpminuq, Vec, Vec, Vec)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpminuq, Vpminuq, Vec, Vec, Mem)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpminuw, Vpminuw, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpminuw, Vpminuw, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovb2m, Vpmovb2m, KReg, Vec)                        //      AVX512_BW
+  ASMJIT_INST_2x(vpmovd2m, Vpmovd2m, KReg, Vec)                        //      AVX512_DQ
+  ASMJIT_INST_2x(vpmovdb, Vpmovdb, Vec, Vec)                           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovdb, Vpmovdb, Mem, Vec)                           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovdw, Vpmovdw, Vec, Vec)                           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovdw, Vpmovdw, Mem, Vec)                           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovm2b, Vpmovm2b, Vec, KReg)                        //      AVX512_BW
+  ASMJIT_INST_2x(vpmovm2d, Vpmovm2d, Vec, KReg)                        //      AVX512_DQ
+  ASMJIT_INST_2x(vpmovm2q, Vpmovm2q, Vec, KReg)                        //      AVX512_DQ
+  ASMJIT_INST_2x(vpmovm2w, Vpmovm2w, Vec, KReg)                        //      AVX512_BW
+  ASMJIT_INST_2x(vpmovmskb, Vpmovmskb, Gp, Vec)                        // AVX+
+  ASMJIT_INST_2x(vpmovq2m, Vpmovq2m, KReg, Vec)                        //      AVX512_DQ
+  ASMJIT_INST_2x(vpmovqb, Vpmovqb, Vec, Vec)                           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovqb, Vpmovqb, Mem, Vec)                           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovqd, Vpmovqd, Vec, Vec)                           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovqd, Vpmovqd, Mem, Vec)                           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovqw, Vpmovqw, Vec, Vec)                           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovqw, Vpmovqw, Mem, Vec)                           //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsdb, Vpmovsdb, Vec, Vec)                         //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsdb, Vpmovsdb, Mem, Vec)                         //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsdw, Vpmovsdw, Vec, Vec)                         //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsdw, Vpmovsdw, Mem, Vec)                         //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsqb, Vpmovsqb, Vec, Vec)                         //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsqb, Vpmovsqb, Mem, Vec)                         //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsqd, Vpmovsqd, Vec, Vec)                         //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsqd, Vpmovsqd, Mem, Vec)                         //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsqw, Vpmovsqw, Vec, Vec)                         //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsqw, Vpmovsqw, Mem, Vec)                         //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovswb, Vpmovswb, Vec, Vec)                         //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovswb, Vpmovswb, Mem, Vec)                         //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovsxbd, Vpmovsxbd, Vec, Vec)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsxbd, Vpmovsxbd, Vec, Mem)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsxbq, Vpmovsxbq, Vec, Vec)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsxbq, Vpmovsxbq, Vec, Mem)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsxbw, Vpmovsxbw, Vec, Vec)                       // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovsxbw, Vpmovsxbw, Vec, Mem)                       // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovsxdq, Vpmovsxdq, Vec, Vec)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsxdq, Vpmovsxdq, Vec, Mem)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsxwd, Vpmovsxwd, Vec, Vec)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsxwd, Vpmovsxwd, Vec, Mem)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsxwq, Vpmovsxwq, Vec, Vec)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovsxwq, Vpmovsxwq, Vec, Mem)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovusdb, Vpmovusdb, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovusdb, Vpmovusdb, Mem, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovusdw, Vpmovusdw, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovusdw, Vpmovusdw, Mem, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovusqb, Vpmovusqb, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovusqb, Vpmovusqb, Mem, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovusqd, Vpmovusqd, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovusqd, Vpmovusqd, Mem, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovusqw, Vpmovusqw, Vec, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovusqw, Vpmovusqw, Mem, Vec)                       //      AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovuswb, Vpmovuswb, Vec, Vec)                       //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovuswb, Vpmovuswb, Mem, Vec)                       //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovw2m, Vpmovw2m, KReg, Vec)                        //      AVX512_BW
+  ASMJIT_INST_2x(vpmovwb, Vpmovwb, Vec, Vec)                           //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovwb, Vpmovwb, Mem, Vec)                           //      AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovzxbd, Vpmovzxbd, Vec, Vec)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovzxbd, Vpmovzxbd, Vec, Mem)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovzxbq, Vpmovzxbq, Vec, Vec)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovzxbq, Vpmovzxbq, Vec, Mem)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovzxbw, Vpmovzxbw, Vec, Vec)                       // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovzxbw, Vpmovzxbw, Vec, Mem)                       // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_2x(vpmovzxdq, Vpmovzxdq, Vec, Vec)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovzxdq, Vpmovzxdq, Vec, Mem)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovzxwd, Vpmovzxwd, Vec, Vec)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovzxwd, Vpmovzxwd, Vec, Mem)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovzxwq, Vpmovzxwq, Vec, Vec)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_2x(vpmovzxwq, Vpmovzxwq, Vec, Mem)                       // AVX+ AVX512_F{kz}
+  ASMJIT_INST_3x(vpmuldq, Vpmuldq, Vec, Vec, Vec)                      // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpmuldq, Vpmuldq, Vec, Vec, Mem)                      // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpmulhrsw, Vpmulhrsw, Vec, Vec, Vec)                  // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmulhrsw, Vpmulhrsw, Vec, Vec, Mem)                  // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmulhuw, Vpmulhuw, Vec, Vec, Vec)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmulhuw, Vpmulhuw, Vec, Vec, Mem)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmulhw, Vpmulhw, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmulhw, Vpmulhw, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmulld, Vpmulld, Vec, Vec, Vec)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpmulld, Vpmulld, Vec, Vec, Mem)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpmullq, Vpmullq, Vec, Vec, Vec)                      //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vpmullq, Vpmullq, Vec, Vec, Mem)                      //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vpmullw, Vpmullw, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmullw, Vpmullw, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpmultishiftqb, Vpmultishiftqb, Vec, Vec, Vec)        //      AVX512_VBMI{kz|b64}
+  ASMJIT_INST_3x(vpmultishiftqb, Vpmultishiftqb, Vec, Vec, Mem)        //      AVX512_VBMI{kz|b64}
+  ASMJIT_INST_3x(vpmuludq, Vpmuludq, Vec, Vec, Vec)                    // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpmuludq, Vpmuludq, Vec, Vec, Mem)                    // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vpopcntb, Vpopcntb, Vec, Vec)                         //      AVX512_BITALG{kz|b32}
+  ASMJIT_INST_2x(vpopcntb, Vpopcntb, Vec, Mem)                         //      AVX512_BITALG{kz|b32}
+  ASMJIT_INST_2x(vpopcntd, Vpopcntd, Vec, Vec)                         //      AVX512_VPOPCNTDQ{kz|b32}
+  ASMJIT_INST_2x(vpopcntd, Vpopcntd, Vec, Mem)                         //      AVX512_VPOPCNTDQ{kz|b32}
+  ASMJIT_INST_2x(vpopcntq, Vpopcntq, Vec, Vec)                         //      AVX512_VPOPCNTDQ{kz|b64}
+  ASMJIT_INST_2x(vpopcntq, Vpopcntq, Vec, Mem)                         //      AVX512_VPOPCNTDQ{kz|b64}
+  ASMJIT_INST_2x(vpopcntw, Vpopcntw, Vec, Vec)                         //      AVX512_BITALG{kz|b32}
+  ASMJIT_INST_2x(vpopcntw, Vpopcntw, Vec, Mem)                         //      AVX512_BITALG{kz|b32}
+  ASMJIT_INST_3x(vpor, Vpor, Vec, Vec, Vec)                            // AV+
+  ASMJIT_INST_3x(vpor, Vpor, Vec, Vec, Mem)                            // AVX+
+  ASMJIT_INST_3x(vpord, Vpord, Vec, Vec, Vec)                          //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpord, Vpord, Vec, Vec, Mem)                          //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vporq, Vporq, Vec, Vec, Vec)                          //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vporq, Vporq, Vec, Vec, Mem)                          //      AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vprold, Vprold, Vec, Vec, Imm)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vprold, Vprold, Vec, Mem, Imm)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vprolq, Vprolq, Vec, Vec, Imm)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vprolq, Vprolq, Vec, Mem, Imm)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vprolvd, Vprolvd, Vec, Vec, Vec)                      //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vprolvd, Vprolvd, Vec, Vec, Mem)                      //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vprolvq, Vprolvq, Vec, Vec, Vec)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vprolvq, Vprolvq, Vec, Vec, Mem)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vprord, Vprord, Vec, Vec, Imm)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vprord, Vprord, Vec, Mem, Imm)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vprorq, Vprorq, Vec, Vec, Imm)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vprorq, Vprorq, Vec, Mem, Imm)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vprorvd, Vprorvd, Vec, Vec, Vec)                      //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vprorvd, Vprorvd, Vec, Vec, Mem)                      //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vprorvq, Vprorvq, Vec, Vec, Vec)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vprorvq, Vprorvq, Vec, Vec, Mem)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsadbw, Vpsadbw, Vec, Vec, Vec)                      // AVX+ AVX512_BW
+  ASMJIT_INST_3x(vpsadbw, Vpsadbw, Vec, Vec, Mem)                      // AVX+ AVX512_BW
+  ASMJIT_INST_2x(vpscatterdd, Vpscatterdd, Mem, Vec)                   //      AVX512_F{k}
+  ASMJIT_INST_2x(vpscatterdq, Vpscatterdq, Mem, Vec)                   //      AVX512_F{k}
+  ASMJIT_INST_2x(vpscatterqd, Vpscatterqd, Mem, Vec)                   //      AVX512_F{k}
+  ASMJIT_INST_2x(vpscatterqq, Vpscatterqq, Mem, Vec)                   //      AVX512_F{k}
+  ASMJIT_INST_4i(vpshldd, Vpshldd, Vec, Vec, Vec, Imm)                 //      AVX512_VBMI2{kz}
+  ASMJIT_INST_4i(vpshldd, Vpshldd, Vec, Vec, Mem, Imm)                 //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshldvd, Vpshldvd, Vec, Vec, Vec)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshldvd, Vpshldvd, Vec, Vec, Mem)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshldvq, Vpshldvq, Vec, Vec, Vec)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshldvq, Vpshldvq, Vec, Vec, Mem)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshldvw, Vpshldvw, Vec, Vec, Vec)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshldvw, Vpshldvw, Vec, Vec, Mem)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_4i(vpshrdd, Vpshrdd, Vec, Vec, Vec, Imm)                 //      AVX512_VBMI2{kz}
+  ASMJIT_INST_4i(vpshrdd, Vpshrdd, Vec, Vec, Mem, Imm)                 //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshrdvd, Vpshrdvd, Vec, Vec, Vec)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshrdvd, Vpshrdvd, Vec, Vec, Mem)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshrdvq, Vpshrdvq, Vec, Vec, Vec)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshrdvq, Vpshrdvq, Vec, Vec, Mem)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshrdvw, Vpshrdvw, Vec, Vec, Vec)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshrdvw, Vpshrdvw, Vec, Vec, Mem)                    //      AVX512_VBMI2{kz}
+  ASMJIT_INST_4i(vpshrdw, Vpshrdw, Vec, Vec, Vec, Imm)                 //      AVX512_VBMI2{kz}
+  ASMJIT_INST_4i(vpshrdw, Vpshrdw, Vec, Vec, Mem, Imm)                 //      AVX512_VBMI2{kz}
+  ASMJIT_INST_3x(vpshufb, Vpshufb, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpshufb, Vpshufb, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpshufbitqmb, Vpshufbitqmb, KReg, Vec, Vec)           //      AVX512_BITALG{k}
+  ASMJIT_INST_3x(vpshufbitqmb, Vpshufbitqmb, KReg, Vec, Mem)           //      AVX512_BITALG{k}
+  ASMJIT_INST_3i(vpshufd, Vpshufd, Vec, Vec, Imm)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vpshufd, Vpshufd, Vec, Mem, Imm)                      // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vpshufhw, Vpshufhw, Vec, Vec, Imm)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3i(vpshufhw, Vpshufhw, Vec, Mem, Imm)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3i(vpshuflw, Vpshuflw, Vec, Vec, Imm)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3i(vpshuflw, Vpshuflw, Vec, Mem, Imm)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsignb, Vpsignb, Vec, Vec, Vec)                      // AVX+
+  ASMJIT_INST_3x(vpsignb, Vpsignb, Vec, Vec, Mem)                      // AVX+
+  ASMJIT_INST_3x(vpsignd, Vpsignd, Vec, Vec, Vec)                      // AVX+
+  ASMJIT_INST_3x(vpsignd, Vpsignd, Vec, Vec, Mem)                      // AVX+
+  ASMJIT_INST_3x(vpsignw, Vpsignw, Vec, Vec, Vec)                      // AVX+
+  ASMJIT_INST_3x(vpsignw, Vpsignw, Vec, Vec, Mem)                      // AVX+
+  ASMJIT_INST_3i(vpslld, Vpslld, Vec, Vec, Imm)                        // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpslld, Vpslld, Vec, Vec, Vec)                        // AVX+ AVX512_F{kz}
+  ASMJIT_INST_3x(vpslld, Vpslld, Vec, Vec, Mem)                        // AVX+ AVX512_F{kz}
+  ASMJIT_INST_3i(vpslld, Vpslld, Vec, Mem, Imm)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vpslldq, Vpslldq, Vec, Vec, Imm)                      // AVX+ AVX512_BW
+  ASMJIT_INST_3i(vpslldq, Vpslldq, Vec, Mem, Imm)                      //      AVX512_BW
+  ASMJIT_INST_3i(vpsllq, Vpsllq, Vec, Vec, Imm)                        // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsllq, Vpsllq, Vec, Vec, Vec)                        // AVX+ AVX512_F{kz}
+  ASMJIT_INST_3x(vpsllq, Vpsllq, Vec, Vec, Mem)                        // AVX+ AVX512_F{kz}
+  ASMJIT_INST_3i(vpsllq, Vpsllq, Vec, Mem, Imm)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsllvd, Vpsllvd, Vec, Vec, Vec)                      // AVX2 AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsllvd, Vpsllvd, Vec, Vec, Mem)                      // AVX2 AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsllvq, Vpsllvq, Vec, Vec, Vec)                      // AVX2 AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsllvq, Vpsllvq, Vec, Vec, Mem)                      // AVX2 AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsllvw, Vpsllvw, Vec, Vec, Vec)                      //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsllvw, Vpsllvw, Vec, Vec, Mem)                      //      AVX512_BW{kz}
+  ASMJIT_INST_3i(vpsllw, Vpsllw, Vec, Vec, Imm)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsllw, Vpsllw, Vec, Vec, Vec)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsllw, Vpsllw, Vec, Vec, Mem)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3i(vpsllw, Vpsllw, Vec, Mem, Imm)                        //      AVX512_BW{kz}
+  ASMJIT_INST_3i(vpsrad, Vpsrad, Vec, Vec, Imm)                        // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsrad, Vpsrad, Vec, Vec, Vec)                        // AVX+ AVX512_F{kz}
+  ASMJIT_INST_3x(vpsrad, Vpsrad, Vec, Vec, Mem)                        // AVX+ AVX512_F{kz}
+  ASMJIT_INST_3i(vpsrad, Vpsrad, Vec, Mem, Imm)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsraq, Vpsraq, Vec, Vec, Vec)                        //      AVX512_F{kz}
+  ASMJIT_INST_3x(vpsraq, Vpsraq, Vec, Vec, Mem)                        //      AVX512_F{kz}
+  ASMJIT_INST_3i(vpsraq, Vpsraq, Vec, Vec, Imm)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vpsraq, Vpsraq, Vec, Mem, Imm)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsravd, Vpsravd, Vec, Vec, Vec)                      // AVX2 AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsravd, Vpsravd, Vec, Vec, Mem)                      // AVX2 AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsravq, Vpsravq, Vec, Vec, Vec)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsravq, Vpsravq, Vec, Vec, Mem)                      //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsravw, Vpsravw, Vec, Vec, Vec)                      //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsravw, Vpsravw, Vec, Vec, Mem)                      //      AVX512_BW{kz}
+  ASMJIT_INST_3i(vpsraw, Vpsraw, Vec, Vec, Imm)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsraw, Vpsraw, Vec, Vec, Vec)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsraw, Vpsraw, Vec, Vec, Mem)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3i(vpsraw, Vpsraw, Vec, Mem, Imm)                        //      AVX512_BW{kz}
+  ASMJIT_INST_3i(vpsrld, Vpsrld, Vec, Vec, Imm)                        // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsrld, Vpsrld, Vec, Vec, Vec)                        // AVX+ AVX512_F{kz}
+  ASMJIT_INST_3x(vpsrld, Vpsrld, Vec, Vec, Mem)                        // AVX+ AVX512_F{kz}
+  ASMJIT_INST_3i(vpsrld, Vpsrld, Vec, Mem, Imm)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vpsrldq, Vpsrldq, Vec, Vec, Imm)                      // AVX+ AVX512_BW
+  ASMJIT_INST_3i(vpsrldq, Vpsrldq, Vec, Mem, Imm)                      //      AVX512_BW
+  ASMJIT_INST_3i(vpsrlq, Vpsrlq, Vec, Vec, Imm)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsrlq, Vpsrlq, Vec, Vec, Vec)                        // AVX  AVX512_F{kz}
+  ASMJIT_INST_3x(vpsrlq, Vpsrlq, Vec, Vec, Mem)                        // AVX  AVX512_F{kz}
+  ASMJIT_INST_3i(vpsrlq, Vpsrlq, Vec, Mem, Imm)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsrlvd, Vpsrlvd, Vec, Vec, Vec)                      // AVX2 AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsrlvd, Vpsrlvd, Vec, Vec, Mem)                      // AVX2 AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsrlvq, Vpsrlvq, Vec, Vec, Vec)                      // AVX2 AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsrlvq, Vpsrlvq, Vec, Vec, Mem)                      // AVX2 AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsrlvw, Vpsrlvw, Vec, Vec, Vec)                      //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsrlvw, Vpsrlvw, Vec, Vec, Mem)                      //      AVX512_BW{kz}
+  ASMJIT_INST_3i(vpsrlw, Vpsrlw, Vec, Vec, Imm)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsrlw, Vpsrlw, Vec, Vec, Vec)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsrlw, Vpsrlw, Vec, Vec, Mem)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3i(vpsrlw, Vpsrlw, Vec, Mem, Imm)                        //      AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubb, Vpsubb, Vec, Vec, Vec)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubb, Vpsubb, Vec, Vec, Mem)                        // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubd, Vpsubd, Vec, Vec, Vec)                        // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsubd, Vpsubd, Vec, Vec, Mem)                        // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpsubq, Vpsubq, Vec, Vec, Vec)                        // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsubq, Vpsubq, Vec, Vec, Mem)                        // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpsubsb, Vpsubsb, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubsb, Vpsubsb, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubsw, Vpsubsw, Vec, Vec, Vec)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubsw, Vpsubsw, Vec, Vec, Mem)                      // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubusb, Vpsubusb, Vec, Vec, Vec)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubusb, Vpsubusb, Vec, Vec, Mem)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubusw, Vpsubusw, Vec, Vec, Vec)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubusw, Vpsubusw, Vec, Vec, Mem)                    // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubw, Vpsubw, Vec, Vec, Vec)                        // AVX  AVX512_BW{kz}
+  ASMJIT_INST_3x(vpsubw, Vpsubw, Vec, Vec, Mem)                        // AVX  AVX512_BW{kz}
+  ASMJIT_INST_4i(vpternlogd, Vpternlogd, Vec, Vec, Vec, Imm)           //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vpternlogd, Vpternlogd, Vec, Vec, Mem, Imm)           //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vpternlogq, Vpternlogq, Vec, Vec, Vec, Imm)           //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vpternlogq, Vpternlogq, Vec, Vec, Mem, Imm)           //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vptest, Vptest, Vec, Vec)                             // AVX
+  ASMJIT_INST_2x(vptest, Vptest, Vec, Mem)                             // AVX
+  ASMJIT_INST_3x(vptestmb, Vptestmb, KReg, Vec, Vec)                   //      AVX512_BW{k}
+  ASMJIT_INST_3x(vptestmb, Vptestmb, KReg, Vec, Mem)                   //      AVX512_BW{k}
+  ASMJIT_INST_3x(vptestmd, Vptestmd, KReg, Vec, Vec)                   //      AVX512_F{k|b32}
+  ASMJIT_INST_3x(vptestmd, Vptestmd, KReg, Vec, Mem)                   //      AVX512_F{k|b32}
+  ASMJIT_INST_3x(vptestmq, Vptestmq, KReg, Vec, Vec)                   //      AVX512_F{k|b64}
+  ASMJIT_INST_3x(vptestmq, Vptestmq, KReg, Vec, Mem)                   //      AVX512_F{k|b64}
+  ASMJIT_INST_3x(vptestmw, Vptestmw, KReg, Vec, Vec)                   //      AVX512_BW{k}
+  ASMJIT_INST_3x(vptestmw, Vptestmw, KReg, Vec, Mem)                   //      AVX512_BW{k}
+  ASMJIT_INST_3x(vptestnmb, Vptestnmb, KReg, Vec, Vec)                 //      AVX512_BW{k}
+  ASMJIT_INST_3x(vptestnmb, Vptestnmb, KReg, Vec, Mem)                 //      AVX512_BW{k}
+  ASMJIT_INST_3x(vptestnmd, Vptestnmd, KReg, Vec, Vec)                 //      AVX512_F{k|b32}
+  ASMJIT_INST_3x(vptestnmd, Vptestnmd, KReg, Vec, Mem)                 //      AVX512_F{k|b32}
+  ASMJIT_INST_3x(vptestnmq, Vptestnmq, KReg, Vec, Vec)                 //      AVX512_F{k|b64}
+  ASMJIT_INST_3x(vptestnmq, Vptestnmq, KReg, Vec, Mem)                 //      AVX512_F{k|b64}
+  ASMJIT_INST_3x(vptestnmw, Vptestnmw, KReg, Vec, Vec)                 //      AVX512_BW{k}
+  ASMJIT_INST_3x(vptestnmw, Vptestnmw, KReg, Vec, Mem)                 //      AVX512_BW{k}
+  ASMJIT_INST_3x(vpunpckhbw, Vpunpckhbw, Vec, Vec, Vec)                // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpunpckhbw, Vpunpckhbw, Vec, Vec, Mem)                // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpunpckhdq, Vpunpckhdq, Vec, Vec, Vec)                // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpunpckhdq, Vpunpckhdq, Vec, Vec, Mem)                // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpunpckhqdq, Vpunpckhqdq, Vec, Vec, Vec)              // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpunpckhqdq, Vpunpckhqdq, Vec, Vec, Mem)              // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpunpckhwd, Vpunpckhwd, Vec, Vec, Vec)                // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpunpckhwd, Vpunpckhwd, Vec, Vec, Mem)                // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpunpcklbw, Vpunpcklbw, Vec, Vec, Vec)                // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpunpcklbw, Vpunpcklbw, Vec, Vec, Mem)                // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpunpckldq, Vpunpckldq, Vec, Vec, Vec)                // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpunpckldq, Vpunpckldq, Vec, Vec, Mem)                // AVX+ AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpunpcklqdq, Vpunpcklqdq, Vec, Vec, Vec)              // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpunpcklqdq, Vpunpcklqdq, Vec, Vec, Mem)              // AVX+ AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpunpcklwd, Vpunpcklwd, Vec, Vec, Vec)                // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpunpcklwd, Vpunpcklwd, Vec, Vec, Mem)                // AVX+ AVX512_BW{kz}
+  ASMJIT_INST_3x(vpxor, Vpxor, Vec, Vec, Vec)                          // AVX+
+  ASMJIT_INST_3x(vpxor, Vpxor, Vec, Vec, Mem)                          // AVX+
+  ASMJIT_INST_3x(vpxord, Vpxord, Vec, Vec, Vec)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpxord, Vpxord, Vec, Vec, Mem)                        //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vpxorq, Vpxorq, Vec, Vec, Vec)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vpxorq, Vpxorq, Vec, Vec, Mem)                        //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vrangepd, Vrangepd, Vec, Vec, Vec, Imm)               //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_4i(vrangepd, Vrangepd, Vec, Vec, Mem, Imm)               //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_4i(vrangeps, Vrangeps, Vec, Vec, Vec, Imm)               //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_4i(vrangeps, Vrangeps, Vec, Vec, Mem, Imm)               //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_4i(vrangesd, Vrangesd, Xmm, Xmm, Xmm, Imm)               //      AVX512_DQ{kz|sae}
+  ASMJIT_INST_4i(vrangesd, Vrangesd, Xmm, Xmm, Mem, Imm)               //      AVX512_DQ{kz|sae}
+  ASMJIT_INST_4i(vrangess, Vrangess, Xmm, Xmm, Xmm, Imm)               //      AVX512_DQ{kz|sae}
+  ASMJIT_INST_4i(vrangess, Vrangess, Xmm, Xmm, Mem, Imm)               //      AVX512_DQ{kz|sae}
+  ASMJIT_INST_2x(vrcp14pd, Vrcp14pd, Vec, Vec)                         //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vrcp14pd, Vrcp14pd, Vec, Mem)                         //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vrcp14ps, Vrcp14ps, Vec, Vec)                         //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vrcp14ps, Vrcp14ps, Vec, Mem)                         //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vrcp14sd, Vrcp14sd, Xmm, Xmm, Xmm)                    //      AVX512_F{kz}
+  ASMJIT_INST_3x(vrcp14sd, Vrcp14sd, Xmm, Xmm, Mem)                    //      AVX512_F{kz}
+  ASMJIT_INST_3x(vrcp14ss, Vrcp14ss, Xmm, Xmm, Xmm)                    //      AVX512_F{kz}
+  ASMJIT_INST_3x(vrcp14ss, Vrcp14ss, Xmm, Xmm, Mem)                    //      AVX512_F{kz}
+  ASMJIT_INST_2x(vrcp28pd, Vrcp28pd, Vec, Vec)                         //      AVX512_ER{kz|sae|b64}
+  ASMJIT_INST_2x(vrcp28pd, Vrcp28pd, Vec, Mem)                         //      AVX512_ER{kz|sae|b64}
+  ASMJIT_INST_2x(vrcp28ps, Vrcp28ps, Vec, Vec)                         //      AVX512_ER{kz|sae|b32}
+  ASMJIT_INST_2x(vrcp28ps, Vrcp28ps, Vec, Mem)                         //      AVX512_ER{kz|sae|b32}
+  ASMJIT_INST_3x(vrcp28sd, Vrcp28sd, Xmm, Xmm, Xmm)                    //      AVX512_ER{kz|sae}
+  ASMJIT_INST_3x(vrcp28sd, Vrcp28sd, Xmm, Xmm, Mem)                    //      AVX512_ER{kz|sae}
+  ASMJIT_INST_3x(vrcp28ss, Vrcp28ss, Xmm, Xmm, Xmm)                    //      AVX512_ER{kz|sae}
+  ASMJIT_INST_3x(vrcp28ss, Vrcp28ss, Xmm, Xmm, Mem)                    //      AVX512_ER{kz|sae}
+  ASMJIT_INST_2x(vrcpps, Vrcpps, Vec, Vec)                             // AVX
+  ASMJIT_INST_2x(vrcpps, Vrcpps, Vec, Mem)                             // AVX
+  ASMJIT_INST_3x(vrcpss, Vrcpss, Xmm, Xmm, Xmm)                        // AVX
+  ASMJIT_INST_3x(vrcpss, Vrcpss, Xmm, Xmm, Mem)                        // AVX
+  ASMJIT_INST_3i(vreducepd, Vreducepd, Vec, Vec, Imm)                  //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_3i(vreducepd, Vreducepd, Vec, Mem, Imm)                  //      AVX512_DQ{kz|b64}
+  ASMJIT_INST_3i(vreduceps, Vreduceps, Vec, Vec, Imm)                  //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_3i(vreduceps, Vreduceps, Vec, Mem, Imm)                  //      AVX512_DQ{kz|b32}
+  ASMJIT_INST_4i(vreducesd, Vreducesd, Xmm, Xmm, Xmm, Imm)             //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vreducesd, Vreducesd, Xmm, Xmm, Mem, Imm)             //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vreducess, Vreducess, Xmm, Xmm, Xmm, Imm)             //      AVX512_DQ{kz}
+  ASMJIT_INST_4i(vreducess, Vreducess, Xmm, Xmm, Mem, Imm)             //      AVX512_DQ{kz}
+  ASMJIT_INST_3i(vrndscalepd, Vrndscalepd, Vec, Vec, Imm)              //      AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vrndscalepd, Vrndscalepd, Vec, Mem, Imm)              //      AVX512_F{kz|b64}
+  ASMJIT_INST_3i(vrndscaleps, Vrndscaleps, Vec, Vec, Imm)              //      AVX512_F{kz|b32}
+  ASMJIT_INST_3i(vrndscaleps, Vrndscaleps, Vec, Mem, Imm)              //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vrndscalesd, Vrndscalesd, Xmm, Xmm, Xmm, Imm)         //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vrndscalesd, Vrndscalesd, Xmm, Xmm, Mem, Imm)         //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vrndscaless, Vrndscaless, Xmm, Xmm, Xmm, Imm)         //      AVX512_F{kz|sae}
+  ASMJIT_INST_4i(vrndscaless, Vrndscaless, Xmm, Xmm, Mem, Imm)         //      AVX512_F{kz|sae}
+  ASMJIT_INST_3i(vroundpd, Vroundpd, Vec, Vec, Imm)                    // AVX
+  ASMJIT_INST_3i(vroundpd, Vroundpd, Vec, Mem, Imm)                    // AVX
+  ASMJIT_INST_3i(vroundps, Vroundps, Vec, Vec, Imm)                    // AVX
+  ASMJIT_INST_3i(vroundps, Vroundps, Vec, Mem, Imm)                    // AVX
+  ASMJIT_INST_4i(vroundsd, Vroundsd, Xmm, Xmm, Xmm, Imm)               // AVX
+  ASMJIT_INST_4i(vroundsd, Vroundsd, Xmm, Xmm, Mem, Imm)               // AVX
+  ASMJIT_INST_4i(vroundss, Vroundss, Xmm, Xmm, Xmm, Imm)               // AVX
+  ASMJIT_INST_4i(vroundss, Vroundss, Xmm, Xmm, Mem, Imm)               // AVX
+  ASMJIT_INST_2x(vrsqrt14pd, Vrsqrt14pd, Vec, Vec)                     //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vrsqrt14pd, Vrsqrt14pd, Vec, Mem)                     //      AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vrsqrt14ps, Vrsqrt14ps, Vec, Vec)                     //      AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vrsqrt14ps, Vrsqrt14ps, Vec, Mem)                     //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vrsqrt14sd, Vrsqrt14sd, Xmm, Xmm, Xmm)                //      AVX512_F{kz}
+  ASMJIT_INST_3x(vrsqrt14sd, Vrsqrt14sd, Xmm, Xmm, Mem)                //      AVX512_F{kz}
+  ASMJIT_INST_3x(vrsqrt14ss, Vrsqrt14ss, Xmm, Xmm, Xmm)                //      AVX512_F{kz}
+  ASMJIT_INST_3x(vrsqrt14ss, Vrsqrt14ss, Xmm, Xmm, Mem)                //      AVX512_F{kz}
+  ASMJIT_INST_2x(vrsqrt28pd, Vrsqrt28pd, Vec, Vec)                     //      AVX512_ER{kz|sae|b64}
+  ASMJIT_INST_2x(vrsqrt28pd, Vrsqrt28pd, Vec, Mem)                     //      AVX512_ER{kz|sae|b64}
+  ASMJIT_INST_2x(vrsqrt28ps, Vrsqrt28ps, Vec, Vec)                     //      AVX512_ER{kz|sae|b32}
+  ASMJIT_INST_2x(vrsqrt28ps, Vrsqrt28ps, Vec, Mem)                     //      AVX512_ER{kz|sae|b32}
+  ASMJIT_INST_3x(vrsqrt28sd, Vrsqrt28sd, Xmm, Xmm, Xmm)                //      AVX512_ER{kz|sae}
+  ASMJIT_INST_3x(vrsqrt28sd, Vrsqrt28sd, Xmm, Xmm, Mem)                //      AVX512_ER{kz|sae}
+  ASMJIT_INST_3x(vrsqrt28ss, Vrsqrt28ss, Xmm, Xmm, Xmm)                //      AVX512_ER{kz|sae}
+  ASMJIT_INST_3x(vrsqrt28ss, Vrsqrt28ss, Xmm, Xmm, Mem)                //      AVX512_ER{kz|sae}
+  ASMJIT_INST_2x(vrsqrtps, Vrsqrtps, Vec, Vec)                         // AVX
+  ASMJIT_INST_2x(vrsqrtps, Vrsqrtps, Vec, Mem)                         // AVX
+  ASMJIT_INST_3x(vrsqrtss, Vrsqrtss, Xmm, Xmm, Xmm)                    // AVX
+  ASMJIT_INST_3x(vrsqrtss, Vrsqrtss, Xmm, Xmm, Mem)                    // AVX
+  ASMJIT_INST_3x(vscalefpd, Vscalefpd, Vec, Vec, Vec)                  //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vscalefpd, Vscalefpd, Vec, Vec, Mem)                  //      AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vscalefps, Vscalefps, Vec, Vec, Vec)                  //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vscalefps, Vscalefps, Vec, Vec, Mem)                  //      AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vscalefsd, Vscalefsd, Xmm, Xmm, Xmm)                  //      AVX512_F{kz|er}
+  ASMJIT_INST_3x(vscalefsd, Vscalefsd, Xmm, Xmm, Mem)                  //      AVX512_F{kz|er}
+  ASMJIT_INST_3x(vscalefss, Vscalefss, Xmm, Xmm, Xmm)                  //      AVX512_F{kz|er}
+  ASMJIT_INST_3x(vscalefss, Vscalefss, Xmm, Xmm, Mem)                  //      AVX512_F{kz|er}
+  ASMJIT_INST_2x(vscatterdpd, Vscatterdpd, Mem, Vec)                   //      AVX512_F{k}
+  ASMJIT_INST_2x(vscatterdps, Vscatterdps, Mem, Vec)                   //      AVX512_F{k}
+  ASMJIT_INST_1x(vscatterpf0dpd, Vscatterpf0dpd, Mem)                  //      AVX512_PF{k}
+  ASMJIT_INST_1x(vscatterpf0dps, Vscatterpf0dps, Mem)                  //      AVX512_PF{k}
+  ASMJIT_INST_1x(vscatterpf0qpd, Vscatterpf0qpd, Mem)                  //      AVX512_PF{k}
+  ASMJIT_INST_1x(vscatterpf0qps, Vscatterpf0qps, Mem)                  //      AVX512_PF{k}
+  ASMJIT_INST_1x(vscatterpf1dpd, Vscatterpf1dpd, Mem)                  //      AVX512_PF{k}
+  ASMJIT_INST_1x(vscatterpf1dps, Vscatterpf1dps, Mem)                  //      AVX512_PF{k}
+  ASMJIT_INST_1x(vscatterpf1qpd, Vscatterpf1qpd, Mem)                  //      AVX512_PF{k}
+  ASMJIT_INST_1x(vscatterpf1qps, Vscatterpf1qps, Mem)                  //      AVX512_PF{k}
+  ASMJIT_INST_2x(vscatterqpd, Vscatterqpd, Mem, Vec)                   //      AVX512_F{k}
+  ASMJIT_INST_2x(vscatterqps, Vscatterqps, Mem, Vec)                   //      AVX512_F{k}
+  ASMJIT_INST_4i(vshuff32x4, Vshuff32x4, Vec, Vec, Vec, Imm)           //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vshuff32x4, Vshuff32x4, Vec, Vec, Mem, Imm)           //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vshuff64x2, Vshuff64x2, Vec, Vec, Vec, Imm)           //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vshuff64x2, Vshuff64x2, Vec, Vec, Mem, Imm)           //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vshufi32x4, Vshufi32x4, Vec, Vec, Vec, Imm)           //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vshufi32x4, Vshufi32x4, Vec, Vec, Mem, Imm)           //      AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vshufi64x2, Vshufi64x2, Vec, Vec, Vec, Imm)           //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vshufi64x2, Vshufi64x2, Vec, Vec, Mem, Imm)           //      AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vshufpd, Vshufpd, Vec, Vec, Vec, Imm)                 // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vshufpd, Vshufpd, Vec, Vec, Mem, Imm)                 // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_4i(vshufps, Vshufps, Vec, Vec, Vec, Imm)                 // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_4i(vshufps, Vshufps, Vec, Vec, Mem, Imm)                 // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vsqrtpd, Vsqrtpd, Vec, Vec)                           // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vsqrtpd, Vsqrtpd, Vec, Mem)                           // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_2x(vsqrtps, Vsqrtps, Vec, Vec)                           // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_2x(vsqrtps, Vsqrtps, Vec, Mem)                           // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vsqrtsd, Vsqrtsd, Xmm, Xmm, Xmm)                      // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vsqrtsd, Vsqrtsd, Xmm, Xmm, Mem)                      // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vsqrtss, Vsqrtss, Xmm, Xmm, Xmm)                      // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vsqrtss, Vsqrtss, Xmm, Xmm, Mem)                      // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_1x(vstmxcsr, Vstmxcsr, Mem)                              // AVX
+  ASMJIT_INST_3x(vsubpd, Vsubpd, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vsubpd, Vsubpd, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vsubps, Vsubps, Vec, Vec, Vec)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vsubps, Vsubps, Vec, Vec, Mem)                        // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vsubsd, Vsubsd, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vsubsd, Vsubsd, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vsubss, Vsubss, Xmm, Xmm, Xmm)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_3x(vsubss, Vsubss, Xmm, Xmm, Mem)                        // AVX  AVX512_F{kz|er}
+  ASMJIT_INST_2x(vtestpd, Vtestpd, Vec, Vec)                           // AVX
+  ASMJIT_INST_2x(vtestpd, Vtestpd, Vec, Mem)                           // AVX
+  ASMJIT_INST_2x(vtestps, Vtestps, Vec, Vec)                           // AVX
+  ASMJIT_INST_2x(vtestps, Vtestps, Vec, Mem)                           // AVX
+  ASMJIT_INST_2x(vucomisd, Vucomisd, Xmm, Xmm)                         // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vucomisd, Vucomisd, Xmm, Mem)                         // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vucomiss, Vucomiss, Xmm, Xmm)                         // AVX  AVX512_F{sae}
+  ASMJIT_INST_2x(vucomiss, Vucomiss, Xmm, Mem)                         // AVX  AVX512_F{sae}
+  ASMJIT_INST_3x(vunpckhpd, Vunpckhpd, Vec, Vec, Vec)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vunpckhpd, Vunpckhpd, Vec, Vec, Mem)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vunpckhps, Vunpckhps, Vec, Vec, Vec)                  // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vunpckhps, Vunpckhps, Vec, Vec, Mem)                  // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vunpcklpd, Vunpcklpd, Vec, Vec, Vec)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vunpcklpd, Vunpcklpd, Vec, Vec, Mem)                  // AVX  AVX512_F{kz|b64}
+  ASMJIT_INST_3x(vunpcklps, Vunpcklps, Vec, Vec, Vec)                  // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vunpcklps, Vunpcklps, Vec, Vec, Mem)                  // AVX  AVX512_F{kz|b32}
+  ASMJIT_INST_3x(vxorpd, Vxorpd, Vec, Vec, Vec)                        // AVX  AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vxorpd, Vxorpd, Vec, Vec, Mem)                        // AVX  AVX512_DQ{kz|b64}
+  ASMJIT_INST_3x(vxorps, Vxorps, Vec, Vec, Vec)                        // AVX  AVX512_DQ{kz|b32}
+  ASMJIT_INST_3x(vxorps, Vxorps, Vec, Vec, Mem)                        // AVX  AVX512_DQ{kz|b32}
+  ASMJIT_INST_0x(vzeroall, Vzeroall)                                   // AVX
+  ASMJIT_INST_0x(vzeroupper, Vzeroupper)                               // AVX
+
+  //! \}
+
+  //! \name FMA4 Instructions
+  //! \{
+
+  ASMJIT_INST_4x(vfmaddpd, Vfmaddpd, Vec, Vec, Vec, Vec)               // FMA4
+  ASMJIT_INST_4x(vfmaddpd, Vfmaddpd, Vec, Vec, Mem, Vec)               // FMA4
+  ASMJIT_INST_4x(vfmaddpd, Vfmaddpd, Vec, Vec, Vec, Mem)               // FMA4
+  ASMJIT_INST_4x(vfmaddps, Vfmaddps, Vec, Vec, Vec, Vec)               // FMA4
+  ASMJIT_INST_4x(vfmaddps, Vfmaddps, Vec, Vec, Mem, Vec)               // FMA4
+  ASMJIT_INST_4x(vfmaddps, Vfmaddps, Vec, Vec, Vec, Mem)               // FMA4
+  ASMJIT_INST_4x(vfmaddsd, Vfmaddsd, Xmm, Xmm, Xmm, Xmm)               // FMA4
+  ASMJIT_INST_4x(vfmaddsd, Vfmaddsd, Xmm, Xmm, Mem, Xmm)               // FMA4
+  ASMJIT_INST_4x(vfmaddsd, Vfmaddsd, Xmm, Xmm, Xmm, Mem)               // FMA4
+  ASMJIT_INST_4x(vfmaddss, Vfmaddss, Xmm, Xmm, Xmm, Xmm)               // FMA4
+  ASMJIT_INST_4x(vfmaddss, Vfmaddss, Xmm, Xmm, Mem, Xmm)               // FMA4
+  ASMJIT_INST_4x(vfmaddss, Vfmaddss, Xmm, Xmm, Xmm, Mem)               // FMA4
+  ASMJIT_INST_4x(vfmaddsubpd, Vfmaddsubpd, Vec, Vec, Vec, Vec)         // FMA4
+  ASMJIT_INST_4x(vfmaddsubpd, Vfmaddsubpd, Vec, Vec, Mem, Vec)         // FMA4
+  ASMJIT_INST_4x(vfmaddsubpd, Vfmaddsubpd, Vec, Vec, Vec, Mem)         // FMA4
+  ASMJIT_INST_4x(vfmaddsubps, Vfmaddsubps, Vec, Vec, Vec, Vec)         // FMA4
+  ASMJIT_INST_4x(vfmaddsubps, Vfmaddsubps, Vec, Vec, Mem, Vec)         // FMA4
+  ASMJIT_INST_4x(vfmaddsubps, Vfmaddsubps, Vec, Vec, Vec, Mem)         // FMA4
+  ASMJIT_INST_4x(vfmsubaddpd, Vfmsubaddpd, Vec, Vec, Vec, Vec)         // FMA4
+  ASMJIT_INST_4x(vfmsubaddpd, Vfmsubaddpd, Vec, Vec, Mem, Vec)         // FMA4
+  ASMJIT_INST_4x(vfmsubaddpd, Vfmsubaddpd, Vec, Vec, Vec, Mem)         // FMA4
+  ASMJIT_INST_4x(vfmsubaddps, Vfmsubaddps, Vec, Vec, Vec, Vec)         // FMA4
+  ASMJIT_INST_4x(vfmsubaddps, Vfmsubaddps, Vec, Vec, Mem, Vec)         // FMA4
+  ASMJIT_INST_4x(vfmsubaddps, Vfmsubaddps, Vec, Vec, Vec, Mem)         // FMA4
+  ASMJIT_INST_4x(vfmsubpd, Vfmsubpd, Vec, Vec, Vec, Vec)               // FMA4
+  ASMJIT_INST_4x(vfmsubpd, Vfmsubpd, Vec, Vec, Mem, Vec)               // FMA4
+  ASMJIT_INST_4x(vfmsubpd, Vfmsubpd, Vec, Vec, Vec, Mem)               // FMA4
+  ASMJIT_INST_4x(vfmsubps, Vfmsubps, Vec, Vec, Vec, Vec)               // FMA4
+  ASMJIT_INST_4x(vfmsubps, Vfmsubps, Vec, Vec, Mem, Vec)               // FMA4
+  ASMJIT_INST_4x(vfmsubps, Vfmsubps, Vec, Vec, Vec, Mem)               // FMA4
+  ASMJIT_INST_4x(vfmsubsd, Vfmsubsd, Xmm, Xmm, Xmm, Xmm)               // FMA4
+  ASMJIT_INST_4x(vfmsubsd, Vfmsubsd, Xmm, Xmm, Mem, Xmm)               // FMA4
+  ASMJIT_INST_4x(vfmsubsd, Vfmsubsd, Xmm, Xmm, Xmm, Mem)               // FMA4
+  ASMJIT_INST_4x(vfmsubss, Vfmsubss, Xmm, Xmm, Xmm, Xmm)               // FMA4
+  ASMJIT_INST_4x(vfmsubss, Vfmsubss, Xmm, Xmm, Mem, Xmm)               // FMA4
+  ASMJIT_INST_4x(vfmsubss, Vfmsubss, Xmm, Xmm, Xmm, Mem)               // FMA4
+  ASMJIT_INST_4x(vfnmaddpd, Vfnmaddpd, Vec, Vec, Vec, Vec)             // FMA4
+  ASMJIT_INST_4x(vfnmaddpd, Vfnmaddpd, Vec, Vec, Mem, Vec)             // FMA4
+  ASMJIT_INST_4x(vfnmaddpd, Vfnmaddpd, Vec, Vec, Vec, Mem)             // FMA4
+  ASMJIT_INST_4x(vfnmaddps, Vfnmaddps, Vec, Vec, Vec, Vec)             // FMA4
+  ASMJIT_INST_4x(vfnmaddps, Vfnmaddps, Vec, Vec, Mem, Vec)             // FMA4
+  ASMJIT_INST_4x(vfnmaddps, Vfnmaddps, Vec, Vec, Vec, Mem)             // FMA4
+  ASMJIT_INST_4x(vfnmaddsd, Vfnmaddsd, Xmm, Xmm, Xmm, Xmm)             // FMA4
+  ASMJIT_INST_4x(vfnmaddsd, Vfnmaddsd, Xmm, Xmm, Mem, Xmm)             // FMA4
+  ASMJIT_INST_4x(vfnmaddsd, Vfnmaddsd, Xmm, Xmm, Xmm, Mem)             // FMA4
+  ASMJIT_INST_4x(vfnmaddss, Vfnmaddss, Xmm, Xmm, Xmm, Xmm)             // FMA4
+  ASMJIT_INST_4x(vfnmaddss, Vfnmaddss, Xmm, Xmm, Mem, Xmm)             // FMA4
+  ASMJIT_INST_4x(vfnmaddss, Vfnmaddss, Xmm, Xmm, Xmm, Mem)             // FMA4
+  ASMJIT_INST_4x(vfnmsubpd, Vfnmsubpd, Vec, Vec, Vec, Vec)             // FMA4
+  ASMJIT_INST_4x(vfnmsubpd, Vfnmsubpd, Vec, Vec, Mem, Vec)             // FMA4
+  ASMJIT_INST_4x(vfnmsubpd, Vfnmsubpd, Vec, Vec, Vec, Mem)             // FMA4
+  ASMJIT_INST_4x(vfnmsubps, Vfnmsubps, Vec, Vec, Vec, Vec)             // FMA4
+  ASMJIT_INST_4x(vfnmsubps, Vfnmsubps, Vec, Vec, Mem, Vec)             // FMA4
+  ASMJIT_INST_4x(vfnmsubps, Vfnmsubps, Vec, Vec, Vec, Mem)             // FMA4
+  ASMJIT_INST_4x(vfnmsubsd, Vfnmsubsd, Xmm, Xmm, Xmm, Xmm)             // FMA4
+  ASMJIT_INST_4x(vfnmsubsd, Vfnmsubsd, Xmm, Xmm, Mem, Xmm)             // FMA4
+  ASMJIT_INST_4x(vfnmsubsd, Vfnmsubsd, Xmm, Xmm, Xmm, Mem)             // FMA4
+  ASMJIT_INST_4x(vfnmsubss, Vfnmsubss, Xmm, Xmm, Xmm, Xmm)             // FMA4
+  ASMJIT_INST_4x(vfnmsubss, Vfnmsubss, Xmm, Xmm, Mem, Xmm)             // FMA4
+  ASMJIT_INST_4x(vfnmsubss, Vfnmsubss, Xmm, Xmm, Xmm, Mem)             // FMA4
+
+  //! \}
+
+  //! \name XOP Instructions (Deprecated)
+  //! \{
+
+  ASMJIT_INST_2x(vfrczpd, Vfrczpd, Vec, Vec)                           // XOP
+  ASMJIT_INST_2x(vfrczpd, Vfrczpd, Vec, Mem)                           // XOP
+  ASMJIT_INST_2x(vfrczps, Vfrczps, Vec, Vec)                           // XOP
+  ASMJIT_INST_2x(vfrczps, Vfrczps, Vec, Mem)                           // XOP
+  ASMJIT_INST_2x(vfrczsd, Vfrczsd, Xmm, Xmm)                           // XOP
+  ASMJIT_INST_2x(vfrczsd, Vfrczsd, Xmm, Mem)                           // XOP
+  ASMJIT_INST_2x(vfrczss, Vfrczss, Xmm, Xmm)                           // XOP
+  ASMJIT_INST_2x(vfrczss, Vfrczss, Xmm, Mem)                           // XOP
+  ASMJIT_INST_4x(vpcmov, Vpcmov, Vec, Vec, Vec, Vec)                   // XOP
+  ASMJIT_INST_4x(vpcmov, Vpcmov, Vec, Vec, Mem, Vec)                   // XOP
+  ASMJIT_INST_4x(vpcmov, Vpcmov, Vec, Vec, Vec, Mem)                   // XOP
+  ASMJIT_INST_4i(vpcomb, Vpcomb, Xmm, Xmm, Xmm, Imm)                   // XOP
+  ASMJIT_INST_4i(vpcomb, Vpcomb, Xmm, Xmm, Mem, Imm)                   // XOP
+  ASMJIT_INST_4i(vpcomd, Vpcomd, Xmm, Xmm, Xmm, Imm)                   // XOP
+  ASMJIT_INST_4i(vpcomd, Vpcomd, Xmm, Xmm, Mem, Imm)                   // XOP
+  ASMJIT_INST_4i(vpcomq, Vpcomq, Xmm, Xmm, Xmm, Imm)                   // XOP
+  ASMJIT_INST_4i(vpcomq, Vpcomq, Xmm, Xmm, Mem, Imm)                   // XOP
+  ASMJIT_INST_4i(vpcomw, Vpcomw, Xmm, Xmm, Xmm, Imm)                   // XOP
+  ASMJIT_INST_4i(vpcomw, Vpcomw, Xmm, Xmm, Mem, Imm)                   // XOP
+  ASMJIT_INST_4i(vpcomub, Vpcomub, Xmm, Xmm, Xmm, Imm)                 // XOP
+  ASMJIT_INST_4i(vpcomub, Vpcomub, Xmm, Xmm, Mem, Imm)                 // XOP
+  ASMJIT_INST_4i(vpcomud, Vpcomud, Xmm, Xmm, Xmm, Imm)                 // XOP
+  ASMJIT_INST_4i(vpcomud, Vpcomud, Xmm, Xmm, Mem, Imm)                 // XOP
+  ASMJIT_INST_4i(vpcomuq, Vpcomuq, Xmm, Xmm, Xmm, Imm)                 // XOP
+  ASMJIT_INST_4i(vpcomuq, Vpcomuq, Xmm, Xmm, Mem, Imm)                 // XOP
+  ASMJIT_INST_4i(vpcomuw, Vpcomuw, Xmm, Xmm, Xmm, Imm)                 // XOP
+  ASMJIT_INST_4i(vpcomuw, Vpcomuw, Xmm, Xmm, Mem, Imm)                 // XOP
+  ASMJIT_INST_5i(vpermil2pd, Vpermil2pd, Vec, Vec, Vec, Vec, Imm)      // XOP
+  ASMJIT_INST_5i(vpermil2pd, Vpermil2pd, Vec, Vec, Mem, Vec, Imm)      // XOP
+  ASMJIT_INST_5i(vpermil2pd, Vpermil2pd, Vec, Vec, Vec, Mem, Imm)      // XOP
+  ASMJIT_INST_5i(vpermil2ps, Vpermil2ps, Vec, Vec, Vec, Vec, Imm)      // XOP
+  ASMJIT_INST_5i(vpermil2ps, Vpermil2ps, Vec, Vec, Mem, Vec, Imm)      // XOP
+  ASMJIT_INST_5i(vpermil2ps, Vpermil2ps, Vec, Vec, Vec, Mem, Imm)      // XOP
+  ASMJIT_INST_2x(vphaddbd, Vphaddbd, Xmm, Xmm)                         // XOP
+  ASMJIT_INST_2x(vphaddbd, Vphaddbd, Xmm, Mem)                         // XOP
+  ASMJIT_INST_2x(vphaddbq, Vphaddbq, Xmm, Xmm)                         // XOP
+  ASMJIT_INST_2x(vphaddbq, Vphaddbq, Xmm, Mem)                         // XOP
+  ASMJIT_INST_2x(vphaddbw, Vphaddbw, Xmm, Xmm)                         // XOP
+  ASMJIT_INST_2x(vphaddbw, Vphaddbw, Xmm, Mem)                         // XOP
+  ASMJIT_INST_2x(vphadddq, Vphadddq, Xmm, Xmm)                         // XOP
+  ASMJIT_INST_2x(vphadddq, Vphadddq, Xmm, Mem)                         // XOP
+  ASMJIT_INST_2x(vphaddwd, Vphaddwd, Xmm, Xmm)                         // XOP
+  ASMJIT_INST_2x(vphaddwd, Vphaddwd, Xmm, Mem)                         // XOP
+  ASMJIT_INST_2x(vphaddwq, Vphaddwq, Xmm, Xmm)                         // XOP
+  ASMJIT_INST_2x(vphaddwq, Vphaddwq, Xmm, Mem)                         // XOP
+  ASMJIT_INST_2x(vphaddubd, Vphaddubd, Xmm, Xmm)                       // XOP
+  ASMJIT_INST_2x(vphaddubd, Vphaddubd, Xmm, Mem)                       // XOP
+  ASMJIT_INST_2x(vphaddubq, Vphaddubq, Xmm, Xmm)                       // XOP
+  ASMJIT_INST_2x(vphaddubq, Vphaddubq, Xmm, Mem)                       // XOP
+  ASMJIT_INST_2x(vphaddubw, Vphaddubw, Xmm, Xmm)                       // XOP
+  ASMJIT_INST_2x(vphaddubw, Vphaddubw, Xmm, Mem)                       // XOP
+  ASMJIT_INST_2x(vphaddudq, Vphaddudq, Xmm, Xmm)                       // XOP
+  ASMJIT_INST_2x(vphaddudq, Vphaddudq, Xmm, Mem)                       // XOP
+  ASMJIT_INST_2x(vphadduwd, Vphadduwd, Xmm, Xmm)                       // XOP
+  ASMJIT_INST_2x(vphadduwd, Vphadduwd, Xmm, Mem)                       // XOP
+  ASMJIT_INST_2x(vphadduwq, Vphadduwq, Xmm, Xmm)                       // XOP
+  ASMJIT_INST_2x(vphadduwq, Vphadduwq, Xmm, Mem)                       // XOP
+  ASMJIT_INST_2x(vphsubbw, Vphsubbw, Xmm, Xmm)                         // XOP
+  ASMJIT_INST_2x(vphsubbw, Vphsubbw, Xmm, Mem)                         // XOP
+  ASMJIT_INST_2x(vphsubdq, Vphsubdq, Xmm, Xmm)                         // XOP
+  ASMJIT_INST_2x(vphsubdq, Vphsubdq, Xmm, Mem)                         // XOP
+  ASMJIT_INST_2x(vphsubwd, Vphsubwd, Xmm, Xmm)                         // XOP
+  ASMJIT_INST_2x(vphsubwd, Vphsubwd, Xmm, Mem)                         // XOP
+  ASMJIT_INST_4x(vpmacsdd, Vpmacsdd, Xmm, Xmm, Xmm, Xmm)               // XOP
+  ASMJIT_INST_4x(vpmacsdd, Vpmacsdd, Xmm, Xmm, Mem, Xmm)               // XOP
+  ASMJIT_INST_4x(vpmacsdqh, Vpmacsdqh, Xmm, Xmm, Xmm, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmacsdqh, Vpmacsdqh, Xmm, Xmm, Mem, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmacsdql, Vpmacsdql, Xmm, Xmm, Xmm, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmacsdql, Vpmacsdql, Xmm, Xmm, Mem, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmacswd, Vpmacswd, Xmm, Xmm, Xmm, Xmm)               // XOP
+  ASMJIT_INST_4x(vpmacswd, Vpmacswd, Xmm, Xmm, Mem, Xmm)               // XOP
+  ASMJIT_INST_4x(vpmacsww, Vpmacsww, Xmm, Xmm, Xmm, Xmm)               // XOP
+  ASMJIT_INST_4x(vpmacsww, Vpmacsww, Xmm, Xmm, Mem, Xmm)               // XOP
+  ASMJIT_INST_4x(vpmacssdd, Vpmacssdd, Xmm, Xmm, Xmm, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmacssdd, Vpmacssdd, Xmm, Xmm, Mem, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmacssdqh, Vpmacssdqh, Xmm, Xmm, Xmm, Xmm)           // XOP
+  ASMJIT_INST_4x(vpmacssdqh, Vpmacssdqh, Xmm, Xmm, Mem, Xmm)           // XOP
+  ASMJIT_INST_4x(vpmacssdql, Vpmacssdql, Xmm, Xmm, Xmm, Xmm)           // XOP
+  ASMJIT_INST_4x(vpmacssdql, Vpmacssdql, Xmm, Xmm, Mem, Xmm)           // XOP
+  ASMJIT_INST_4x(vpmacsswd, Vpmacsswd, Xmm, Xmm, Xmm, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmacsswd, Vpmacsswd, Xmm, Xmm, Mem, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmacssww, Vpmacssww, Xmm, Xmm, Xmm, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmacssww, Vpmacssww, Xmm, Xmm, Mem, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmadcsswd, Vpmadcsswd, Xmm, Xmm, Xmm, Xmm)           // XOP
+  ASMJIT_INST_4x(vpmadcsswd, Vpmadcsswd, Xmm, Xmm, Mem, Xmm)           // XOP
+  ASMJIT_INST_4x(vpmadcswd, Vpmadcswd, Xmm, Xmm, Xmm, Xmm)             // XOP
+  ASMJIT_INST_4x(vpmadcswd, Vpmadcswd, Xmm, Xmm, Mem, Xmm)             // XOP
+  ASMJIT_INST_4x(vpperm, Vpperm, Xmm, Xmm, Xmm, Xmm)                   // XOP
+  ASMJIT_INST_4x(vpperm, Vpperm, Xmm, Xmm, Mem, Xmm)                   // XOP
+  ASMJIT_INST_4x(vpperm, Vpperm, Xmm, Xmm, Xmm, Mem)                   // XOP
+  ASMJIT_INST_3x(vprotb, Vprotb, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vprotb, Vprotb, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vprotb, Vprotb, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3i(vprotb, Vprotb, Xmm, Xmm, Imm)                        // XOP
+  ASMJIT_INST_3i(vprotb, Vprotb, Xmm, Mem, Imm)                        // XOP
+  ASMJIT_INST_3x(vprotd, Vprotd, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vprotd, Vprotd, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vprotd, Vprotd, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3i(vprotd, Vprotd, Xmm, Xmm, Imm)                        // XOP
+  ASMJIT_INST_3i(vprotd, Vprotd, Xmm, Mem, Imm)                        // XOP
+  ASMJIT_INST_3x(vprotq, Vprotq, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vprotq, Vprotq, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vprotq, Vprotq, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3i(vprotq, Vprotq, Xmm, Xmm, Imm)                        // XOP
+  ASMJIT_INST_3i(vprotq, Vprotq, Xmm, Mem, Imm)                        // XOP
+  ASMJIT_INST_3x(vprotw, Vprotw, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vprotw, Vprotw, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vprotw, Vprotw, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3i(vprotw, Vprotw, Xmm, Xmm, Imm)                        // XOP
+  ASMJIT_INST_3i(vprotw, Vprotw, Xmm, Mem, Imm)                        // XOP
+  ASMJIT_INST_3x(vpshab, Vpshab, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshab, Vpshab, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshab, Vpshab, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3x(vpshad, Vpshad, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshad, Vpshad, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshad, Vpshad, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3x(vpshaq, Vpshaq, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshaq, Vpshaq, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshaq, Vpshaq, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3x(vpshaw, Vpshaw, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshaw, Vpshaw, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshaw, Vpshaw, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3x(vpshlb, Vpshlb, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshlb, Vpshlb, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshlb, Vpshlb, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3x(vpshld, Vpshld, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshld, Vpshld, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshld, Vpshld, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3x(vpshlq, Vpshlq, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshlq, Vpshlq, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshlq, Vpshlq, Xmm, Xmm, Mem)                        // XOP
+  ASMJIT_INST_3x(vpshlw, Vpshlw, Xmm, Xmm, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshlw, Vpshlw, Xmm, Mem, Xmm)                        // XOP
+  ASMJIT_INST_3x(vpshlw, Vpshlw, Xmm, Xmm, Mem)                        // XOP
+
+  //! \}
+
+  //! \name AMX Instructions
+  //! \{
+
+  ASMJIT_INST_1x(ldtilecfg, Ldtilecfg, Mem)                            // AMX_TILE
+  ASMJIT_INST_1x(sttilecfg, Sttilecfg, Mem)                            // AMX_TILE
+  ASMJIT_INST_2x(tileloadd, Tileloadd, Tmm, Mem)                       // AMX_TILE
+  ASMJIT_INST_2x(tileloaddt1, Tileloaddt1, Tmm, Mem)                   // AMX_TILE
+  ASMJIT_INST_0x(tilerelease, Tilerelease)                             // AMX_TILE
+  ASMJIT_INST_2x(tilestored, Tilestored, Mem, Tmm)                     // AMX_TILE
+  ASMJIT_INST_1x(tilezero, Tilezero, Tmm)                              // AMX_TILE
+
+  ASMJIT_INST_3x(tdpbf16ps, Tdpbf16ps, Tmm, Tmm, Tmm)                  // AMX_BF16
+  ASMJIT_INST_3x(tdpbssd, Tdpbssd, Tmm, Tmm, Tmm)                      // AMX_INT8
+  ASMJIT_INST_3x(tdpbsud, Tdpbsud, Tmm, Tmm, Tmm)                      // AMX_INT8
+  ASMJIT_INST_3x(tdpbusd, Tdpbusd, Tmm, Tmm, Tmm)                      // AMX_INT8
+  ASMJIT_INST_3x(tdpbuud, Tdpbuud, Tmm, Tmm, Tmm)                      // AMX_INT8
+
+  //! \}
+};
+
+// ============================================================================
+// [asmjit::x86::EmitterImplicitT]
+// ============================================================================
+
+//! Emitter (X86 - implicit).
+template<typename This>
+struct EmitterImplicitT : public EmitterExplicitT<This> {
+  //! \cond
+  using EmitterExplicitT<This>::_emitter;
+  //! \endcond
+
+  //! \name Prefix Options
+  //! \{
+
+  //! Use REP/REPE prefix.
+  inline This& rep() noexcept { return EmitterExplicitT<This>::_addInstOptions(Inst::kOptionRep); }
+  //! Use REP/REPE prefix.
+  inline This& repe() noexcept { return rep(); }
+  //! Use REP/REPE prefix.
+  inline This& repz() noexcept { return rep(); }
+
+  //! Use REPNE prefix.
+  inline This& repne() noexcept { return EmitterExplicitT<This>::_addInstOptions(Inst::kOptionRepne); }
+  //! Use REPNE prefix.
+  inline This& repnz() noexcept { return repne(); }
+
+  //! \}
+
+  //! \name Core Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::cbw;
+  using EmitterExplicitT<This>::cdq;
+  using EmitterExplicitT<This>::cdqe;
+  using EmitterExplicitT<This>::cqo;
+  using EmitterExplicitT<This>::cwd;
+  using EmitterExplicitT<This>::cwde;
+  using EmitterExplicitT<This>::cmpsd;
+  using EmitterExplicitT<This>::cmpxchg;
+  using EmitterExplicitT<This>::cmpxchg8b;
+  using EmitterExplicitT<This>::cmpxchg16b;
+  using EmitterExplicitT<This>::div;
+  using EmitterExplicitT<This>::idiv;
+  using EmitterExplicitT<This>::imul;
+  using EmitterExplicitT<This>::jecxz;
+  using EmitterExplicitT<This>::loop;
+  using EmitterExplicitT<This>::loope;
+  using EmitterExplicitT<This>::loopne;
+  using EmitterExplicitT<This>::mul;
+  //! \endcond
+
+  ASMJIT_INST_0x(cbw, Cbw)                                             // ANY       [IMPLICIT] AX      <- Sign Extend AL
+  ASMJIT_INST_0x(cdq, Cdq)                                             // ANY       [IMPLICIT] EDX:EAX <- Sign Extend EAX
+  ASMJIT_INST_0x(cdqe, Cdqe)                                           // X64       [IMPLICIT] RAX     <- Sign Extend EAX
+  ASMJIT_INST_2x(cmpxchg, Cmpxchg, Gp, Gp)                             // I486      [IMPLICIT]
+  ASMJIT_INST_2x(cmpxchg, Cmpxchg, Mem, Gp)                            // I486      [IMPLICIT]
+  ASMJIT_INST_1x(cmpxchg16b, Cmpxchg16b, Mem)                          // CMPXCHG8B [IMPLICIT] m == RDX:RAX ? m <- RCX:RBX
+  ASMJIT_INST_1x(cmpxchg8b, Cmpxchg8b, Mem)                            // CMPXCHG16B[IMPLICIT] m == EDX:EAX ? m <- ECX:EBX
+  ASMJIT_INST_0x(cqo, Cqo)                                             // X64       [IMPLICIT] RDX:RAX <- Sign Extend RAX
+  ASMJIT_INST_0x(cwd, Cwd)                                             // ANY       [IMPLICIT] DX:AX   <- Sign Extend AX
+  ASMJIT_INST_0x(cwde, Cwde)                                           // ANY       [IMPLICIT] EAX     <- Sign Extend AX
+  ASMJIT_INST_1x(div, Div, Gp)                                         // ANY       [IMPLICIT] {AH[Rem]: AL[Quot] <- AX / r8} {xDX[Rem]:xAX[Quot] <- DX:AX / r16|r32|r64}
+  ASMJIT_INST_1x(div, Div, Mem)                                        // ANY       [IMPLICIT] {AH[Rem]: AL[Quot] <- AX / m8} {xDX[Rem]:xAX[Quot] <- DX:AX / m16|m32|m64}
+  ASMJIT_INST_1x(idiv, Idiv, Gp)                                       // ANY       [IMPLICIT] {AH[Rem]: AL[Quot] <- AX / r8} {xDX[Rem]:xAX[Quot] <- DX:AX / r16|r32|r64}
+  ASMJIT_INST_1x(idiv, Idiv, Mem)                                      // ANY       [IMPLICIT] {AH[Rem]: AL[Quot] <- AX / m8} {xDX[Rem]:xAX[Quot] <- DX:AX / m16|m32|m64}
+  ASMJIT_INST_1x(imul, Imul, Gp)                                       // ANY       [IMPLICIT] {AX <- AL * r8} {xAX:xDX <- xAX * r16|r32|r64}
+  ASMJIT_INST_1x(imul, Imul, Mem)                                      // ANY       [IMPLICIT] {AX <- AL * m8} {xAX:xDX <- xAX * m16|m32|m64}
+  ASMJIT_INST_0x(iret, Iret)                                           // ANY       [IMPLICIT]
+  ASMJIT_INST_0x(iretd, Iretd)                                         // ANY       [IMPLICIT]
+  ASMJIT_INST_0x(iretq, Iretq)                                         // X64       [IMPLICIT]
+  ASMJIT_INST_0x(iretw, Iretw)                                         // ANY       [IMPLICIT]
+  ASMJIT_INST_1x(jecxz, Jecxz, Label)                                  // ANY       [IMPLICIT] Short jump if CX/ECX/RCX is zero.
+  ASMJIT_INST_1x(jecxz, Jecxz, Imm)                                    // ANY       [IMPLICIT] Short jump if CX/ECX/RCX is zero.
+  ASMJIT_INST_1x(jecxz, Jecxz, uint64_t)                               // ANY       [IMPLICIT] Short jump if CX/ECX/RCX is zero.
+  ASMJIT_INST_1x(loop, Loop, Label)                                    // ANY       [IMPLICIT] Decrement xCX; short jump if xCX != 0.
+  ASMJIT_INST_1x(loop, Loop, Imm)                                      // ANY       [IMPLICIT] Decrement xCX; short jump if xCX != 0.
+  ASMJIT_INST_1x(loop, Loop, uint64_t)                                 // ANY       [IMPLICIT] Decrement xCX; short jump if xCX != 0.
+  ASMJIT_INST_1x(loope, Loope, Label)                                  // ANY       [IMPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
+  ASMJIT_INST_1x(loope, Loope, Imm)                                    // ANY       [IMPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
+  ASMJIT_INST_1x(loope, Loope, uint64_t)                               // ANY       [IMPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 1.
+  ASMJIT_INST_1x(loopne, Loopne, Label)                                // ANY       [IMPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
+  ASMJIT_INST_1x(loopne, Loopne, Imm)                                  // ANY       [IMPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
+  ASMJIT_INST_1x(loopne, Loopne, uint64_t)                             // ANY       [IMPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0.
+  ASMJIT_INST_1x(mul, Mul, Gp)                                         // ANY       [IMPLICIT] {AX <- AL * r8} {xDX:xAX <- xAX * r16|r32|r64}
+  ASMJIT_INST_1x(mul, Mul, Mem)                                        // ANY       [IMPLICIT] {AX <- AL * m8} {xDX:xAX <- xAX * m16|m32|m64}
+  ASMJIT_INST_0x(ret, Ret)
+  ASMJIT_INST_1i(ret, Ret, Imm)
+  ASMJIT_INST_0x(xlatb, Xlatb)                                         // ANY       [IMPLICIT]
+
+  //! \}
+
+  //! \name String Instruction Aliases
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::movsd;
+  //! \endcond
+
+  inline Error cmpsb() { return _emitter()->emit(Inst::kIdCmps, EmitterExplicitT<This>::ptr_zsi(0, 1), EmitterExplicitT<This>::ptr_zdi(0, 1)); }
+  inline Error cmpsd() { return _emitter()->emit(Inst::kIdCmps, EmitterExplicitT<This>::ptr_zsi(0, 4), EmitterExplicitT<This>::ptr_zdi(0, 4)); }
+  inline Error cmpsq() { return _emitter()->emit(Inst::kIdCmps, EmitterExplicitT<This>::ptr_zsi(0, 8), EmitterExplicitT<This>::ptr_zdi(0, 8)); }
+  inline Error cmpsw() { return _emitter()->emit(Inst::kIdCmps, EmitterExplicitT<This>::ptr_zsi(0, 2), EmitterExplicitT<This>::ptr_zdi(0, 2)); }
+
+  inline Error lodsb() { return _emitter()->emit(Inst::kIdLods, al , EmitterExplicitT<This>::ptr_zsi(0, 1)); }
+  inline Error lodsd() { return _emitter()->emit(Inst::kIdLods, eax, EmitterExplicitT<This>::ptr_zsi(0, 4)); }
+  inline Error lodsq() { return _emitter()->emit(Inst::kIdLods, rax, EmitterExplicitT<This>::ptr_zsi(0, 8)); }
+  inline Error lodsw() { return _emitter()->emit(Inst::kIdLods, ax , EmitterExplicitT<This>::ptr_zsi(0, 2)); }
+
+  inline Error movsb() { return _emitter()->emit(Inst::kIdMovs, EmitterExplicitT<This>::ptr_zdi(0, 1), EmitterExplicitT<This>::ptr_zsi(0, 1)); }
+  inline Error movsd() { return _emitter()->emit(Inst::kIdMovs, EmitterExplicitT<This>::ptr_zdi(0, 4), EmitterExplicitT<This>::ptr_zsi(0, 4)); }
+  inline Error movsq() { return _emitter()->emit(Inst::kIdMovs, EmitterExplicitT<This>::ptr_zdi(0, 8), EmitterExplicitT<This>::ptr_zsi(0, 8)); }
+  inline Error movsw() { return _emitter()->emit(Inst::kIdMovs, EmitterExplicitT<This>::ptr_zdi(0, 2), EmitterExplicitT<This>::ptr_zsi(0, 2)); }
+
+  inline Error scasb() { return _emitter()->emit(Inst::kIdScas, al , EmitterExplicitT<This>::ptr_zdi(0, 1)); }
+  inline Error scasd() { return _emitter()->emit(Inst::kIdScas, eax, EmitterExplicitT<This>::ptr_zdi(0, 4)); }
+  inline Error scasq() { return _emitter()->emit(Inst::kIdScas, rax, EmitterExplicitT<This>::ptr_zdi(0, 8)); }
+  inline Error scasw() { return _emitter()->emit(Inst::kIdScas, ax , EmitterExplicitT<This>::ptr_zdi(0, 2)); }
+
+  inline Error stosb() { return _emitter()->emit(Inst::kIdStos, EmitterExplicitT<This>::ptr_zdi(0, 1), al ); }
+  inline Error stosd() { return _emitter()->emit(Inst::kIdStos, EmitterExplicitT<This>::ptr_zdi(0, 4), eax); }
+  inline Error stosq() { return _emitter()->emit(Inst::kIdStos, EmitterExplicitT<This>::ptr_zdi(0, 8), rax); }
+  inline Error stosw() { return _emitter()->emit(Inst::kIdStos, EmitterExplicitT<This>::ptr_zdi(0, 2), ax ); }
+
+  //! \}
+
+  //! \name Deprecated 32-bit Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::aaa;
+  using EmitterExplicitT<This>::aad;
+  using EmitterExplicitT<This>::aam;
+  using EmitterExplicitT<This>::aas;
+  using EmitterExplicitT<This>::daa;
+  using EmitterExplicitT<This>::das;
+  //! \endcond
+
+  ASMJIT_INST_0x(aaa, Aaa)                                             // X86 [IMPLICIT]
+  ASMJIT_INST_1i(aad, Aad, Imm)                                        // X86 [IMPLICIT]
+  ASMJIT_INST_1i(aam, Aam, Imm)                                        // X86 [IMPLICIT]
+  ASMJIT_INST_0x(aas, Aas)                                             // X86 [IMPLICIT]
+  ASMJIT_INST_0x(daa, Daa)                                             // X86 [IMPLICIT]
+  ASMJIT_INST_0x(das, Das)                                             // X86 [IMPLICIT]
+
+  //! \}
+
+  //! \name LAHF/SAHF Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::lahf;
+  using EmitterExplicitT<This>::sahf;
+  //! \endcond
+
+  ASMJIT_INST_0x(lahf, Lahf)                                           // LAHFSAHF  [IMPLICIT] AH <- EFL
+  ASMJIT_INST_0x(sahf, Sahf)                                           // LAHFSAHF  [IMPLICIT] EFL <- AH
+
+  //! \}
+
+  //! \name CPUID Instruction
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::cpuid;
+  //! \endcond
+
+  ASMJIT_INST_0x(cpuid, Cpuid)                                         // I486      [IMPLICIT] EAX:EBX:ECX:EDX  <- CPUID[EAX:ECX]
+
+  //! \}
+
+  //! \name CacheLine Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::clzero;
+  //! \endcond
+
+  ASMJIT_INST_0x(clzero, Clzero)                                       // CLZERO    [IMPLICIT]
+
+  //! \}
+
+  //! \name RDPRU/RDPKRU Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::rdpru;
+  using EmitterExplicitT<This>::rdpkru;
+  //! \endcond
+
+  ASMJIT_INST_0x(rdpru, Rdpru)                                         // RDPRU     [IMPLICIT] EDX:EAX <- PRU[ECX]
+  ASMJIT_INST_0x(rdpkru, Rdpkru)                                       // RDPKRU    [IMPLICIT] EDX:EAX <- PKRU[ECX]
+
+  //! \}
+
+  //! \name RDTSC/RDTSCP Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::rdtsc;
+  using EmitterExplicitT<This>::rdtscp;
+  //! \endcond
+
+  ASMJIT_INST_0x(rdtsc, Rdtsc)                                         // RDTSC     [IMPLICIT] EDX:EAX <- CNT
+  ASMJIT_INST_0x(rdtscp, Rdtscp)                                       // RDTSCP    [IMPLICIT] EDX:EAX:EXC <- CNT
+
+  //! \}
+
+  //! \name BMI2 Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::mulx;
+  //! \endcond
+
+  ASMJIT_INST_3x(mulx, Mulx, Gp, Gp, Gp)                               // BMI2      [IMPLICIT]
+  ASMJIT_INST_3x(mulx, Mulx, Gp, Gp, Mem)                              // BMI2      [IMPLICIT]
+
+  //! \}
+
+  //! \name XSAVE Instructions
+  //! \{
+
+  // TODO: xrstor and xsave don't have explicit variants yet.
+
+  //! \cond
+  using EmitterExplicitT<This>::xgetbv;
+  //! \endcond
+
+  ASMJIT_INST_0x(xgetbv, Xgetbv)                                       // XSAVE     [IMPLICIT] EDX:EAX <- XCR[ECX]
+  ASMJIT_INST_1x(xrstor, Xrstor, Mem)                                  // XSAVE     [IMPLICIT]
+  ASMJIT_INST_1x(xrstor64, Xrstor64, Mem)                              // XSAVE+X64 [IMPLICIT]
+  ASMJIT_INST_1x(xrstors, Xrstors, Mem)                                // XSAVE     [IMPLICIT]
+  ASMJIT_INST_1x(xrstors64, Xrstors64, Mem)                            // XSAVE+X64 [IMPLICIT]
+  ASMJIT_INST_1x(xsave, Xsave, Mem)                                    // XSAVE     [IMPLICIT]
+  ASMJIT_INST_1x(xsave64, Xsave64, Mem)                                // XSAVE+X64 [IMPLICIT]
+  ASMJIT_INST_1x(xsavec, Xsavec, Mem)                                  // XSAVE     [IMPLICIT]
+  ASMJIT_INST_1x(xsavec64, Xsavec64, Mem)                              // XSAVE+X64 [IMPLICIT]
+  ASMJIT_INST_1x(xsaveopt, Xsaveopt, Mem)                              // XSAVE     [IMPLICIT]
+  ASMJIT_INST_1x(xsaveopt64, Xsaveopt64, Mem)                          // XSAVE+X64 [IMPLICIT]
+  ASMJIT_INST_1x(xsaves, Xsaves, Mem)                                  // XSAVE     [IMPLICIT]
+  ASMJIT_INST_1x(xsaves64, Xsaves64, Mem)                              // XSAVE+X64 [IMPLICIT]
+
+  //! \}
+
+  //! \name SYSCALL/SYSENTER Instructions
+  //! \{
+
+  ASMJIT_INST_0x(syscall, Syscall)                                     // X64       [IMPLICIT]
+  ASMJIT_INST_0x(sysenter, Sysenter)                                   // X64       [IMPLICIT]
+
+  //! \}
+
+  //! \name Privileged Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::rdmsr;
+  using EmitterExplicitT<This>::rdpmc;
+  using EmitterExplicitT<This>::wrmsr;
+  using EmitterExplicitT<This>::xsetbv;
+  //! \endcond
+
+  ASMJIT_INST_0x(pconfig, Pconfig)                                     // PCONFIG   [IMPLICIT]
+  ASMJIT_INST_0x(rdmsr, Rdmsr)                                         // ANY       [IMPLICIT]
+  ASMJIT_INST_0x(rdpmc, Rdpmc)                                         // ANY       [IMPLICIT]
+  ASMJIT_INST_0x(sysexit, Sysexit)                                     // X64       [IMPLICIT]
+  ASMJIT_INST_0x(sysexit64, Sysexit64)                                 // X64       [IMPLICIT]
+  ASMJIT_INST_0x(sysret, Sysret)                                       // X64       [IMPLICIT]
+  ASMJIT_INST_0x(sysret64, Sysret64)                                   // X64       [IMPLICIT]
+  ASMJIT_INST_0x(wrmsr, Wrmsr)                                         // ANY       [IMPLICIT]
+  ASMJIT_INST_0x(xsetbv, Xsetbv)                                       // XSAVE     [IMPLICIT] XCR[ECX] <- EDX:EAX
+
+  //! \}
+
+  //! \name Monitor & MWait Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::monitor;
+  using EmitterExplicitT<This>::monitorx;
+  using EmitterExplicitT<This>::mwait;
+  using EmitterExplicitT<This>::mwaitx;
+  //! \endcond
+
+  ASMJIT_INST_0x(monitor, Monitor)
+  ASMJIT_INST_0x(monitorx, Monitorx)
+  ASMJIT_INST_0x(mwait, Mwait)
+  ASMJIT_INST_0x(mwaitx, Mwaitx)
+
+  //! \}
+
+  //! \name WAITPKG Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::tpause;
+  using EmitterExplicitT<This>::umwait;
+  //! \endcond
+
+  ASMJIT_INST_1x(tpause, Tpause, Gp)
+  ASMJIT_INST_1x(umwait, Umwait, Gp)
+
+  //! \}
+
+  //! \name MMX & SSE Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::blendvpd;
+  using EmitterExplicitT<This>::blendvps;
+  using EmitterExplicitT<This>::maskmovq;
+  using EmitterExplicitT<This>::maskmovdqu;
+  using EmitterExplicitT<This>::pblendvb;
+  using EmitterExplicitT<This>::pcmpestri;
+  using EmitterExplicitT<This>::pcmpestrm;
+  using EmitterExplicitT<This>::pcmpistri;
+  using EmitterExplicitT<This>::pcmpistrm;
+  //! \endcond
+
+  ASMJIT_INST_2x(blendvpd, Blendvpd, Xmm, Xmm)                         // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_2x(blendvpd, Blendvpd, Xmm, Mem)                         // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_2x(blendvps, Blendvps, Xmm, Xmm)                         // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_2x(blendvps, Blendvps, Xmm, Mem)                         // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_2x(pblendvb, Pblendvb, Xmm, Xmm)                         // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_2x(pblendvb, Pblendvb, Xmm, Mem)                         // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_2x(maskmovq, Maskmovq, Mm, Mm)                           // SSE    [IMPLICIT]
+  ASMJIT_INST_2x(maskmovdqu, Maskmovdqu, Xmm, Xmm)                     // SSE2   [IMPLICIT]
+  ASMJIT_INST_3i(pcmpestri, Pcmpestri, Xmm, Xmm, Imm)                  // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_3i(pcmpestri, Pcmpestri, Xmm, Mem, Imm)                  // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_3i(pcmpestrm, Pcmpestrm, Xmm, Xmm, Imm)                  // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_3i(pcmpestrm, Pcmpestrm, Xmm, Mem, Imm)                  // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_3i(pcmpistri, Pcmpistri, Xmm, Xmm, Imm)                  // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_3i(pcmpistri, Pcmpistri, Xmm, Mem, Imm)                  // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_3i(pcmpistrm, Pcmpistrm, Xmm, Xmm, Imm)                  // SSE4_1 [IMPLICIT]
+  ASMJIT_INST_3i(pcmpistrm, Pcmpistrm, Xmm, Mem, Imm)                  // SSE4_1 [IMPLICIT]
+
+  //! \}
+
+  //! \name SHA Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::sha256rnds2;
+  //! \endcond
+
+  ASMJIT_INST_2x(sha256rnds2, Sha256rnds2, Xmm, Xmm)                   // SHA [IMPLICIT]
+  ASMJIT_INST_2x(sha256rnds2, Sha256rnds2, Xmm, Mem)                   // SHA [IMPLICIT]
+
+  //! \}
+
+  //! \name AVX, FMA, and AVX512 Instructions
+  //! \{
+
+  //! \cond
+  using EmitterExplicitT<This>::vmaskmovdqu;
+  using EmitterExplicitT<This>::vpcmpestri;
+  using EmitterExplicitT<This>::vpcmpestrm;
+  using EmitterExplicitT<This>::vpcmpistri;
+  using EmitterExplicitT<This>::vpcmpistrm;
+  //! \endcond
+
+  ASMJIT_INST_2x(vmaskmovdqu, Vmaskmovdqu, Xmm, Xmm)                   // AVX [IMPLICIT]
+  ASMJIT_INST_3i(vpcmpestri, Vpcmpestri, Xmm, Xmm, Imm)                // AVX [IMPLICIT]
+  ASMJIT_INST_3i(vpcmpestri, Vpcmpestri, Xmm, Mem, Imm)                // AVX [IMPLICIT]
+  ASMJIT_INST_3i(vpcmpestrm, Vpcmpestrm, Xmm, Xmm, Imm)                // AVX [IMPLICIT]
+  ASMJIT_INST_3i(vpcmpestrm, Vpcmpestrm, Xmm, Mem, Imm)                // AVX [IMPLICIT]
+  ASMJIT_INST_3i(vpcmpistri, Vpcmpistri, Xmm, Xmm, Imm)                // AVX [IMPLICIT]
+  ASMJIT_INST_3i(vpcmpistri, Vpcmpistri, Xmm, Mem, Imm)                // AVX [IMPLICIT]
+  ASMJIT_INST_3i(vpcmpistrm, Vpcmpistrm, Xmm, Xmm, Imm)                // AVX [IMPLICIT]
+  ASMJIT_INST_3i(vpcmpistrm, Vpcmpistrm, Xmm, Mem, Imm)                // AVX [IMPLICIT]
+
+  //! \}
+};
+
+// ============================================================================
+// [asmjit::x86::Emitter]
+// ============================================================================
+
+//! Emitter (X86).
+//!
+//! \note This class cannot be instantiated, you can only cast to it and use
+//! it as emitter that emits to either `x86::Assembler`, `x86::Builder`, or
+//! `x86::Compiler` (use with caution with `x86::Compiler` as it requires virtual
+//! registers).
+class Emitter : public BaseEmitter, public EmitterImplicitT<Emitter> {
+  ASMJIT_NONCONSTRUCTIBLE(Emitter)
+};
+
+//! \}
+
+#undef ASMJIT_INST_0x
+#undef ASMJIT_INST_1x
+#undef ASMJIT_INST_1i
+#undef ASMJIT_INST_1c
+#undef ASMJIT_INST_2x
+#undef ASMJIT_INST_2i
+#undef ASMJIT_INST_2c
+#undef ASMJIT_INST_3x
+#undef ASMJIT_INST_3i
+#undef ASMJIT_INST_3ii
+#undef ASMJIT_INST_4x
+#undef ASMJIT_INST_4i
+#undef ASMJIT_INST_4ii
+#undef ASMJIT_INST_5x
+#undef ASMJIT_INST_5i
+#undef ASMJIT_INST_6x
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86EMITTER_H_INCLUDED
diff --git a/client/asmjit/x86/x86features.cpp b/client/asmjit/x86/x86features.cpp
new file mode 100644
index 0000000..5f851f3
--- /dev/null
+++ b/client/asmjit/x86/x86features.cpp
@@ -0,0 +1,447 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#include "../core/api-build_p.h"
+#if defined(ASMJIT_BUILD_X86) && ASMJIT_ARCH_X86
+
+#include "../core/cpuinfo.h"
+#include "../core/support.h"
+#include "../x86/x86features.h"
+
+// Required by `__cpuidex()` and `_xgetbv()`.
+#if defined(_MSC_VER)
+  #include <intrin.h>
+#endif
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::x86::Features - Detect]
+// ============================================================================
+
+struct cpuid_t { uint32_t eax, ebx, ecx, edx; };
+struct xgetbv_t { uint32_t eax, edx; };
+
+// Executes `cpuid` instruction.
+static inline void cpuidQuery(cpuid_t* out, uint32_t inEax, uint32_t inEcx = 0) noexcept {
+#if defined(_MSC_VER)
+  __cpuidex(reinterpret_cast<int*>(out), inEax, inEcx);
+#elif defined(__GNUC__) && ASMJIT_ARCH_X86 == 32
+  __asm__ __volatile__(
+    "mov %%ebx, %%edi\n"
+    "cpuid\n"
+    "xchg %%edi, %%ebx\n" : "=a"(out->eax), "=D"(out->ebx), "=c"(out->ecx), "=d"(out->edx) : "a"(inEax), "c"(inEcx));
+#elif defined(__GNUC__) && ASMJIT_ARCH_X86 == 64
+  __asm__ __volatile__(
+    "mov %%rbx, %%rdi\n"
+    "cpuid\n"
+    "xchg %%rdi, %%rbx\n" : "=a"(out->eax), "=D"(out->ebx), "=c"(out->ecx), "=d"(out->edx) : "a"(inEax), "c"(inEcx));
+#else
+  #error "[asmjit] x86::cpuidQuery() - Unsupported compiler."
+#endif
+}
+
+// Executes 'xgetbv' instruction.
+static inline void xgetbvQuery(xgetbv_t* out, uint32_t inEcx) noexcept {
+#if defined(_MSC_VER)
+  uint64_t value = _xgetbv(inEcx);
+  out->eax = uint32_t(value & 0xFFFFFFFFu);
+  out->edx = uint32_t(value >> 32);
+#elif defined(__GNUC__)
+  uint32_t outEax;
+  uint32_t outEdx;
+
+  // Replaced, because the world is not perfect:
+  //   __asm__ __volatile__("xgetbv" : "=a"(outEax), "=d"(outEdx) : "c"(inEcx));
+  __asm__ __volatile__(".byte 0x0F, 0x01, 0xD0" : "=a"(outEax), "=d"(outEdx) : "c"(inEcx));
+
+  out->eax = outEax;
+  out->edx = outEdx;
+#else
+  out->eax = 0;
+  out->edx = 0;
+#endif
+}
+
+// Map a 12-byte vendor string returned by `cpuid` into a `CpuInfo::Vendor` ID.
+static inline void simplifyCpuVendor(CpuInfo& cpu, uint32_t d0, uint32_t d1, uint32_t d2) noexcept {
+  struct Vendor {
+    char normalized[8];
+    union { char text[12]; uint32_t d[3]; };
+  };
+
+  static const Vendor table[] = {
+    { { 'A', 'M', 'D'                     }, {{ 'A', 'u', 't', 'h', 'e', 'n', 't', 'i', 'c', 'A', 'M', 'D' }} },
+    { { 'I', 'N', 'T', 'E', 'L'           }, {{ 'G', 'e', 'n', 'u', 'i', 'n', 'e', 'I', 'n', 't', 'e', 'l' }} },
+    { { 'V', 'I', 'A'                     }, {{ 'C', 'e', 'n', 't', 'a', 'u', 'r', 'H', 'a', 'u', 'l', 's' }} },
+    { { 'V', 'I', 'A'                     }, {{ 'V', 'I', 'A',  0 , 'V', 'I', 'A',  0 , 'V', 'I', 'A',  0  }} },
+    { { 'U', 'N', 'K', 'N', 'O', 'W', 'N' }, {{ 0                                                          }} }
+  };
+
+  uint32_t i;
+  for (i = 0; i < ASMJIT_ARRAY_SIZE(table) - 1; i++)
+    if (table[i].d[0] == d0 && table[i].d[1] == d1 && table[i].d[2] == d2)
+      break;
+  memcpy(cpu._vendor.str, table[i].normalized, 8);
+}
+
+static inline void simplifyCpuBrand(char* s) noexcept {
+  char* d = s;
+
+  char c = s[0];
+  char prev = 0;
+
+  // Used to always clear the current character to ensure that the result
+  // doesn't contain garbage after a new null terminator is placed at the end.
+  s[0] = '\0';
+
+  for (;;) {
+    if (!c)
+      break;
+
+    if (!(c == ' ' && (prev == '@' || s[1] == ' ' || s[1] == '@'))) {
+      *d++ = c;
+      prev = c;
+    }
+
+    c = *++s;
+    s[0] = '\0';
+  }
+
+  d[0] = '\0';
+}
+
+ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept {
+  using Support::bitTest;
+
+  cpuid_t regs;
+  xgetbv_t xcr0 { 0, 0 };
+  Features& features = cpu._features.as<Features>();
+
+  cpu.reset();
+  cpu._arch = Environment::kArchHost;
+  cpu._subArch = Environment::kSubArchUnknown;
+  cpu._reserved = 0;
+  cpu._maxLogicalProcessors = 1;
+  features.add(Features::kI486);
+
+  // --------------------------------------------------------------------------
+  // [CPUID EAX=0]
+  // --------------------------------------------------------------------------
+
+  // Get vendor string/id.
+  cpuidQuery(&regs, 0x0);
+
+  uint32_t maxId = regs.eax;
+  uint32_t maxSubLeafId_0x7 = 0;
+
+  simplifyCpuVendor(cpu, regs.ebx, regs.edx, regs.ecx);
+
+  // --------------------------------------------------------------------------
+  // [CPUID EAX=1]
+  // --------------------------------------------------------------------------
+
+  if (maxId >= 0x1) {
+    // Get feature flags in ECX/EDX and family/model in EAX.
+    cpuidQuery(&regs, 0x1);
+
+    // Fill family and model fields.
+    uint32_t modelId  = (regs.eax >> 4) & 0x0F;
+    uint32_t familyId = (regs.eax >> 8) & 0x0F;
+
+    // Use extended family and model fields.
+    if (familyId == 0x06u || familyId == 0x0Fu)
+      modelId += (((regs.eax >> 16) & 0x0Fu) << 4);
+
+    if (familyId == 0x0Fu)
+      familyId += (((regs.eax >> 20) & 0xFFu) << 4);
+
+    cpu._modelId              = modelId;
+    cpu._familyId             = familyId;
+    cpu._brandId              = ((regs.ebx      ) & 0xFF);
+    cpu._processorType        = ((regs.eax >> 12) & 0x03);
+    cpu._maxLogicalProcessors = ((regs.ebx >> 16) & 0xFF);
+    cpu._stepping             = ((regs.eax      ) & 0x0F);
+    cpu._cacheLineSize        = ((regs.ebx >>  8) & 0xFF) * 8;
+
+    if (bitTest(regs.ecx,  0)) features.add(Features::kSSE3);
+    if (bitTest(regs.ecx,  1)) features.add(Features::kPCLMULQDQ);
+    if (bitTest(regs.ecx,  3)) features.add(Features::kMONITOR);
+    if (bitTest(regs.ecx,  5)) features.add(Features::kVMX);
+    if (bitTest(regs.ecx,  6)) features.add(Features::kSMX);
+    if (bitTest(regs.ecx,  9)) features.add(Features::kSSSE3);
+    if (bitTest(regs.ecx, 13)) features.add(Features::kCMPXCHG16B);
+    if (bitTest(regs.ecx, 19)) features.add(Features::kSSE4_1);
+    if (bitTest(regs.ecx, 20)) features.add(Features::kSSE4_2);
+    if (bitTest(regs.ecx, 22)) features.add(Features::kMOVBE);
+    if (bitTest(regs.ecx, 23)) features.add(Features::kPOPCNT);
+    if (bitTest(regs.ecx, 25)) features.add(Features::kAESNI);
+    if (bitTest(regs.ecx, 26)) features.add(Features::kXSAVE);
+    if (bitTest(regs.ecx, 27)) features.add(Features::kOSXSAVE);
+    if (bitTest(regs.ecx, 30)) features.add(Features::kRDRAND);
+    if (bitTest(regs.edx,  0)) features.add(Features::kFPU);
+    if (bitTest(regs.edx,  4)) features.add(Features::kRDTSC);
+    if (bitTest(regs.edx,  5)) features.add(Features::kMSR);
+    if (bitTest(regs.edx,  8)) features.add(Features::kCMPXCHG8B);
+    if (bitTest(regs.edx, 15)) features.add(Features::kCMOV);
+    if (bitTest(regs.edx, 19)) features.add(Features::kCLFLUSH);
+    if (bitTest(regs.edx, 23)) features.add(Features::kMMX);
+    if (bitTest(regs.edx, 24)) features.add(Features::kFXSR);
+    if (bitTest(regs.edx, 25)) features.add(Features::kSSE);
+    if (bitTest(regs.edx, 26)) features.add(Features::kSSE, Features::kSSE2);
+    if (bitTest(regs.edx, 28)) features.add(Features::kMT);
+
+    // Get the content of XCR0 if supported by the CPU and enabled by the OS.
+    if (features.hasXSAVE() && features.hasOSXSAVE()) {
+      xgetbvQuery(&xcr0, 0);
+    }
+
+    // Detect AVX+.
+    if (bitTest(regs.ecx, 28)) {
+      // - XCR0[2:1] == 11b
+      //   XMM & YMM states need to be enabled by OS.
+      if ((xcr0.eax & 0x00000006u) == 0x00000006u) {
+        features.add(Features::kAVX);
+
+        if (bitTest(regs.ecx, 12)) features.add(Features::kFMA);
+        if (bitTest(regs.ecx, 29)) features.add(Features::kF16C);
+      }
+    }
+  }
+
+  constexpr uint32_t kXCR0_AMX_Bits = 0x3u << 17;
+  bool amxEnabledByOS = (xcr0.eax & kXCR0_AMX_Bits) == kXCR0_AMX_Bits;
+
+#if defined(__APPLE__)
+  // Apple platform provides on-demand AVX512 support. When an AVX512 instruction is used
+  // the first time it results in #UD, which would cause the thread being promoted to use
+  // AVX512 support by the OS in addition to enabling the necessary bits in XCR0 register.
+  bool avx512EnabledByOS = true;
+#else
+  // - XCR0[2:1] ==  11b - XMM/YMM states need to be enabled by OS.
+  // - XCR0[7:5] == 111b - Upper 256-bit of ZMM0-XMM15 and ZMM16-ZMM31 need to be enabled by OS.
+  constexpr uint32_t kXCR0_AVX512_Bits = (0x3u << 1) | (0x7u << 5);
+  bool avx512EnabledByOS = (xcr0.eax & kXCR0_AVX512_Bits) == kXCR0_AVX512_Bits;
+#endif
+
+  // --------------------------------------------------------------------------
+  // [CPUID EAX=7 ECX=0]
+  // --------------------------------------------------------------------------
+
+  // Detect new features if the processor supports CPUID-07.
+  bool maybeMPX = false;
+
+  if (maxId >= 0x7) {
+    cpuidQuery(&regs, 0x7);
+
+    maybeMPX = bitTest(regs.ebx, 14);
+    maxSubLeafId_0x7 = regs.eax;
+
+    if (bitTest(regs.ebx,  0)) features.add(Features::kFSGSBASE);
+    if (bitTest(regs.ebx,  3)) features.add(Features::kBMI);
+    if (bitTest(regs.ebx,  4)) features.add(Features::kHLE);
+    if (bitTest(regs.ebx,  7)) features.add(Features::kSMEP);
+    if (bitTest(regs.ebx,  8)) features.add(Features::kBMI2);
+    if (bitTest(regs.ebx,  9)) features.add(Features::kERMS);
+    if (bitTest(regs.ebx, 11)) features.add(Features::kRTM);
+    if (bitTest(regs.ebx, 18)) features.add(Features::kRDSEED);
+    if (bitTest(regs.ebx, 19)) features.add(Features::kADX);
+    if (bitTest(regs.ebx, 20)) features.add(Features::kSMAP);
+    if (bitTest(regs.ebx, 23)) features.add(Features::kCLFLUSHOPT);
+    if (bitTest(regs.ebx, 24)) features.add(Features::kCLWB);
+    if (bitTest(regs.ebx, 29)) features.add(Features::kSHA);
+    if (bitTest(regs.ecx,  0)) features.add(Features::kPREFETCHWT1);
+    if (bitTest(regs.ecx,  4)) features.add(Features::kOSPKE);
+    if (bitTest(regs.ecx,  5)) features.add(Features::kWAITPKG);
+    if (bitTest(regs.ecx,  8)) features.add(Features::kGFNI);
+    if (bitTest(regs.ecx,  9)) features.add(Features::kVAES);
+    if (bitTest(regs.ecx, 10)) features.add(Features::kVPCLMULQDQ);
+    if (bitTest(regs.ecx, 22)) features.add(Features::kRDPID);
+    if (bitTest(regs.ecx, 25)) features.add(Features::kCLDEMOTE);
+    if (bitTest(regs.ecx, 27)) features.add(Features::kMOVDIRI);
+    if (bitTest(regs.ecx, 28)) features.add(Features::kMOVDIR64B);
+    if (bitTest(regs.ecx, 29)) features.add(Features::kENQCMD);
+    if (bitTest(regs.edx, 14)) features.add(Features::kSERIALIZE);
+    if (bitTest(regs.edx, 16)) features.add(Features::kTSXLDTRK);
+    if (bitTest(regs.edx, 18)) features.add(Features::kPCONFIG);
+
+    // Detect 'TSX' - Requires at least one of `HLE` and `RTM` features.
+    if (features.hasHLE() || features.hasRTM())
+      features.add(Features::kTSX);
+
+    // Detect 'AVX2' - Requires AVX as well.
+    if (bitTest(regs.ebx, 5) && features.hasAVX())
+      features.add(Features::kAVX2);
+
+    // Detect 'AMX'.
+    if (amxEnabledByOS) {
+      if (bitTest(regs.edx, 22)) features.add(Features::kAMX_BF16);
+      if (bitTest(regs.edx, 24)) features.add(Features::kAMX_TILE);
+      if (bitTest(regs.edx, 25)) features.add(Features::kAMX_INT8);
+    }
+
+    // Detect 'AVX_512'.
+    if (avx512EnabledByOS && bitTest(regs.ebx, 16)) {
+      features.add(Features::kAVX512_F);
+
+      if (bitTest(regs.ebx, 17)) features.add(Features::kAVX512_DQ);
+      if (bitTest(regs.ebx, 21)) features.add(Features::kAVX512_IFMA);
+      if (bitTest(regs.ebx, 26)) features.add(Features::kAVX512_PFI);
+      if (bitTest(regs.ebx, 27)) features.add(Features::kAVX512_ERI);
+      if (bitTest(regs.ebx, 28)) features.add(Features::kAVX512_CDI);
+      if (bitTest(regs.ebx, 30)) features.add(Features::kAVX512_BW);
+      if (bitTest(regs.ebx, 31)) features.add(Features::kAVX512_VL);
+      if (bitTest(regs.ecx,  1)) features.add(Features::kAVX512_VBMI);
+      if (bitTest(regs.ecx,  6)) features.add(Features::kAVX512_VBMI2);
+      if (bitTest(regs.ecx, 11)) features.add(Features::kAVX512_VNNI);
+      if (bitTest(regs.ecx, 12)) features.add(Features::kAVX512_BITALG);
+      if (bitTest(regs.ecx, 14)) features.add(Features::kAVX512_VPOPCNTDQ);
+      if (bitTest(regs.edx,  2)) features.add(Features::kAVX512_4VNNIW);
+      if (bitTest(regs.edx,  3)) features.add(Features::kAVX512_4FMAPS);
+      if (bitTest(regs.edx,  8)) features.add(Features::kAVX512_VP2INTERSECT);
+    }
+  }
+
+  // --------------------------------------------------------------------------
+  // [CPUID EAX=7 ECX=1]
+  // --------------------------------------------------------------------------
+
+  if (features.hasAVX512_F() && maxSubLeafId_0x7 >= 1) {
+    cpuidQuery(&regs, 0x7, 1);
+
+    if (bitTest(regs.eax, 5)) features.add(Features::kAVX512_BF16);
+  }
+
+  // --------------------------------------------------------------------------
+  // [CPUID EAX=13 ECX=0]
+  // --------------------------------------------------------------------------
+
+  if (maxId >= 0xD) {
+    cpuidQuery(&regs, 0xD, 0);
+
+    // Both CPUID result and XCR0 has to be enabled to have support for MPX.
+    if (((regs.eax & xcr0.eax) & 0x00000018u) == 0x00000018u && maybeMPX)
+      features.add(Features::kMPX);
+
+    cpuidQuery(&regs, 0xD, 1);
+
+    if (bitTest(regs.eax, 0)) features.add(Features::kXSAVEOPT);
+    if (bitTest(regs.eax, 1)) features.add(Features::kXSAVEC);
+    if (bitTest(regs.eax, 3)) features.add(Features::kXSAVES);
+  }
+
+  // --------------------------------------------------------------------------
+  // [CPUID EAX=14 ECX=0]
+  // --------------------------------------------------------------------------
+
+  if (maxId >= 0xE) {
+    cpuidQuery(&regs, 0xE, 0);
+
+    if (bitTest(regs.ebx, 4)) features.add(Features::kPTWRITE);
+  }
+
+  // --------------------------------------------------------------------------
+  // [CPUID EAX=0x80000000...maxId]
+  // --------------------------------------------------------------------------
+
+  maxId = 0x80000000u;
+  uint32_t i = maxId;
+
+  // The highest EAX that we understand.
+  uint32_t kHighestProcessedEAX = 0x8000001Fu;
+
+  // Several CPUID calls are required to get the whole branc string. It's easy
+  // to copy one DWORD at a time instead of performing a byte copy.
+  uint32_t* brand = cpu._brand.u32;
+  do {
+    cpuidQuery(&regs, i);
+    switch (i) {
+      case 0x80000000u:
+        maxId = Support::min<uint32_t>(regs.eax, kHighestProcessedEAX);
+        break;
+
+      case 0x80000001u:
+        if (bitTest(regs.ecx,  0)) features.add(Features::kLAHFSAHF);
+        if (bitTest(regs.ecx,  2)) features.add(Features::kSVM);
+        if (bitTest(regs.ecx,  5)) features.add(Features::kLZCNT);
+        if (bitTest(regs.ecx,  6)) features.add(Features::kSSE4A);
+        if (bitTest(regs.ecx,  7)) features.add(Features::kMSSE);
+        if (bitTest(regs.ecx,  8)) features.add(Features::kPREFETCHW);
+        if (bitTest(regs.ecx, 12)) features.add(Features::kSKINIT);
+        if (bitTest(regs.ecx, 15)) features.add(Features::kLWP);
+        if (bitTest(regs.ecx, 21)) features.add(Features::kTBM);
+        if (bitTest(regs.ecx, 29)) features.add(Features::kMONITORX);
+        if (bitTest(regs.edx, 20)) features.add(Features::kNX);
+        if (bitTest(regs.edx, 21)) features.add(Features::kFXSROPT);
+        if (bitTest(regs.edx, 22)) features.add(Features::kMMX2);
+        if (bitTest(regs.edx, 27)) features.add(Features::kRDTSCP);
+        if (bitTest(regs.edx, 29)) features.add(Features::kPREFETCHW);
+        if (bitTest(regs.edx, 30)) features.add(Features::k3DNOW2, Features::kMMX2);
+        if (bitTest(regs.edx, 31)) features.add(Features::kPREFETCHW);
+
+        if (cpu.hasFeature(Features::kAVX)) {
+          if (bitTest(regs.ecx, 11)) features.add(Features::kXOP);
+          if (bitTest(regs.ecx, 16)) features.add(Features::kFMA4);
+        }
+
+        // These seem to be only supported by AMD.
+        if (cpu.isVendor("AMD")) {
+          if (bitTest(regs.ecx,  4)) features.add(Features::kALTMOVCR8);
+        }
+        break;
+
+      case 0x80000002u:
+      case 0x80000003u:
+      case 0x80000004u:
+        *brand++ = regs.eax;
+        *brand++ = regs.ebx;
+        *brand++ = regs.ecx;
+        *brand++ = regs.edx;
+
+        // Go directly to the next one we are interested in.
+        if (i == 0x80000004u) i = 0x80000008u - 1;
+        break;
+
+      case 0x80000008u:
+        if (bitTest(regs.ebx,  0)) features.add(Features::kCLZERO);
+        if (bitTest(regs.ebx,  0)) features.add(Features::kRDPRU);
+        if (bitTest(regs.ebx,  8)) features.add(Features::kMCOMMIT);
+        if (bitTest(regs.ebx,  9)) features.add(Features::kWBNOINVD);
+
+        // Go directly to the next one we are interested in.
+        i = 0x8000001Fu - 1;
+        break;
+
+      case 0x8000001Fu:
+        if (bitTest(regs.eax,  4)) features.add(Features::kSNP);
+        break;
+    }
+  } while (++i <= maxId);
+
+  // Simplify CPU brand string a bit by removing some unnecessary spaces.
+  simplifyCpuBrand(cpu._brand.str);
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86 && ASMJIT_ARCH_X86
diff --git a/client/asmjit/x86/x86features.h b/client/asmjit/x86/x86features.h
new file mode 100644
index 0000000..24a73f5
--- /dev/null
+++ b/client/asmjit/x86/x86features.h
@@ -0,0 +1,309 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86FEATURES_H_INCLUDED
+#define ASMJIT_X86_X86FEATURES_H_INCLUDED
+
+#include "../core/features.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::x86::Features]
+// ============================================================================
+
+//! CPU features (X86).
+class Features : public BaseFeatures {
+public:
+  //! CPU feature ID.
+  enum Id : uint32_t {
+    // @EnumValuesBegin{"enum": "x86::Features::Id"}@
+
+    kNone = 0,                 //!< No feature (never set, used internally).
+
+    kMT,                       //!< CPU has multi-threading capabilities.
+    kNX,                       //!< CPU has Not-Execute-Bit aka DEP (data-execution prevention).
+
+    k3DNOW,                    //!< CPU has 3DNOW            (3DNOW base instructions) [AMD].
+    k3DNOW2,                   //!< CPU has 3DNOW2           (enhanced 3DNOW) [AMD].
+    kADX,                      //!< CPU has ADX              (multi-precision add-carry instruction extensions).
+    kAESNI,                    //!< CPU has AESNI            (AES encode/decode instructions).
+    kALTMOVCR8,                //!< CPU has LOCK MOV R<->CR0 (supports `MOV R<->CR8` via `LOCK MOV R<->CR0` in 32-bit mode) [AMD].
+    kAMX_BF16,                 //!< CPU has AMX_BF16         (advanced matrix extensions - BF16 instructions).
+    kAMX_INT8,                 //!< CPU has AMX_INT8         (advanced matrix extensions - INT8 instructions).
+    kAMX_TILE,                 //!< CPU has AMX_TILE         (advanced matrix extensions).
+    kAVX,                      //!< CPU has AVX              (advanced vector extensions).
+    kAVX2,                     //!< CPU has AVX2             (advanced vector extensions 2).
+    kAVX512_4FMAPS,            //!< CPU has AVX512_FMAPS     (FMA packed single).
+    kAVX512_4VNNIW,            //!< CPU has AVX512_VNNIW     (vector NN instructions word variable precision).
+    kAVX512_BF16,              //!< CPU has AVX512_BF16      (BFLOAT16 support instruction).
+    kAVX512_BITALG,            //!< CPU has AVX512_BITALG    (VPOPCNT[B|W], VPSHUFBITQMB).
+    kAVX512_BW,                //!< CPU has AVX512_BW        (packed BYTE|WORD).
+    kAVX512_CDI,               //!< CPU has AVX512_CDI       (conflict detection).
+    kAVX512_DQ,                //!< CPU has AVX512_DQ        (packed DWORD|QWORD).
+    kAVX512_ERI,               //!< CPU has AVX512_ERI       (exponential and reciprocal).
+    kAVX512_F,                 //!< CPU has AVX512_F         (AVX512 foundation).
+    kAVX512_IFMA,              //!< CPU has AVX512_IFMA      (integer fused-multiply-add using 52-bit precision).
+    kAVX512_PFI,               //!< CPU has AVX512_PFI       (prefetch instructions).
+    kAVX512_VBMI,              //!< CPU has AVX512_VBMI      (vector byte manipulation).
+    kAVX512_VBMI2,             //!< CPU has AVX512_VBMI2     (vector byte manipulation 2).
+    kAVX512_VL,                //!< CPU has AVX512_VL        (vector length extensions).
+    kAVX512_VNNI,              //!< CPU has AVX512_VNNI      (vector neural network instructions).
+    kAVX512_VP2INTERSECT,      //!< CPU has AVX512_VP2INTERSECT
+    kAVX512_VPOPCNTDQ,         //!< CPU has AVX512_VPOPCNTDQ (VPOPCNT[D|Q] instructions).
+    kBMI,                      //!< CPU has BMI              (bit manipulation instructions #1).
+    kBMI2,                     //!< CPU has BMI2             (bit manipulation instructions #2).
+    kCET_IBT,                  //!< CPU has CET-IBT.
+    kCET_SS,                   //!< CPU has CET-SS.
+    kCLDEMOTE,                 //!< CPU has CLDEMOTE         (cache line demote).
+    kCLFLUSH,                  //!< CPU has CLFUSH           (Cache Line flush).
+    kCLFLUSHOPT,               //!< CPU has CLFUSHOPT        (Cache Line flush - optimized).
+    kCLWB,                     //!< CPU has CLWB.
+    kCLZERO,                   //!< CPU has CLZERO.
+    kCMOV,                     //!< CPU has CMOV             (CMOV and FCMOV instructions).
+    kCMPXCHG16B,               //!< CPU has CMPXCHG16B       (compare-exchange 16 bytes) [X86_64].
+    kCMPXCHG8B,                //!< CPU has CMPXCHG8B        (compare-exchange 8 bytes).
+    kENCLV,                    //!< CPU has ENCLV.
+    kENQCMD,                   //!< CPU has ENQCMD           (enqueue stores).
+    kERMS,                     //!< CPU has ERMS             (enhanced REP MOVSB/STOSB).
+    kF16C,                     //!< CPU has F16C.
+    kFMA,                      //!< CPU has FMA              (fused-multiply-add 3 operand form).
+    kFMA4,                     //!< CPU has FMA4             (fused-multiply-add 4 operand form).
+    kFPU,                      //!< CPU has FPU              (FPU support).
+    kFSGSBASE,                 //!< CPU has FSGSBASE.
+    kFXSR,                     //!< CPU has FXSR             (FXSAVE/FXRSTOR instructions).
+    kFXSROPT,                  //!< CPU has FXSROTP          (FXSAVE/FXRSTOR is optimized).
+    kGEODE,                    //!< CPU has GEODE extensions (3DNOW additions).
+    kGFNI,                     //!< CPU has GFNI             (Galois field instructions).
+    kHLE,                      //!< CPU has HLE.
+    kI486,                     //!< CPU has I486 features    (I486+ support).
+    kLAHFSAHF,                 //!< CPU has LAHF/SAHF        (LAHF/SAHF in 64-bit mode) [X86_64].
+    kLWP,                      //!< CPU has LWP              (lightweight profiling) [AMD].
+    kLZCNT,                    //!< CPU has LZCNT            (LZCNT instruction).
+    kMCOMMIT,                  //!< CPU has MCOMMIT          (MCOMMIT instruction).
+    kMMX,                      //!< CPU has MMX              (MMX base instructions).
+    kMMX2,                     //!< CPU has MMX2             (MMX extensions or MMX2).
+    kMONITOR,                  //!< CPU has MONITOR          (MONITOR/MWAIT instructions).
+    kMONITORX,                 //!< CPU has MONITORX         (MONITORX/MWAITX instructions).
+    kMOVBE,                    //!< CPU has MOVBE            (move with byte-order swap).
+    kMOVDIR64B,                //!< CPU has MOVDIR64B        (move 64 bytes as direct store).
+    kMOVDIRI,                  //!< CPU has MOVDIRI          (move dword/qword as direct store).
+    kMPX,                      //!< CPU has MPX              (memory protection extensions).
+    kMSR,                      //!< CPU has MSR              (RDMSR/WRMSR instructions).
+    kMSSE,                     //!< CPU has MSSE             (misaligned SSE support).
+    kOSXSAVE,                  //!< CPU has OSXSAVE          (XSAVE enabled by OS).
+    kOSPKE,                    //!< CPU has OSPKE            (PKE enabled by OS).
+    kPCLMULQDQ,                //!< CPU has PCLMULQDQ        (packed carry-less multiplication).
+    kPCONFIG,                  //!< CPU has PCONFIG          (PCONFIG instruction).
+    kPOPCNT,                   //!< CPU has POPCNT           (POPCNT instruction).
+    kPREFETCHW,                //!< CPU has PREFETCHW.
+    kPREFETCHWT1,              //!< CPU has PREFETCHWT1.
+    kPTWRITE,                  //!< CPU has PTWRITE.
+    kRDPID,                    //!< CPU has RDPID.
+    kRDPRU,                    //!< CPU has RDPRU.
+    kRDRAND,                   //!< CPU has RDRAND.
+    kRDSEED,                   //!< CPU has RDSEED.
+    kRDTSC,                    //!< CPU has RDTSC.
+    kRDTSCP,                   //!< CPU has RDTSCP.
+    kRTM,                      //!< CPU has RTM.
+    kSERIALIZE,                //!< CPU has SERIALIZE.
+    kSHA,                      //!< CPU has SHA              (SHA-1 and SHA-256 instructions).
+    kSKINIT,                   //!< CPU has SKINIT           (SKINIT/STGI instructions) [AMD].
+    kSMAP,                     //!< CPU has SMAP             (supervisor-mode access prevention).
+    kSMEP,                     //!< CPU has SMEP             (supervisor-mode execution prevention).
+    kSMX,                      //!< CPU has SMX              (safer mode extensions).
+    kSNP,                      //!< CPU has SNP.
+    kSSE,                      //!< CPU has SSE.
+    kSSE2,                     //!< CPU has SSE2.
+    kSSE3,                     //!< CPU has SSE3.
+    kSSE4_1,                   //!< CPU has SSE4.1.
+    kSSE4_2,                   //!< CPU has SSE4.2.
+    kSSE4A,                    //!< CPU has SSE4A [AMD].
+    kSSSE3,                    //!< CPU has SSSE3.
+    kSVM,                      //!< CPU has SVM              (virtualization) [AMD].
+    kTBM,                      //!< CPU has TBM              (trailing bit manipulation) [AMD].
+    kTSX,                      //!< CPU has TSX.
+    kTSXLDTRK,                 //!< CPU has TSXLDTRK.
+    kVAES,                     //!< CPU has VAES             (vector AES 256|512 bit support).
+    kVMX,                      //!< CPU has VMX              (virtualization) [INTEL].
+    kVPCLMULQDQ,               //!< CPU has VPCLMULQDQ       (vector PCLMULQDQ 256|512-bit support).
+    kWAITPKG,                  //!< CPU has WAITPKG          (UMONITOR, UMWAIT, TPAUSE).
+    kWBNOINVD,                 //!< CPU has WBNOINVD.
+    kXOP,                      //!< CPU has XOP              (XOP instructions) [AMD].
+    kXSAVE,                    //!< CPU has XSAVE.
+    kXSAVEC,                   //!< CPU has XSAVEC.
+    kXSAVEOPT,                 //!< CPU has XSAVEOPT.
+    kXSAVES,                   //!< CPU has XSAVES.
+
+    // @EnumValuesEnd@
+
+    kCount                     //!< Count of X86 CPU features.
+  };
+
+  //! \name Construction / Destruction
+  //! \{
+
+  inline Features() noexcept
+    : BaseFeatures() {}
+  inline Features(const Features& other) noexcept
+    : BaseFeatures(other) {}
+
+  //! \}
+
+  //! \name Overloaded Operators
+  //! \{
+
+  inline Features& operator=(const Features& other) noexcept = default;
+
+  //! \}
+
+  //! \name Accessors
+  //! \{
+
+  #define ASMJIT_X86_FEATURE(FEATURE) \
+    inline bool has##FEATURE() const noexcept { return has(k##FEATURE); }
+
+  ASMJIT_X86_FEATURE(MT)
+  ASMJIT_X86_FEATURE(NX)
+
+  ASMJIT_X86_FEATURE(3DNOW)
+  ASMJIT_X86_FEATURE(3DNOW2)
+  ASMJIT_X86_FEATURE(ADX)
+  ASMJIT_X86_FEATURE(AESNI)
+  ASMJIT_X86_FEATURE(ALTMOVCR8)
+  ASMJIT_X86_FEATURE(AMX_BF16)
+  ASMJIT_X86_FEATURE(AMX_INT8)
+  ASMJIT_X86_FEATURE(AMX_TILE)
+  ASMJIT_X86_FEATURE(AVX)
+  ASMJIT_X86_FEATURE(AVX2)
+  ASMJIT_X86_FEATURE(AVX512_4FMAPS)
+  ASMJIT_X86_FEATURE(AVX512_4VNNIW)
+  ASMJIT_X86_FEATURE(AVX512_BF16)
+  ASMJIT_X86_FEATURE(AVX512_BITALG)
+  ASMJIT_X86_FEATURE(AVX512_BW)
+  ASMJIT_X86_FEATURE(AVX512_CDI)
+  ASMJIT_X86_FEATURE(AVX512_DQ)
+  ASMJIT_X86_FEATURE(AVX512_ERI)
+  ASMJIT_X86_FEATURE(AVX512_F)
+  ASMJIT_X86_FEATURE(AVX512_IFMA)
+  ASMJIT_X86_FEATURE(AVX512_PFI)
+  ASMJIT_X86_FEATURE(AVX512_VBMI)
+  ASMJIT_X86_FEATURE(AVX512_VBMI2)
+  ASMJIT_X86_FEATURE(AVX512_VL)
+  ASMJIT_X86_FEATURE(AVX512_VNNI)
+  ASMJIT_X86_FEATURE(AVX512_VP2INTERSECT)
+  ASMJIT_X86_FEATURE(AVX512_VPOPCNTDQ)
+  ASMJIT_X86_FEATURE(BMI)
+  ASMJIT_X86_FEATURE(BMI2)
+  ASMJIT_X86_FEATURE(CLDEMOTE)
+  ASMJIT_X86_FEATURE(CLFLUSH)
+  ASMJIT_X86_FEATURE(CLFLUSHOPT)
+  ASMJIT_X86_FEATURE(CLWB)
+  ASMJIT_X86_FEATURE(CLZERO)
+  ASMJIT_X86_FEATURE(CMOV)
+  ASMJIT_X86_FEATURE(CMPXCHG16B)
+  ASMJIT_X86_FEATURE(CMPXCHG8B)
+  ASMJIT_X86_FEATURE(ENCLV)
+  ASMJIT_X86_FEATURE(ENQCMD)
+  ASMJIT_X86_FEATURE(ERMS)
+  ASMJIT_X86_FEATURE(F16C)
+  ASMJIT_X86_FEATURE(FMA)
+  ASMJIT_X86_FEATURE(FMA4)
+  ASMJIT_X86_FEATURE(FPU)
+  ASMJIT_X86_FEATURE(FSGSBASE)
+  ASMJIT_X86_FEATURE(FXSR)
+  ASMJIT_X86_FEATURE(FXSROPT)
+  ASMJIT_X86_FEATURE(GEODE)
+  ASMJIT_X86_FEATURE(GFNI)
+  ASMJIT_X86_FEATURE(HLE)
+  ASMJIT_X86_FEATURE(I486)
+  ASMJIT_X86_FEATURE(LAHFSAHF)
+  ASMJIT_X86_FEATURE(LWP)
+  ASMJIT_X86_FEATURE(LZCNT)
+  ASMJIT_X86_FEATURE(MCOMMIT)
+  ASMJIT_X86_FEATURE(MMX)
+  ASMJIT_X86_FEATURE(MMX2)
+  ASMJIT_X86_FEATURE(MONITOR)
+  ASMJIT_X86_FEATURE(MONITORX)
+  ASMJIT_X86_FEATURE(MOVBE)
+  ASMJIT_X86_FEATURE(MOVDIR64B)
+  ASMJIT_X86_FEATURE(MOVDIRI)
+  ASMJIT_X86_FEATURE(MPX)
+  ASMJIT_X86_FEATURE(MSR)
+  ASMJIT_X86_FEATURE(MSSE)
+  ASMJIT_X86_FEATURE(OSXSAVE)
+  ASMJIT_X86_FEATURE(PCLMULQDQ)
+  ASMJIT_X86_FEATURE(PCONFIG)
+  ASMJIT_X86_FEATURE(POPCNT)
+  ASMJIT_X86_FEATURE(PREFETCHW)
+  ASMJIT_X86_FEATURE(PREFETCHWT1)
+  ASMJIT_X86_FEATURE(PTWRITE)
+  ASMJIT_X86_FEATURE(RDPID)
+  ASMJIT_X86_FEATURE(RDPRU)
+  ASMJIT_X86_FEATURE(RDRAND)
+  ASMJIT_X86_FEATURE(RDSEED)
+  ASMJIT_X86_FEATURE(RDTSC)
+  ASMJIT_X86_FEATURE(RDTSCP)
+  ASMJIT_X86_FEATURE(RTM)
+  ASMJIT_X86_FEATURE(SERIALIZE)
+  ASMJIT_X86_FEATURE(SHA)
+  ASMJIT_X86_FEATURE(SKINIT)
+  ASMJIT_X86_FEATURE(SMAP)
+  ASMJIT_X86_FEATURE(SMEP)
+  ASMJIT_X86_FEATURE(SMX)
+  ASMJIT_X86_FEATURE(SNP)
+  ASMJIT_X86_FEATURE(SSE)
+  ASMJIT_X86_FEATURE(SSE2)
+  ASMJIT_X86_FEATURE(SSE3)
+  ASMJIT_X86_FEATURE(SSSE3)
+  ASMJIT_X86_FEATURE(SSE4A)
+  ASMJIT_X86_FEATURE(SSE4_1)
+  ASMJIT_X86_FEATURE(SSE4_2)
+  ASMJIT_X86_FEATURE(SVM)
+  ASMJIT_X86_FEATURE(TBM)
+  ASMJIT_X86_FEATURE(TSX)
+  ASMJIT_X86_FEATURE(TSXLDTRK)
+  ASMJIT_X86_FEATURE(XSAVE)
+  ASMJIT_X86_FEATURE(XSAVEC)
+  ASMJIT_X86_FEATURE(XSAVEOPT)
+  ASMJIT_X86_FEATURE(XSAVES)
+  ASMJIT_X86_FEATURE(VAES)
+  ASMJIT_X86_FEATURE(VMX)
+  ASMJIT_X86_FEATURE(VPCLMULQDQ)
+  ASMJIT_X86_FEATURE(WAITPKG)
+  ASMJIT_X86_FEATURE(WBNOINVD)
+  ASMJIT_X86_FEATURE(XOP)
+
+  #undef ASMJIT_X86_FEATURE
+
+  //! \}
+};
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86FEATURES_H_INCLUDED
diff --git a/client/asmjit/x86/x86formatter.cpp b/client/asmjit/x86/x86formatter.cpp
new file mode 100644
index 0000000..398a30c
--- /dev/null
+++ b/client/asmjit/x86/x86formatter.cpp
@@ -0,0 +1,924 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#include "../core/api-build_p.h"
+#ifndef ASMJIT_NO_LOGGING
+
+#include "../core/misc_p.h"
+#include "../core/support.h"
+#include "../x86/x86features.h"
+#include "../x86/x86formatter_p.h"
+#include "../x86/x86instdb_p.h"
+#include "../x86/x86operand.h"
+
+#ifndef ASMJIT_NO_COMPILER
+  #include "../core/compiler.h"
+#endif
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::x86::FormatterInternal - Constants]
+// ============================================================================
+
+struct RegFormatInfo {
+  struct TypeEntry {
+    uint8_t index;
+  };
+
+  struct NameEntry {
+    uint8_t count;
+    uint8_t formatIndex;
+    uint8_t specialIndex;
+    uint8_t specialCount;
+  };
+
+  TypeEntry typeEntries[BaseReg::kTypeMax + 1];
+  char typeStrings[128 - 32];
+
+  NameEntry nameEntries[BaseReg::kTypeMax + 1];
+  char nameStrings[280];
+};
+
+template<uint32_t X>
+struct RegFormatInfo_T {
+  enum {
+    kTypeIndex    = X == Reg::kTypeGpbLo ? 1   :
+                    X == Reg::kTypeGpbHi ? 8   :
+                    X == Reg::kTypeGpw   ? 15  :
+                    X == Reg::kTypeGpd   ? 19  :
+                    X == Reg::kTypeGpq   ? 23  :
+                    X == Reg::kTypeXmm   ? 27  :
+                    X == Reg::kTypeYmm   ? 31  :
+                    X == Reg::kTypeZmm   ? 35  :
+                    X == Reg::kTypeMm    ? 50  :
+                    X == Reg::kTypeKReg  ? 53  :
+                    X == Reg::kTypeSReg  ? 43  :
+                    X == Reg::kTypeCReg  ? 59  :
+                    X == Reg::kTypeDReg  ? 62  :
+                    X == Reg::kTypeSt    ? 47  :
+                    X == Reg::kTypeBnd   ? 55  :
+                    X == Reg::kTypeTmm   ? 65  :
+                    X == Reg::kTypeRip   ? 39  : 0,
+
+    kFormatIndex  = X == Reg::kTypeGpbLo ? 1   :
+                    X == Reg::kTypeGpbHi ? 6   :
+                    X == Reg::kTypeGpw   ? 11  :
+                    X == Reg::kTypeGpd   ? 16  :
+                    X == Reg::kTypeGpq   ? 21  :
+                    X == Reg::kTypeXmm   ? 25  :
+                    X == Reg::kTypeYmm   ? 31  :
+                    X == Reg::kTypeZmm   ? 37  :
+                    X == Reg::kTypeMm    ? 60  :
+                    X == Reg::kTypeKReg  ? 65  :
+                    X == Reg::kTypeSReg  ? 49  :
+                    X == Reg::kTypeCReg  ? 75  :
+                    X == Reg::kTypeDReg  ? 80  :
+                    X == Reg::kTypeSt    ? 55  :
+                    X == Reg::kTypeBnd   ? 69  :
+                    X == Reg::kTypeTmm   ? 89  :
+                    X == Reg::kTypeRip   ? 43  : 0,
+
+    kSpecialIndex = X == Reg::kTypeGpbLo ? 96  :
+                    X == Reg::kTypeGpbHi ? 128 :
+                    X == Reg::kTypeGpw   ? 161 :
+                    X == Reg::kTypeGpd   ? 160 :
+                    X == Reg::kTypeGpq   ? 192 :
+                    X == Reg::kTypeSReg  ? 224 :
+                    X == Reg::kTypeRip   ? 85  : 0,
+
+    kSpecialCount = X == Reg::kTypeGpbLo ? 8   :
+                    X == Reg::kTypeGpbHi ? 4   :
+                    X == Reg::kTypeGpw   ? 8   :
+                    X == Reg::kTypeGpd   ? 8   :
+                    X == Reg::kTypeGpq   ? 8   :
+                    X == Reg::kTypeSReg  ? 7   :
+                    X == Reg::kTypeRip   ? 1   : 0
+  };
+};
+
+#define ASMJIT_REG_TYPE_ENTRY(TYPE) {   \
+  RegFormatInfo_T<TYPE>::kTypeIndex     \
+}
+
+#define ASMJIT_REG_NAME_ENTRY(TYPE) {   \
+  RegTraits<TYPE>::kCount,              \
+  RegFormatInfo_T<TYPE>::kFormatIndex,  \
+  RegFormatInfo_T<TYPE>::kSpecialIndex, \
+  RegFormatInfo_T<TYPE>::kSpecialCount  \
+}
+
+static const RegFormatInfo x86RegFormatInfo = {
+  // Register type entries and strings.
+  { ASMJIT_LOOKUP_TABLE_32(ASMJIT_REG_TYPE_ENTRY, 0) },
+
+  "\0"             // #0
+  "gpb\0\0\0\0"    // #1
+  "gpb.hi\0"       // #8
+  "gpw\0"          // #15
+  "gpd\0"          // #19
+  "gpq\0"          // #23
+  "xmm\0"          // #27
+  "ymm\0"          // #31
+  "zmm\0"          // #35
+  "rip\0"          // #39
+  "seg\0"          // #43
+  "st\0"           // #47
+  "mm\0"           // #50
+  "k\0"            // #53
+  "bnd\0"          // #55
+  "cr\0"           // #59
+  "dr\0"           // #62
+  "tmm\0"          // #65
+  ,
+
+  // Register name entries and strings.
+  { ASMJIT_LOOKUP_TABLE_32(ASMJIT_REG_NAME_ENTRY, 0) },
+
+  "\0"
+  "r%ub\0"         // #1
+  "r%uh\0"         // #6
+  "r%uw\0"         // #11
+  "r%ud\0"         // #16
+  "r%u\0"          // #21
+  "xmm%u\0"        // #25
+  "ymm%u\0"        // #31
+  "zmm%u\0"        // #37
+  "rip%u\0"        // #43
+  "seg%u\0"        // #49
+  "st%u\0"         // #55
+  "mm%u\0"         // #60
+  "k%u\0"          // #65
+  "bnd%u\0"        // #69
+  "cr%u\0"         // #75
+  "dr%u\0"         // #80
+
+  "rip\0"          // #85
+  "tmm%u\0"        // #89
+  "\0"             // #95
+
+  "al\0\0" "cl\0\0" "dl\0\0" "bl\0\0" "spl\0"  "bpl\0"  "sil\0"  "dil\0" // #96
+  "ah\0\0" "ch\0\0" "dh\0\0" "bh\0\0" "n/a\0"  "n/a\0"  "n/a\0"  "n/a\0" // #128
+  "eax\0"  "ecx\0"  "edx\0"  "ebx\0"  "esp\0"  "ebp\0"  "esi\0"  "edi\0" // #160
+  "rax\0"  "rcx\0"  "rdx\0"  "rbx\0"  "rsp\0"  "rbp\0"  "rsi\0"  "rdi\0" // #192
+  "n/a\0"  "es\0\0" "cs\0\0" "ss\0\0" "ds\0\0" "fs\0\0" "gs\0\0" "n/a\0" // #224
+};
+#undef ASMJIT_REG_NAME_ENTRY
+#undef ASMJIT_REG_TYPE_ENTRY
+
+static const char* x86GetAddressSizeString(uint32_t size) noexcept {
+  switch (size) {
+    case 1 : return "byte ";
+    case 2 : return "word ";
+    case 4 : return "dword ";
+    case 6 : return "fword ";
+    case 8 : return "qword ";
+    case 10: return "tword ";
+    case 16: return "oword ";
+    case 32: return "yword ";
+    case 64: return "zword ";
+    default: return "";
+  }
+}
+
+// ============================================================================
+// [asmjit::x86::FormatterInternal - Format Feature]
+// ============================================================================
+
+Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept {
+  // @EnumStringBegin{"enum": "x86::Features::Id", "output": "sFeature", "strip": "k"}@
+  static const char sFeatureString[] =
+    "None\0"
+    "MT\0"
+    "NX\0"
+    "3DNOW\0"
+    "3DNOW2\0"
+    "ADX\0"
+    "AESNI\0"
+    "ALTMOVCR8\0"
+    "AMX_BF16\0"
+    "AMX_INT8\0"
+    "AMX_TILE\0"
+    "AVX\0"
+    "AVX2\0"
+    "AVX512_4FMAPS\0"
+    "AVX512_4VNNIW\0"
+    "AVX512_BF16\0"
+    "AVX512_BITALG\0"
+    "AVX512_BW\0"
+    "AVX512_CDI\0"
+    "AVX512_DQ\0"
+    "AVX512_ERI\0"
+    "AVX512_F\0"
+    "AVX512_IFMA\0"
+    "AVX512_PFI\0"
+    "AVX512_VBMI\0"
+    "AVX512_VBMI2\0"
+    "AVX512_VL\0"
+    "AVX512_VNNI\0"
+    "AVX512_VP2INTERSECT\0"
+    "AVX512_VPOPCNTDQ\0"
+    "BMI\0"
+    "BMI2\0"
+    "CET_IBT\0"
+    "CET_SS\0"
+    "CLDEMOTE\0"
+    "CLFLUSH\0"
+    "CLFLUSHOPT\0"
+    "CLWB\0"
+    "CLZERO\0"
+    "CMOV\0"
+    "CMPXCHG16B\0"
+    "CMPXCHG8B\0"
+    "ENCLV\0"
+    "ENQCMD\0"
+    "ERMS\0"
+    "F16C\0"
+    "FMA\0"
+    "FMA4\0"
+    "FPU\0"
+    "FSGSBASE\0"
+    "FXSR\0"
+    "FXSROPT\0"
+    "GEODE\0"
+    "GFNI\0"
+    "HLE\0"
+    "I486\0"
+    "LAHFSAHF\0"
+    "LWP\0"
+    "LZCNT\0"
+    "MCOMMIT\0"
+    "MMX\0"
+    "MMX2\0"
+    "MONITOR\0"
+    "MONITORX\0"
+    "MOVBE\0"
+    "MOVDIR64B\0"
+    "MOVDIRI\0"
+    "MPX\0"
+    "MSR\0"
+    "MSSE\0"
+    "OSXSAVE\0"
+    "OSPKE\0"
+    "PCLMULQDQ\0"
+    "PCONFIG\0"
+    "POPCNT\0"
+    "PREFETCHW\0"
+    "PREFETCHWT1\0"
+    "PTWRITE\0"
+    "RDPID\0"
+    "RDPRU\0"
+    "RDRAND\0"
+    "RDSEED\0"
+    "RDTSC\0"
+    "RDTSCP\0"
+    "RTM\0"
+    "SERIALIZE\0"
+    "SHA\0"
+    "SKINIT\0"
+    "SMAP\0"
+    "SMEP\0"
+    "SMX\0"
+    "SNP\0"
+    "SSE\0"
+    "SSE2\0"
+    "SSE3\0"
+    "SSE4_1\0"
+    "SSE4_2\0"
+    "SSE4A\0"
+    "SSSE3\0"
+    "SVM\0"
+    "TBM\0"
+    "TSX\0"
+    "TSXLDTRK\0"
+    "VAES\0"
+    "VMX\0"
+    "VPCLMULQDQ\0"
+    "WAITPKG\0"
+    "WBNOINVD\0"
+    "XOP\0"
+    "XSAVE\0"
+    "XSAVEC\0"
+    "XSAVEOPT\0"
+    "XSAVES\0"
+    "<Unknown>\0";
+
+  static const uint16_t sFeatureIndex[] = {
+    0, 5, 8, 11, 17, 24, 28, 34, 44, 53, 62, 71, 75, 80, 94, 108, 120, 134, 144,
+    155, 165, 176, 185, 197, 208, 220, 233, 243, 255, 275, 292, 296, 301, 309,
+    316, 325, 333, 344, 349, 356, 361, 372, 382, 388, 395, 400, 405, 409, 414,
+    418, 427, 432, 440, 446, 451, 455, 460, 469, 473, 479, 487, 491, 496, 504,
+    513, 519, 529, 537, 541, 545, 550, 558, 564, 574, 582, 589, 599, 611, 619,
+    625, 631, 638, 645, 651, 658, 662, 672, 676, 683, 688, 693, 697, 701, 705,
+    710, 715, 722, 729, 735, 741, 745, 749, 753, 762, 767, 771, 782, 790, 799,
+    803, 809, 816, 825, 832
+  };
+  // @EnumStringEnd@
+
+  return sb.append(sFeatureString + sFeatureIndex[Support::min<uint32_t>(featureId, x86::Features::kCount)]);
+}
+
+// ============================================================================
+// [asmjit::x86::FormatterInternal - Format Operand]
+// ============================================================================
+
+ASMJIT_FAVOR_SIZE Error FormatterInternal::formatOperand(
+  String& sb,
+  uint32_t flags,
+  const BaseEmitter* emitter,
+  uint32_t arch,
+  const Operand_& op) noexcept {
+
+  if (op.isReg())
+    return formatRegister(sb, flags, emitter, arch, op.as<BaseReg>().type(), op.as<BaseReg>().id());
+
+  if (op.isMem()) {
+    const Mem& m = op.as<Mem>();
+    ASMJIT_PROPAGATE(sb.append(x86GetAddressSizeString(m.size())));
+
+    // Segment override prefix.
+    uint32_t seg = m.segmentId();
+    if (seg != SReg::kIdNone && seg < SReg::kIdCount)
+      ASMJIT_PROPAGATE(sb.appendFormat("%s:", x86RegFormatInfo.nameStrings + 224 + size_t(seg) * 4));
+
+    ASMJIT_PROPAGATE(sb.append('['));
+    switch (m.addrType()) {
+      case BaseMem::kAddrTypeAbs: ASMJIT_PROPAGATE(sb.append("abs ")); break;
+      case BaseMem::kAddrTypeRel: ASMJIT_PROPAGATE(sb.append("rel ")); break;
+    }
+
+    char opSign = '\0';
+    if (m.hasBase()) {
+      opSign = '+';
+      if (m.hasBaseLabel()) {
+        ASMJIT_PROPAGATE(Formatter::formatLabel(sb, flags, emitter, m.baseId()));
+      }
+      else {
+        uint32_t modifiedFlags = flags;
+        if (m.isRegHome()) {
+          ASMJIT_PROPAGATE(sb.append("&"));
+          modifiedFlags &= ~FormatOptions::kFlagRegCasts;
+        }
+        ASMJIT_PROPAGATE(formatRegister(sb, modifiedFlags, emitter, arch, m.baseType(), m.baseId()));
+      }
+    }
+
+    if (m.hasIndex()) {
+      if (opSign)
+        ASMJIT_PROPAGATE(sb.append(opSign));
+
+      opSign = '+';
+      ASMJIT_PROPAGATE(formatRegister(sb, flags, emitter, arch, m.indexType(), m.indexId()));
+      if (m.hasShift())
+        ASMJIT_PROPAGATE(sb.appendFormat("*%u", 1 << m.shift()));
+    }
+
+    uint64_t off = uint64_t(m.offset());
+    if (off || !m.hasBaseOrIndex()) {
+      if (int64_t(off) < 0) {
+        opSign = '-';
+        off = ~off + 1;
+      }
+
+      if (opSign)
+        ASMJIT_PROPAGATE(sb.append(opSign));
+
+      uint32_t base = 10;
+      if ((flags & FormatOptions::kFlagHexOffsets) != 0 && off > 9) {
+        ASMJIT_PROPAGATE(sb.append("0x", 2));
+        base = 16;
+      }
+
+      ASMJIT_PROPAGATE(sb.appendUInt(off, base));
+    }
+
+    return sb.append(']');
+  }
+
+  if (op.isImm()) {
+    const Imm& i = op.as<Imm>();
+    int64_t val = i.value();
+
+    if ((flags & FormatOptions::kFlagHexImms) != 0 && uint64_t(val) > 9) {
+      ASMJIT_PROPAGATE(sb.append("0x", 2));
+      return sb.appendUInt(uint64_t(val), 16);
+    }
+    else {
+      return sb.appendInt(val, 10);
+    }
+  }
+
+  if (op.isLabel()) {
+    return Formatter::formatLabel(sb, flags, emitter, op.id());
+  }
+
+  return sb.append("<None>");
+}
+
+// ============================================================================
+// [asmjit::x86::FormatterInternal - Format Immediate (Extension)]
+// ============================================================================
+
+static constexpr char kImmCharStart = '{';
+static constexpr char kImmCharEnd   = '}';
+static constexpr char kImmCharOr    = '|';
+
+struct ImmBits {
+  enum Mode : uint32_t {
+    kModeLookup = 0,
+    kModeFormat = 1
+  };
+
+  uint8_t mask;
+  uint8_t shift;
+  uint8_t mode;
+  char text[48 - 3];
+};
+
+ASMJIT_FAVOR_SIZE static Error FormatterInternal_formatImmShuf(String& sb, uint32_t u8, uint32_t bits, uint32_t count) noexcept {
+  uint32_t mask = (1 << bits) - 1;
+
+  for (uint32_t i = 0; i < count; i++, u8 >>= bits) {
+    uint32_t value = u8 & mask;
+    ASMJIT_PROPAGATE(sb.append(i == 0 ? kImmCharStart : kImmCharOr));
+    ASMJIT_PROPAGATE(sb.appendUInt(value));
+  }
+
+  if (kImmCharEnd)
+    ASMJIT_PROPAGATE(sb.append(kImmCharEnd));
+
+  return kErrorOk;
+}
+
+ASMJIT_FAVOR_SIZE static Error FormatterInternal_formatImmBits(String& sb, uint32_t u8, const ImmBits* bits, uint32_t count) noexcept {
+  uint32_t n = 0;
+  char buf[64];
+
+  for (uint32_t i = 0; i < count; i++) {
+    const ImmBits& spec = bits[i];
+
+    uint32_t value = (u8 & uint32_t(spec.mask)) >> spec.shift;
+    const char* str = nullptr;
+
+    switch (spec.mode) {
+      case ImmBits::kModeLookup:
+        str = Support::findPackedString(spec.text, value);
+        break;
+
+      case ImmBits::kModeFormat:
+        snprintf(buf, sizeof(buf), spec.text, unsigned(value));
+        str = buf;
+        break;
+
+      default:
+        return DebugUtils::errored(kErrorInvalidState);
+    }
+
+    if (!str[0])
+      continue;
+
+    ASMJIT_PROPAGATE(sb.append(++n == 1 ? kImmCharStart : kImmCharOr));
+    ASMJIT_PROPAGATE(sb.append(str));
+  }
+
+  if (n && kImmCharEnd)
+    ASMJIT_PROPAGATE(sb.append(kImmCharEnd));
+
+  return kErrorOk;
+}
+
+ASMJIT_FAVOR_SIZE static Error FormatterInternal_formatImmText(String& sb, uint32_t u8, uint32_t bits, uint32_t advance, const char* text, uint32_t count = 1) noexcept {
+  uint32_t mask = (1u << bits) - 1;
+  uint32_t pos = 0;
+
+  for (uint32_t i = 0; i < count; i++, u8 >>= bits, pos += advance) {
+    uint32_t value = (u8 & mask) + pos;
+    ASMJIT_PROPAGATE(sb.append(i == 0 ? kImmCharStart : kImmCharOr));
+    ASMJIT_PROPAGATE(sb.append(Support::findPackedString(text, value)));
+  }
+
+  if (kImmCharEnd)
+    ASMJIT_PROPAGATE(sb.append(kImmCharEnd));
+
+  return kErrorOk;
+}
+
+ASMJIT_FAVOR_SIZE static Error FormatterInternal_explainConst(
+  String& sb,
+  uint32_t flags,
+  uint32_t instId,
+  uint32_t vecSize,
+  const Imm& imm) noexcept {
+
+  DebugUtils::unused(flags);
+
+  static const char vcmpx[] =
+    "EQ_OQ\0" "LT_OS\0"  "LE_OS\0"  "UNORD_Q\0"  "NEQ_UQ\0" "NLT_US\0" "NLE_US\0" "ORD_Q\0"
+    "EQ_UQ\0" "NGE_US\0" "NGT_US\0" "FALSE_OQ\0" "NEQ_OQ\0" "GE_OS\0"  "GT_OS\0"  "TRUE_UQ\0"
+    "EQ_OS\0" "LT_OQ\0"  "LE_OQ\0"  "UNORD_S\0"  "NEQ_US\0" "NLT_UQ\0" "NLE_UQ\0" "ORD_S\0"
+    "EQ_US\0" "NGE_UQ\0" "NGT_UQ\0" "FALSE_OS\0" "NEQ_OS\0" "GE_OQ\0"  "GT_OQ\0"  "TRUE_US\0";
+
+  // Why to make it compatible...
+  static const char vpcmpx[] = "EQ\0" "LT\0" "LE\0" "FALSE\0" "NEQ\0" "GE\0"  "GT\0"    "TRUE\0";
+  static const char vpcomx[] = "LT\0" "LE\0" "GT\0" "GE\0"    "EQ\0"  "NEQ\0" "FALSE\0" "TRUE\0";
+
+  static const char vshufpd[] = "A0\0A1\0B0\0B1\0A2\0A3\0B2\0B3\0A4\0A5\0B4\0B5\0A6\0A7\0B6\0B7\0";
+  static const char vshufps[] = "A0\0A1\0A2\0A3\0A0\0A1\0A2\0A3\0B0\0B1\0B2\0B3\0B0\0B1\0B2\0B3\0";
+
+  static const ImmBits vfpclassxx[] = {
+    { 0x07u, 0, ImmBits::kModeLookup, "QNAN\0" "+0\0" "-0\0" "+INF\0" "-INF\0" "DENORMAL\0" "-FINITE\0" "SNAN\0" }
+  };
+
+  static const ImmBits vfixupimmxx[] = {
+    { 0x01u, 0, ImmBits::kModeLookup, "\0" "+INF_IE\0" },
+    { 0x02u, 1, ImmBits::kModeLookup, "\0" "-VE_IE\0"  },
+    { 0x04u, 2, ImmBits::kModeLookup, "\0" "-INF_IE\0" },
+    { 0x08u, 3, ImmBits::kModeLookup, "\0" "SNAN_IE\0" },
+    { 0x10u, 4, ImmBits::kModeLookup, "\0" "ONE_IE\0"  },
+    { 0x20u, 5, ImmBits::kModeLookup, "\0" "ONE_ZE\0"  },
+    { 0x40u, 6, ImmBits::kModeLookup, "\0" "ZERO_IE\0" },
+    { 0x80u, 7, ImmBits::kModeLookup, "\0" "ZERO_ZE\0" }
+  };
+
+  static const ImmBits vgetmantxx[] = {
+    { 0x03u, 0, ImmBits::kModeLookup, "[1, 2)\0" "[.5, 2)\0" "[.5, 1)\0" "[.75, 1.5)\0" },
+    { 0x04u, 2, ImmBits::kModeLookup, "\0" "NO_SIGN\0" },
+    { 0x08u, 3, ImmBits::kModeLookup, "\0" "QNAN_IF_SIGN\0" }
+  };
+
+  static const ImmBits vmpsadbw[] = {
+    { 0x04u, 2, ImmBits::kModeLookup, "BLK1[0]\0" "BLK1[1]\0" },
+    { 0x03u, 0, ImmBits::kModeLookup, "BLK2[0]\0" "BLK2[1]\0" "BLK2[2]\0" "BLK2[3]\0" },
+    { 0x40u, 6, ImmBits::kModeLookup, "BLK1[4]\0" "BLK1[5]\0" },
+    { 0x30u, 4, ImmBits::kModeLookup, "BLK2[4]\0" "BLK2[5]\0" "BLK2[6]\0" "BLK2[7]\0" }
+  };
+
+  static const ImmBits vpclmulqdq[] = {
+    { 0x01u, 0, ImmBits::kModeLookup, "LQ\0" "HQ\0" },
+    { 0x10u, 4, ImmBits::kModeLookup, "LQ\0" "HQ\0" }
+  };
+
+  static const ImmBits vperm2x128[] = {
+    { 0x0Bu, 0, ImmBits::kModeLookup, "A0\0" "A1\0" "B0\0" "B1\0" "\0" "\0" "\0" "\0" "0\0" "0\0" "0\0" "0\0" },
+    { 0xB0u, 4, ImmBits::kModeLookup, "A0\0" "A1\0" "B0\0" "B1\0" "\0" "\0" "\0" "\0" "0\0" "0\0" "0\0" "0\0" }
+  };
+
+  static const ImmBits vrangexx[] = {
+    { 0x03u, 0, ImmBits::kModeLookup, "MIN\0" "MAX\0" "MIN_ABS\0" "MAX_ABS\0" },
+    { 0x0Cu, 2, ImmBits::kModeLookup, "SIGN_A\0" "SIGN_B\0" "SIGN_0\0" "SIGN_1\0" }
+  };
+
+  static const ImmBits vreducexx_vrndscalexx[] = {
+    { 0x07u, 0, ImmBits::kModeLookup, "\0" "\0" "\0" "\0" "ROUND\0" "FLOOR\0" "CEIL\0" "TRUNC\0" },
+    { 0x08u, 3, ImmBits::kModeLookup, "\0" "SAE\0" },
+    { 0xF0u, 4, ImmBits::kModeFormat, "LEN=%d" }
+  };
+
+  static const ImmBits vroundxx[] = {
+    { 0x07u, 0, ImmBits::kModeLookup, "ROUND\0" "FLOOR\0" "CEIL\0" "TRUNC\0" "\0" "\0" "\0" "\0" },
+    { 0x08u, 3, ImmBits::kModeLookup, "\0" "INEXACT\0" }
+  };
+
+  uint32_t u8 = imm.valueAs<uint8_t>();
+  switch (instId) {
+    case Inst::kIdVblendpd:
+    case Inst::kIdBlendpd:
+      return FormatterInternal_formatImmShuf(sb, u8, 1, vecSize / 8);
+
+    case Inst::kIdVblendps:
+    case Inst::kIdBlendps:
+      return FormatterInternal_formatImmShuf(sb, u8, 1, vecSize / 4);
+
+    case Inst::kIdVcmppd:
+    case Inst::kIdVcmpps:
+    case Inst::kIdVcmpsd:
+    case Inst::kIdVcmpss:
+      return FormatterInternal_formatImmText(sb, u8, 5, 0, vcmpx);
+
+    case Inst::kIdCmppd:
+    case Inst::kIdCmpps:
+    case Inst::kIdCmpsd:
+    case Inst::kIdCmpss:
+      return FormatterInternal_formatImmText(sb, u8, 3, 0, vcmpx);
+
+    case Inst::kIdVdbpsadbw:
+      return FormatterInternal_formatImmShuf(sb, u8, 2, 4);
+
+    case Inst::kIdVdppd:
+    case Inst::kIdVdpps:
+    case Inst::kIdDppd:
+    case Inst::kIdDpps:
+      return FormatterInternal_formatImmShuf(sb, u8, 1, 8);
+
+    case Inst::kIdVmpsadbw:
+    case Inst::kIdMpsadbw:
+      return FormatterInternal_formatImmBits(sb, u8, vmpsadbw, Support::min<uint32_t>(vecSize / 8, 4));
+
+    case Inst::kIdVpblendw:
+    case Inst::kIdPblendw:
+      return FormatterInternal_formatImmShuf(sb, u8, 1, 8);
+
+    case Inst::kIdVpblendd:
+      return FormatterInternal_formatImmShuf(sb, u8, 1, Support::min<uint32_t>(vecSize / 4, 8));
+
+    case Inst::kIdVpclmulqdq:
+    case Inst::kIdPclmulqdq:
+      return FormatterInternal_formatImmBits(sb, u8, vpclmulqdq, ASMJIT_ARRAY_SIZE(vpclmulqdq));
+
+    case Inst::kIdVroundpd:
+    case Inst::kIdVroundps:
+    case Inst::kIdVroundsd:
+    case Inst::kIdVroundss:
+    case Inst::kIdRoundpd:
+    case Inst::kIdRoundps:
+    case Inst::kIdRoundsd:
+    case Inst::kIdRoundss:
+      return FormatterInternal_formatImmBits(sb, u8, vroundxx, ASMJIT_ARRAY_SIZE(vroundxx));
+
+    case Inst::kIdVshufpd:
+    case Inst::kIdShufpd:
+      return FormatterInternal_formatImmText(sb, u8, 1, 2, vshufpd, Support::min<uint32_t>(vecSize / 8, 8));
+
+    case Inst::kIdVshufps:
+    case Inst::kIdShufps:
+      return FormatterInternal_formatImmText(sb, u8, 2, 4, vshufps, 4);
+
+    case Inst::kIdVcvtps2ph:
+      return FormatterInternal_formatImmBits(sb, u8, vroundxx, 1);
+
+    case Inst::kIdVperm2f128:
+    case Inst::kIdVperm2i128:
+      return FormatterInternal_formatImmBits(sb, u8, vperm2x128, ASMJIT_ARRAY_SIZE(vperm2x128));
+
+    case Inst::kIdVpermilpd:
+      return FormatterInternal_formatImmShuf(sb, u8, 1, vecSize / 8);
+
+    case Inst::kIdVpermilps:
+      return FormatterInternal_formatImmShuf(sb, u8, 2, 4);
+
+    case Inst::kIdVpshufd:
+    case Inst::kIdPshufd:
+      return FormatterInternal_formatImmShuf(sb, u8, 2, 4);
+
+    case Inst::kIdVpshufhw:
+    case Inst::kIdVpshuflw:
+    case Inst::kIdPshufhw:
+    case Inst::kIdPshuflw:
+    case Inst::kIdPshufw:
+      return FormatterInternal_formatImmShuf(sb, u8, 2, 4);
+
+    case Inst::kIdVfixupimmpd:
+    case Inst::kIdVfixupimmps:
+    case Inst::kIdVfixupimmsd:
+    case Inst::kIdVfixupimmss:
+      return FormatterInternal_formatImmBits(sb, u8, vfixupimmxx, ASMJIT_ARRAY_SIZE(vfixupimmxx));
+
+    case Inst::kIdVfpclasspd:
+    case Inst::kIdVfpclassps:
+    case Inst::kIdVfpclasssd:
+    case Inst::kIdVfpclassss:
+      return FormatterInternal_formatImmBits(sb, u8, vfpclassxx, ASMJIT_ARRAY_SIZE(vfpclassxx));
+
+    case Inst::kIdVgetmantpd:
+    case Inst::kIdVgetmantps:
+    case Inst::kIdVgetmantsd:
+    case Inst::kIdVgetmantss:
+      return FormatterInternal_formatImmBits(sb, u8, vgetmantxx, ASMJIT_ARRAY_SIZE(vgetmantxx));
+
+    case Inst::kIdVpcmpb:
+    case Inst::kIdVpcmpd:
+    case Inst::kIdVpcmpq:
+    case Inst::kIdVpcmpw:
+    case Inst::kIdVpcmpub:
+    case Inst::kIdVpcmpud:
+    case Inst::kIdVpcmpuq:
+    case Inst::kIdVpcmpuw:
+      return FormatterInternal_formatImmText(sb, u8, 3, 0, vpcmpx);
+
+    case Inst::kIdVpcomb:
+    case Inst::kIdVpcomd:
+    case Inst::kIdVpcomq:
+    case Inst::kIdVpcomw:
+    case Inst::kIdVpcomub:
+    case Inst::kIdVpcomud:
+    case Inst::kIdVpcomuq:
+    case Inst::kIdVpcomuw:
+      return FormatterInternal_formatImmText(sb, u8, 3, 0, vpcomx);
+
+    case Inst::kIdVpermq:
+    case Inst::kIdVpermpd:
+      return FormatterInternal_formatImmShuf(sb, u8, 2, 4);
+
+    case Inst::kIdVpternlogd:
+    case Inst::kIdVpternlogq:
+      return FormatterInternal_formatImmShuf(sb, u8, 1, 8);
+
+    case Inst::kIdVrangepd:
+    case Inst::kIdVrangeps:
+    case Inst::kIdVrangesd:
+    case Inst::kIdVrangess:
+      return FormatterInternal_formatImmBits(sb, u8, vrangexx, ASMJIT_ARRAY_SIZE(vrangexx));
+
+    case Inst::kIdVreducepd:
+    case Inst::kIdVreduceps:
+    case Inst::kIdVreducesd:
+    case Inst::kIdVreducess:
+    case Inst::kIdVrndscalepd:
+    case Inst::kIdVrndscaleps:
+    case Inst::kIdVrndscalesd:
+    case Inst::kIdVrndscaless:
+      return FormatterInternal_formatImmBits(sb, u8, vreducexx_vrndscalexx, ASMJIT_ARRAY_SIZE(vreducexx_vrndscalexx));
+
+    case Inst::kIdVshuff32x4:
+    case Inst::kIdVshuff64x2:
+    case Inst::kIdVshufi32x4:
+    case Inst::kIdVshufi64x2: {
+      uint32_t count = Support::max<uint32_t>(vecSize / 16, 2u);
+      uint32_t bits = count <= 2 ? 1u : 2u;
+      return FormatterInternal_formatImmShuf(sb, u8, bits, count);
+    }
+
+    default:
+      return kErrorOk;
+  }
+}
+
+// ============================================================================
+// [asmjit::x86::FormatterInternal - Format Register]
+// ============================================================================
+
+ASMJIT_FAVOR_SIZE Error FormatterInternal::formatRegister(String& sb, uint32_t flags, const BaseEmitter* emitter, uint32_t arch, uint32_t rType, uint32_t rId) noexcept {
+  DebugUtils::unused(arch);
+  const RegFormatInfo& info = x86RegFormatInfo;
+
+#ifndef ASMJIT_NO_COMPILER
+  if (Operand::isVirtId(rId)) {
+    if (emitter && emitter->emitterType() == BaseEmitter::kTypeCompiler) {
+      const BaseCompiler* cc = static_cast<const BaseCompiler*>(emitter);
+      if (cc->isVirtIdValid(rId)) {
+        VirtReg* vReg = cc->virtRegById(rId);
+        ASMJIT_ASSERT(vReg != nullptr);
+
+        const char* name = vReg->name();
+        if (name && name[0] != '\0')
+          ASMJIT_PROPAGATE(sb.append(name));
+        else
+          ASMJIT_PROPAGATE(sb.appendFormat("%%%u", unsigned(Operand::virtIdToIndex(rId))));
+
+        if (vReg->type() != rType && rType <= BaseReg::kTypeMax && (flags & FormatOptions::kFlagRegCasts) != 0) {
+          const RegFormatInfo::TypeEntry& typeEntry = info.typeEntries[rType];
+          if (typeEntry.index)
+            ASMJIT_PROPAGATE(sb.appendFormat("@%s", info.typeStrings + typeEntry.index));
+        }
+
+        return kErrorOk;
+      }
+    }
+  }
+#else
+  DebugUtils::unused(emitter, flags);
+#endif
+
+  if (ASMJIT_LIKELY(rType <= BaseReg::kTypeMax)) {
+    const RegFormatInfo::NameEntry& nameEntry = info.nameEntries[rType];
+
+    if (rId < nameEntry.specialCount)
+      return sb.append(info.nameStrings + nameEntry.specialIndex + rId * 4);
+
+    if (rId < nameEntry.count)
+      return sb.appendFormat(info.nameStrings + nameEntry.formatIndex, unsigned(rId));
+
+    const RegFormatInfo::TypeEntry& typeEntry = info.typeEntries[rType];
+    if (typeEntry.index)
+      return sb.appendFormat("%s@%u", info.typeStrings + typeEntry.index, rId);
+  }
+
+  return sb.appendFormat("Reg?%u@%u", rType, rId);
+}
+
+// ============================================================================
+// [asmjit::x86::FormatterInternal - Format Instruction]
+// ============================================================================
+
+ASMJIT_FAVOR_SIZE Error FormatterInternal::formatInstruction(
+  String& sb,
+  uint32_t flags,
+  const BaseEmitter* emitter,
+  uint32_t arch,
+  const BaseInst& inst, const Operand_* operands, size_t opCount) noexcept {
+
+  uint32_t instId = inst.id();
+  uint32_t options = inst.options();
+
+  // Format instruction options and instruction mnemonic.
+  if (instId < Inst::_kIdCount) {
+    // SHORT|LONG options.
+    if (options & Inst::kOptionShortForm) ASMJIT_PROPAGATE(sb.append("short "));
+    if (options & Inst::kOptionLongForm) ASMJIT_PROPAGATE(sb.append("long "));
+
+    // LOCK|XACQUIRE|XRELEASE options.
+    if (options & Inst::kOptionXAcquire) ASMJIT_PROPAGATE(sb.append("xacquire "));
+    if (options & Inst::kOptionXRelease) ASMJIT_PROPAGATE(sb.append("xrelease "));
+    if (options & Inst::kOptionLock) ASMJIT_PROPAGATE(sb.append("lock "));
+
+    // REP|REPNE options.
+    if (options & (Inst::kOptionRep | Inst::kOptionRepne)) {
+      sb.append((options & Inst::kOptionRep) ? "rep " : "repnz ");
+      if (inst.hasExtraReg()) {
+        ASMJIT_PROPAGATE(sb.append("{"));
+        ASMJIT_PROPAGATE(formatOperand(sb, flags, emitter, arch, inst.extraReg().toReg<BaseReg>()));
+        ASMJIT_PROPAGATE(sb.append("} "));
+      }
+    }
+
+    // REX options.
+    if (options & Inst::kOptionRex) {
+      const uint32_t kRXBWMask = Inst::kOptionOpCodeR |
+                                 Inst::kOptionOpCodeX |
+                                 Inst::kOptionOpCodeB |
+                                 Inst::kOptionOpCodeW ;
+      if (options & kRXBWMask) {
+        sb.append("rex.");
+        if (options & Inst::kOptionOpCodeR) sb.append('r');
+        if (options & Inst::kOptionOpCodeX) sb.append('x');
+        if (options & Inst::kOptionOpCodeB) sb.append('b');
+        if (options & Inst::kOptionOpCodeW) sb.append('w');
+        sb.append(' ');
+      }
+      else {
+        ASMJIT_PROPAGATE(sb.append("rex "));
+      }
+    }
+
+    // VEX|EVEX options.
+    if (options & Inst::kOptionVex3) ASMJIT_PROPAGATE(sb.append("vex3 "));
+    if (options & Inst::kOptionEvex) ASMJIT_PROPAGATE(sb.append("evex "));
+
+    ASMJIT_PROPAGATE(InstAPI::instIdToString(arch, instId, sb));
+  }
+  else {
+    ASMJIT_PROPAGATE(sb.appendFormat("[InstId=#%u]", unsigned(instId)));
+  }
+
+  for (uint32_t i = 0; i < opCount; i++) {
+    const Operand_& op = operands[i];
+    if (op.isNone()) break;
+
+    ASMJIT_PROPAGATE(sb.append(i == 0 ? " " : ", "));
+    ASMJIT_PROPAGATE(formatOperand(sb, flags, emitter, arch, op));
+
+    if (op.isImm() && (flags & FormatOptions::kFlagExplainImms)) {
+      uint32_t vecSize = 16;
+      for (uint32_t j = 0; j < opCount; j++)
+        if (operands[j].isReg())
+          vecSize = Support::max<uint32_t>(vecSize, operands[j].size());
+      ASMJIT_PROPAGATE(FormatterInternal_explainConst(sb, flags, instId, vecSize, op.as<Imm>()));
+    }
+
+    // Support AVX-512 masking - {k}{z}.
+    if (i == 0) {
+      if (inst.extraReg().group() == Reg::kGroupKReg) {
+        ASMJIT_PROPAGATE(sb.append(" {"));
+        ASMJIT_PROPAGATE(formatRegister(sb, flags, emitter, arch, inst.extraReg().type(), inst.extraReg().id()));
+        ASMJIT_PROPAGATE(sb.append('}'));
+
+        if (options & Inst::kOptionZMask)
+          ASMJIT_PROPAGATE(sb.append("{z}"));
+      }
+      else if (options & Inst::kOptionZMask) {
+        ASMJIT_PROPAGATE(sb.append(" {z}"));
+      }
+    }
+
+    // Support AVX-512 broadcast - {1tox}.
+    if (op.isMem() && op.as<Mem>().hasBroadcast()) {
+      ASMJIT_PROPAGATE(sb.appendFormat(" {1to%u}", Support::bitMask(op.as<Mem>().getBroadcast())));
+    }
+  }
+
+  return kErrorOk;
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_LOGGING
diff --git a/client/asmjit/x86/x86formatter_p.h b/client/asmjit/x86/x86formatter_p.h
new file mode 100644
index 0000000..d7d58e4
--- /dev/null
+++ b/client/asmjit/x86/x86formatter_p.h
@@ -0,0 +1,80 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86FORMATTER_P_H_INCLUDED
+#define ASMJIT_X86_X86FORMATTER_P_H_INCLUDED
+
+#include "../core/api-config.h"
+#ifndef ASMJIT_NO_LOGGING
+
+#include "../core/formatter.h"
+#include "../core/string.h"
+#include "../x86/x86globals.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::x86::FormatterInternal]
+// ============================================================================
+
+namespace FormatterInternal {
+
+Error formatFeature(
+  String& sb,
+  uint32_t featureId) noexcept;
+
+Error formatRegister(
+  String& sb,
+  uint32_t flags,
+  const BaseEmitter* emitter,
+  uint32_t arch,
+  uint32_t regType,
+  uint32_t regId) noexcept;
+
+Error formatOperand(
+  String& sb,
+  uint32_t flags,
+  const BaseEmitter* emitter,
+  uint32_t arch,
+  const Operand_& op) noexcept;
+
+Error formatInstruction(
+  String& sb,
+  uint32_t flags,
+  const BaseEmitter* emitter,
+  uint32_t arch,
+  const BaseInst& inst, const Operand_* operands, size_t opCount) noexcept;
+
+} // {FormatterInternal}
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_LOGGING
+#endif // ASMJIT_X86_X86FORMATTER_P_H_INCLUDED
diff --git a/client/asmjit/x86/x86globals.h b/client/asmjit/x86/x86globals.h
new file mode 100644
index 0000000..4e11565
--- /dev/null
+++ b/client/asmjit/x86/x86globals.h
@@ -0,0 +1,2161 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86GLOBALS_H_INCLUDED
+#define ASMJIT_X86_X86GLOBALS_H_INCLUDED
+
+#include "../core/arch.h"
+#include "../core/inst.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \namespace asmjit::x86
+//! \ingroup asmjit_x86
+//!
+//! X86/X64 API.
+
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::x86::Inst]
+// ============================================================================
+
+//! Instruction.
+//!
+//! \note Only used to hold x86-specific enumerations and static functions.
+struct Inst : public BaseInst {
+  //! Instruction id.
+  enum Id : uint32_t {
+    // ${InstId:Begin}
+    kIdNone = 0,                         //!< Invalid instruction id.
+    kIdAaa,                              //!< Instruction 'aaa' (X86).
+    kIdAad,                              //!< Instruction 'aad' (X86).
+    kIdAam,                              //!< Instruction 'aam' (X86).
+    kIdAas,                              //!< Instruction 'aas' (X86).
+    kIdAdc,                              //!< Instruction 'adc'.
+    kIdAdcx,                             //!< Instruction 'adcx' {ADX}.
+    kIdAdd,                              //!< Instruction 'add'.
+    kIdAddpd,                            //!< Instruction 'addpd' {SSE2}.
+    kIdAddps,                            //!< Instruction 'addps' {SSE}.
+    kIdAddsd,                            //!< Instruction 'addsd' {SSE2}.
+    kIdAddss,                            //!< Instruction 'addss' {SSE}.
+    kIdAddsubpd,                         //!< Instruction 'addsubpd' {SSE3}.
+    kIdAddsubps,                         //!< Instruction 'addsubps' {SSE3}.
+    kIdAdox,                             //!< Instruction 'adox' {ADX}.
+    kIdAesdec,                           //!< Instruction 'aesdec' {AESNI}.
+    kIdAesdeclast,                       //!< Instruction 'aesdeclast' {AESNI}.
+    kIdAesenc,                           //!< Instruction 'aesenc' {AESNI}.
+    kIdAesenclast,                       //!< Instruction 'aesenclast' {AESNI}.
+    kIdAesimc,                           //!< Instruction 'aesimc' {AESNI}.
+    kIdAeskeygenassist,                  //!< Instruction 'aeskeygenassist' {AESNI}.
+    kIdAnd,                              //!< Instruction 'and'.
+    kIdAndn,                             //!< Instruction 'andn' {BMI}.
+    kIdAndnpd,                           //!< Instruction 'andnpd' {SSE2}.
+    kIdAndnps,                           //!< Instruction 'andnps' {SSE}.
+    kIdAndpd,                            //!< Instruction 'andpd' {SSE2}.
+    kIdAndps,                            //!< Instruction 'andps' {SSE}.
+    kIdArpl,                             //!< Instruction 'arpl' (X86).
+    kIdBextr,                            //!< Instruction 'bextr' {BMI}.
+    kIdBlcfill,                          //!< Instruction 'blcfill' {TBM}.
+    kIdBlci,                             //!< Instruction 'blci' {TBM}.
+    kIdBlcic,                            //!< Instruction 'blcic' {TBM}.
+    kIdBlcmsk,                           //!< Instruction 'blcmsk' {TBM}.
+    kIdBlcs,                             //!< Instruction 'blcs' {TBM}.
+    kIdBlendpd,                          //!< Instruction 'blendpd' {SSE4_1}.
+    kIdBlendps,                          //!< Instruction 'blendps' {SSE4_1}.
+    kIdBlendvpd,                         //!< Instruction 'blendvpd' {SSE4_1}.
+    kIdBlendvps,                         //!< Instruction 'blendvps' {SSE4_1}.
+    kIdBlsfill,                          //!< Instruction 'blsfill' {TBM}.
+    kIdBlsi,                             //!< Instruction 'blsi' {BMI}.
+    kIdBlsic,                            //!< Instruction 'blsic' {TBM}.
+    kIdBlsmsk,                           //!< Instruction 'blsmsk' {BMI}.
+    kIdBlsr,                             //!< Instruction 'blsr' {BMI}.
+    kIdBndcl,                            //!< Instruction 'bndcl' {MPX}.
+    kIdBndcn,                            //!< Instruction 'bndcn' {MPX}.
+    kIdBndcu,                            //!< Instruction 'bndcu' {MPX}.
+    kIdBndldx,                           //!< Instruction 'bndldx' {MPX}.
+    kIdBndmk,                            //!< Instruction 'bndmk' {MPX}.
+    kIdBndmov,                           //!< Instruction 'bndmov' {MPX}.
+    kIdBndstx,                           //!< Instruction 'bndstx' {MPX}.
+    kIdBound,                            //!< Instruction 'bound' (X86).
+    kIdBsf,                              //!< Instruction 'bsf'.
+    kIdBsr,                              //!< Instruction 'bsr'.
+    kIdBswap,                            //!< Instruction 'bswap'.
+    kIdBt,                               //!< Instruction 'bt'.
+    kIdBtc,                              //!< Instruction 'btc'.
+    kIdBtr,                              //!< Instruction 'btr'.
+    kIdBts,                              //!< Instruction 'bts'.
+    kIdBzhi,                             //!< Instruction 'bzhi' {BMI2}.
+    kIdCall,                             //!< Instruction 'call'.
+    kIdCbw,                              //!< Instruction 'cbw'.
+    kIdCdq,                              //!< Instruction 'cdq'.
+    kIdCdqe,                             //!< Instruction 'cdqe' (X64).
+    kIdClac,                             //!< Instruction 'clac' {SMAP}.
+    kIdClc,                              //!< Instruction 'clc'.
+    kIdCld,                              //!< Instruction 'cld'.
+    kIdCldemote,                         //!< Instruction 'cldemote' {CLDEMOTE}.
+    kIdClflush,                          //!< Instruction 'clflush' {CLFLUSH}.
+    kIdClflushopt,                       //!< Instruction 'clflushopt' {CLFLUSHOPT}.
+    kIdClgi,                             //!< Instruction 'clgi' {SVM}.
+    kIdCli,                              //!< Instruction 'cli'.
+    kIdClrssbsy,                         //!< Instruction 'clrssbsy' {CET_SS}.
+    kIdClts,                             //!< Instruction 'clts'.
+    kIdClwb,                             //!< Instruction 'clwb' {CLWB}.
+    kIdClzero,                           //!< Instruction 'clzero' {CLZERO}.
+    kIdCmc,                              //!< Instruction 'cmc'.
+    kIdCmova,                            //!< Instruction 'cmova' {CMOV}.
+    kIdCmovae,                           //!< Instruction 'cmovae' {CMOV}.
+    kIdCmovb,                            //!< Instruction 'cmovb' {CMOV}.
+    kIdCmovbe,                           //!< Instruction 'cmovbe' {CMOV}.
+    kIdCmovc,                            //!< Instruction 'cmovc' {CMOV}.
+    kIdCmove,                            //!< Instruction 'cmove' {CMOV}.
+    kIdCmovg,                            //!< Instruction 'cmovg' {CMOV}.
+    kIdCmovge,                           //!< Instruction 'cmovge' {CMOV}.
+    kIdCmovl,                            //!< Instruction 'cmovl' {CMOV}.
+    kIdCmovle,                           //!< Instruction 'cmovle' {CMOV}.
+    kIdCmovna,                           //!< Instruction 'cmovna' {CMOV}.
+    kIdCmovnae,                          //!< Instruction 'cmovnae' {CMOV}.
+    kIdCmovnb,                           //!< Instruction 'cmovnb' {CMOV}.
+    kIdCmovnbe,                          //!< Instruction 'cmovnbe' {CMOV}.
+    kIdCmovnc,                           //!< Instruction 'cmovnc' {CMOV}.
+    kIdCmovne,                           //!< Instruction 'cmovne' {CMOV}.
+    kIdCmovng,                           //!< Instruction 'cmovng' {CMOV}.
+    kIdCmovnge,                          //!< Instruction 'cmovnge' {CMOV}.
+    kIdCmovnl,                           //!< Instruction 'cmovnl' {CMOV}.
+    kIdCmovnle,                          //!< Instruction 'cmovnle' {CMOV}.
+    kIdCmovno,                           //!< Instruction 'cmovno' {CMOV}.
+    kIdCmovnp,                           //!< Instruction 'cmovnp' {CMOV}.
+    kIdCmovns,                           //!< Instruction 'cmovns' {CMOV}.
+    kIdCmovnz,                           //!< Instruction 'cmovnz' {CMOV}.
+    kIdCmovo,                            //!< Instruction 'cmovo' {CMOV}.
+    kIdCmovp,                            //!< Instruction 'cmovp' {CMOV}.
+    kIdCmovpe,                           //!< Instruction 'cmovpe' {CMOV}.
+    kIdCmovpo,                           //!< Instruction 'cmovpo' {CMOV}.
+    kIdCmovs,                            //!< Instruction 'cmovs' {CMOV}.
+    kIdCmovz,                            //!< Instruction 'cmovz' {CMOV}.
+    kIdCmp,                              //!< Instruction 'cmp'.
+    kIdCmppd,                            //!< Instruction 'cmppd' {SSE2}.
+    kIdCmpps,                            //!< Instruction 'cmpps' {SSE}.
+    kIdCmps,                             //!< Instruction 'cmps'.
+    kIdCmpsd,                            //!< Instruction 'cmpsd' {SSE2}.
+    kIdCmpss,                            //!< Instruction 'cmpss' {SSE}.
+    kIdCmpxchg,                          //!< Instruction 'cmpxchg' {I486}.
+    kIdCmpxchg16b,                       //!< Instruction 'cmpxchg16b' {CMPXCHG16B} (X64).
+    kIdCmpxchg8b,                        //!< Instruction 'cmpxchg8b' {CMPXCHG8B}.
+    kIdComisd,                           //!< Instruction 'comisd' {SSE2}.
+    kIdComiss,                           //!< Instruction 'comiss' {SSE}.
+    kIdCpuid,                            //!< Instruction 'cpuid' {I486}.
+    kIdCqo,                              //!< Instruction 'cqo' (X64).
+    kIdCrc32,                            //!< Instruction 'crc32' {SSE4_2}.
+    kIdCvtdq2pd,                         //!< Instruction 'cvtdq2pd' {SSE2}.
+    kIdCvtdq2ps,                         //!< Instruction 'cvtdq2ps' {SSE2}.
+    kIdCvtpd2dq,                         //!< Instruction 'cvtpd2dq' {SSE2}.
+    kIdCvtpd2pi,                         //!< Instruction 'cvtpd2pi' {SSE2}.
+    kIdCvtpd2ps,                         //!< Instruction 'cvtpd2ps' {SSE2}.
+    kIdCvtpi2pd,                         //!< Instruction 'cvtpi2pd' {SSE2}.
+    kIdCvtpi2ps,                         //!< Instruction 'cvtpi2ps' {SSE}.
+    kIdCvtps2dq,                         //!< Instruction 'cvtps2dq' {SSE2}.
+    kIdCvtps2pd,                         //!< Instruction 'cvtps2pd' {SSE2}.
+    kIdCvtps2pi,                         //!< Instruction 'cvtps2pi' {SSE}.
+    kIdCvtsd2si,                         //!< Instruction 'cvtsd2si' {SSE2}.
+    kIdCvtsd2ss,                         //!< Instruction 'cvtsd2ss' {SSE2}.
+    kIdCvtsi2sd,                         //!< Instruction 'cvtsi2sd' {SSE2}.
+    kIdCvtsi2ss,                         //!< Instruction 'cvtsi2ss' {SSE}.
+    kIdCvtss2sd,                         //!< Instruction 'cvtss2sd' {SSE2}.
+    kIdCvtss2si,                         //!< Instruction 'cvtss2si' {SSE}.
+    kIdCvttpd2dq,                        //!< Instruction 'cvttpd2dq' {SSE2}.
+    kIdCvttpd2pi,                        //!< Instruction 'cvttpd2pi' {SSE2}.
+    kIdCvttps2dq,                        //!< Instruction 'cvttps2dq' {SSE2}.
+    kIdCvttps2pi,                        //!< Instruction 'cvttps2pi' {SSE}.
+    kIdCvttsd2si,                        //!< Instruction 'cvttsd2si' {SSE2}.
+    kIdCvttss2si,                        //!< Instruction 'cvttss2si' {SSE}.
+    kIdCwd,                              //!< Instruction 'cwd'.
+    kIdCwde,                             //!< Instruction 'cwde'.
+    kIdDaa,                              //!< Instruction 'daa' (X86).
+    kIdDas,                              //!< Instruction 'das' (X86).
+    kIdDec,                              //!< Instruction 'dec'.
+    kIdDiv,                              //!< Instruction 'div'.
+    kIdDivpd,                            //!< Instruction 'divpd' {SSE2}.
+    kIdDivps,                            //!< Instruction 'divps' {SSE}.
+    kIdDivsd,                            //!< Instruction 'divsd' {SSE2}.
+    kIdDivss,                            //!< Instruction 'divss' {SSE}.
+    kIdDppd,                             //!< Instruction 'dppd' {SSE4_1}.
+    kIdDpps,                             //!< Instruction 'dpps' {SSE4_1}.
+    kIdEmms,                             //!< Instruction 'emms' {MMX}.
+    kIdEndbr32,                          //!< Instruction 'endbr32' {CET_IBT}.
+    kIdEndbr64,                          //!< Instruction 'endbr64' {CET_IBT}.
+    kIdEnqcmd,                           //!< Instruction 'enqcmd' {ENQCMD}.
+    kIdEnqcmds,                          //!< Instruction 'enqcmds' {ENQCMD}.
+    kIdEnter,                            //!< Instruction 'enter'.
+    kIdExtractps,                        //!< Instruction 'extractps' {SSE4_1}.
+    kIdExtrq,                            //!< Instruction 'extrq' {SSE4A}.
+    kIdF2xm1,                            //!< Instruction 'f2xm1'.
+    kIdFabs,                             //!< Instruction 'fabs'.
+    kIdFadd,                             //!< Instruction 'fadd'.
+    kIdFaddp,                            //!< Instruction 'faddp'.
+    kIdFbld,                             //!< Instruction 'fbld'.
+    kIdFbstp,                            //!< Instruction 'fbstp'.
+    kIdFchs,                             //!< Instruction 'fchs'.
+    kIdFclex,                            //!< Instruction 'fclex'.
+    kIdFcmovb,                           //!< Instruction 'fcmovb' {CMOV}.
+    kIdFcmovbe,                          //!< Instruction 'fcmovbe' {CMOV}.
+    kIdFcmove,                           //!< Instruction 'fcmove' {CMOV}.
+    kIdFcmovnb,                          //!< Instruction 'fcmovnb' {CMOV}.
+    kIdFcmovnbe,                         //!< Instruction 'fcmovnbe' {CMOV}.
+    kIdFcmovne,                          //!< Instruction 'fcmovne' {CMOV}.
+    kIdFcmovnu,                          //!< Instruction 'fcmovnu' {CMOV}.
+    kIdFcmovu,                           //!< Instruction 'fcmovu' {CMOV}.
+    kIdFcom,                             //!< Instruction 'fcom'.
+    kIdFcomi,                            //!< Instruction 'fcomi'.
+    kIdFcomip,                           //!< Instruction 'fcomip'.
+    kIdFcomp,                            //!< Instruction 'fcomp'.
+    kIdFcompp,                           //!< Instruction 'fcompp'.
+    kIdFcos,                             //!< Instruction 'fcos'.
+    kIdFdecstp,                          //!< Instruction 'fdecstp'.
+    kIdFdiv,                             //!< Instruction 'fdiv'.
+    kIdFdivp,                            //!< Instruction 'fdivp'.
+    kIdFdivr,                            //!< Instruction 'fdivr'.
+    kIdFdivrp,                           //!< Instruction 'fdivrp'.
+    kIdFemms,                            //!< Instruction 'femms' {3DNOW}.
+    kIdFfree,                            //!< Instruction 'ffree'.
+    kIdFiadd,                            //!< Instruction 'fiadd'.
+    kIdFicom,                            //!< Instruction 'ficom'.
+    kIdFicomp,                           //!< Instruction 'ficomp'.
+    kIdFidiv,                            //!< Instruction 'fidiv'.
+    kIdFidivr,                           //!< Instruction 'fidivr'.
+    kIdFild,                             //!< Instruction 'fild'.
+    kIdFimul,                            //!< Instruction 'fimul'.
+    kIdFincstp,                          //!< Instruction 'fincstp'.
+    kIdFinit,                            //!< Instruction 'finit'.
+    kIdFist,                             //!< Instruction 'fist'.
+    kIdFistp,                            //!< Instruction 'fistp'.
+    kIdFisttp,                           //!< Instruction 'fisttp' {SSE3}.
+    kIdFisub,                            //!< Instruction 'fisub'.
+    kIdFisubr,                           //!< Instruction 'fisubr'.
+    kIdFld,                              //!< Instruction 'fld'.
+    kIdFld1,                             //!< Instruction 'fld1'.
+    kIdFldcw,                            //!< Instruction 'fldcw'.
+    kIdFldenv,                           //!< Instruction 'fldenv'.
+    kIdFldl2e,                           //!< Instruction 'fldl2e'.
+    kIdFldl2t,                           //!< Instruction 'fldl2t'.
+    kIdFldlg2,                           //!< Instruction 'fldlg2'.
+    kIdFldln2,                           //!< Instruction 'fldln2'.
+    kIdFldpi,                            //!< Instruction 'fldpi'.
+    kIdFldz,                             //!< Instruction 'fldz'.
+    kIdFmul,                             //!< Instruction 'fmul'.
+    kIdFmulp,                            //!< Instruction 'fmulp'.
+    kIdFnclex,                           //!< Instruction 'fnclex'.
+    kIdFninit,                           //!< Instruction 'fninit'.
+    kIdFnop,                             //!< Instruction 'fnop'.
+    kIdFnsave,                           //!< Instruction 'fnsave'.
+    kIdFnstcw,                           //!< Instruction 'fnstcw'.
+    kIdFnstenv,                          //!< Instruction 'fnstenv'.
+    kIdFnstsw,                           //!< Instruction 'fnstsw'.
+    kIdFpatan,                           //!< Instruction 'fpatan'.
+    kIdFprem,                            //!< Instruction 'fprem'.
+    kIdFprem1,                           //!< Instruction 'fprem1'.
+    kIdFptan,                            //!< Instruction 'fptan'.
+    kIdFrndint,                          //!< Instruction 'frndint'.
+    kIdFrstor,                           //!< Instruction 'frstor'.
+    kIdFsave,                            //!< Instruction 'fsave'.
+    kIdFscale,                           //!< Instruction 'fscale'.
+    kIdFsin,                             //!< Instruction 'fsin'.
+    kIdFsincos,                          //!< Instruction 'fsincos'.
+    kIdFsqrt,                            //!< Instruction 'fsqrt'.
+    kIdFst,                              //!< Instruction 'fst'.
+    kIdFstcw,                            //!< Instruction 'fstcw'.
+    kIdFstenv,                           //!< Instruction 'fstenv'.
+    kIdFstp,                             //!< Instruction 'fstp'.
+    kIdFstsw,                            //!< Instruction 'fstsw'.
+    kIdFsub,                             //!< Instruction 'fsub'.
+    kIdFsubp,                            //!< Instruction 'fsubp'.
+    kIdFsubr,                            //!< Instruction 'fsubr'.
+    kIdFsubrp,                           //!< Instruction 'fsubrp'.
+    kIdFtst,                             //!< Instruction 'ftst'.
+    kIdFucom,                            //!< Instruction 'fucom'.
+    kIdFucomi,                           //!< Instruction 'fucomi'.
+    kIdFucomip,                          //!< Instruction 'fucomip'.
+    kIdFucomp,                           //!< Instruction 'fucomp'.
+    kIdFucompp,                          //!< Instruction 'fucompp'.
+    kIdFwait,                            //!< Instruction 'fwait'.
+    kIdFxam,                             //!< Instruction 'fxam'.
+    kIdFxch,                             //!< Instruction 'fxch'.
+    kIdFxrstor,                          //!< Instruction 'fxrstor' {FXSR}.
+    kIdFxrstor64,                        //!< Instruction 'fxrstor64' {FXSR} (X64).
+    kIdFxsave,                           //!< Instruction 'fxsave' {FXSR}.
+    kIdFxsave64,                         //!< Instruction 'fxsave64' {FXSR} (X64).
+    kIdFxtract,                          //!< Instruction 'fxtract'.
+    kIdFyl2x,                            //!< Instruction 'fyl2x'.
+    kIdFyl2xp1,                          //!< Instruction 'fyl2xp1'.
+    kIdGetsec,                           //!< Instruction 'getsec' {SMX}.
+    kIdGf2p8affineinvqb,                 //!< Instruction 'gf2p8affineinvqb' {GFNI}.
+    kIdGf2p8affineqb,                    //!< Instruction 'gf2p8affineqb' {GFNI}.
+    kIdGf2p8mulb,                        //!< Instruction 'gf2p8mulb' {GFNI}.
+    kIdHaddpd,                           //!< Instruction 'haddpd' {SSE3}.
+    kIdHaddps,                           //!< Instruction 'haddps' {SSE3}.
+    kIdHlt,                              //!< Instruction 'hlt'.
+    kIdHsubpd,                           //!< Instruction 'hsubpd' {SSE3}.
+    kIdHsubps,                           //!< Instruction 'hsubps' {SSE3}.
+    kIdIdiv,                             //!< Instruction 'idiv'.
+    kIdImul,                             //!< Instruction 'imul'.
+    kIdIn,                               //!< Instruction 'in'.
+    kIdInc,                              //!< Instruction 'inc'.
+    kIdIncsspd,                          //!< Instruction 'incsspd' {CET_SS}.
+    kIdIncsspq,                          //!< Instruction 'incsspq' {CET_SS} (X64).
+    kIdIns,                              //!< Instruction 'ins'.
+    kIdInsertps,                         //!< Instruction 'insertps' {SSE4_1}.
+    kIdInsertq,                          //!< Instruction 'insertq' {SSE4A}.
+    kIdInt,                              //!< Instruction 'int'.
+    kIdInt3,                             //!< Instruction 'int3'.
+    kIdInto,                             //!< Instruction 'into' (X86).
+    kIdInvd,                             //!< Instruction 'invd' {I486}.
+    kIdInvept,                           //!< Instruction 'invept' {VMX}.
+    kIdInvlpg,                           //!< Instruction 'invlpg' {I486}.
+    kIdInvlpga,                          //!< Instruction 'invlpga' {SVM}.
+    kIdInvpcid,                          //!< Instruction 'invpcid' {I486}.
+    kIdInvvpid,                          //!< Instruction 'invvpid' {VMX}.
+    kIdIret,                             //!< Instruction 'iret'.
+    kIdIretd,                            //!< Instruction 'iretd'.
+    kIdIretq,                            //!< Instruction 'iretq' (X64).
+    kIdIretw,                            //!< Instruction 'iretw'.
+    kIdJa,                               //!< Instruction 'ja'.
+    kIdJae,                              //!< Instruction 'jae'.
+    kIdJb,                               //!< Instruction 'jb'.
+    kIdJbe,                              //!< Instruction 'jbe'.
+    kIdJc,                               //!< Instruction 'jc'.
+    kIdJe,                               //!< Instruction 'je'.
+    kIdJecxz,                            //!< Instruction 'jecxz'.
+    kIdJg,                               //!< Instruction 'jg'.
+    kIdJge,                              //!< Instruction 'jge'.
+    kIdJl,                               //!< Instruction 'jl'.
+    kIdJle,                              //!< Instruction 'jle'.
+    kIdJmp,                              //!< Instruction 'jmp'.
+    kIdJna,                              //!< Instruction 'jna'.
+    kIdJnae,                             //!< Instruction 'jnae'.
+    kIdJnb,                              //!< Instruction 'jnb'.
+    kIdJnbe,                             //!< Instruction 'jnbe'.
+    kIdJnc,                              //!< Instruction 'jnc'.
+    kIdJne,                              //!< Instruction 'jne'.
+    kIdJng,                              //!< Instruction 'jng'.
+    kIdJnge,                             //!< Instruction 'jnge'.
+    kIdJnl,                              //!< Instruction 'jnl'.
+    kIdJnle,                             //!< Instruction 'jnle'.
+    kIdJno,                              //!< Instruction 'jno'.
+    kIdJnp,                              //!< Instruction 'jnp'.
+    kIdJns,                              //!< Instruction 'jns'.
+    kIdJnz,                              //!< Instruction 'jnz'.
+    kIdJo,                               //!< Instruction 'jo'.
+    kIdJp,                               //!< Instruction 'jp'.
+    kIdJpe,                              //!< Instruction 'jpe'.
+    kIdJpo,                              //!< Instruction 'jpo'.
+    kIdJs,                               //!< Instruction 'js'.
+    kIdJz,                               //!< Instruction 'jz'.
+    kIdKaddb,                            //!< Instruction 'kaddb' {AVX512_DQ}.
+    kIdKaddd,                            //!< Instruction 'kaddd' {AVX512_BW}.
+    kIdKaddq,                            //!< Instruction 'kaddq' {AVX512_BW}.
+    kIdKaddw,                            //!< Instruction 'kaddw' {AVX512_DQ}.
+    kIdKandb,                            //!< Instruction 'kandb' {AVX512_DQ}.
+    kIdKandd,                            //!< Instruction 'kandd' {AVX512_BW}.
+    kIdKandnb,                           //!< Instruction 'kandnb' {AVX512_DQ}.
+    kIdKandnd,                           //!< Instruction 'kandnd' {AVX512_BW}.
+    kIdKandnq,                           //!< Instruction 'kandnq' {AVX512_BW}.
+    kIdKandnw,                           //!< Instruction 'kandnw' {AVX512_F}.
+    kIdKandq,                            //!< Instruction 'kandq' {AVX512_BW}.
+    kIdKandw,                            //!< Instruction 'kandw' {AVX512_F}.
+    kIdKmovb,                            //!< Instruction 'kmovb' {AVX512_DQ}.
+    kIdKmovd,                            //!< Instruction 'kmovd' {AVX512_BW}.
+    kIdKmovq,                            //!< Instruction 'kmovq' {AVX512_BW}.
+    kIdKmovw,                            //!< Instruction 'kmovw' {AVX512_F}.
+    kIdKnotb,                            //!< Instruction 'knotb' {AVX512_DQ}.
+    kIdKnotd,                            //!< Instruction 'knotd' {AVX512_BW}.
+    kIdKnotq,                            //!< Instruction 'knotq' {AVX512_BW}.
+    kIdKnotw,                            //!< Instruction 'knotw' {AVX512_F}.
+    kIdKorb,                             //!< Instruction 'korb' {AVX512_DQ}.
+    kIdKord,                             //!< Instruction 'kord' {AVX512_BW}.
+    kIdKorq,                             //!< Instruction 'korq' {AVX512_BW}.
+    kIdKortestb,                         //!< Instruction 'kortestb' {AVX512_DQ}.
+    kIdKortestd,                         //!< Instruction 'kortestd' {AVX512_BW}.
+    kIdKortestq,                         //!< Instruction 'kortestq' {AVX512_BW}.
+    kIdKortestw,                         //!< Instruction 'kortestw' {AVX512_F}.
+    kIdKorw,                             //!< Instruction 'korw' {AVX512_F}.
+    kIdKshiftlb,                         //!< Instruction 'kshiftlb' {AVX512_DQ}.
+    kIdKshiftld,                         //!< Instruction 'kshiftld' {AVX512_BW}.
+    kIdKshiftlq,                         //!< Instruction 'kshiftlq' {AVX512_BW}.
+    kIdKshiftlw,                         //!< Instruction 'kshiftlw' {AVX512_F}.
+    kIdKshiftrb,                         //!< Instruction 'kshiftrb' {AVX512_DQ}.
+    kIdKshiftrd,                         //!< Instruction 'kshiftrd' {AVX512_BW}.
+    kIdKshiftrq,                         //!< Instruction 'kshiftrq' {AVX512_BW}.
+    kIdKshiftrw,                         //!< Instruction 'kshiftrw' {AVX512_F}.
+    kIdKtestb,                           //!< Instruction 'ktestb' {AVX512_DQ}.
+    kIdKtestd,                           //!< Instruction 'ktestd' {AVX512_BW}.
+    kIdKtestq,                           //!< Instruction 'ktestq' {AVX512_BW}.
+    kIdKtestw,                           //!< Instruction 'ktestw' {AVX512_DQ}.
+    kIdKunpckbw,                         //!< Instruction 'kunpckbw' {AVX512_F}.
+    kIdKunpckdq,                         //!< Instruction 'kunpckdq' {AVX512_BW}.
+    kIdKunpckwd,                         //!< Instruction 'kunpckwd' {AVX512_BW}.
+    kIdKxnorb,                           //!< Instruction 'kxnorb' {AVX512_DQ}.
+    kIdKxnord,                           //!< Instruction 'kxnord' {AVX512_BW}.
+    kIdKxnorq,                           //!< Instruction 'kxnorq' {AVX512_BW}.
+    kIdKxnorw,                           //!< Instruction 'kxnorw' {AVX512_F}.
+    kIdKxorb,                            //!< Instruction 'kxorb' {AVX512_DQ}.
+    kIdKxord,                            //!< Instruction 'kxord' {AVX512_BW}.
+    kIdKxorq,                            //!< Instruction 'kxorq' {AVX512_BW}.
+    kIdKxorw,                            //!< Instruction 'kxorw' {AVX512_F}.
+    kIdLahf,                             //!< Instruction 'lahf' {LAHFSAHF}.
+    kIdLar,                              //!< Instruction 'lar'.
+    kIdLddqu,                            //!< Instruction 'lddqu' {SSE3}.
+    kIdLdmxcsr,                          //!< Instruction 'ldmxcsr' {SSE}.
+    kIdLds,                              //!< Instruction 'lds' (X86).
+    kIdLdtilecfg,                        //!< Instruction 'ldtilecfg' {AMX_TILE} (X64).
+    kIdLea,                              //!< Instruction 'lea'.
+    kIdLeave,                            //!< Instruction 'leave'.
+    kIdLes,                              //!< Instruction 'les' (X86).
+    kIdLfence,                           //!< Instruction 'lfence' {SSE2}.
+    kIdLfs,                              //!< Instruction 'lfs'.
+    kIdLgdt,                             //!< Instruction 'lgdt'.
+    kIdLgs,                              //!< Instruction 'lgs'.
+    kIdLidt,                             //!< Instruction 'lidt'.
+    kIdLldt,                             //!< Instruction 'lldt'.
+    kIdLlwpcb,                           //!< Instruction 'llwpcb' {LWP}.
+    kIdLmsw,                             //!< Instruction 'lmsw'.
+    kIdLods,                             //!< Instruction 'lods'.
+    kIdLoop,                             //!< Instruction 'loop'.
+    kIdLoope,                            //!< Instruction 'loope'.
+    kIdLoopne,                           //!< Instruction 'loopne'.
+    kIdLsl,                              //!< Instruction 'lsl'.
+    kIdLss,                              //!< Instruction 'lss'.
+    kIdLtr,                              //!< Instruction 'ltr'.
+    kIdLwpins,                           //!< Instruction 'lwpins' {LWP}.
+    kIdLwpval,                           //!< Instruction 'lwpval' {LWP}.
+    kIdLzcnt,                            //!< Instruction 'lzcnt' {LZCNT}.
+    kIdMaskmovdqu,                       //!< Instruction 'maskmovdqu' {SSE2}.
+    kIdMaskmovq,                         //!< Instruction 'maskmovq' {MMX2}.
+    kIdMaxpd,                            //!< Instruction 'maxpd' {SSE2}.
+    kIdMaxps,                            //!< Instruction 'maxps' {SSE}.
+    kIdMaxsd,                            //!< Instruction 'maxsd' {SSE2}.
+    kIdMaxss,                            //!< Instruction 'maxss' {SSE}.
+    kIdMcommit,                          //!< Instruction 'mcommit' {MCOMMIT}.
+    kIdMfence,                           //!< Instruction 'mfence' {SSE2}.
+    kIdMinpd,                            //!< Instruction 'minpd' {SSE2}.
+    kIdMinps,                            //!< Instruction 'minps' {SSE}.
+    kIdMinsd,                            //!< Instruction 'minsd' {SSE2}.
+    kIdMinss,                            //!< Instruction 'minss' {SSE}.
+    kIdMonitor,                          //!< Instruction 'monitor' {MONITOR}.
+    kIdMonitorx,                         //!< Instruction 'monitorx' {MONITORX}.
+    kIdMov,                              //!< Instruction 'mov'.
+    kIdMovapd,                           //!< Instruction 'movapd' {SSE2}.
+    kIdMovaps,                           //!< Instruction 'movaps' {SSE}.
+    kIdMovbe,                            //!< Instruction 'movbe' {MOVBE}.
+    kIdMovd,                             //!< Instruction 'movd' {MMX|SSE2}.
+    kIdMovddup,                          //!< Instruction 'movddup' {SSE3}.
+    kIdMovdir64b,                        //!< Instruction 'movdir64b' {MOVDIR64B}.
+    kIdMovdiri,                          //!< Instruction 'movdiri' {MOVDIRI}.
+    kIdMovdq2q,                          //!< Instruction 'movdq2q' {SSE2}.
+    kIdMovdqa,                           //!< Instruction 'movdqa' {SSE2}.
+    kIdMovdqu,                           //!< Instruction 'movdqu' {SSE2}.
+    kIdMovhlps,                          //!< Instruction 'movhlps' {SSE}.
+    kIdMovhpd,                           //!< Instruction 'movhpd' {SSE2}.
+    kIdMovhps,                           //!< Instruction 'movhps' {SSE}.
+    kIdMovlhps,                          //!< Instruction 'movlhps' {SSE}.
+    kIdMovlpd,                           //!< Instruction 'movlpd' {SSE2}.
+    kIdMovlps,                           //!< Instruction 'movlps' {SSE}.
+    kIdMovmskpd,                         //!< Instruction 'movmskpd' {SSE2}.
+    kIdMovmskps,                         //!< Instruction 'movmskps' {SSE}.
+    kIdMovntdq,                          //!< Instruction 'movntdq' {SSE2}.
+    kIdMovntdqa,                         //!< Instruction 'movntdqa' {SSE4_1}.
+    kIdMovnti,                           //!< Instruction 'movnti' {SSE2}.
+    kIdMovntpd,                          //!< Instruction 'movntpd' {SSE2}.
+    kIdMovntps,                          //!< Instruction 'movntps' {SSE}.
+    kIdMovntq,                           //!< Instruction 'movntq' {MMX2}.
+    kIdMovntsd,                          //!< Instruction 'movntsd' {SSE4A}.
+    kIdMovntss,                          //!< Instruction 'movntss' {SSE4A}.
+    kIdMovq,                             //!< Instruction 'movq' {MMX|SSE2}.
+    kIdMovq2dq,                          //!< Instruction 'movq2dq' {SSE2}.
+    kIdMovs,                             //!< Instruction 'movs'.
+    kIdMovsd,                            //!< Instruction 'movsd' {SSE2}.
+    kIdMovshdup,                         //!< Instruction 'movshdup' {SSE3}.
+    kIdMovsldup,                         //!< Instruction 'movsldup' {SSE3}.
+    kIdMovss,                            //!< Instruction 'movss' {SSE}.
+    kIdMovsx,                            //!< Instruction 'movsx'.
+    kIdMovsxd,                           //!< Instruction 'movsxd' (X64).
+    kIdMovupd,                           //!< Instruction 'movupd' {SSE2}.
+    kIdMovups,                           //!< Instruction 'movups' {SSE}.
+    kIdMovzx,                            //!< Instruction 'movzx'.
+    kIdMpsadbw,                          //!< Instruction 'mpsadbw' {SSE4_1}.
+    kIdMul,                              //!< Instruction 'mul'.
+    kIdMulpd,                            //!< Instruction 'mulpd' {SSE2}.
+    kIdMulps,                            //!< Instruction 'mulps' {SSE}.
+    kIdMulsd,                            //!< Instruction 'mulsd' {SSE2}.
+    kIdMulss,                            //!< Instruction 'mulss' {SSE}.
+    kIdMulx,                             //!< Instruction 'mulx' {BMI2}.
+    kIdMwait,                            //!< Instruction 'mwait' {MONITOR}.
+    kIdMwaitx,                           //!< Instruction 'mwaitx' {MONITORX}.
+    kIdNeg,                              //!< Instruction 'neg'.
+    kIdNop,                              //!< Instruction 'nop'.
+    kIdNot,                              //!< Instruction 'not'.
+    kIdOr,                               //!< Instruction 'or'.
+    kIdOrpd,                             //!< Instruction 'orpd' {SSE2}.
+    kIdOrps,                             //!< Instruction 'orps' {SSE}.
+    kIdOut,                              //!< Instruction 'out'.
+    kIdOuts,                             //!< Instruction 'outs'.
+    kIdPabsb,                            //!< Instruction 'pabsb' {SSSE3}.
+    kIdPabsd,                            //!< Instruction 'pabsd' {SSSE3}.
+    kIdPabsw,                            //!< Instruction 'pabsw' {SSSE3}.
+    kIdPackssdw,                         //!< Instruction 'packssdw' {MMX|SSE2}.
+    kIdPacksswb,                         //!< Instruction 'packsswb' {MMX|SSE2}.
+    kIdPackusdw,                         //!< Instruction 'packusdw' {SSE4_1}.
+    kIdPackuswb,                         //!< Instruction 'packuswb' {MMX|SSE2}.
+    kIdPaddb,                            //!< Instruction 'paddb' {MMX|SSE2}.
+    kIdPaddd,                            //!< Instruction 'paddd' {MMX|SSE2}.
+    kIdPaddq,                            //!< Instruction 'paddq' {SSE2}.
+    kIdPaddsb,                           //!< Instruction 'paddsb' {MMX|SSE2}.
+    kIdPaddsw,                           //!< Instruction 'paddsw' {MMX|SSE2}.
+    kIdPaddusb,                          //!< Instruction 'paddusb' {MMX|SSE2}.
+    kIdPaddusw,                          //!< Instruction 'paddusw' {MMX|SSE2}.
+    kIdPaddw,                            //!< Instruction 'paddw' {MMX|SSE2}.
+    kIdPalignr,                          //!< Instruction 'palignr' {SSE3}.
+    kIdPand,                             //!< Instruction 'pand' {MMX|SSE2}.
+    kIdPandn,                            //!< Instruction 'pandn' {MMX|SSE2}.
+    kIdPause,                            //!< Instruction 'pause'.
+    kIdPavgb,                            //!< Instruction 'pavgb' {MMX2|SSE2}.
+    kIdPavgusb,                          //!< Instruction 'pavgusb' {3DNOW}.
+    kIdPavgw,                            //!< Instruction 'pavgw' {MMX2|SSE2}.
+    kIdPblendvb,                         //!< Instruction 'pblendvb' {SSE4_1}.
+    kIdPblendw,                          //!< Instruction 'pblendw' {SSE4_1}.
+    kIdPclmulqdq,                        //!< Instruction 'pclmulqdq' {PCLMULQDQ}.
+    kIdPcmpeqb,                          //!< Instruction 'pcmpeqb' {MMX|SSE2}.
+    kIdPcmpeqd,                          //!< Instruction 'pcmpeqd' {MMX|SSE2}.
+    kIdPcmpeqq,                          //!< Instruction 'pcmpeqq' {SSE4_1}.
+    kIdPcmpeqw,                          //!< Instruction 'pcmpeqw' {MMX|SSE2}.
+    kIdPcmpestri,                        //!< Instruction 'pcmpestri' {SSE4_2}.
+    kIdPcmpestrm,                        //!< Instruction 'pcmpestrm' {SSE4_2}.
+    kIdPcmpgtb,                          //!< Instruction 'pcmpgtb' {MMX|SSE2}.
+    kIdPcmpgtd,                          //!< Instruction 'pcmpgtd' {MMX|SSE2}.
+    kIdPcmpgtq,                          //!< Instruction 'pcmpgtq' {SSE4_2}.
+    kIdPcmpgtw,                          //!< Instruction 'pcmpgtw' {MMX|SSE2}.
+    kIdPcmpistri,                        //!< Instruction 'pcmpistri' {SSE4_2}.
+    kIdPcmpistrm,                        //!< Instruction 'pcmpistrm' {SSE4_2}.
+    kIdPconfig,                          //!< Instruction 'pconfig' {PCONFIG}.
+    kIdPdep,                             //!< Instruction 'pdep' {BMI2}.
+    kIdPext,                             //!< Instruction 'pext' {BMI2}.
+    kIdPextrb,                           //!< Instruction 'pextrb' {SSE4_1}.
+    kIdPextrd,                           //!< Instruction 'pextrd' {SSE4_1}.
+    kIdPextrq,                           //!< Instruction 'pextrq' {SSE4_1} (X64).
+    kIdPextrw,                           //!< Instruction 'pextrw' {MMX2|SSE2|SSE4_1}.
+    kIdPf2id,                            //!< Instruction 'pf2id' {3DNOW}.
+    kIdPf2iw,                            //!< Instruction 'pf2iw' {3DNOW2}.
+    kIdPfacc,                            //!< Instruction 'pfacc' {3DNOW}.
+    kIdPfadd,                            //!< Instruction 'pfadd' {3DNOW}.
+    kIdPfcmpeq,                          //!< Instruction 'pfcmpeq' {3DNOW}.
+    kIdPfcmpge,                          //!< Instruction 'pfcmpge' {3DNOW}.
+    kIdPfcmpgt,                          //!< Instruction 'pfcmpgt' {3DNOW}.
+    kIdPfmax,                            //!< Instruction 'pfmax' {3DNOW}.
+    kIdPfmin,                            //!< Instruction 'pfmin' {3DNOW}.
+    kIdPfmul,                            //!< Instruction 'pfmul' {3DNOW}.
+    kIdPfnacc,                           //!< Instruction 'pfnacc' {3DNOW2}.
+    kIdPfpnacc,                          //!< Instruction 'pfpnacc' {3DNOW2}.
+    kIdPfrcp,                            //!< Instruction 'pfrcp' {3DNOW}.
+    kIdPfrcpit1,                         //!< Instruction 'pfrcpit1' {3DNOW}.
+    kIdPfrcpit2,                         //!< Instruction 'pfrcpit2' {3DNOW}.
+    kIdPfrcpv,                           //!< Instruction 'pfrcpv' {GEODE}.
+    kIdPfrsqit1,                         //!< Instruction 'pfrsqit1' {3DNOW}.
+    kIdPfrsqrt,                          //!< Instruction 'pfrsqrt' {3DNOW}.
+    kIdPfrsqrtv,                         //!< Instruction 'pfrsqrtv' {GEODE}.
+    kIdPfsub,                            //!< Instruction 'pfsub' {3DNOW}.
+    kIdPfsubr,                           //!< Instruction 'pfsubr' {3DNOW}.
+    kIdPhaddd,                           //!< Instruction 'phaddd' {SSSE3}.
+    kIdPhaddsw,                          //!< Instruction 'phaddsw' {SSSE3}.
+    kIdPhaddw,                           //!< Instruction 'phaddw' {SSSE3}.
+    kIdPhminposuw,                       //!< Instruction 'phminposuw' {SSE4_1}.
+    kIdPhsubd,                           //!< Instruction 'phsubd' {SSSE3}.
+    kIdPhsubsw,                          //!< Instruction 'phsubsw' {SSSE3}.
+    kIdPhsubw,                           //!< Instruction 'phsubw' {SSSE3}.
+    kIdPi2fd,                            //!< Instruction 'pi2fd' {3DNOW}.
+    kIdPi2fw,                            //!< Instruction 'pi2fw' {3DNOW2}.
+    kIdPinsrb,                           //!< Instruction 'pinsrb' {SSE4_1}.
+    kIdPinsrd,                           //!< Instruction 'pinsrd' {SSE4_1}.
+    kIdPinsrq,                           //!< Instruction 'pinsrq' {SSE4_1} (X64).
+    kIdPinsrw,                           //!< Instruction 'pinsrw' {MMX2|SSE2}.
+    kIdPmaddubsw,                        //!< Instruction 'pmaddubsw' {SSSE3}.
+    kIdPmaddwd,                          //!< Instruction 'pmaddwd' {MMX|SSE2}.
+    kIdPmaxsb,                           //!< Instruction 'pmaxsb' {SSE4_1}.
+    kIdPmaxsd,                           //!< Instruction 'pmaxsd' {SSE4_1}.
+    kIdPmaxsw,                           //!< Instruction 'pmaxsw' {MMX2|SSE2}.
+    kIdPmaxub,                           //!< Instruction 'pmaxub' {MMX2|SSE2}.
+    kIdPmaxud,                           //!< Instruction 'pmaxud' {SSE4_1}.
+    kIdPmaxuw,                           //!< Instruction 'pmaxuw' {SSE4_1}.
+    kIdPminsb,                           //!< Instruction 'pminsb' {SSE4_1}.
+    kIdPminsd,                           //!< Instruction 'pminsd' {SSE4_1}.
+    kIdPminsw,                           //!< Instruction 'pminsw' {MMX2|SSE2}.
+    kIdPminub,                           //!< Instruction 'pminub' {MMX2|SSE2}.
+    kIdPminud,                           //!< Instruction 'pminud' {SSE4_1}.
+    kIdPminuw,                           //!< Instruction 'pminuw' {SSE4_1}.
+    kIdPmovmskb,                         //!< Instruction 'pmovmskb' {MMX2|SSE2}.
+    kIdPmovsxbd,                         //!< Instruction 'pmovsxbd' {SSE4_1}.
+    kIdPmovsxbq,                         //!< Instruction 'pmovsxbq' {SSE4_1}.
+    kIdPmovsxbw,                         //!< Instruction 'pmovsxbw' {SSE4_1}.
+    kIdPmovsxdq,                         //!< Instruction 'pmovsxdq' {SSE4_1}.
+    kIdPmovsxwd,                         //!< Instruction 'pmovsxwd' {SSE4_1}.
+    kIdPmovsxwq,                         //!< Instruction 'pmovsxwq' {SSE4_1}.
+    kIdPmovzxbd,                         //!< Instruction 'pmovzxbd' {SSE4_1}.
+    kIdPmovzxbq,                         //!< Instruction 'pmovzxbq' {SSE4_1}.
+    kIdPmovzxbw,                         //!< Instruction 'pmovzxbw' {SSE4_1}.
+    kIdPmovzxdq,                         //!< Instruction 'pmovzxdq' {SSE4_1}.
+    kIdPmovzxwd,                         //!< Instruction 'pmovzxwd' {SSE4_1}.
+    kIdPmovzxwq,                         //!< Instruction 'pmovzxwq' {SSE4_1}.
+    kIdPmuldq,                           //!< Instruction 'pmuldq' {SSE4_1}.
+    kIdPmulhrsw,                         //!< Instruction 'pmulhrsw' {SSSE3}.
+    kIdPmulhrw,                          //!< Instruction 'pmulhrw' {3DNOW}.
+    kIdPmulhuw,                          //!< Instruction 'pmulhuw' {MMX2|SSE2}.
+    kIdPmulhw,                           //!< Instruction 'pmulhw' {MMX|SSE2}.
+    kIdPmulld,                           //!< Instruction 'pmulld' {SSE4_1}.
+    kIdPmullw,                           //!< Instruction 'pmullw' {MMX|SSE2}.
+    kIdPmuludq,                          //!< Instruction 'pmuludq' {SSE2}.
+    kIdPop,                              //!< Instruction 'pop'.
+    kIdPopa,                             //!< Instruction 'popa' (X86).
+    kIdPopad,                            //!< Instruction 'popad' (X86).
+    kIdPopcnt,                           //!< Instruction 'popcnt' {POPCNT}.
+    kIdPopf,                             //!< Instruction 'popf'.
+    kIdPopfd,                            //!< Instruction 'popfd' (X86).
+    kIdPopfq,                            //!< Instruction 'popfq' (X64).
+    kIdPor,                              //!< Instruction 'por' {MMX|SSE2}.
+    kIdPrefetch,                         //!< Instruction 'prefetch' {3DNOW}.
+    kIdPrefetchnta,                      //!< Instruction 'prefetchnta' {MMX2}.
+    kIdPrefetcht0,                       //!< Instruction 'prefetcht0' {MMX2}.
+    kIdPrefetcht1,                       //!< Instruction 'prefetcht1' {MMX2}.
+    kIdPrefetcht2,                       //!< Instruction 'prefetcht2' {MMX2}.
+    kIdPrefetchw,                        //!< Instruction 'prefetchw' {PREFETCHW}.
+    kIdPrefetchwt1,                      //!< Instruction 'prefetchwt1' {PREFETCHWT1}.
+    kIdPsadbw,                           //!< Instruction 'psadbw' {MMX2|SSE2}.
+    kIdPshufb,                           //!< Instruction 'pshufb' {SSSE3}.
+    kIdPshufd,                           //!< Instruction 'pshufd' {SSE2}.
+    kIdPshufhw,                          //!< Instruction 'pshufhw' {SSE2}.
+    kIdPshuflw,                          //!< Instruction 'pshuflw' {SSE2}.
+    kIdPshufw,                           //!< Instruction 'pshufw' {MMX2}.
+    kIdPsignb,                           //!< Instruction 'psignb' {SSSE3}.
+    kIdPsignd,                           //!< Instruction 'psignd' {SSSE3}.
+    kIdPsignw,                           //!< Instruction 'psignw' {SSSE3}.
+    kIdPslld,                            //!< Instruction 'pslld' {MMX|SSE2}.
+    kIdPslldq,                           //!< Instruction 'pslldq' {SSE2}.
+    kIdPsllq,                            //!< Instruction 'psllq' {MMX|SSE2}.
+    kIdPsllw,                            //!< Instruction 'psllw' {MMX|SSE2}.
+    kIdPsmash,                           //!< Instruction 'psmash' {SNP} (X64).
+    kIdPsrad,                            //!< Instruction 'psrad' {MMX|SSE2}.
+    kIdPsraw,                            //!< Instruction 'psraw' {MMX|SSE2}.
+    kIdPsrld,                            //!< Instruction 'psrld' {MMX|SSE2}.
+    kIdPsrldq,                           //!< Instruction 'psrldq' {SSE2}.
+    kIdPsrlq,                            //!< Instruction 'psrlq' {MMX|SSE2}.
+    kIdPsrlw,                            //!< Instruction 'psrlw' {MMX|SSE2}.
+    kIdPsubb,                            //!< Instruction 'psubb' {MMX|SSE2}.
+    kIdPsubd,                            //!< Instruction 'psubd' {MMX|SSE2}.
+    kIdPsubq,                            //!< Instruction 'psubq' {SSE2}.
+    kIdPsubsb,                           //!< Instruction 'psubsb' {MMX|SSE2}.
+    kIdPsubsw,                           //!< Instruction 'psubsw' {MMX|SSE2}.
+    kIdPsubusb,                          //!< Instruction 'psubusb' {MMX|SSE2}.
+    kIdPsubusw,                          //!< Instruction 'psubusw' {MMX|SSE2}.
+    kIdPsubw,                            //!< Instruction 'psubw' {MMX|SSE2}.
+    kIdPswapd,                           //!< Instruction 'pswapd' {3DNOW2}.
+    kIdPtest,                            //!< Instruction 'ptest' {SSE4_1}.
+    kIdPtwrite,                          //!< Instruction 'ptwrite' {PTWRITE}.
+    kIdPunpckhbw,                        //!< Instruction 'punpckhbw' {MMX|SSE2}.
+    kIdPunpckhdq,                        //!< Instruction 'punpckhdq' {MMX|SSE2}.
+    kIdPunpckhqdq,                       //!< Instruction 'punpckhqdq' {SSE2}.
+    kIdPunpckhwd,                        //!< Instruction 'punpckhwd' {MMX|SSE2}.
+    kIdPunpcklbw,                        //!< Instruction 'punpcklbw' {MMX|SSE2}.
+    kIdPunpckldq,                        //!< Instruction 'punpckldq' {MMX|SSE2}.
+    kIdPunpcklqdq,                       //!< Instruction 'punpcklqdq' {SSE2}.
+    kIdPunpcklwd,                        //!< Instruction 'punpcklwd' {MMX|SSE2}.
+    kIdPush,                             //!< Instruction 'push'.
+    kIdPusha,                            //!< Instruction 'pusha' (X86).
+    kIdPushad,                           //!< Instruction 'pushad' (X86).
+    kIdPushf,                            //!< Instruction 'pushf'.
+    kIdPushfd,                           //!< Instruction 'pushfd' (X86).
+    kIdPushfq,                           //!< Instruction 'pushfq' (X64).
+    kIdPvalidate,                        //!< Instruction 'pvalidate' {SNP}.
+    kIdPxor,                             //!< Instruction 'pxor' {MMX|SSE2}.
+    kIdRcl,                              //!< Instruction 'rcl'.
+    kIdRcpps,                            //!< Instruction 'rcpps' {SSE}.
+    kIdRcpss,                            //!< Instruction 'rcpss' {SSE}.
+    kIdRcr,                              //!< Instruction 'rcr'.
+    kIdRdfsbase,                         //!< Instruction 'rdfsbase' {FSGSBASE} (X64).
+    kIdRdgsbase,                         //!< Instruction 'rdgsbase' {FSGSBASE} (X64).
+    kIdRdmsr,                            //!< Instruction 'rdmsr' {MSR}.
+    kIdRdpid,                            //!< Instruction 'rdpid' {RDPID}.
+    kIdRdpkru,                           //!< Instruction 'rdpkru' {OSPKE}.
+    kIdRdpmc,                            //!< Instruction 'rdpmc'.
+    kIdRdpru,                            //!< Instruction 'rdpru' {RDPRU}.
+    kIdRdrand,                           //!< Instruction 'rdrand' {RDRAND}.
+    kIdRdseed,                           //!< Instruction 'rdseed' {RDSEED}.
+    kIdRdsspd,                           //!< Instruction 'rdsspd' {CET_SS}.
+    kIdRdsspq,                           //!< Instruction 'rdsspq' {CET_SS} (X64).
+    kIdRdtsc,                            //!< Instruction 'rdtsc' {RDTSC}.
+    kIdRdtscp,                           //!< Instruction 'rdtscp' {RDTSCP}.
+    kIdRet,                              //!< Instruction 'ret'.
+    kIdRmpadjust,                        //!< Instruction 'rmpadjust' {SNP} (X64).
+    kIdRmpupdate,                        //!< Instruction 'rmpupdate' {SNP} (X64).
+    kIdRol,                              //!< Instruction 'rol'.
+    kIdRor,                              //!< Instruction 'ror'.
+    kIdRorx,                             //!< Instruction 'rorx' {BMI2}.
+    kIdRoundpd,                          //!< Instruction 'roundpd' {SSE4_1}.
+    kIdRoundps,                          //!< Instruction 'roundps' {SSE4_1}.
+    kIdRoundsd,                          //!< Instruction 'roundsd' {SSE4_1}.
+    kIdRoundss,                          //!< Instruction 'roundss' {SSE4_1}.
+    kIdRsm,                              //!< Instruction 'rsm' (X86).
+    kIdRsqrtps,                          //!< Instruction 'rsqrtps' {SSE}.
+    kIdRsqrtss,                          //!< Instruction 'rsqrtss' {SSE}.
+    kIdRstorssp,                         //!< Instruction 'rstorssp' {CET_SS}.
+    kIdSahf,                             //!< Instruction 'sahf' {LAHFSAHF}.
+    kIdSal,                              //!< Instruction 'sal'.
+    kIdSar,                              //!< Instruction 'sar'.
+    kIdSarx,                             //!< Instruction 'sarx' {BMI2}.
+    kIdSaveprevssp,                      //!< Instruction 'saveprevssp' {CET_SS}.
+    kIdSbb,                              //!< Instruction 'sbb'.
+    kIdScas,                             //!< Instruction 'scas'.
+    kIdSerialize,                        //!< Instruction 'serialize' {SERIALIZE}.
+    kIdSeta,                             //!< Instruction 'seta'.
+    kIdSetae,                            //!< Instruction 'setae'.
+    kIdSetb,                             //!< Instruction 'setb'.
+    kIdSetbe,                            //!< Instruction 'setbe'.
+    kIdSetc,                             //!< Instruction 'setc'.
+    kIdSete,                             //!< Instruction 'sete'.
+    kIdSetg,                             //!< Instruction 'setg'.
+    kIdSetge,                            //!< Instruction 'setge'.
+    kIdSetl,                             //!< Instruction 'setl'.
+    kIdSetle,                            //!< Instruction 'setle'.
+    kIdSetna,                            //!< Instruction 'setna'.
+    kIdSetnae,                           //!< Instruction 'setnae'.
+    kIdSetnb,                            //!< Instruction 'setnb'.
+    kIdSetnbe,                           //!< Instruction 'setnbe'.
+    kIdSetnc,                            //!< Instruction 'setnc'.
+    kIdSetne,                            //!< Instruction 'setne'.
+    kIdSetng,                            //!< Instruction 'setng'.
+    kIdSetnge,                           //!< Instruction 'setnge'.
+    kIdSetnl,                            //!< Instruction 'setnl'.
+    kIdSetnle,                           //!< Instruction 'setnle'.
+    kIdSetno,                            //!< Instruction 'setno'.
+    kIdSetnp,                            //!< Instruction 'setnp'.
+    kIdSetns,                            //!< Instruction 'setns'.
+    kIdSetnz,                            //!< Instruction 'setnz'.
+    kIdSeto,                             //!< Instruction 'seto'.
+    kIdSetp,                             //!< Instruction 'setp'.
+    kIdSetpe,                            //!< Instruction 'setpe'.
+    kIdSetpo,                            //!< Instruction 'setpo'.
+    kIdSets,                             //!< Instruction 'sets'.
+    kIdSetssbsy,                         //!< Instruction 'setssbsy' {CET_SS}.
+    kIdSetz,                             //!< Instruction 'setz'.
+    kIdSfence,                           //!< Instruction 'sfence' {MMX2}.
+    kIdSgdt,                             //!< Instruction 'sgdt'.
+    kIdSha1msg1,                         //!< Instruction 'sha1msg1' {SHA}.
+    kIdSha1msg2,                         //!< Instruction 'sha1msg2' {SHA}.
+    kIdSha1nexte,                        //!< Instruction 'sha1nexte' {SHA}.
+    kIdSha1rnds4,                        //!< Instruction 'sha1rnds4' {SHA}.
+    kIdSha256msg1,                       //!< Instruction 'sha256msg1' {SHA}.
+    kIdSha256msg2,                       //!< Instruction 'sha256msg2' {SHA}.
+    kIdSha256rnds2,                      //!< Instruction 'sha256rnds2' {SHA}.
+    kIdShl,                              //!< Instruction 'shl'.
+    kIdShld,                             //!< Instruction 'shld'.
+    kIdShlx,                             //!< Instruction 'shlx' {BMI2}.
+    kIdShr,                              //!< Instruction 'shr'.
+    kIdShrd,                             //!< Instruction 'shrd'.
+    kIdShrx,                             //!< Instruction 'shrx' {BMI2}.
+    kIdShufpd,                           //!< Instruction 'shufpd' {SSE2}.
+    kIdShufps,                           //!< Instruction 'shufps' {SSE}.
+    kIdSidt,                             //!< Instruction 'sidt'.
+    kIdSkinit,                           //!< Instruction 'skinit' {SKINIT}.
+    kIdSldt,                             //!< Instruction 'sldt'.
+    kIdSlwpcb,                           //!< Instruction 'slwpcb' {LWP}.
+    kIdSmsw,                             //!< Instruction 'smsw'.
+    kIdSqrtpd,                           //!< Instruction 'sqrtpd' {SSE2}.
+    kIdSqrtps,                           //!< Instruction 'sqrtps' {SSE}.
+    kIdSqrtsd,                           //!< Instruction 'sqrtsd' {SSE2}.
+    kIdSqrtss,                           //!< Instruction 'sqrtss' {SSE}.
+    kIdStac,                             //!< Instruction 'stac' {SMAP}.
+    kIdStc,                              //!< Instruction 'stc'.
+    kIdStd,                              //!< Instruction 'std'.
+    kIdStgi,                             //!< Instruction 'stgi' {SKINIT}.
+    kIdSti,                              //!< Instruction 'sti'.
+    kIdStmxcsr,                          //!< Instruction 'stmxcsr' {SSE}.
+    kIdStos,                             //!< Instruction 'stos'.
+    kIdStr,                              //!< Instruction 'str'.
+    kIdSttilecfg,                        //!< Instruction 'sttilecfg' {AMX_TILE} (X64).
+    kIdSub,                              //!< Instruction 'sub'.
+    kIdSubpd,                            //!< Instruction 'subpd' {SSE2}.
+    kIdSubps,                            //!< Instruction 'subps' {SSE}.
+    kIdSubsd,                            //!< Instruction 'subsd' {SSE2}.
+    kIdSubss,                            //!< Instruction 'subss' {SSE}.
+    kIdSwapgs,                           //!< Instruction 'swapgs' (X64).
+    kIdSyscall,                          //!< Instruction 'syscall' (X64).
+    kIdSysenter,                         //!< Instruction 'sysenter'.
+    kIdSysexit,                          //!< Instruction 'sysexit'.
+    kIdSysexit64,                        //!< Instruction 'sysexit64'.
+    kIdSysret,                           //!< Instruction 'sysret' (X64).
+    kIdSysret64,                         //!< Instruction 'sysret64' (X64).
+    kIdT1mskc,                           //!< Instruction 't1mskc' {TBM}.
+    kIdTdpbf16ps,                        //!< Instruction 'tdpbf16ps' {AMX_BF16} (X64).
+    kIdTdpbssd,                          //!< Instruction 'tdpbssd' {AMX_INT8} (X64).
+    kIdTdpbsud,                          //!< Instruction 'tdpbsud' {AMX_INT8} (X64).
+    kIdTdpbusd,                          //!< Instruction 'tdpbusd' {AMX_INT8} (X64).
+    kIdTdpbuud,                          //!< Instruction 'tdpbuud' {AMX_INT8} (X64).
+    kIdTest,                             //!< Instruction 'test'.
+    kIdTileloadd,                        //!< Instruction 'tileloadd' {AMX_TILE} (X64).
+    kIdTileloaddt1,                      //!< Instruction 'tileloaddt1' {AMX_TILE} (X64).
+    kIdTilerelease,                      //!< Instruction 'tilerelease' {AMX_TILE} (X64).
+    kIdTilestored,                       //!< Instruction 'tilestored' {AMX_TILE} (X64).
+    kIdTilezero,                         //!< Instruction 'tilezero' {AMX_TILE} (X64).
+    kIdTpause,                           //!< Instruction 'tpause' {WAITPKG}.
+    kIdTzcnt,                            //!< Instruction 'tzcnt' {BMI}.
+    kIdTzmsk,                            //!< Instruction 'tzmsk' {TBM}.
+    kIdUcomisd,                          //!< Instruction 'ucomisd' {SSE2}.
+    kIdUcomiss,                          //!< Instruction 'ucomiss' {SSE}.
+    kIdUd0,                              //!< Instruction 'ud0'.
+    kIdUd1,                              //!< Instruction 'ud1'.
+    kIdUd2,                              //!< Instruction 'ud2'.
+    kIdUmonitor,                         //!< Instruction 'umonitor' {WAITPKG}.
+    kIdUmwait,                           //!< Instruction 'umwait' {WAITPKG}.
+    kIdUnpckhpd,                         //!< Instruction 'unpckhpd' {SSE2}.
+    kIdUnpckhps,                         //!< Instruction 'unpckhps' {SSE}.
+    kIdUnpcklpd,                         //!< Instruction 'unpcklpd' {SSE2}.
+    kIdUnpcklps,                         //!< Instruction 'unpcklps' {SSE}.
+    kIdV4fmaddps,                        //!< Instruction 'v4fmaddps' {AVX512_4FMAPS}.
+    kIdV4fmaddss,                        //!< Instruction 'v4fmaddss' {AVX512_4FMAPS}.
+    kIdV4fnmaddps,                       //!< Instruction 'v4fnmaddps' {AVX512_4FMAPS}.
+    kIdV4fnmaddss,                       //!< Instruction 'v4fnmaddss' {AVX512_4FMAPS}.
+    kIdVaddpd,                           //!< Instruction 'vaddpd' {AVX|AVX512_F+VL}.
+    kIdVaddps,                           //!< Instruction 'vaddps' {AVX|AVX512_F+VL}.
+    kIdVaddsd,                           //!< Instruction 'vaddsd' {AVX|AVX512_F}.
+    kIdVaddss,                           //!< Instruction 'vaddss' {AVX|AVX512_F}.
+    kIdVaddsubpd,                        //!< Instruction 'vaddsubpd' {AVX}.
+    kIdVaddsubps,                        //!< Instruction 'vaddsubps' {AVX}.
+    kIdVaesdec,                          //!< Instruction 'vaesdec' {AVX|AVX512_F+VL & AESNI|VAES}.
+    kIdVaesdeclast,                      //!< Instruction 'vaesdeclast' {AVX|AVX512_F+VL & AESNI|VAES}.
+    kIdVaesenc,                          //!< Instruction 'vaesenc' {AVX|AVX512_F+VL & AESNI|VAES}.
+    kIdVaesenclast,                      //!< Instruction 'vaesenclast' {AVX|AVX512_F+VL & AESNI|VAES}.
+    kIdVaesimc,                          //!< Instruction 'vaesimc' {AVX & AESNI}.
+    kIdVaeskeygenassist,                 //!< Instruction 'vaeskeygenassist' {AVX & AESNI}.
+    kIdValignd,                          //!< Instruction 'valignd' {AVX512_F+VL}.
+    kIdValignq,                          //!< Instruction 'valignq' {AVX512_F+VL}.
+    kIdVandnpd,                          //!< Instruction 'vandnpd' {AVX|AVX512_DQ+VL}.
+    kIdVandnps,                          //!< Instruction 'vandnps' {AVX|AVX512_DQ+VL}.
+    kIdVandpd,                           //!< Instruction 'vandpd' {AVX|AVX512_DQ+VL}.
+    kIdVandps,                           //!< Instruction 'vandps' {AVX|AVX512_DQ+VL}.
+    kIdVblendmb,                         //!< Instruction 'vblendmb' {AVX512_BW+VL}.
+    kIdVblendmd,                         //!< Instruction 'vblendmd' {AVX512_F+VL}.
+    kIdVblendmpd,                        //!< Instruction 'vblendmpd' {AVX512_F+VL}.
+    kIdVblendmps,                        //!< Instruction 'vblendmps' {AVX512_F+VL}.
+    kIdVblendmq,                         //!< Instruction 'vblendmq' {AVX512_F+VL}.
+    kIdVblendmw,                         //!< Instruction 'vblendmw' {AVX512_BW+VL}.
+    kIdVblendpd,                         //!< Instruction 'vblendpd' {AVX}.
+    kIdVblendps,                         //!< Instruction 'vblendps' {AVX}.
+    kIdVblendvpd,                        //!< Instruction 'vblendvpd' {AVX}.
+    kIdVblendvps,                        //!< Instruction 'vblendvps' {AVX}.
+    kIdVbroadcastf128,                   //!< Instruction 'vbroadcastf128' {AVX}.
+    kIdVbroadcastf32x2,                  //!< Instruction 'vbroadcastf32x2' {AVX512_DQ+VL}.
+    kIdVbroadcastf32x4,                  //!< Instruction 'vbroadcastf32x4' {AVX512_F}.
+    kIdVbroadcastf32x8,                  //!< Instruction 'vbroadcastf32x8' {AVX512_DQ}.
+    kIdVbroadcastf64x2,                  //!< Instruction 'vbroadcastf64x2' {AVX512_DQ+VL}.
+    kIdVbroadcastf64x4,                  //!< Instruction 'vbroadcastf64x4' {AVX512_F}.
+    kIdVbroadcasti128,                   //!< Instruction 'vbroadcasti128' {AVX2}.
+    kIdVbroadcasti32x2,                  //!< Instruction 'vbroadcasti32x2' {AVX512_DQ+VL}.
+    kIdVbroadcasti32x4,                  //!< Instruction 'vbroadcasti32x4' {AVX512_F+VL}.
+    kIdVbroadcasti32x8,                  //!< Instruction 'vbroadcasti32x8' {AVX512_DQ}.
+    kIdVbroadcasti64x2,                  //!< Instruction 'vbroadcasti64x2' {AVX512_DQ+VL}.
+    kIdVbroadcasti64x4,                  //!< Instruction 'vbroadcasti64x4' {AVX512_F}.
+    kIdVbroadcastsd,                     //!< Instruction 'vbroadcastsd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVbroadcastss,                     //!< Instruction 'vbroadcastss' {AVX|AVX2|AVX512_F+VL}.
+    kIdVcmppd,                           //!< Instruction 'vcmppd' {AVX|AVX512_F+VL}.
+    kIdVcmpps,                           //!< Instruction 'vcmpps' {AVX|AVX512_F+VL}.
+    kIdVcmpsd,                           //!< Instruction 'vcmpsd' {AVX|AVX512_F}.
+    kIdVcmpss,                           //!< Instruction 'vcmpss' {AVX|AVX512_F}.
+    kIdVcomisd,                          //!< Instruction 'vcomisd' {AVX|AVX512_F}.
+    kIdVcomiss,                          //!< Instruction 'vcomiss' {AVX|AVX512_F}.
+    kIdVcompresspd,                      //!< Instruction 'vcompresspd' {AVX512_F+VL}.
+    kIdVcompressps,                      //!< Instruction 'vcompressps' {AVX512_F+VL}.
+    kIdVcvtdq2pd,                        //!< Instruction 'vcvtdq2pd' {AVX|AVX512_F+VL}.
+    kIdVcvtdq2ps,                        //!< Instruction 'vcvtdq2ps' {AVX|AVX512_F+VL}.
+    kIdVcvtne2ps2bf16,                   //!< Instruction 'vcvtne2ps2bf16' {AVX512_BF16+VL}.
+    kIdVcvtneps2bf16,                    //!< Instruction 'vcvtneps2bf16' {AVX512_BF16+VL}.
+    kIdVcvtpd2dq,                        //!< Instruction 'vcvtpd2dq' {AVX|AVX512_F+VL}.
+    kIdVcvtpd2ps,                        //!< Instruction 'vcvtpd2ps' {AVX|AVX512_F+VL}.
+    kIdVcvtpd2qq,                        //!< Instruction 'vcvtpd2qq' {AVX512_DQ+VL}.
+    kIdVcvtpd2udq,                       //!< Instruction 'vcvtpd2udq' {AVX512_F+VL}.
+    kIdVcvtpd2uqq,                       //!< Instruction 'vcvtpd2uqq' {AVX512_DQ+VL}.
+    kIdVcvtph2ps,                        //!< Instruction 'vcvtph2ps' {AVX512_F+VL & F16C}.
+    kIdVcvtps2dq,                        //!< Instruction 'vcvtps2dq' {AVX|AVX512_F+VL}.
+    kIdVcvtps2pd,                        //!< Instruction 'vcvtps2pd' {AVX|AVX512_F+VL}.
+    kIdVcvtps2ph,                        //!< Instruction 'vcvtps2ph' {AVX512_F+VL & F16C}.
+    kIdVcvtps2qq,                        //!< Instruction 'vcvtps2qq' {AVX512_DQ+VL}.
+    kIdVcvtps2udq,                       //!< Instruction 'vcvtps2udq' {AVX512_F+VL}.
+    kIdVcvtps2uqq,                       //!< Instruction 'vcvtps2uqq' {AVX512_DQ+VL}.
+    kIdVcvtqq2pd,                        //!< Instruction 'vcvtqq2pd' {AVX512_DQ+VL}.
+    kIdVcvtqq2ps,                        //!< Instruction 'vcvtqq2ps' {AVX512_DQ+VL}.
+    kIdVcvtsd2si,                        //!< Instruction 'vcvtsd2si' {AVX|AVX512_F}.
+    kIdVcvtsd2ss,                        //!< Instruction 'vcvtsd2ss' {AVX|AVX512_F}.
+    kIdVcvtsd2usi,                       //!< Instruction 'vcvtsd2usi' {AVX512_F}.
+    kIdVcvtsi2sd,                        //!< Instruction 'vcvtsi2sd' {AVX|AVX512_F}.
+    kIdVcvtsi2ss,                        //!< Instruction 'vcvtsi2ss' {AVX|AVX512_F}.
+    kIdVcvtss2sd,                        //!< Instruction 'vcvtss2sd' {AVX|AVX512_F}.
+    kIdVcvtss2si,                        //!< Instruction 'vcvtss2si' {AVX|AVX512_F}.
+    kIdVcvtss2usi,                       //!< Instruction 'vcvtss2usi' {AVX512_F}.
+    kIdVcvttpd2dq,                       //!< Instruction 'vcvttpd2dq' {AVX|AVX512_F+VL}.
+    kIdVcvttpd2qq,                       //!< Instruction 'vcvttpd2qq' {AVX512_F+VL}.
+    kIdVcvttpd2udq,                      //!< Instruction 'vcvttpd2udq' {AVX512_F+VL}.
+    kIdVcvttpd2uqq,                      //!< Instruction 'vcvttpd2uqq' {AVX512_DQ+VL}.
+    kIdVcvttps2dq,                       //!< Instruction 'vcvttps2dq' {AVX|AVX512_F+VL}.
+    kIdVcvttps2qq,                       //!< Instruction 'vcvttps2qq' {AVX512_DQ+VL}.
+    kIdVcvttps2udq,                      //!< Instruction 'vcvttps2udq' {AVX512_F+VL}.
+    kIdVcvttps2uqq,                      //!< Instruction 'vcvttps2uqq' {AVX512_DQ+VL}.
+    kIdVcvttsd2si,                       //!< Instruction 'vcvttsd2si' {AVX|AVX512_F}.
+    kIdVcvttsd2usi,                      //!< Instruction 'vcvttsd2usi' {AVX512_F}.
+    kIdVcvttss2si,                       //!< Instruction 'vcvttss2si' {AVX|AVX512_F}.
+    kIdVcvttss2usi,                      //!< Instruction 'vcvttss2usi' {AVX512_F}.
+    kIdVcvtudq2pd,                       //!< Instruction 'vcvtudq2pd' {AVX512_F+VL}.
+    kIdVcvtudq2ps,                       //!< Instruction 'vcvtudq2ps' {AVX512_F+VL}.
+    kIdVcvtuqq2pd,                       //!< Instruction 'vcvtuqq2pd' {AVX512_DQ+VL}.
+    kIdVcvtuqq2ps,                       //!< Instruction 'vcvtuqq2ps' {AVX512_DQ+VL}.
+    kIdVcvtusi2sd,                       //!< Instruction 'vcvtusi2sd' {AVX512_F}.
+    kIdVcvtusi2ss,                       //!< Instruction 'vcvtusi2ss' {AVX512_F}.
+    kIdVdbpsadbw,                        //!< Instruction 'vdbpsadbw' {AVX512_BW+VL}.
+    kIdVdivpd,                           //!< Instruction 'vdivpd' {AVX|AVX512_F+VL}.
+    kIdVdivps,                           //!< Instruction 'vdivps' {AVX|AVX512_F+VL}.
+    kIdVdivsd,                           //!< Instruction 'vdivsd' {AVX|AVX512_F}.
+    kIdVdivss,                           //!< Instruction 'vdivss' {AVX|AVX512_F}.
+    kIdVdpbf16ps,                        //!< Instruction 'vdpbf16ps' {AVX512_BF16+VL}.
+    kIdVdppd,                            //!< Instruction 'vdppd' {AVX}.
+    kIdVdpps,                            //!< Instruction 'vdpps' {AVX}.
+    kIdVerr,                             //!< Instruction 'verr'.
+    kIdVerw,                             //!< Instruction 'verw'.
+    kIdVexp2pd,                          //!< Instruction 'vexp2pd' {AVX512_ERI}.
+    kIdVexp2ps,                          //!< Instruction 'vexp2ps' {AVX512_ERI}.
+    kIdVexpandpd,                        //!< Instruction 'vexpandpd' {AVX512_F+VL}.
+    kIdVexpandps,                        //!< Instruction 'vexpandps' {AVX512_F+VL}.
+    kIdVextractf128,                     //!< Instruction 'vextractf128' {AVX}.
+    kIdVextractf32x4,                    //!< Instruction 'vextractf32x4' {AVX512_F+VL}.
+    kIdVextractf32x8,                    //!< Instruction 'vextractf32x8' {AVX512_DQ}.
+    kIdVextractf64x2,                    //!< Instruction 'vextractf64x2' {AVX512_DQ+VL}.
+    kIdVextractf64x4,                    //!< Instruction 'vextractf64x4' {AVX512_F}.
+    kIdVextracti128,                     //!< Instruction 'vextracti128' {AVX2}.
+    kIdVextracti32x4,                    //!< Instruction 'vextracti32x4' {AVX512_F+VL}.
+    kIdVextracti32x8,                    //!< Instruction 'vextracti32x8' {AVX512_DQ}.
+    kIdVextracti64x2,                    //!< Instruction 'vextracti64x2' {AVX512_DQ+VL}.
+    kIdVextracti64x4,                    //!< Instruction 'vextracti64x4' {AVX512_F}.
+    kIdVextractps,                       //!< Instruction 'vextractps' {AVX|AVX512_F}.
+    kIdVfixupimmpd,                      //!< Instruction 'vfixupimmpd' {AVX512_F+VL}.
+    kIdVfixupimmps,                      //!< Instruction 'vfixupimmps' {AVX512_F+VL}.
+    kIdVfixupimmsd,                      //!< Instruction 'vfixupimmsd' {AVX512_F}.
+    kIdVfixupimmss,                      //!< Instruction 'vfixupimmss' {AVX512_F}.
+    kIdVfmadd132pd,                      //!< Instruction 'vfmadd132pd' {FMA|AVX512_F+VL}.
+    kIdVfmadd132ps,                      //!< Instruction 'vfmadd132ps' {FMA|AVX512_F+VL}.
+    kIdVfmadd132sd,                      //!< Instruction 'vfmadd132sd' {FMA|AVX512_F}.
+    kIdVfmadd132ss,                      //!< Instruction 'vfmadd132ss' {FMA|AVX512_F}.
+    kIdVfmadd213pd,                      //!< Instruction 'vfmadd213pd' {FMA|AVX512_F+VL}.
+    kIdVfmadd213ps,                      //!< Instruction 'vfmadd213ps' {FMA|AVX512_F+VL}.
+    kIdVfmadd213sd,                      //!< Instruction 'vfmadd213sd' {FMA|AVX512_F}.
+    kIdVfmadd213ss,                      //!< Instruction 'vfmadd213ss' {FMA|AVX512_F}.
+    kIdVfmadd231pd,                      //!< Instruction 'vfmadd231pd' {FMA|AVX512_F+VL}.
+    kIdVfmadd231ps,                      //!< Instruction 'vfmadd231ps' {FMA|AVX512_F+VL}.
+    kIdVfmadd231sd,                      //!< Instruction 'vfmadd231sd' {FMA|AVX512_F}.
+    kIdVfmadd231ss,                      //!< Instruction 'vfmadd231ss' {FMA|AVX512_F}.
+    kIdVfmaddpd,                         //!< Instruction 'vfmaddpd' {FMA4}.
+    kIdVfmaddps,                         //!< Instruction 'vfmaddps' {FMA4}.
+    kIdVfmaddsd,                         //!< Instruction 'vfmaddsd' {FMA4}.
+    kIdVfmaddss,                         //!< Instruction 'vfmaddss' {FMA4}.
+    kIdVfmaddsub132pd,                   //!< Instruction 'vfmaddsub132pd' {FMA|AVX512_F+VL}.
+    kIdVfmaddsub132ps,                   //!< Instruction 'vfmaddsub132ps' {FMA|AVX512_F+VL}.
+    kIdVfmaddsub213pd,                   //!< Instruction 'vfmaddsub213pd' {FMA|AVX512_F+VL}.
+    kIdVfmaddsub213ps,                   //!< Instruction 'vfmaddsub213ps' {FMA|AVX512_F+VL}.
+    kIdVfmaddsub231pd,                   //!< Instruction 'vfmaddsub231pd' {FMA|AVX512_F+VL}.
+    kIdVfmaddsub231ps,                   //!< Instruction 'vfmaddsub231ps' {FMA|AVX512_F+VL}.
+    kIdVfmaddsubpd,                      //!< Instruction 'vfmaddsubpd' {FMA4}.
+    kIdVfmaddsubps,                      //!< Instruction 'vfmaddsubps' {FMA4}.
+    kIdVfmsub132pd,                      //!< Instruction 'vfmsub132pd' {FMA|AVX512_F+VL}.
+    kIdVfmsub132ps,                      //!< Instruction 'vfmsub132ps' {FMA|AVX512_F+VL}.
+    kIdVfmsub132sd,                      //!< Instruction 'vfmsub132sd' {FMA|AVX512_F}.
+    kIdVfmsub132ss,                      //!< Instruction 'vfmsub132ss' {FMA|AVX512_F}.
+    kIdVfmsub213pd,                      //!< Instruction 'vfmsub213pd' {FMA|AVX512_F+VL}.
+    kIdVfmsub213ps,                      //!< Instruction 'vfmsub213ps' {FMA|AVX512_F+VL}.
+    kIdVfmsub213sd,                      //!< Instruction 'vfmsub213sd' {FMA|AVX512_F}.
+    kIdVfmsub213ss,                      //!< Instruction 'vfmsub213ss' {FMA|AVX512_F}.
+    kIdVfmsub231pd,                      //!< Instruction 'vfmsub231pd' {FMA|AVX512_F+VL}.
+    kIdVfmsub231ps,                      //!< Instruction 'vfmsub231ps' {FMA|AVX512_F+VL}.
+    kIdVfmsub231sd,                      //!< Instruction 'vfmsub231sd' {FMA|AVX512_F}.
+    kIdVfmsub231ss,                      //!< Instruction 'vfmsub231ss' {FMA|AVX512_F}.
+    kIdVfmsubadd132pd,                   //!< Instruction 'vfmsubadd132pd' {FMA|AVX512_F+VL}.
+    kIdVfmsubadd132ps,                   //!< Instruction 'vfmsubadd132ps' {FMA|AVX512_F+VL}.
+    kIdVfmsubadd213pd,                   //!< Instruction 'vfmsubadd213pd' {FMA|AVX512_F+VL}.
+    kIdVfmsubadd213ps,                   //!< Instruction 'vfmsubadd213ps' {FMA|AVX512_F+VL}.
+    kIdVfmsubadd231pd,                   //!< Instruction 'vfmsubadd231pd' {FMA|AVX512_F+VL}.
+    kIdVfmsubadd231ps,                   //!< Instruction 'vfmsubadd231ps' {FMA|AVX512_F+VL}.
+    kIdVfmsubaddpd,                      //!< Instruction 'vfmsubaddpd' {FMA4}.
+    kIdVfmsubaddps,                      //!< Instruction 'vfmsubaddps' {FMA4}.
+    kIdVfmsubpd,                         //!< Instruction 'vfmsubpd' {FMA4}.
+    kIdVfmsubps,                         //!< Instruction 'vfmsubps' {FMA4}.
+    kIdVfmsubsd,                         //!< Instruction 'vfmsubsd' {FMA4}.
+    kIdVfmsubss,                         //!< Instruction 'vfmsubss' {FMA4}.
+    kIdVfnmadd132pd,                     //!< Instruction 'vfnmadd132pd' {FMA|AVX512_F+VL}.
+    kIdVfnmadd132ps,                     //!< Instruction 'vfnmadd132ps' {FMA|AVX512_F+VL}.
+    kIdVfnmadd132sd,                     //!< Instruction 'vfnmadd132sd' {FMA|AVX512_F}.
+    kIdVfnmadd132ss,                     //!< Instruction 'vfnmadd132ss' {FMA|AVX512_F}.
+    kIdVfnmadd213pd,                     //!< Instruction 'vfnmadd213pd' {FMA|AVX512_F+VL}.
+    kIdVfnmadd213ps,                     //!< Instruction 'vfnmadd213ps' {FMA|AVX512_F+VL}.
+    kIdVfnmadd213sd,                     //!< Instruction 'vfnmadd213sd' {FMA|AVX512_F}.
+    kIdVfnmadd213ss,                     //!< Instruction 'vfnmadd213ss' {FMA|AVX512_F}.
+    kIdVfnmadd231pd,                     //!< Instruction 'vfnmadd231pd' {FMA|AVX512_F+VL}.
+    kIdVfnmadd231ps,                     //!< Instruction 'vfnmadd231ps' {FMA|AVX512_F+VL}.
+    kIdVfnmadd231sd,                     //!< Instruction 'vfnmadd231sd' {FMA|AVX512_F}.
+    kIdVfnmadd231ss,                     //!< Instruction 'vfnmadd231ss' {FMA|AVX512_F}.
+    kIdVfnmaddpd,                        //!< Instruction 'vfnmaddpd' {FMA4}.
+    kIdVfnmaddps,                        //!< Instruction 'vfnmaddps' {FMA4}.
+    kIdVfnmaddsd,                        //!< Instruction 'vfnmaddsd' {FMA4}.
+    kIdVfnmaddss,                        //!< Instruction 'vfnmaddss' {FMA4}.
+    kIdVfnmsub132pd,                     //!< Instruction 'vfnmsub132pd' {FMA|AVX512_F+VL}.
+    kIdVfnmsub132ps,                     //!< Instruction 'vfnmsub132ps' {FMA|AVX512_F+VL}.
+    kIdVfnmsub132sd,                     //!< Instruction 'vfnmsub132sd' {FMA|AVX512_F}.
+    kIdVfnmsub132ss,                     //!< Instruction 'vfnmsub132ss' {FMA|AVX512_F}.
+    kIdVfnmsub213pd,                     //!< Instruction 'vfnmsub213pd' {FMA|AVX512_F+VL}.
+    kIdVfnmsub213ps,                     //!< Instruction 'vfnmsub213ps' {FMA|AVX512_F+VL}.
+    kIdVfnmsub213sd,                     //!< Instruction 'vfnmsub213sd' {FMA|AVX512_F}.
+    kIdVfnmsub213ss,                     //!< Instruction 'vfnmsub213ss' {FMA|AVX512_F}.
+    kIdVfnmsub231pd,                     //!< Instruction 'vfnmsub231pd' {FMA|AVX512_F+VL}.
+    kIdVfnmsub231ps,                     //!< Instruction 'vfnmsub231ps' {FMA|AVX512_F+VL}.
+    kIdVfnmsub231sd,                     //!< Instruction 'vfnmsub231sd' {FMA|AVX512_F}.
+    kIdVfnmsub231ss,                     //!< Instruction 'vfnmsub231ss' {FMA|AVX512_F}.
+    kIdVfnmsubpd,                        //!< Instruction 'vfnmsubpd' {FMA4}.
+    kIdVfnmsubps,                        //!< Instruction 'vfnmsubps' {FMA4}.
+    kIdVfnmsubsd,                        //!< Instruction 'vfnmsubsd' {FMA4}.
+    kIdVfnmsubss,                        //!< Instruction 'vfnmsubss' {FMA4}.
+    kIdVfpclasspd,                       //!< Instruction 'vfpclasspd' {AVX512_DQ+VL}.
+    kIdVfpclassps,                       //!< Instruction 'vfpclassps' {AVX512_DQ+VL}.
+    kIdVfpclasssd,                       //!< Instruction 'vfpclasssd' {AVX512_DQ}.
+    kIdVfpclassss,                       //!< Instruction 'vfpclassss' {AVX512_DQ}.
+    kIdVfrczpd,                          //!< Instruction 'vfrczpd' {XOP}.
+    kIdVfrczps,                          //!< Instruction 'vfrczps' {XOP}.
+    kIdVfrczsd,                          //!< Instruction 'vfrczsd' {XOP}.
+    kIdVfrczss,                          //!< Instruction 'vfrczss' {XOP}.
+    kIdVgatherdpd,                       //!< Instruction 'vgatherdpd' {AVX2|AVX512_F+VL}.
+    kIdVgatherdps,                       //!< Instruction 'vgatherdps' {AVX2|AVX512_F+VL}.
+    kIdVgatherpf0dpd,                    //!< Instruction 'vgatherpf0dpd' {AVX512_PFI}.
+    kIdVgatherpf0dps,                    //!< Instruction 'vgatherpf0dps' {AVX512_PFI}.
+    kIdVgatherpf0qpd,                    //!< Instruction 'vgatherpf0qpd' {AVX512_PFI}.
+    kIdVgatherpf0qps,                    //!< Instruction 'vgatherpf0qps' {AVX512_PFI}.
+    kIdVgatherpf1dpd,                    //!< Instruction 'vgatherpf1dpd' {AVX512_PFI}.
+    kIdVgatherpf1dps,                    //!< Instruction 'vgatherpf1dps' {AVX512_PFI}.
+    kIdVgatherpf1qpd,                    //!< Instruction 'vgatherpf1qpd' {AVX512_PFI}.
+    kIdVgatherpf1qps,                    //!< Instruction 'vgatherpf1qps' {AVX512_PFI}.
+    kIdVgatherqpd,                       //!< Instruction 'vgatherqpd' {AVX2|AVX512_F+VL}.
+    kIdVgatherqps,                       //!< Instruction 'vgatherqps' {AVX2|AVX512_F+VL}.
+    kIdVgetexppd,                        //!< Instruction 'vgetexppd' {AVX512_F+VL}.
+    kIdVgetexpps,                        //!< Instruction 'vgetexpps' {AVX512_F+VL}.
+    kIdVgetexpsd,                        //!< Instruction 'vgetexpsd' {AVX512_F}.
+    kIdVgetexpss,                        //!< Instruction 'vgetexpss' {AVX512_F}.
+    kIdVgetmantpd,                       //!< Instruction 'vgetmantpd' {AVX512_F+VL}.
+    kIdVgetmantps,                       //!< Instruction 'vgetmantps' {AVX512_F+VL}.
+    kIdVgetmantsd,                       //!< Instruction 'vgetmantsd' {AVX512_F}.
+    kIdVgetmantss,                       //!< Instruction 'vgetmantss' {AVX512_F}.
+    kIdVgf2p8affineinvqb,                //!< Instruction 'vgf2p8affineinvqb' {AVX|AVX512_F+VL & GFNI}.
+    kIdVgf2p8affineqb,                   //!< Instruction 'vgf2p8affineqb' {AVX|AVX512_F+VL & GFNI}.
+    kIdVgf2p8mulb,                       //!< Instruction 'vgf2p8mulb' {AVX|AVX512_F+VL & GFNI}.
+    kIdVhaddpd,                          //!< Instruction 'vhaddpd' {AVX}.
+    kIdVhaddps,                          //!< Instruction 'vhaddps' {AVX}.
+    kIdVhsubpd,                          //!< Instruction 'vhsubpd' {AVX}.
+    kIdVhsubps,                          //!< Instruction 'vhsubps' {AVX}.
+    kIdVinsertf128,                      //!< Instruction 'vinsertf128' {AVX}.
+    kIdVinsertf32x4,                     //!< Instruction 'vinsertf32x4' {AVX512_F+VL}.
+    kIdVinsertf32x8,                     //!< Instruction 'vinsertf32x8' {AVX512_DQ}.
+    kIdVinsertf64x2,                     //!< Instruction 'vinsertf64x2' {AVX512_DQ+VL}.
+    kIdVinsertf64x4,                     //!< Instruction 'vinsertf64x4' {AVX512_F}.
+    kIdVinserti128,                      //!< Instruction 'vinserti128' {AVX2}.
+    kIdVinserti32x4,                     //!< Instruction 'vinserti32x4' {AVX512_F+VL}.
+    kIdVinserti32x8,                     //!< Instruction 'vinserti32x8' {AVX512_DQ}.
+    kIdVinserti64x2,                     //!< Instruction 'vinserti64x2' {AVX512_DQ+VL}.
+    kIdVinserti64x4,                     //!< Instruction 'vinserti64x4' {AVX512_F}.
+    kIdVinsertps,                        //!< Instruction 'vinsertps' {AVX|AVX512_F}.
+    kIdVlddqu,                           //!< Instruction 'vlddqu' {AVX}.
+    kIdVldmxcsr,                         //!< Instruction 'vldmxcsr' {AVX}.
+    kIdVmaskmovdqu,                      //!< Instruction 'vmaskmovdqu' {AVX}.
+    kIdVmaskmovpd,                       //!< Instruction 'vmaskmovpd' {AVX}.
+    kIdVmaskmovps,                       //!< Instruction 'vmaskmovps' {AVX}.
+    kIdVmaxpd,                           //!< Instruction 'vmaxpd' {AVX|AVX512_F+VL}.
+    kIdVmaxps,                           //!< Instruction 'vmaxps' {AVX|AVX512_F+VL}.
+    kIdVmaxsd,                           //!< Instruction 'vmaxsd' {AVX|AVX512_F+VL}.
+    kIdVmaxss,                           //!< Instruction 'vmaxss' {AVX|AVX512_F+VL}.
+    kIdVmcall,                           //!< Instruction 'vmcall' {VMX}.
+    kIdVmclear,                          //!< Instruction 'vmclear' {VMX}.
+    kIdVmfunc,                           //!< Instruction 'vmfunc' {VMX}.
+    kIdVminpd,                           //!< Instruction 'vminpd' {AVX|AVX512_F+VL}.
+    kIdVminps,                           //!< Instruction 'vminps' {AVX|AVX512_F+VL}.
+    kIdVminsd,                           //!< Instruction 'vminsd' {AVX|AVX512_F+VL}.
+    kIdVminss,                           //!< Instruction 'vminss' {AVX|AVX512_F+VL}.
+    kIdVmlaunch,                         //!< Instruction 'vmlaunch' {VMX}.
+    kIdVmload,                           //!< Instruction 'vmload' {SVM}.
+    kIdVmmcall,                          //!< Instruction 'vmmcall' {SVM}.
+    kIdVmovapd,                          //!< Instruction 'vmovapd' {AVX|AVX512_F+VL}.
+    kIdVmovaps,                          //!< Instruction 'vmovaps' {AVX|AVX512_F+VL}.
+    kIdVmovd,                            //!< Instruction 'vmovd' {AVX|AVX512_F}.
+    kIdVmovddup,                         //!< Instruction 'vmovddup' {AVX|AVX512_F+VL}.
+    kIdVmovdqa,                          //!< Instruction 'vmovdqa' {AVX}.
+    kIdVmovdqa32,                        //!< Instruction 'vmovdqa32' {AVX512_F+VL}.
+    kIdVmovdqa64,                        //!< Instruction 'vmovdqa64' {AVX512_F+VL}.
+    kIdVmovdqu,                          //!< Instruction 'vmovdqu' {AVX}.
+    kIdVmovdqu16,                        //!< Instruction 'vmovdqu16' {AVX512_BW+VL}.
+    kIdVmovdqu32,                        //!< Instruction 'vmovdqu32' {AVX512_F+VL}.
+    kIdVmovdqu64,                        //!< Instruction 'vmovdqu64' {AVX512_F+VL}.
+    kIdVmovdqu8,                         //!< Instruction 'vmovdqu8' {AVX512_BW+VL}.
+    kIdVmovhlps,                         //!< Instruction 'vmovhlps' {AVX|AVX512_F}.
+    kIdVmovhpd,                          //!< Instruction 'vmovhpd' {AVX|AVX512_F}.
+    kIdVmovhps,                          //!< Instruction 'vmovhps' {AVX|AVX512_F}.
+    kIdVmovlhps,                         //!< Instruction 'vmovlhps' {AVX|AVX512_F}.
+    kIdVmovlpd,                          //!< Instruction 'vmovlpd' {AVX|AVX512_F}.
+    kIdVmovlps,                          //!< Instruction 'vmovlps' {AVX|AVX512_F}.
+    kIdVmovmskpd,                        //!< Instruction 'vmovmskpd' {AVX}.
+    kIdVmovmskps,                        //!< Instruction 'vmovmskps' {AVX}.
+    kIdVmovntdq,                         //!< Instruction 'vmovntdq' {AVX|AVX512_F+VL}.
+    kIdVmovntdqa,                        //!< Instruction 'vmovntdqa' {AVX|AVX2|AVX512_F+VL}.
+    kIdVmovntpd,                         //!< Instruction 'vmovntpd' {AVX|AVX512_F+VL}.
+    kIdVmovntps,                         //!< Instruction 'vmovntps' {AVX|AVX512_F+VL}.
+    kIdVmovq,                            //!< Instruction 'vmovq' {AVX|AVX512_F}.
+    kIdVmovsd,                           //!< Instruction 'vmovsd' {AVX|AVX512_F}.
+    kIdVmovshdup,                        //!< Instruction 'vmovshdup' {AVX|AVX512_F+VL}.
+    kIdVmovsldup,                        //!< Instruction 'vmovsldup' {AVX|AVX512_F+VL}.
+    kIdVmovss,                           //!< Instruction 'vmovss' {AVX|AVX512_F}.
+    kIdVmovupd,                          //!< Instruction 'vmovupd' {AVX|AVX512_F+VL}.
+    kIdVmovups,                          //!< Instruction 'vmovups' {AVX|AVX512_F+VL}.
+    kIdVmpsadbw,                         //!< Instruction 'vmpsadbw' {AVX|AVX2}.
+    kIdVmptrld,                          //!< Instruction 'vmptrld' {VMX}.
+    kIdVmptrst,                          //!< Instruction 'vmptrst' {VMX}.
+    kIdVmread,                           //!< Instruction 'vmread' {VMX}.
+    kIdVmresume,                         //!< Instruction 'vmresume' {VMX}.
+    kIdVmrun,                            //!< Instruction 'vmrun' {SVM}.
+    kIdVmsave,                           //!< Instruction 'vmsave' {SVM}.
+    kIdVmulpd,                           //!< Instruction 'vmulpd' {AVX|AVX512_F+VL}.
+    kIdVmulps,                           //!< Instruction 'vmulps' {AVX|AVX512_F+VL}.
+    kIdVmulsd,                           //!< Instruction 'vmulsd' {AVX|AVX512_F}.
+    kIdVmulss,                           //!< Instruction 'vmulss' {AVX|AVX512_F}.
+    kIdVmwrite,                          //!< Instruction 'vmwrite' {VMX}.
+    kIdVmxon,                            //!< Instruction 'vmxon' {VMX}.
+    kIdVorpd,                            //!< Instruction 'vorpd' {AVX|AVX512_DQ+VL}.
+    kIdVorps,                            //!< Instruction 'vorps' {AVX|AVX512_DQ+VL}.
+    kIdVp2intersectd,                    //!< Instruction 'vp2intersectd' {AVX512_VP2INTERSECT}.
+    kIdVp2intersectq,                    //!< Instruction 'vp2intersectq' {AVX512_VP2INTERSECT}.
+    kIdVp4dpwssd,                        //!< Instruction 'vp4dpwssd' {AVX512_4VNNIW}.
+    kIdVp4dpwssds,                       //!< Instruction 'vp4dpwssds' {AVX512_4VNNIW}.
+    kIdVpabsb,                           //!< Instruction 'vpabsb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpabsd,                           //!< Instruction 'vpabsd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpabsq,                           //!< Instruction 'vpabsq' {AVX512_F+VL}.
+    kIdVpabsw,                           //!< Instruction 'vpabsw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpackssdw,                        //!< Instruction 'vpackssdw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpacksswb,                        //!< Instruction 'vpacksswb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpackusdw,                        //!< Instruction 'vpackusdw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpackuswb,                        //!< Instruction 'vpackuswb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpaddb,                           //!< Instruction 'vpaddb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpaddd,                           //!< Instruction 'vpaddd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpaddq,                           //!< Instruction 'vpaddq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpaddsb,                          //!< Instruction 'vpaddsb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpaddsw,                          //!< Instruction 'vpaddsw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpaddusb,                         //!< Instruction 'vpaddusb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpaddusw,                         //!< Instruction 'vpaddusw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpaddw,                           //!< Instruction 'vpaddw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpalignr,                         //!< Instruction 'vpalignr' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpand,                            //!< Instruction 'vpand' {AVX|AVX2}.
+    kIdVpandd,                           //!< Instruction 'vpandd' {AVX512_F+VL}.
+    kIdVpandn,                           //!< Instruction 'vpandn' {AVX|AVX2}.
+    kIdVpandnd,                          //!< Instruction 'vpandnd' {AVX512_F+VL}.
+    kIdVpandnq,                          //!< Instruction 'vpandnq' {AVX512_F+VL}.
+    kIdVpandq,                           //!< Instruction 'vpandq' {AVX512_F+VL}.
+    kIdVpavgb,                           //!< Instruction 'vpavgb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpavgw,                           //!< Instruction 'vpavgw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpblendd,                         //!< Instruction 'vpblendd' {AVX2}.
+    kIdVpblendvb,                        //!< Instruction 'vpblendvb' {AVX|AVX2}.
+    kIdVpblendw,                         //!< Instruction 'vpblendw' {AVX|AVX2}.
+    kIdVpbroadcastb,                     //!< Instruction 'vpbroadcastb' {AVX2|AVX512_BW+VL}.
+    kIdVpbroadcastd,                     //!< Instruction 'vpbroadcastd' {AVX2|AVX512_F+VL}.
+    kIdVpbroadcastmb2d,                  //!< Instruction 'vpbroadcastmb2d' {AVX512_CDI+VL}.
+    kIdVpbroadcastmb2q,                  //!< Instruction 'vpbroadcastmb2q' {AVX512_CDI+VL}.
+    kIdVpbroadcastq,                     //!< Instruction 'vpbroadcastq' {AVX2|AVX512_F+VL}.
+    kIdVpbroadcastw,                     //!< Instruction 'vpbroadcastw' {AVX2|AVX512_BW+VL}.
+    kIdVpclmulqdq,                       //!< Instruction 'vpclmulqdq' {AVX|AVX512_F+VL & PCLMULQDQ|VPCLMULQDQ}.
+    kIdVpcmov,                           //!< Instruction 'vpcmov' {XOP}.
+    kIdVpcmpb,                           //!< Instruction 'vpcmpb' {AVX512_BW+VL}.
+    kIdVpcmpd,                           //!< Instruction 'vpcmpd' {AVX512_F+VL}.
+    kIdVpcmpeqb,                         //!< Instruction 'vpcmpeqb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpcmpeqd,                         //!< Instruction 'vpcmpeqd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpcmpeqq,                         //!< Instruction 'vpcmpeqq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpcmpeqw,                         //!< Instruction 'vpcmpeqw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpcmpestri,                       //!< Instruction 'vpcmpestri' {AVX}.
+    kIdVpcmpestrm,                       //!< Instruction 'vpcmpestrm' {AVX}.
+    kIdVpcmpgtb,                         //!< Instruction 'vpcmpgtb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpcmpgtd,                         //!< Instruction 'vpcmpgtd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpcmpgtq,                         //!< Instruction 'vpcmpgtq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpcmpgtw,                         //!< Instruction 'vpcmpgtw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpcmpistri,                       //!< Instruction 'vpcmpistri' {AVX}.
+    kIdVpcmpistrm,                       //!< Instruction 'vpcmpistrm' {AVX}.
+    kIdVpcmpq,                           //!< Instruction 'vpcmpq' {AVX512_F+VL}.
+    kIdVpcmpub,                          //!< Instruction 'vpcmpub' {AVX512_BW+VL}.
+    kIdVpcmpud,                          //!< Instruction 'vpcmpud' {AVX512_F+VL}.
+    kIdVpcmpuq,                          //!< Instruction 'vpcmpuq' {AVX512_F+VL}.
+    kIdVpcmpuw,                          //!< Instruction 'vpcmpuw' {AVX512_BW+VL}.
+    kIdVpcmpw,                           //!< Instruction 'vpcmpw' {AVX512_BW+VL}.
+    kIdVpcomb,                           //!< Instruction 'vpcomb' {XOP}.
+    kIdVpcomd,                           //!< Instruction 'vpcomd' {XOP}.
+    kIdVpcompressb,                      //!< Instruction 'vpcompressb' {AVX512_VBMI2+VL}.
+    kIdVpcompressd,                      //!< Instruction 'vpcompressd' {AVX512_F+VL}.
+    kIdVpcompressq,                      //!< Instruction 'vpcompressq' {AVX512_F+VL}.
+    kIdVpcompressw,                      //!< Instruction 'vpcompressw' {AVX512_VBMI2+VL}.
+    kIdVpcomq,                           //!< Instruction 'vpcomq' {XOP}.
+    kIdVpcomub,                          //!< Instruction 'vpcomub' {XOP}.
+    kIdVpcomud,                          //!< Instruction 'vpcomud' {XOP}.
+    kIdVpcomuq,                          //!< Instruction 'vpcomuq' {XOP}.
+    kIdVpcomuw,                          //!< Instruction 'vpcomuw' {XOP}.
+    kIdVpcomw,                           //!< Instruction 'vpcomw' {XOP}.
+    kIdVpconflictd,                      //!< Instruction 'vpconflictd' {AVX512_CDI+VL}.
+    kIdVpconflictq,                      //!< Instruction 'vpconflictq' {AVX512_CDI+VL}.
+    kIdVpdpbusd,                         //!< Instruction 'vpdpbusd' {AVX512_VNNI+VL}.
+    kIdVpdpbusds,                        //!< Instruction 'vpdpbusds' {AVX512_VNNI+VL}.
+    kIdVpdpwssd,                         //!< Instruction 'vpdpwssd' {AVX512_VNNI+VL}.
+    kIdVpdpwssds,                        //!< Instruction 'vpdpwssds' {AVX512_VNNI+VL}.
+    kIdVperm2f128,                       //!< Instruction 'vperm2f128' {AVX}.
+    kIdVperm2i128,                       //!< Instruction 'vperm2i128' {AVX2}.
+    kIdVpermb,                           //!< Instruction 'vpermb' {AVX512_VBMI+VL}.
+    kIdVpermd,                           //!< Instruction 'vpermd' {AVX2|AVX512_F+VL}.
+    kIdVpermi2b,                         //!< Instruction 'vpermi2b' {AVX512_VBMI+VL}.
+    kIdVpermi2d,                         //!< Instruction 'vpermi2d' {AVX512_F+VL}.
+    kIdVpermi2pd,                        //!< Instruction 'vpermi2pd' {AVX512_F+VL}.
+    kIdVpermi2ps,                        //!< Instruction 'vpermi2ps' {AVX512_F+VL}.
+    kIdVpermi2q,                         //!< Instruction 'vpermi2q' {AVX512_F+VL}.
+    kIdVpermi2w,                         //!< Instruction 'vpermi2w' {AVX512_BW+VL}.
+    kIdVpermil2pd,                       //!< Instruction 'vpermil2pd' {XOP}.
+    kIdVpermil2ps,                       //!< Instruction 'vpermil2ps' {XOP}.
+    kIdVpermilpd,                        //!< Instruction 'vpermilpd' {AVX|AVX512_F+VL}.
+    kIdVpermilps,                        //!< Instruction 'vpermilps' {AVX|AVX512_F+VL}.
+    kIdVpermpd,                          //!< Instruction 'vpermpd' {AVX2|AVX512_F+VL}.
+    kIdVpermps,                          //!< Instruction 'vpermps' {AVX2|AVX512_F+VL}.
+    kIdVpermq,                           //!< Instruction 'vpermq' {AVX2|AVX512_F+VL}.
+    kIdVpermt2b,                         //!< Instruction 'vpermt2b' {AVX512_VBMI+VL}.
+    kIdVpermt2d,                         //!< Instruction 'vpermt2d' {AVX512_F+VL}.
+    kIdVpermt2pd,                        //!< Instruction 'vpermt2pd' {AVX512_F+VL}.
+    kIdVpermt2ps,                        //!< Instruction 'vpermt2ps' {AVX512_F+VL}.
+    kIdVpermt2q,                         //!< Instruction 'vpermt2q' {AVX512_F+VL}.
+    kIdVpermt2w,                         //!< Instruction 'vpermt2w' {AVX512_BW+VL}.
+    kIdVpermw,                           //!< Instruction 'vpermw' {AVX512_BW+VL}.
+    kIdVpexpandb,                        //!< Instruction 'vpexpandb' {AVX512_VBMI2+VL}.
+    kIdVpexpandd,                        //!< Instruction 'vpexpandd' {AVX512_F+VL}.
+    kIdVpexpandq,                        //!< Instruction 'vpexpandq' {AVX512_F+VL}.
+    kIdVpexpandw,                        //!< Instruction 'vpexpandw' {AVX512_VBMI2+VL}.
+    kIdVpextrb,                          //!< Instruction 'vpextrb' {AVX|AVX512_BW}.
+    kIdVpextrd,                          //!< Instruction 'vpextrd' {AVX|AVX512_DQ}.
+    kIdVpextrq,                          //!< Instruction 'vpextrq' {AVX|AVX512_DQ} (X64).
+    kIdVpextrw,                          //!< Instruction 'vpextrw' {AVX|AVX512_BW}.
+    kIdVpgatherdd,                       //!< Instruction 'vpgatherdd' {AVX2|AVX512_F+VL}.
+    kIdVpgatherdq,                       //!< Instruction 'vpgatherdq' {AVX2|AVX512_F+VL}.
+    kIdVpgatherqd,                       //!< Instruction 'vpgatherqd' {AVX2|AVX512_F+VL}.
+    kIdVpgatherqq,                       //!< Instruction 'vpgatherqq' {AVX2|AVX512_F+VL}.
+    kIdVphaddbd,                         //!< Instruction 'vphaddbd' {XOP}.
+    kIdVphaddbq,                         //!< Instruction 'vphaddbq' {XOP}.
+    kIdVphaddbw,                         //!< Instruction 'vphaddbw' {XOP}.
+    kIdVphaddd,                          //!< Instruction 'vphaddd' {AVX|AVX2}.
+    kIdVphadddq,                         //!< Instruction 'vphadddq' {XOP}.
+    kIdVphaddsw,                         //!< Instruction 'vphaddsw' {AVX|AVX2}.
+    kIdVphaddubd,                        //!< Instruction 'vphaddubd' {XOP}.
+    kIdVphaddubq,                        //!< Instruction 'vphaddubq' {XOP}.
+    kIdVphaddubw,                        //!< Instruction 'vphaddubw' {XOP}.
+    kIdVphaddudq,                        //!< Instruction 'vphaddudq' {XOP}.
+    kIdVphadduwd,                        //!< Instruction 'vphadduwd' {XOP}.
+    kIdVphadduwq,                        //!< Instruction 'vphadduwq' {XOP}.
+    kIdVphaddw,                          //!< Instruction 'vphaddw' {AVX|AVX2}.
+    kIdVphaddwd,                         //!< Instruction 'vphaddwd' {XOP}.
+    kIdVphaddwq,                         //!< Instruction 'vphaddwq' {XOP}.
+    kIdVphminposuw,                      //!< Instruction 'vphminposuw' {AVX}.
+    kIdVphsubbw,                         //!< Instruction 'vphsubbw' {XOP}.
+    kIdVphsubd,                          //!< Instruction 'vphsubd' {AVX|AVX2}.
+    kIdVphsubdq,                         //!< Instruction 'vphsubdq' {XOP}.
+    kIdVphsubsw,                         //!< Instruction 'vphsubsw' {AVX|AVX2}.
+    kIdVphsubw,                          //!< Instruction 'vphsubw' {AVX|AVX2}.
+    kIdVphsubwd,                         //!< Instruction 'vphsubwd' {XOP}.
+    kIdVpinsrb,                          //!< Instruction 'vpinsrb' {AVX|AVX512_BW}.
+    kIdVpinsrd,                          //!< Instruction 'vpinsrd' {AVX|AVX512_DQ}.
+    kIdVpinsrq,                          //!< Instruction 'vpinsrq' {AVX|AVX512_DQ} (X64).
+    kIdVpinsrw,                          //!< Instruction 'vpinsrw' {AVX|AVX512_BW}.
+    kIdVplzcntd,                         //!< Instruction 'vplzcntd' {AVX512_CDI+VL}.
+    kIdVplzcntq,                         //!< Instruction 'vplzcntq' {AVX512_CDI+VL}.
+    kIdVpmacsdd,                         //!< Instruction 'vpmacsdd' {XOP}.
+    kIdVpmacsdqh,                        //!< Instruction 'vpmacsdqh' {XOP}.
+    kIdVpmacsdql,                        //!< Instruction 'vpmacsdql' {XOP}.
+    kIdVpmacssdd,                        //!< Instruction 'vpmacssdd' {XOP}.
+    kIdVpmacssdqh,                       //!< Instruction 'vpmacssdqh' {XOP}.
+    kIdVpmacssdql,                       //!< Instruction 'vpmacssdql' {XOP}.
+    kIdVpmacsswd,                        //!< Instruction 'vpmacsswd' {XOP}.
+    kIdVpmacssww,                        //!< Instruction 'vpmacssww' {XOP}.
+    kIdVpmacswd,                         //!< Instruction 'vpmacswd' {XOP}.
+    kIdVpmacsww,                         //!< Instruction 'vpmacsww' {XOP}.
+    kIdVpmadcsswd,                       //!< Instruction 'vpmadcsswd' {XOP}.
+    kIdVpmadcswd,                        //!< Instruction 'vpmadcswd' {XOP}.
+    kIdVpmadd52huq,                      //!< Instruction 'vpmadd52huq' {AVX512_IFMA+VL}.
+    kIdVpmadd52luq,                      //!< Instruction 'vpmadd52luq' {AVX512_IFMA+VL}.
+    kIdVpmaddubsw,                       //!< Instruction 'vpmaddubsw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmaddwd,                         //!< Instruction 'vpmaddwd' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmaskmovd,                       //!< Instruction 'vpmaskmovd' {AVX2}.
+    kIdVpmaskmovq,                       //!< Instruction 'vpmaskmovq' {AVX2}.
+    kIdVpmaxsb,                          //!< Instruction 'vpmaxsb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmaxsd,                          //!< Instruction 'vpmaxsd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmaxsq,                          //!< Instruction 'vpmaxsq' {AVX512_F+VL}.
+    kIdVpmaxsw,                          //!< Instruction 'vpmaxsw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmaxub,                          //!< Instruction 'vpmaxub' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmaxud,                          //!< Instruction 'vpmaxud' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmaxuq,                          //!< Instruction 'vpmaxuq' {AVX512_F+VL}.
+    kIdVpmaxuw,                          //!< Instruction 'vpmaxuw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpminsb,                          //!< Instruction 'vpminsb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpminsd,                          //!< Instruction 'vpminsd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpminsq,                          //!< Instruction 'vpminsq' {AVX512_F+VL}.
+    kIdVpminsw,                          //!< Instruction 'vpminsw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpminub,                          //!< Instruction 'vpminub' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpminud,                          //!< Instruction 'vpminud' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpminuq,                          //!< Instruction 'vpminuq' {AVX512_F+VL}.
+    kIdVpminuw,                          //!< Instruction 'vpminuw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmovb2m,                         //!< Instruction 'vpmovb2m' {AVX512_BW+VL}.
+    kIdVpmovd2m,                         //!< Instruction 'vpmovd2m' {AVX512_DQ+VL}.
+    kIdVpmovdb,                          //!< Instruction 'vpmovdb' {AVX512_F+VL}.
+    kIdVpmovdw,                          //!< Instruction 'vpmovdw' {AVX512_F+VL}.
+    kIdVpmovm2b,                         //!< Instruction 'vpmovm2b' {AVX512_BW+VL}.
+    kIdVpmovm2d,                         //!< Instruction 'vpmovm2d' {AVX512_DQ+VL}.
+    kIdVpmovm2q,                         //!< Instruction 'vpmovm2q' {AVX512_DQ+VL}.
+    kIdVpmovm2w,                         //!< Instruction 'vpmovm2w' {AVX512_BW+VL}.
+    kIdVpmovmskb,                        //!< Instruction 'vpmovmskb' {AVX|AVX2}.
+    kIdVpmovq2m,                         //!< Instruction 'vpmovq2m' {AVX512_DQ+VL}.
+    kIdVpmovqb,                          //!< Instruction 'vpmovqb' {AVX512_F+VL}.
+    kIdVpmovqd,                          //!< Instruction 'vpmovqd' {AVX512_F+VL}.
+    kIdVpmovqw,                          //!< Instruction 'vpmovqw' {AVX512_F+VL}.
+    kIdVpmovsdb,                         //!< Instruction 'vpmovsdb' {AVX512_F+VL}.
+    kIdVpmovsdw,                         //!< Instruction 'vpmovsdw' {AVX512_F+VL}.
+    kIdVpmovsqb,                         //!< Instruction 'vpmovsqb' {AVX512_F+VL}.
+    kIdVpmovsqd,                         //!< Instruction 'vpmovsqd' {AVX512_F+VL}.
+    kIdVpmovsqw,                         //!< Instruction 'vpmovsqw' {AVX512_F+VL}.
+    kIdVpmovswb,                         //!< Instruction 'vpmovswb' {AVX512_BW+VL}.
+    kIdVpmovsxbd,                        //!< Instruction 'vpmovsxbd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmovsxbq,                        //!< Instruction 'vpmovsxbq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmovsxbw,                        //!< Instruction 'vpmovsxbw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmovsxdq,                        //!< Instruction 'vpmovsxdq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmovsxwd,                        //!< Instruction 'vpmovsxwd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmovsxwq,                        //!< Instruction 'vpmovsxwq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmovusdb,                        //!< Instruction 'vpmovusdb' {AVX512_F+VL}.
+    kIdVpmovusdw,                        //!< Instruction 'vpmovusdw' {AVX512_F+VL}.
+    kIdVpmovusqb,                        //!< Instruction 'vpmovusqb' {AVX512_F+VL}.
+    kIdVpmovusqd,                        //!< Instruction 'vpmovusqd' {AVX512_F+VL}.
+    kIdVpmovusqw,                        //!< Instruction 'vpmovusqw' {AVX512_F+VL}.
+    kIdVpmovuswb,                        //!< Instruction 'vpmovuswb' {AVX512_BW+VL}.
+    kIdVpmovw2m,                         //!< Instruction 'vpmovw2m' {AVX512_BW+VL}.
+    kIdVpmovwb,                          //!< Instruction 'vpmovwb' {AVX512_BW+VL}.
+    kIdVpmovzxbd,                        //!< Instruction 'vpmovzxbd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmovzxbq,                        //!< Instruction 'vpmovzxbq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmovzxbw,                        //!< Instruction 'vpmovzxbw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmovzxdq,                        //!< Instruction 'vpmovzxdq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmovzxwd,                        //!< Instruction 'vpmovzxwd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmovzxwq,                        //!< Instruction 'vpmovzxwq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmuldq,                          //!< Instruction 'vpmuldq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmulhrsw,                        //!< Instruction 'vpmulhrsw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmulhuw,                         //!< Instruction 'vpmulhuw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmulhw,                          //!< Instruction 'vpmulhw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmulld,                          //!< Instruction 'vpmulld' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpmullq,                          //!< Instruction 'vpmullq' {AVX512_DQ+VL}.
+    kIdVpmullw,                          //!< Instruction 'vpmullw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpmultishiftqb,                   //!< Instruction 'vpmultishiftqb' {AVX512_VBMI+VL}.
+    kIdVpmuludq,                         //!< Instruction 'vpmuludq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpopcntb,                         //!< Instruction 'vpopcntb' {AVX512_BITALG+VL}.
+    kIdVpopcntd,                         //!< Instruction 'vpopcntd' {AVX512_VPOPCNTDQ+VL}.
+    kIdVpopcntq,                         //!< Instruction 'vpopcntq' {AVX512_VPOPCNTDQ+VL}.
+    kIdVpopcntw,                         //!< Instruction 'vpopcntw' {AVX512_BITALG+VL}.
+    kIdVpor,                             //!< Instruction 'vpor' {AVX|AVX2}.
+    kIdVpord,                            //!< Instruction 'vpord' {AVX512_F+VL}.
+    kIdVporq,                            //!< Instruction 'vporq' {AVX512_F+VL}.
+    kIdVpperm,                           //!< Instruction 'vpperm' {XOP}.
+    kIdVprold,                           //!< Instruction 'vprold' {AVX512_F+VL}.
+    kIdVprolq,                           //!< Instruction 'vprolq' {AVX512_F+VL}.
+    kIdVprolvd,                          //!< Instruction 'vprolvd' {AVX512_F+VL}.
+    kIdVprolvq,                          //!< Instruction 'vprolvq' {AVX512_F+VL}.
+    kIdVprord,                           //!< Instruction 'vprord' {AVX512_F+VL}.
+    kIdVprorq,                           //!< Instruction 'vprorq' {AVX512_F+VL}.
+    kIdVprorvd,                          //!< Instruction 'vprorvd' {AVX512_F+VL}.
+    kIdVprorvq,                          //!< Instruction 'vprorvq' {AVX512_F+VL}.
+    kIdVprotb,                           //!< Instruction 'vprotb' {XOP}.
+    kIdVprotd,                           //!< Instruction 'vprotd' {XOP}.
+    kIdVprotq,                           //!< Instruction 'vprotq' {XOP}.
+    kIdVprotw,                           //!< Instruction 'vprotw' {XOP}.
+    kIdVpsadbw,                          //!< Instruction 'vpsadbw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpscatterdd,                      //!< Instruction 'vpscatterdd' {AVX512_F+VL}.
+    kIdVpscatterdq,                      //!< Instruction 'vpscatterdq' {AVX512_F+VL}.
+    kIdVpscatterqd,                      //!< Instruction 'vpscatterqd' {AVX512_F+VL}.
+    kIdVpscatterqq,                      //!< Instruction 'vpscatterqq' {AVX512_F+VL}.
+    kIdVpshab,                           //!< Instruction 'vpshab' {XOP}.
+    kIdVpshad,                           //!< Instruction 'vpshad' {XOP}.
+    kIdVpshaq,                           //!< Instruction 'vpshaq' {XOP}.
+    kIdVpshaw,                           //!< Instruction 'vpshaw' {XOP}.
+    kIdVpshlb,                           //!< Instruction 'vpshlb' {XOP}.
+    kIdVpshld,                           //!< Instruction 'vpshld' {XOP}.
+    kIdVpshldd,                          //!< Instruction 'vpshldd' {AVX512_VBMI2+VL}.
+    kIdVpshldq,                          //!< Instruction 'vpshldq' {AVX512_VBMI2+VL}.
+    kIdVpshldvd,                         //!< Instruction 'vpshldvd' {AVX512_VBMI2+VL}.
+    kIdVpshldvq,                         //!< Instruction 'vpshldvq' {AVX512_VBMI2+VL}.
+    kIdVpshldvw,                         //!< Instruction 'vpshldvw' {AVX512_VBMI2+VL}.
+    kIdVpshldw,                          //!< Instruction 'vpshldw' {AVX512_VBMI2+VL}.
+    kIdVpshlq,                           //!< Instruction 'vpshlq' {XOP}.
+    kIdVpshlw,                           //!< Instruction 'vpshlw' {XOP}.
+    kIdVpshrdd,                          //!< Instruction 'vpshrdd' {AVX512_VBMI2+VL}.
+    kIdVpshrdq,                          //!< Instruction 'vpshrdq' {AVX512_VBMI2+VL}.
+    kIdVpshrdvd,                         //!< Instruction 'vpshrdvd' {AVX512_VBMI2+VL}.
+    kIdVpshrdvq,                         //!< Instruction 'vpshrdvq' {AVX512_VBMI2+VL}.
+    kIdVpshrdvw,                         //!< Instruction 'vpshrdvw' {AVX512_VBMI2+VL}.
+    kIdVpshrdw,                          //!< Instruction 'vpshrdw' {AVX512_VBMI2+VL}.
+    kIdVpshufb,                          //!< Instruction 'vpshufb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpshufbitqmb,                     //!< Instruction 'vpshufbitqmb' {AVX512_BITALG+VL}.
+    kIdVpshufd,                          //!< Instruction 'vpshufd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpshufhw,                         //!< Instruction 'vpshufhw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpshuflw,                         //!< Instruction 'vpshuflw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsignb,                          //!< Instruction 'vpsignb' {AVX|AVX2}.
+    kIdVpsignd,                          //!< Instruction 'vpsignd' {AVX|AVX2}.
+    kIdVpsignw,                          //!< Instruction 'vpsignw' {AVX|AVX2}.
+    kIdVpslld,                           //!< Instruction 'vpslld' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpslldq,                          //!< Instruction 'vpslldq' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsllq,                           //!< Instruction 'vpsllq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpsllvd,                          //!< Instruction 'vpsllvd' {AVX2|AVX512_F+VL}.
+    kIdVpsllvq,                          //!< Instruction 'vpsllvq' {AVX2|AVX512_F+VL}.
+    kIdVpsllvw,                          //!< Instruction 'vpsllvw' {AVX512_BW+VL}.
+    kIdVpsllw,                           //!< Instruction 'vpsllw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsrad,                           //!< Instruction 'vpsrad' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpsraq,                           //!< Instruction 'vpsraq' {AVX512_F+VL}.
+    kIdVpsravd,                          //!< Instruction 'vpsravd' {AVX2|AVX512_F+VL}.
+    kIdVpsravq,                          //!< Instruction 'vpsravq' {AVX512_F+VL}.
+    kIdVpsravw,                          //!< Instruction 'vpsravw' {AVX512_BW+VL}.
+    kIdVpsraw,                           //!< Instruction 'vpsraw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsrld,                           //!< Instruction 'vpsrld' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpsrldq,                          //!< Instruction 'vpsrldq' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsrlq,                           //!< Instruction 'vpsrlq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpsrlvd,                          //!< Instruction 'vpsrlvd' {AVX2|AVX512_F+VL}.
+    kIdVpsrlvq,                          //!< Instruction 'vpsrlvq' {AVX2|AVX512_F+VL}.
+    kIdVpsrlvw,                          //!< Instruction 'vpsrlvw' {AVX512_BW+VL}.
+    kIdVpsrlw,                           //!< Instruction 'vpsrlw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsubb,                           //!< Instruction 'vpsubb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsubd,                           //!< Instruction 'vpsubd' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpsubq,                           //!< Instruction 'vpsubq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpsubsb,                          //!< Instruction 'vpsubsb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsubsw,                          //!< Instruction 'vpsubsw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsubusb,                         //!< Instruction 'vpsubusb' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsubusw,                         //!< Instruction 'vpsubusw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpsubw,                           //!< Instruction 'vpsubw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpternlogd,                       //!< Instruction 'vpternlogd' {AVX512_F+VL}.
+    kIdVpternlogq,                       //!< Instruction 'vpternlogq' {AVX512_F+VL}.
+    kIdVptest,                           //!< Instruction 'vptest' {AVX}.
+    kIdVptestmb,                         //!< Instruction 'vptestmb' {AVX512_BW+VL}.
+    kIdVptestmd,                         //!< Instruction 'vptestmd' {AVX512_F+VL}.
+    kIdVptestmq,                         //!< Instruction 'vptestmq' {AVX512_F+VL}.
+    kIdVptestmw,                         //!< Instruction 'vptestmw' {AVX512_BW+VL}.
+    kIdVptestnmb,                        //!< Instruction 'vptestnmb' {AVX512_BW+VL}.
+    kIdVptestnmd,                        //!< Instruction 'vptestnmd' {AVX512_F+VL}.
+    kIdVptestnmq,                        //!< Instruction 'vptestnmq' {AVX512_F+VL}.
+    kIdVptestnmw,                        //!< Instruction 'vptestnmw' {AVX512_BW+VL}.
+    kIdVpunpckhbw,                       //!< Instruction 'vpunpckhbw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpunpckhdq,                       //!< Instruction 'vpunpckhdq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpunpckhqdq,                      //!< Instruction 'vpunpckhqdq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpunpckhwd,                       //!< Instruction 'vpunpckhwd' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpunpcklbw,                       //!< Instruction 'vpunpcklbw' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpunpckldq,                       //!< Instruction 'vpunpckldq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpunpcklqdq,                      //!< Instruction 'vpunpcklqdq' {AVX|AVX2|AVX512_F+VL}.
+    kIdVpunpcklwd,                       //!< Instruction 'vpunpcklwd' {AVX|AVX2|AVX512_BW+VL}.
+    kIdVpxor,                            //!< Instruction 'vpxor' {AVX|AVX2}.
+    kIdVpxord,                           //!< Instruction 'vpxord' {AVX512_F+VL}.
+    kIdVpxorq,                           //!< Instruction 'vpxorq' {AVX512_F+VL}.
+    kIdVrangepd,                         //!< Instruction 'vrangepd' {AVX512_DQ+VL}.
+    kIdVrangeps,                         //!< Instruction 'vrangeps' {AVX512_DQ+VL}.
+    kIdVrangesd,                         //!< Instruction 'vrangesd' {AVX512_DQ}.
+    kIdVrangess,                         //!< Instruction 'vrangess' {AVX512_DQ}.
+    kIdVrcp14pd,                         //!< Instruction 'vrcp14pd' {AVX512_F+VL}.
+    kIdVrcp14ps,                         //!< Instruction 'vrcp14ps' {AVX512_F+VL}.
+    kIdVrcp14sd,                         //!< Instruction 'vrcp14sd' {AVX512_F}.
+    kIdVrcp14ss,                         //!< Instruction 'vrcp14ss' {AVX512_F}.
+    kIdVrcp28pd,                         //!< Instruction 'vrcp28pd' {AVX512_ERI}.
+    kIdVrcp28ps,                         //!< Instruction 'vrcp28ps' {AVX512_ERI}.
+    kIdVrcp28sd,                         //!< Instruction 'vrcp28sd' {AVX512_ERI}.
+    kIdVrcp28ss,                         //!< Instruction 'vrcp28ss' {AVX512_ERI}.
+    kIdVrcpps,                           //!< Instruction 'vrcpps' {AVX}.
+    kIdVrcpss,                           //!< Instruction 'vrcpss' {AVX}.
+    kIdVreducepd,                        //!< Instruction 'vreducepd' {AVX512_DQ+VL}.
+    kIdVreduceps,                        //!< Instruction 'vreduceps' {AVX512_DQ+VL}.
+    kIdVreducesd,                        //!< Instruction 'vreducesd' {AVX512_DQ}.
+    kIdVreducess,                        //!< Instruction 'vreducess' {AVX512_DQ}.
+    kIdVrndscalepd,                      //!< Instruction 'vrndscalepd' {AVX512_F+VL}.
+    kIdVrndscaleps,                      //!< Instruction 'vrndscaleps' {AVX512_F+VL}.
+    kIdVrndscalesd,                      //!< Instruction 'vrndscalesd' {AVX512_F}.
+    kIdVrndscaless,                      //!< Instruction 'vrndscaless' {AVX512_F}.
+    kIdVroundpd,                         //!< Instruction 'vroundpd' {AVX}.
+    kIdVroundps,                         //!< Instruction 'vroundps' {AVX}.
+    kIdVroundsd,                         //!< Instruction 'vroundsd' {AVX}.
+    kIdVroundss,                         //!< Instruction 'vroundss' {AVX}.
+    kIdVrsqrt14pd,                       //!< Instruction 'vrsqrt14pd' {AVX512_F+VL}.
+    kIdVrsqrt14ps,                       //!< Instruction 'vrsqrt14ps' {AVX512_F+VL}.
+    kIdVrsqrt14sd,                       //!< Instruction 'vrsqrt14sd' {AVX512_F}.
+    kIdVrsqrt14ss,                       //!< Instruction 'vrsqrt14ss' {AVX512_F}.
+    kIdVrsqrt28pd,                       //!< Instruction 'vrsqrt28pd' {AVX512_ERI}.
+    kIdVrsqrt28ps,                       //!< Instruction 'vrsqrt28ps' {AVX512_ERI}.
+    kIdVrsqrt28sd,                       //!< Instruction 'vrsqrt28sd' {AVX512_ERI}.
+    kIdVrsqrt28ss,                       //!< Instruction 'vrsqrt28ss' {AVX512_ERI}.
+    kIdVrsqrtps,                         //!< Instruction 'vrsqrtps' {AVX}.
+    kIdVrsqrtss,                         //!< Instruction 'vrsqrtss' {AVX}.
+    kIdVscalefpd,                        //!< Instruction 'vscalefpd' {AVX512_F+VL}.
+    kIdVscalefps,                        //!< Instruction 'vscalefps' {AVX512_F+VL}.
+    kIdVscalefsd,                        //!< Instruction 'vscalefsd' {AVX512_F}.
+    kIdVscalefss,                        //!< Instruction 'vscalefss' {AVX512_F}.
+    kIdVscatterdpd,                      //!< Instruction 'vscatterdpd' {AVX512_F+VL}.
+    kIdVscatterdps,                      //!< Instruction 'vscatterdps' {AVX512_F+VL}.
+    kIdVscatterpf0dpd,                   //!< Instruction 'vscatterpf0dpd' {AVX512_PFI}.
+    kIdVscatterpf0dps,                   //!< Instruction 'vscatterpf0dps' {AVX512_PFI}.
+    kIdVscatterpf0qpd,                   //!< Instruction 'vscatterpf0qpd' {AVX512_PFI}.
+    kIdVscatterpf0qps,                   //!< Instruction 'vscatterpf0qps' {AVX512_PFI}.
+    kIdVscatterpf1dpd,                   //!< Instruction 'vscatterpf1dpd' {AVX512_PFI}.
+    kIdVscatterpf1dps,                   //!< Instruction 'vscatterpf1dps' {AVX512_PFI}.
+    kIdVscatterpf1qpd,                   //!< Instruction 'vscatterpf1qpd' {AVX512_PFI}.
+    kIdVscatterpf1qps,                   //!< Instruction 'vscatterpf1qps' {AVX512_PFI}.
+    kIdVscatterqpd,                      //!< Instruction 'vscatterqpd' {AVX512_F+VL}.
+    kIdVscatterqps,                      //!< Instruction 'vscatterqps' {AVX512_F+VL}.
+    kIdVshuff32x4,                       //!< Instruction 'vshuff32x4' {AVX512_F+VL}.
+    kIdVshuff64x2,                       //!< Instruction 'vshuff64x2' {AVX512_F+VL}.
+    kIdVshufi32x4,                       //!< Instruction 'vshufi32x4' {AVX512_F+VL}.
+    kIdVshufi64x2,                       //!< Instruction 'vshufi64x2' {AVX512_F+VL}.
+    kIdVshufpd,                          //!< Instruction 'vshufpd' {AVX|AVX512_F+VL}.
+    kIdVshufps,                          //!< Instruction 'vshufps' {AVX|AVX512_F+VL}.
+    kIdVsqrtpd,                          //!< Instruction 'vsqrtpd' {AVX|AVX512_F+VL}.
+    kIdVsqrtps,                          //!< Instruction 'vsqrtps' {AVX|AVX512_F+VL}.
+    kIdVsqrtsd,                          //!< Instruction 'vsqrtsd' {AVX|AVX512_F}.
+    kIdVsqrtss,                          //!< Instruction 'vsqrtss' {AVX|AVX512_F}.
+    kIdVstmxcsr,                         //!< Instruction 'vstmxcsr' {AVX}.
+    kIdVsubpd,                           //!< Instruction 'vsubpd' {AVX|AVX512_F+VL}.
+    kIdVsubps,                           //!< Instruction 'vsubps' {AVX|AVX512_F+VL}.
+    kIdVsubsd,                           //!< Instruction 'vsubsd' {AVX|AVX512_F}.
+    kIdVsubss,                           //!< Instruction 'vsubss' {AVX|AVX512_F}.
+    kIdVtestpd,                          //!< Instruction 'vtestpd' {AVX}.
+    kIdVtestps,                          //!< Instruction 'vtestps' {AVX}.
+    kIdVucomisd,                         //!< Instruction 'vucomisd' {AVX|AVX512_F}.
+    kIdVucomiss,                         //!< Instruction 'vucomiss' {AVX|AVX512_F}.
+    kIdVunpckhpd,                        //!< Instruction 'vunpckhpd' {AVX|AVX512_F+VL}.
+    kIdVunpckhps,                        //!< Instruction 'vunpckhps' {AVX|AVX512_F+VL}.
+    kIdVunpcklpd,                        //!< Instruction 'vunpcklpd' {AVX|AVX512_F+VL}.
+    kIdVunpcklps,                        //!< Instruction 'vunpcklps' {AVX|AVX512_F+VL}.
+    kIdVxorpd,                           //!< Instruction 'vxorpd' {AVX|AVX512_DQ+VL}.
+    kIdVxorps,                           //!< Instruction 'vxorps' {AVX|AVX512_DQ+VL}.
+    kIdVzeroall,                         //!< Instruction 'vzeroall' {AVX}.
+    kIdVzeroupper,                       //!< Instruction 'vzeroupper' {AVX}.
+    kIdWbinvd,                           //!< Instruction 'wbinvd'.
+    kIdWbnoinvd,                         //!< Instruction 'wbnoinvd' {WBNOINVD}.
+    kIdWrfsbase,                         //!< Instruction 'wrfsbase' {FSGSBASE} (X64).
+    kIdWrgsbase,                         //!< Instruction 'wrgsbase' {FSGSBASE} (X64).
+    kIdWrmsr,                            //!< Instruction 'wrmsr' {MSR}.
+    kIdWrssd,                            //!< Instruction 'wrssd' {CET_SS}.
+    kIdWrssq,                            //!< Instruction 'wrssq' {CET_SS} (X64).
+    kIdWrussd,                           //!< Instruction 'wrussd' {CET_SS}.
+    kIdWrussq,                           //!< Instruction 'wrussq' {CET_SS} (X64).
+    kIdXabort,                           //!< Instruction 'xabort' {RTM}.
+    kIdXadd,                             //!< Instruction 'xadd' {I486}.
+    kIdXbegin,                           //!< Instruction 'xbegin' {RTM}.
+    kIdXchg,                             //!< Instruction 'xchg'.
+    kIdXend,                             //!< Instruction 'xend' {RTM}.
+    kIdXgetbv,                           //!< Instruction 'xgetbv' {XSAVE}.
+    kIdXlatb,                            //!< Instruction 'xlatb'.
+    kIdXor,                              //!< Instruction 'xor'.
+    kIdXorpd,                            //!< Instruction 'xorpd' {SSE2}.
+    kIdXorps,                            //!< Instruction 'xorps' {SSE}.
+    kIdXresldtrk,                        //!< Instruction 'xresldtrk' {TSXLDTRK}.
+    kIdXrstor,                           //!< Instruction 'xrstor' {XSAVE}.
+    kIdXrstor64,                         //!< Instruction 'xrstor64' {XSAVE} (X64).
+    kIdXrstors,                          //!< Instruction 'xrstors' {XSAVES}.
+    kIdXrstors64,                        //!< Instruction 'xrstors64' {XSAVES} (X64).
+    kIdXsave,                            //!< Instruction 'xsave' {XSAVE}.
+    kIdXsave64,                          //!< Instruction 'xsave64' {XSAVE} (X64).
+    kIdXsavec,                           //!< Instruction 'xsavec' {XSAVEC}.
+    kIdXsavec64,                         //!< Instruction 'xsavec64' {XSAVEC} (X64).
+    kIdXsaveopt,                         //!< Instruction 'xsaveopt' {XSAVEOPT}.
+    kIdXsaveopt64,                       //!< Instruction 'xsaveopt64' {XSAVEOPT} (X64).
+    kIdXsaves,                           //!< Instruction 'xsaves' {XSAVES}.
+    kIdXsaves64,                         //!< Instruction 'xsaves64' {XSAVES} (X64).
+    kIdXsetbv,                           //!< Instruction 'xsetbv' {XSAVE}.
+    kIdXsusldtrk,                        //!< Instruction 'xsusldtrk' {TSXLDTRK}.
+    kIdXtest,                            //!< Instruction 'xtest' {TSX}.
+    _kIdCount
+    // ${InstId:End}
+  };
+
+  //! Instruction options.
+  enum Options : uint32_t {
+    kOptionVex3           = 0x00000400u, //!< Use 3-byte VEX prefix if possible (AVX) (must be 0x00000400).
+    kOptionModMR          = 0x00000800u, //!< Use ModMR instead of ModRM when it's available.
+    kOptionEvex           = 0x00001000u, //!< Use 4-byte EVEX prefix if possible (AVX-512) (must be 0x00001000).
+
+    kOptionLock           = 0x00002000u, //!< LOCK prefix (lock-enabled instructions only).
+    kOptionRep            = 0x00004000u, //!< REP prefix (string instructions only).
+    kOptionRepne          = 0x00008000u, //!< REPNE prefix (string instructions only).
+
+    kOptionXAcquire       = 0x00010000u, //!< XACQUIRE prefix (only allowed instructions).
+    kOptionXRelease       = 0x00020000u, //!< XRELEASE prefix (only allowed instructions).
+
+    kOptionER             = 0x00040000u, //!< AVX-512: embedded-rounding {er} and implicit {sae}.
+    kOptionSAE            = 0x00080000u, //!< AVX-512: suppress-all-exceptions {sae}.
+    kOptionRN_SAE         = 0x00000000u, //!< AVX-512: round-to-nearest (even)      {rn-sae} (bits 00).
+    kOptionRD_SAE         = 0x00200000u, //!< AVX-512: round-down (toward -inf)     {rd-sae} (bits 01).
+    kOptionRU_SAE         = 0x00400000u, //!< AVX-512: round-up (toward +inf)       {ru-sae} (bits 10).
+    kOptionRZ_SAE         = 0x00600000u, //!< AVX-512: round-toward-zero (truncate) {rz-sae} (bits 11).
+    kOptionZMask          = 0x00800000u, //!< AVX-512: Use zeroing {k}{z} instead of merging {k}.
+    _kOptionAvx512Mask    = 0x00FC0000u, //!< AVX-512: Mask of all possible AVX-512 options except EVEX prefix flag.
+
+    kOptionOpCodeB        = 0x01000000u, //!< REX.B and/or VEX.B field (X64).
+    kOptionOpCodeX        = 0x02000000u, //!< REX.X and/or VEX.X field (X64).
+    kOptionOpCodeR        = 0x04000000u, //!< REX.R and/or VEX.R field (X64).
+    kOptionOpCodeW        = 0x08000000u, //!< REX.W and/or VEX.W field (X64).
+    kOptionRex            = 0x40000000u, //!< Force REX prefix (X64).
+    _kOptionInvalidRex    = 0x80000000u  //!< Invalid REX prefix (set by X86 or when AH|BH|CH|DH regs are used on X64).
+  };
+
+  // --------------------------------------------------------------------------
+  // [Statics]
+  // --------------------------------------------------------------------------
+
+  //! Tests whether the `instId` is defined (counts also Inst::kIdNone, which must be zero).
+  static inline bool isDefinedId(uint32_t instId) noexcept { return instId < _kIdCount; }
+};
+
+// ============================================================================
+// [asmjit::x86::Condition]
+// ============================================================================
+
+namespace Condition {
+  //! Condition code.
+  enum Code : uint32_t {
+    kO                    = 0x00u,       //!<                 OF==1
+    kNO                   = 0x01u,       //!<                 OF==0
+    kB                    = 0x02u,       //!< CF==1                  (unsigned < )
+    kC                    = 0x02u,       //!< CF==1
+    kNAE                  = 0x02u,       //!< CF==1                  (unsigned < )
+    kAE                   = 0x03u,       //!< CF==0                  (unsigned >=)
+    kNB                   = 0x03u,       //!< CF==0                  (unsigned >=)
+    kNC                   = 0x03u,       //!< CF==0
+    kE                    = 0x04u,       //!<         ZF==1          (any_sign ==)
+    kZ                    = 0x04u,       //!<         ZF==1          (any_sign ==)
+    kNE                   = 0x05u,       //!<         ZF==0          (any_sign !=)
+    kNZ                   = 0x05u,       //!<         ZF==0          (any_sign !=)
+    kBE                   = 0x06u,       //!< CF==1 | ZF==1          (unsigned <=)
+    kNA                   = 0x06u,       //!< CF==1 | ZF==1          (unsigned <=)
+    kA                    = 0x07u,       //!< CF==0 & ZF==0          (unsigned > )
+    kNBE                  = 0x07u,       //!< CF==0 & ZF==0          (unsigned > )
+    kS                    = 0x08u,       //!<                 SF==1  (is negative)
+    kNS                   = 0x09u,       //!<                 SF==0  (is positive or zero)
+    kP                    = 0x0Au,       //!< PF==1
+    kPE                   = 0x0Au,       //!< PF==1
+    kPO                   = 0x0Bu,       //!< PF==0
+    kNP                   = 0x0Bu,       //!< PF==0
+    kL                    = 0x0Cu,       //!<                 SF!=OF (signed   < )
+    kNGE                  = 0x0Cu,       //!<                 SF!=OF (signed   < )
+    kGE                   = 0x0Du,       //!<                 SF==OF (signed   >=)
+    kNL                   = 0x0Du,       //!<                 SF==OF (signed   >=)
+    kLE                   = 0x0Eu,       //!<         ZF==1 | SF!=OF (signed   <=)
+    kNG                   = 0x0Eu,       //!<         ZF==1 | SF!=OF (signed   <=)
+    kG                    = 0x0Fu,       //!<         ZF==0 & SF==OF (signed   > )
+    kNLE                  = 0x0Fu,       //!<         ZF==0 & SF==OF (signed   > )
+    kCount                = 0x10u,
+
+    kSign                 = kS,          //!< Sign.
+    kNotSign              = kNS,         //!< Not Sign.
+
+    kOverflow             = kO,          //!< Signed overflow.
+    kNotOverflow          = kNO,         //!< Not signed overflow.
+
+    kEqual                = kE,          //!< Equal      `a == b`.
+    kNotEqual             = kNE,         //!< Not Equal  `a != b`.
+
+    kSignedLT             = kL,          //!< Signed     `a <  b`.
+    kSignedLE             = kLE,         //!< Signed     `a <= b`.
+    kSignedGT             = kG,          //!< Signed     `a >  b`.
+    kSignedGE             = kGE,         //!< Signed     `a >= b`.
+
+    kUnsignedLT           = kB,          //!< Unsigned   `a <  b`.
+    kUnsignedLE           = kBE,         //!< Unsigned   `a <= b`.
+    kUnsignedGT           = kA,          //!< Unsigned   `a >  b`.
+    kUnsignedGE           = kAE,         //!< Unsigned   `a >= b`.
+
+    kZero                 = kZ,          //!< Zero flag.
+    kNotZero              = kNZ,         //!< Non-zero flag.
+
+    kNegative             = kS,          //!< Sign flag.
+    kPositive             = kNS,         //!< No sign flag.
+
+    kParityEven           = kP,          //!< Even parity flag.
+    kParityOdd            = kPO          //!< Odd parity flag.
+  };
+
+  static constexpr uint8_t reverseTable[kCount] = {
+    kO, kNO, kA , kBE, // O|NO|B |AE
+    kE, kNE, kAE, kB , // E|NE|BE|A
+    kS, kNS, kPE, kPO, // S|NS|PE|PO
+    kG, kLE, kGE, kL   // L|GE|LE|G
+  };
+
+  #define ASMJIT_INST_FROM_COND(ID) \
+    ID##o, ID##no, ID##b , ID##ae,  \
+    ID##e, ID##ne, ID##be, ID##a ,  \
+    ID##s, ID##ns, ID##pe, ID##po,  \
+    ID##l, ID##ge, ID##le, ID##g
+  static constexpr uint16_t jccTable[] = { ASMJIT_INST_FROM_COND(Inst::kIdJ) };
+  static constexpr uint16_t setccTable[] = { ASMJIT_INST_FROM_COND(Inst::kIdSet) };
+  static constexpr uint16_t cmovccTable[] = { ASMJIT_INST_FROM_COND(Inst::kIdCmov) };
+  #undef ASMJIT_INST_FROM_COND
+
+  //! Reverse a condition code (reverses the corresponding operands of a comparison).
+  static constexpr uint32_t reverse(uint32_t cond) noexcept { return reverseTable[cond]; }
+  //! Negate a condition code.
+  static constexpr uint32_t negate(uint32_t cond) noexcept { return cond ^ 1u; }
+
+  //! Translate a condition code `cond` to a `jcc` instruction id.
+  static constexpr uint32_t toJcc(uint32_t cond) noexcept { return jccTable[cond]; }
+  //! Translate a condition code `cond` to a `setcc` instruction id.
+  static constexpr uint32_t toSetcc(uint32_t cond) noexcept { return setccTable[cond]; }
+  //! Translate a condition code `cond` to a `cmovcc` instruction id.
+  static constexpr uint32_t toCmovcc(uint32_t cond) noexcept { return cmovccTable[cond]; }
+}
+
+// ============================================================================
+// [asmjit::x86::FpuWord]
+// ============================================================================
+
+//! FPU control and status words.
+namespace FpuWord {
+  //! FPU status word.
+  enum Status : uint32_t {
+    //! Invalid operation.
+    kStatusInvalid        = 0x0001u,
+    //! Denormalized operand.
+    kStatusDenormalized   = 0x0002u,
+    //! Division by zero.
+    kStatusDivByZero      = 0x0004u,
+    //! Overflown.
+    kStatusOverflow       = 0x0008u,
+    //! Underflown.
+    kStatusUnderflow      = 0x0010u,
+    //! Precision lost.
+    kStatusPrecision      = 0x0020u,
+    //! Stack fault.
+    kStatusStackFault     = 0x0040u,
+    //! Interrupt.
+    kStatusInterrupt      = 0x0080u,
+    //! C0 flag.
+    kStatusC0             = 0x0100u,
+    //! C1 flag.
+    kStatusC1             = 0x0200u,
+    //! C2 flag.
+    kStatusC2             = 0x0400u,
+    //! Top of the stack.
+    kStatusTop            = 0x3800u,
+    //! C3 flag.
+    kStatusC3             = 0x4000u,
+    //! FPU is busy.
+    kStatusBusy           = 0x8000u
+  };
+
+  //! FPU control word.
+  enum Control : uint32_t {
+    // [Bits 0-5]
+
+    //! Exception mask (0x3F).
+    kControlEM_Mask       = 0x003Fu,
+    //! Invalid operation exception.
+    kControlEM_Invalid    = 0x0001u,
+    //! Denormalized operand exception.
+    kControlEM_Denormal   = 0x0002u,
+    //! Division by zero exception.
+    kControlEM_DivByZero  = 0x0004u,
+    //! Overflow exception.
+    kControlEM_Overflow   = 0x0008u,
+    //! Underflow exception.
+    kControlEM_Underflow  = 0x0010u,
+    //! Inexact operation exception.
+    kControlEM_Inexact    = 0x0020u,
+
+    // [Bits 8-9]
+
+    //! Precision control mask.
+    kControlPC_Mask       = 0x0300u,
+    //! Single precision (24 bits).
+    kControlPC_Float      = 0x0000u,
+    //! Reserved.
+    kControlPC_Reserved   = 0x0100u,
+    //! Double precision (53 bits).
+    kControlPC_Double     = 0x0200u,
+    //! Extended precision (64 bits).
+    kControlPC_Extended   = 0x0300u,
+
+    // [Bits 10-11]
+
+    //! Rounding control mask.
+    kControlRC_Mask       = 0x0C00u,
+    //! Round to nearest even.
+    kControlRC_Nearest    = 0x0000u,
+    //! Round down (floor).
+    kControlRC_Down       = 0x0400u,
+    //! Round up (ceil).
+    kControlRC_Up         = 0x0800u,
+    //! Round towards zero (truncate).
+    kControlRC_Truncate   = 0x0C00u,
+
+    // [Bit 12]
+
+    //! Infinity control.
+    kControlIC_Mask       = 0x1000u,
+    //! Projective (not supported on X64).
+    kControlIC_Projective = 0x0000u,
+    //! Affine (default).
+    kControlIC_Affine     = 0x1000u
+  };
+}
+
+// ============================================================================
+// [asmjit::x86::Status]
+// ============================================================================
+
+//! CPU and FPU status flags.
+namespace Status {
+  //! CPU and FPU status flags used by `InstRWInfo`
+  enum Flags : uint32_t {
+    // ------------------------------------------------------------------------
+    // [Architecture Neutral Flags - 0x000000FF]
+    // ------------------------------------------------------------------------
+
+    //! Carry flag.
+    kCF = 0x00000001u,
+    //! Signed overflow flag.
+    kOF = 0x00000002u,
+    //! Sign flag (negative/sign, if set).
+    kSF = 0x00000004u,
+    //! Zero and/or equality flag (1 if zero/equal).
+    kZF = 0x00000008u,
+
+    // ------------------------------------------------------------------------
+    // [Architecture Specific Flags - 0xFFFFFF00]
+    // ------------------------------------------------------------------------
+
+    //! Adjust flag.
+    kAF = 0x00000100u,
+    //! Parity flag.
+    kPF = 0x00000200u,
+    //! Direction flag.
+    kDF = 0x00000400u,
+    //! Interrupt enable flag.
+    kIF = 0x00000800u,
+
+    //! Alignment check.
+    kAC = 0x00001000u,
+
+    //! FPU C0 status flag.
+    kC0 = 0x00010000u,
+    //! FPU C1 status flag.
+    kC1 = 0x00020000u,
+    //! FPU C2 status flag.
+    kC2 = 0x00040000u,
+    //! FPU C3 status flag.
+    kC3 = 0x00080000u
+  };
+}
+
+// ============================================================================
+// [asmjit::x86::Predicate]
+// ============================================================================
+
+//! Contains predicates used by SIMD instructions.
+namespace Predicate {
+  //! A predicate used by CMP[PD|PS|SD|SS] instructions.
+  enum Cmp : uint32_t {
+    kCmpEQ                = 0x00u,       //!< Equal (Quiet).
+    kCmpLT                = 0x01u,       //!< Less (Signaling).
+    kCmpLE                = 0x02u,       //!< Less/Equal (Signaling).
+    kCmpUNORD             = 0x03u,       //!< Unordered (Quiet).
+    kCmpNEQ               = 0x04u,       //!< Not Equal (Quiet).
+    kCmpNLT               = 0x05u,       //!< Not Less (Signaling).
+    kCmpNLE               = 0x06u,       //!< Not Less/Equal (Signaling).
+    kCmpORD               = 0x07u        //!< Ordered (Quiet).
+  };
+
+  //! A predicate used by [V]PCMP[I|E]STR[I|M] instructions.
+  enum PCmpStr : uint32_t {
+    // Source data format:
+    kPCmpStrUB            = 0x00u << 0,  //!< The source data format is unsigned bytes.
+    kPCmpStrUW            = 0x01u << 0,  //!< The source data format is unsigned words.
+    kPCmpStrSB            = 0x02u << 0,  //!< The source data format is signed bytes.
+    kPCmpStrSW            = 0x03u << 0,  //!< The source data format is signed words.
+
+    // Aggregation operation:
+    kPCmpStrEqualAny      = 0x00u << 2,  //!< The arithmetic comparison is "equal".
+    kPCmpStrRanges        = 0x01u << 2,  //!< The arithmetic comparison is "greater than or equal"
+                                         //!< between even indexed elements and "less than or equal"
+                                         //!< between odd indexed elements.
+    kPCmpStrEqualEach     = 0x02u << 2,  //!< The arithmetic comparison is "equal".
+    kPCmpStrEqualOrdered  = 0x03u << 2,  //!< The arithmetic comparison is "equal".
+
+    // Polarity:
+    kPCmpStrPosPolarity   = 0x00u << 4,  //!< IntRes2 = IntRes1.
+    kPCmpStrNegPolarity   = 0x01u << 4,  //!< IntRes2 = -1 XOR IntRes1.
+    kPCmpStrPosMasked     = 0x02u << 4,  //!< IntRes2 = IntRes1.
+    kPCmpStrNegMasked     = 0x03u << 4,  //!< IntRes2[i] = second[i] == invalid ? IntRes1[i] : ~IntRes1[i].
+
+    // Output selection (pcmpstri):
+    kPCmpStrOutputLSI     = 0x00u << 6,  //!< The index returned to ECX is of the least significant set bit in IntRes2.
+    kPCmpStrOutputMSI     = 0x01u << 6,  //!< The index returned to ECX is of the most significant set bit in IntRes2.
+
+    // Output selection (pcmpstrm):
+    kPCmpStrBitMask       = 0x00u << 6,  //!< IntRes2 is returned as the mask to the least significant bits of XMM0.
+    kPCmpStrIndexMask     = 0x01u << 6   //!< IntRes2 is expanded into a byte/word mask and placed in XMM0.
+  };
+
+  //! A predicate used by ROUND[PD|PS|SD|SS] instructions.
+  enum Round : uint32_t {
+    //! Round to nearest (even).
+    kRoundNearest = 0x00u,
+    //! Round to down toward -INF (floor),
+    kRoundDown = 0x01u,
+    //! Round to up toward +INF (ceil).
+    kRoundUp = 0x02u,
+    //! Round toward zero (truncate).
+    kRoundTrunc = 0x03u,
+    //! Round to the current rounding mode set (ignores other RC bits).
+    kRoundCurrent = 0x04u,
+    //! Avoids inexact exception, if set.
+    kRoundInexact = 0x08u
+  };
+
+  //! A predicate used by VCMP[PD|PS|SD|SS] instructions.
+  //!
+  //! The first 8 values are compatible with `Cmp`.
+  enum VCmp : uint32_t {
+    kVCmpEQ_OQ            = kCmpEQ,      //!< Equal             (Quiet    , Ordered).
+    kVCmpLT_OS            = kCmpLT,      //!< Less              (Signaling, Ordered).
+    kVCmpLE_OS            = kCmpLE,      //!< Less/Equal        (Signaling, Ordered).
+    kVCmpUNORD_Q          = kCmpUNORD,   //!< Unordered         (Quiet).
+    kVCmpNEQ_UQ           = kCmpNEQ,     //!< Not Equal         (Quiet    , Unordered).
+    kVCmpNLT_US           = kCmpNLT,     //!< Not Less          (Signaling, Unordered).
+    kVCmpNLE_US           = kCmpNLE,     //!< Not Less/Equal    (Signaling, Unordered).
+    kVCmpORD_Q            = kCmpORD,     //!< Ordered           (Quiet).
+    kVCmpEQ_UQ            = 0x08u,       //!< Equal             (Quiet    , Unordered).
+    kVCmpNGE_US           = 0x09u,       //!< Not Greater/Equal (Signaling, Unordered).
+    kVCmpNGT_US           = 0x0Au,       //!< Not Greater       (Signaling, Unordered).
+    kVCmpFALSE_OQ         = 0x0Bu,       //!< False             (Quiet    , Ordered).
+    kVCmpNEQ_OQ           = 0x0Cu,       //!< Not Equal         (Quiet    , Ordered).
+    kVCmpGE_OS            = 0x0Du,       //!< Greater/Equal     (Signaling, Ordered).
+    kVCmpGT_OS            = 0x0Eu,       //!< Greater           (Signaling, Ordered).
+    kVCmpTRUE_UQ          = 0x0Fu,       //!< True              (Quiet    , Unordered).
+    kVCmpEQ_OS            = 0x10u,       //!< Equal             (Signaling, Ordered).
+    kVCmpLT_OQ            = 0x11u,       //!< Less              (Quiet    , Ordered).
+    kVCmpLE_OQ            = 0x12u,       //!< Less/Equal        (Quiet    , Ordered).
+    kVCmpUNORD_S          = 0x13u,       //!< Unordered         (Signaling).
+    kVCmpNEQ_US           = 0x14u,       //!< Not Equal         (Signaling, Unordered).
+    kVCmpNLT_UQ           = 0x15u,       //!< Not Less          (Quiet    , Unordered).
+    kVCmpNLE_UQ           = 0x16u,       //!< Not Less/Equal    (Quiet    , Unordered).
+    kVCmpORD_S            = 0x17u,       //!< Ordered           (Signaling).
+    kVCmpEQ_US            = 0x18u,       //!< Equal             (Signaling, Unordered).
+    kVCmpNGE_UQ           = 0x19u,       //!< Not Greater/Equal (Quiet    , Unordered).
+    kVCmpNGT_UQ           = 0x1Au,       //!< Not Greater       (Quiet    , Unordered).
+    kVCmpFALSE_OS         = 0x1Bu,       //!< False             (Signaling, Ordered).
+    kVCmpNEQ_OS           = 0x1Cu,       //!< Not Equal         (Signaling, Ordered).
+    kVCmpGE_OQ            = 0x1Du,       //!< Greater/Equal     (Quiet    , Ordered).
+    kVCmpGT_OQ            = 0x1Eu,       //!< Greater           (Quiet    , Ordered).
+    kVCmpTRUE_US          = 0x1Fu        //!< True              (Signaling, Unordered).
+  };
+
+  //! A predicate used by VFIXUPIMM[PD|PS|SD|SS] instructions (AVX-512).
+  enum VFixupImm : uint32_t {
+    kVFixupImmZEOnZero    = 0x01u,
+    kVFixupImmIEOnZero    = 0x02u,
+    kVFixupImmZEOnOne     = 0x04u,
+    kVFixupImmIEOnOne     = 0x08u,
+    kVFixupImmIEOnSNaN    = 0x10u,
+    kVFixupImmIEOnNInf    = 0x20u,
+    kVFixupImmIEOnNegative= 0x40u,
+    kVFixupImmIEOnPInf    = 0x80u
+  };
+
+  //! A predicate used by VFPCLASS[PD|PS|SD|SS] instructions (AVX-512).
+  //!
+  //! \note Values can be combined together to form the final 8-bit mask.
+  enum VFPClass : uint32_t {
+    kVFPClassQNaN         = 0x01u,       //!< Checks for QNaN.
+    kVFPClassPZero        = 0x02u,       //!< Checks for +0.
+    kVFPClassNZero        = 0x04u,       //!< Checks for -0.
+    kVFPClassPInf         = 0x08u,       //!< Checks for +Inf.
+    kVFPClassNInf         = 0x10u,       //!< Checks for -Inf.
+    kVFPClassDenormal     = 0x20u,       //!< Checks for denormal.
+    kVFPClassNegative     = 0x40u,       //!< Checks for negative finite value.
+    kVFPClassSNaN         = 0x80u        //!< Checks for SNaN.
+  };
+
+  //! A predicate used by VGETMANT[PD|PS|SD|SS] instructions (AVX-512).
+  enum VGetMant : uint32_t {
+    kVGetMant1To2         = 0x00u,
+    kVGetMant1Div2To2     = 0x01u,
+    kVGetMant1Div2To1     = 0x02u,
+    kVGetMant3Div4To3Div2 = 0x03u,
+    kVGetMantNoSign       = 0x04u,
+    kVGetMantQNaNIfSign   = 0x08u
+  };
+
+  //! A predicate used by VPCMP[U][B|W|D|Q] instructions (AVX-512).
+  enum VPCmp : uint32_t {
+    kVPCmpEQ              = 0x00u,       //!< Equal.
+    kVPCmpLT              = 0x01u,       //!< Less.
+    kVPCmpLE              = 0x02u,       //!< Less/Equal.
+    kVPCmpFALSE           = 0x03u,       //!< False.
+    kVPCmpNE              = 0x04u,       //!< Not Equal.
+    kVPCmpGE              = 0x05u,       //!< Greater/Equal.
+    kVPCmpGT              = 0x06u,       //!< Greater.
+    kVPCmpTRUE            = 0x07u        //!< True.
+  };
+
+  //! A predicate used by VPCOM[U][B|W|D|Q] instructions (XOP).
+  enum VPCom : uint32_t {
+    kVPComLT              = 0x00u,       //!< Less.
+    kVPComLE              = 0x01u,       //!< Less/Equal
+    kVPComGT              = 0x02u,       //!< Greater.
+    kVPComGE              = 0x03u,       //!< Greater/Equal.
+    kVPComEQ              = 0x04u,       //!< Equal.
+    kVPComNE              = 0x05u,       //!< Not Equal.
+    kVPComFALSE           = 0x06u,       //!< False.
+    kVPComTRUE            = 0x07u        //!< True.
+  };
+
+  //! A predicate used by VRANGE[PD|PS|SD|SS] instructions (AVX-512).
+  enum VRange : uint32_t {
+    kVRangeSelectMin      = 0x00u,       //!< Select minimum value.
+    kVRangeSelectMax      = 0x01u,       //!< Select maximum value.
+    kVRangeSelectAbsMin   = 0x02u,       //!< Select minimum absolute value.
+    kVRangeSelectAbsMax   = 0x03u,       //!< Select maximum absolute value.
+    kVRangeSignSrc1       = 0x00u,       //!< Select sign of SRC1.
+    kVRangeSignSrc2       = 0x04u,       //!< Select sign of SRC2.
+    kVRangeSign0          = 0x08u,       //!< Set sign to 0.
+    kVRangeSign1          = 0x0Cu        //!< Set sign to 1.
+  };
+
+  //! A predicate used by VREDUCE[PD|PS|SD|SS] instructions (AVX-512).
+  enum VReduce : uint32_t {
+    kVReduceRoundCurrent  = 0x00u,       //!< Round to the current mode set.
+    kVReduceRoundEven     = 0x04u,       //!< Round to nearest even.
+    kVReduceRoundDown     = 0x05u,       //!< Round down.
+    kVReduceRoundUp       = 0x06u,       //!< Round up.
+    kVReduceRoundTrunc    = 0x07u,       //!< Truncate.
+    kVReduceSuppress      = 0x08u        //!< Suppress exceptions.
+  };
+
+  //! Pack a shuffle constant to be used by SSE/AVX/AVX-512 instructions (2 values).
+  //!
+  //! \param a Position of the first  component [0, 1].
+  //! \param b Position of the second component [0, 1].
+  //!
+  //! Shuffle constants can be used to encode an immediate for these instructions:
+  //!   - `shufpd|vshufpd`
+  static constexpr uint32_t shuf(uint32_t a, uint32_t b) noexcept {
+    return (a << 1) | b;
+  }
+
+  //! Pack a shuffle constant to be used by SSE/AVX/AVX-512 instructions (4 values).
+  //!
+  //! \param a Position of the first  component [0, 3].
+  //! \param b Position of the second component [0, 3].
+  //! \param c Position of the third  component [0, 3].
+  //! \param d Position of the fourth component [0, 3].
+  //!
+  //! Shuffle constants can be used to encode an immediate for these instructions:
+  //!   - `pshufw`
+  //!   - `pshuflw|vpshuflw`
+  //!   - `pshufhw|vpshufhw`
+  //!   - `pshufd|vpshufd`
+  //!   - `shufps|vshufps`
+  static constexpr uint32_t shuf(uint32_t a, uint32_t b, uint32_t c, uint32_t d) noexcept {
+    return (a << 6) | (b << 4) | (c << 2) | d;
+  }
+}
+
+// ============================================================================
+// [asmjit::x86::TLog]
+// ============================================================================
+
+//! Bitwise ternary logic between 3 operands introduced by AVX-512.
+namespace TLog {
+  //! A predicate that can be used to create a common predicate for VPTERNLOG[D|Q].
+  //!
+  //! There are 3 inputs to the instruction (\ref kA, \ref kB, \ref kC), and
+  //! ternary logic can define any combination that would be performed on these
+  //! 3 inputs to get the desired output - any combination of AND, OR, XOR, NOT.
+  enum Operator : uint32_t {
+    //! 0 value.
+    k0 = 0x00u,
+    //! 1 value.
+    k1 = 0xFFu,
+    //! A value.
+    kA = 0xF0u,
+    //! B value.
+    kB = 0xCCu,
+    //! C value.
+    kC = 0xAAu,
+
+    //! `!A` expression.
+    kNotA = kA ^ k1,
+    //! `!B` expression.
+    kNotB = kB ^ k1,
+    //! `!C` expression.
+    kNotC = kC ^ k1,
+
+    //! `A & B` expression.
+    kAB = kA & kB,
+    //! `A & C` expression.
+    kAC = kA & kC,
+    //! `B & C` expression.
+    kBC = kB & kC,
+    //! `!(A & B)` expression.
+    kNotAB = kAB ^ k1,
+    //! `!(A & C)` expression.
+    kNotAC = kAC ^ k1,
+    //! `!(B & C)` expression.
+    kNotBC = kBC ^ k1,
+
+    //! `A & B & C` expression.
+    kABC = kAB & kC,
+    //! `!(A & B & C)` expression.
+    kNotABC = kABC ^ k1
+  };
+
+  //! Creates an immediate that can be used by VPTERNLOG[D|Q] instructions.
+  static constexpr uint32_t make(uint32_t b000, uint32_t b001, uint32_t b010, uint32_t b011, uint32_t b100, uint32_t b101, uint32_t b110, uint32_t b111) noexcept {
+    return (b000 << 0) | (b001 << 1) | (b010 << 2) | (b011 << 3) | (b100 << 4) | (b101 << 5) | (b110 << 6) | (b111 << 7);
+  }
+
+  //! Creates an immediate that can be used by VPTERNLOG[D|Q] instructions.
+  static constexpr uint32_t value(uint32_t x) noexcept { return x & 0xFF; }
+  //! Negate an immediate that can be used by VPTERNLOG[D|Q] instructions.
+  static constexpr uint32_t negate(uint32_t x) noexcept { return x ^ 0xFF; }
+  //! Creates an if/else logic that can be used by VPTERNLOG[D|Q] instructions.
+  static constexpr uint32_t ifElse(uint32_t condition, uint32_t a, uint32_t b) noexcept { return (condition & a) | (negate(condition) & b); }
+}
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86GLOBALS_H_INCLUDED
diff --git a/client/asmjit/x86/x86instapi.cpp b/client/asmjit/x86/x86instapi.cpp
new file mode 100644
index 0000000..9ad8f93
--- /dev/null
+++ b/client/asmjit/x86/x86instapi.cpp
@@ -0,0 +1,1567 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+// ----------------------------------------------------------------------------
+// IMPORTANT: AsmJit now uses an external instruction database to populate
+// static tables within this file. Perform the following steps to regenerate
+// all tables enclosed by ${...}:
+//
+//   1. Install node.js environment <https://nodejs.org>
+//   2. Go to asmjit/tools directory
+//   3. Get the latest asmdb from <https://github.com/asmjit/asmdb> and
+//      copy/link the `asmdb` directory to `asmjit/tools/asmdb`.
+//   4. Execute `node tablegen-x86.js`
+//
+// Instruction encoding and opcodes were added to the `x86inst.cpp` database
+// manually in the past and they are not updated by the script as it became
+// tricky. However, everything else is updated including instruction operands
+// and tables required to validate them, instruction read/write information
+// (including registers and flags), and all indexes to all tables.
+// ----------------------------------------------------------------------------
+
+#include "../core/api-build_p.h"
+#ifdef ASMJIT_BUILD_X86
+
+#include "../core/cpuinfo.h"
+#include "../core/misc_p.h"
+#include "../core/support.h"
+#include "../x86/x86features.h"
+#include "../x86/x86instapi_p.h"
+#include "../x86/x86instdb_p.h"
+#include "../x86/x86opcode_p.h"
+#include "../x86/x86operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::x86::InstInternal - Text]
+// ============================================================================
+
+#ifndef ASMJIT_NO_TEXT
+Error InstInternal::instIdToString(uint32_t arch, uint32_t instId, String& output) noexcept {
+  DebugUtils::unused(arch);
+
+  if (ASMJIT_UNLIKELY(!Inst::isDefinedId(instId)))
+    return DebugUtils::errored(kErrorInvalidInstruction);
+
+  const InstDB::InstInfo& info = InstDB::infoById(instId);
+  return output.append(InstDB::_nameData + info._nameDataIndex);
+}
+
+uint32_t InstInternal::stringToInstId(uint32_t arch, const char* s, size_t len) noexcept {
+  DebugUtils::unused(arch);
+
+  if (ASMJIT_UNLIKELY(!s))
+    return Inst::kIdNone;
+
+  if (len == SIZE_MAX)
+    len = strlen(s);
+
+  if (ASMJIT_UNLIKELY(len == 0 || len > InstDB::kMaxNameSize))
+    return Inst::kIdNone;
+
+  uint32_t prefix = uint32_t(s[0]) - 'a';
+  if (ASMJIT_UNLIKELY(prefix > 'z' - 'a'))
+    return Inst::kIdNone;
+
+  uint32_t index = InstDB::instNameIndex[prefix].start;
+  if (ASMJIT_UNLIKELY(!index))
+    return Inst::kIdNone;
+
+  const char* nameData = InstDB::_nameData;
+  const InstDB::InstInfo* table = InstDB::_instInfoTable;
+
+  const InstDB::InstInfo* base = table + index;
+  const InstDB::InstInfo* end  = table + InstDB::instNameIndex[prefix].end;
+
+  for (size_t lim = (size_t)(end - base); lim != 0; lim >>= 1) {
+    const InstDB::InstInfo* cur = base + (lim >> 1);
+    int result = Support::cmpInstName(nameData + cur[0]._nameDataIndex, s, len);
+
+    if (result < 0) {
+      base = cur + 1;
+      lim--;
+      continue;
+    }
+
+    if (result > 0)
+      continue;
+
+    return uint32_t((size_t)(cur - table));
+  }
+
+  return Inst::kIdNone;
+}
+#endif // !ASMJIT_NO_TEXT
+
+// ============================================================================
+// [asmjit::x86::InstInternal - Validate]
+// ============================================================================
+
+#ifndef ASMJIT_NO_VALIDATION
+struct X86ValidationData {
+  //! Allowed registers by reg-type (x86::Reg::kType...).
+  uint32_t allowedRegMask[Reg::kTypeMax + 1];
+  uint32_t allowedMemBaseRegs;
+  uint32_t allowedMemIndexRegs;
+};
+
+#define VALUE(X) \
+  (X == Reg::kTypeGpbLo) ? InstDB::kOpGpbLo : \
+  (X == Reg::kTypeGpbHi) ? InstDB::kOpGpbHi : \
+  (X == Reg::kTypeGpw  ) ? InstDB::kOpGpw   : \
+  (X == Reg::kTypeGpd  ) ? InstDB::kOpGpd   : \
+  (X == Reg::kTypeGpq  ) ? InstDB::kOpGpq   : \
+  (X == Reg::kTypeXmm  ) ? InstDB::kOpXmm   : \
+  (X == Reg::kTypeYmm  ) ? InstDB::kOpYmm   : \
+  (X == Reg::kTypeZmm  ) ? InstDB::kOpZmm   : \
+  (X == Reg::kTypeMm   ) ? InstDB::kOpMm    : \
+  (X == Reg::kTypeKReg ) ? InstDB::kOpKReg  : \
+  (X == Reg::kTypeSReg ) ? InstDB::kOpSReg  : \
+  (X == Reg::kTypeCReg ) ? InstDB::kOpCReg  : \
+  (X == Reg::kTypeDReg ) ? InstDB::kOpDReg  : \
+  (X == Reg::kTypeSt   ) ? InstDB::kOpSt    : \
+  (X == Reg::kTypeBnd  ) ? InstDB::kOpBnd   : \
+  (X == Reg::kTypeTmm  ) ? InstDB::kOpTmm   : \
+  (X == Reg::kTypeRip  ) ? InstDB::kOpNone  : InstDB::kOpNone
+static const uint32_t _x86OpFlagFromRegType[Reg::kTypeMax + 1] = { ASMJIT_LOOKUP_TABLE_32(VALUE, 0) };
+#undef VALUE
+
+#define REG_MASK_FROM_REG_TYPE_X86(X) \
+  (X == Reg::kTypeGpbLo) ? 0x0000000Fu : \
+  (X == Reg::kTypeGpbHi) ? 0x0000000Fu : \
+  (X == Reg::kTypeGpw  ) ? 0x000000FFu : \
+  (X == Reg::kTypeGpd  ) ? 0x000000FFu : \
+  (X == Reg::kTypeGpq  ) ? 0x000000FFu : \
+  (X == Reg::kTypeXmm  ) ? 0x000000FFu : \
+  (X == Reg::kTypeYmm  ) ? 0x000000FFu : \
+  (X == Reg::kTypeZmm  ) ? 0x000000FFu : \
+  (X == Reg::kTypeMm   ) ? 0x000000FFu : \
+  (X == Reg::kTypeKReg ) ? 0x000000FFu : \
+  (X == Reg::kTypeSReg ) ? 0x0000007Eu : \
+  (X == Reg::kTypeCReg ) ? 0x0000FFFFu : \
+  (X == Reg::kTypeDReg ) ? 0x000000FFu : \
+  (X == Reg::kTypeSt   ) ? 0x000000FFu : \
+  (X == Reg::kTypeBnd  ) ? 0x0000000Fu : \
+  (X == Reg::kTypeTmm  ) ? 0x000000FFu : \
+  (X == Reg::kTypeRip  ) ? 0x00000001u : 0u
+
+#define REG_MASK_FROM_REG_TYPE_X64(X) \
+  (X == Reg::kTypeGpbLo) ? 0x0000FFFFu : \
+  (X == Reg::kTypeGpbHi) ? 0x0000000Fu : \
+  (X == Reg::kTypeGpw  ) ? 0x0000FFFFu : \
+  (X == Reg::kTypeGpd  ) ? 0x0000FFFFu : \
+  (X == Reg::kTypeGpq  ) ? 0x0000FFFFu : \
+  (X == Reg::kTypeXmm  ) ? 0xFFFFFFFFu : \
+  (X == Reg::kTypeYmm  ) ? 0xFFFFFFFFu : \
+  (X == Reg::kTypeZmm  ) ? 0xFFFFFFFFu : \
+  (X == Reg::kTypeMm   ) ? 0x000000FFu : \
+  (X == Reg::kTypeKReg ) ? 0x000000FFu : \
+  (X == Reg::kTypeSReg ) ? 0x0000007Eu : \
+  (X == Reg::kTypeCReg ) ? 0x0000FFFFu : \
+  (X == Reg::kTypeDReg ) ? 0x0000FFFFu : \
+  (X == Reg::kTypeSt   ) ? 0x000000FFu : \
+  (X == Reg::kTypeBnd  ) ? 0x0000000Fu : \
+  (X == Reg::kTypeTmm  ) ? 0x000000FFu : \
+  (X == Reg::kTypeRip  ) ? 0x00000001u : 0u
+
+static const X86ValidationData _x86ValidationData = {
+  { ASMJIT_LOOKUP_TABLE_32(REG_MASK_FROM_REG_TYPE_X86, 0) },
+  (1u << Reg::kTypeGpw) | (1u << Reg::kTypeGpd) | (1u << Reg::kTypeRip) | (1u << Label::kLabelTag),
+  (1u << Reg::kTypeGpw) | (1u << Reg::kTypeGpd) | (1u << Reg::kTypeXmm) | (1u << Reg::kTypeYmm) | (1u << Reg::kTypeZmm)
+};
+
+static const X86ValidationData _x64ValidationData = {
+  { ASMJIT_LOOKUP_TABLE_32(REG_MASK_FROM_REG_TYPE_X64, 0) },
+  (1u << Reg::kTypeGpd) | (1u << Reg::kTypeGpq) | (1u << Reg::kTypeRip) | (1u << Label::kLabelTag),
+  (1u << Reg::kTypeGpd) | (1u << Reg::kTypeGpq) | (1u << Reg::kTypeXmm) | (1u << Reg::kTypeYmm) | (1u << Reg::kTypeZmm)
+};
+
+#undef REG_MASK_FROM_REG_TYPE_X64
+#undef REG_MASK_FROM_REG_TYPE_X86
+
+static ASMJIT_INLINE bool x86IsZmmOrM512(const Operand_& op) noexcept {
+  return Reg::isZmm(op) || (op.isMem() && op.size() == 64);
+}
+
+static ASMJIT_INLINE bool x86CheckOSig(const InstDB::OpSignature& op, const InstDB::OpSignature& ref, bool& immOutOfRange) noexcept {
+  // Fail if operand types are incompatible.
+  uint32_t opFlags = op.opFlags;
+  if ((opFlags & ref.opFlags) == 0) {
+    // Mark temporarily `immOutOfRange` so we can return a more descriptive error later.
+    if ((opFlags & InstDB::kOpAllImm) && (ref.opFlags & InstDB::kOpAllImm)) {
+      immOutOfRange = true;
+      return true;
+    }
+
+    return false;
+  }
+
+  // Fail if memory specific flags and sizes do not match the signature.
+  uint32_t opMemFlags = op.memFlags;
+  if (opMemFlags != 0) {
+    uint32_t refMemFlags = ref.memFlags;
+    if ((refMemFlags & opMemFlags) == 0)
+      return false;
+
+    if ((refMemFlags & InstDB::kMemOpBaseOnly) && !(opMemFlags & InstDB::kMemOpBaseOnly))
+      return false;
+  }
+
+  // Specific register index.
+  if (opFlags & InstDB::kOpAllRegs) {
+    uint32_t refRegMask = ref.regMask;
+    if (refRegMask && !(op.regMask & refRegMask))
+      return false;
+  }
+
+  return true;
+}
+
+ASMJIT_FAVOR_SIZE Error InstInternal::validate(uint32_t arch, const BaseInst& inst, const Operand_* operands, size_t opCount, uint32_t validationFlags) noexcept {
+  // Only called when `arch` matches X86 family.
+  ASMJIT_ASSERT(Environment::isFamilyX86(arch));
+
+  const X86ValidationData* vd;
+  if (arch == Environment::kArchX86)
+    vd = &_x86ValidationData;
+  else
+    vd = &_x64ValidationData;
+
+  uint32_t i;
+  uint32_t mode = InstDB::modeFromArch(arch);
+
+  // Get the instruction data.
+  uint32_t instId = inst.id();
+  uint32_t options = inst.options();
+
+  if (ASMJIT_UNLIKELY(!Inst::isDefinedId(instId)))
+    return DebugUtils::errored(kErrorInvalidInstruction);
+
+  const InstDB::InstInfo& instInfo = InstDB::infoById(instId);
+  const InstDB::CommonInfo& commonInfo = instInfo.commonInfo();
+
+  uint32_t iFlags = instInfo.flags();
+
+  // --------------------------------------------------------------------------
+  // [Validate LOCK|XACQUIRE|XRELEASE]
+  // --------------------------------------------------------------------------
+
+  const uint32_t kLockXAcqRel = Inst::kOptionXAcquire | Inst::kOptionXRelease;
+  if (options & (Inst::kOptionLock | kLockXAcqRel)) {
+    if (options & Inst::kOptionLock) {
+      if (ASMJIT_UNLIKELY(!(iFlags & InstDB::kFlagLock) && !(options & kLockXAcqRel)))
+        return DebugUtils::errored(kErrorInvalidLockPrefix);
+
+      if (ASMJIT_UNLIKELY(opCount < 1 || !operands[0].isMem()))
+        return DebugUtils::errored(kErrorInvalidLockPrefix);
+    }
+
+    if (options & kLockXAcqRel) {
+      if (ASMJIT_UNLIKELY(!(options & Inst::kOptionLock) || (options & kLockXAcqRel) == kLockXAcqRel))
+        return DebugUtils::errored(kErrorInvalidPrefixCombination);
+
+      if (ASMJIT_UNLIKELY((options & Inst::kOptionXAcquire) && !(iFlags & InstDB::kFlagXAcquire)))
+        return DebugUtils::errored(kErrorInvalidXAcquirePrefix);
+
+      if (ASMJIT_UNLIKELY((options & Inst::kOptionXRelease) && !(iFlags & InstDB::kFlagXRelease)))
+        return DebugUtils::errored(kErrorInvalidXReleasePrefix);
+    }
+  }
+
+  // Validate REP and REPNE prefixes.
+  const uint32_t kRepAny = Inst::kOptionRep | Inst::kOptionRepne;
+  if (options & kRepAny) {
+    if (ASMJIT_UNLIKELY((options & kRepAny) == kRepAny))
+      return DebugUtils::errored(kErrorInvalidPrefixCombination);
+
+    if (ASMJIT_UNLIKELY(!(iFlags & InstDB::kFlagRep)))
+      return DebugUtils::errored(kErrorInvalidRepPrefix);
+  }
+
+  // --------------------------------------------------------------------------
+  // [Translate Each Operand to the Corresponding OpSignature]
+  // --------------------------------------------------------------------------
+
+  InstDB::OpSignature oSigTranslated[Globals::kMaxOpCount];
+  uint32_t combinedOpFlags = 0;
+  uint32_t combinedRegMask = 0;
+  const Mem* memOp = nullptr;
+
+  for (i = 0; i < opCount; i++) {
+    const Operand_& op = operands[i];
+    if (op.opType() == Operand::kOpNone)
+      break;
+
+    uint32_t opFlags = 0;
+    uint32_t memFlags = 0;
+    uint32_t regMask = 0;
+
+    switch (op.opType()) {
+      case Operand::kOpReg: {
+        uint32_t regType = op.as<BaseReg>().type();
+        if (ASMJIT_UNLIKELY(regType >= Reg::kTypeCount))
+          return DebugUtils::errored(kErrorInvalidRegType);
+
+        opFlags = _x86OpFlagFromRegType[regType];
+        if (ASMJIT_UNLIKELY(opFlags == 0))
+          return DebugUtils::errored(kErrorInvalidRegType);
+
+        // If `regId` is equal or greater than Operand::kVirtIdMin it means
+        // that the register is virtual and its index will be assigned later
+        // by the register allocator. We must pass unless asked to disallow
+        // virtual registers.
+        uint32_t regId = op.id();
+        if (regId < Operand::kVirtIdMin) {
+          if (ASMJIT_UNLIKELY(regId >= 32))
+            return DebugUtils::errored(kErrorInvalidPhysId);
+
+          if (ASMJIT_UNLIKELY(Support::bitTest(vd->allowedRegMask[regType], regId) == 0))
+            return DebugUtils::errored(kErrorInvalidPhysId);
+
+          regMask = Support::bitMask(regId);
+          combinedRegMask |= regMask;
+        }
+        else {
+          if (!(validationFlags & InstAPI::kValidationFlagVirtRegs))
+            return DebugUtils::errored(kErrorIllegalVirtReg);
+          regMask = 0xFFFFFFFFu;
+        }
+        break;
+      }
+
+      // TODO: Validate base and index and combine these with `combinedRegMask`.
+      case Operand::kOpMem: {
+        const Mem& m = op.as<Mem>();
+        memOp = &m;
+
+        uint32_t memSize = m.size();
+        uint32_t baseType = m.baseType();
+        uint32_t indexType = m.indexType();
+
+        if (m.segmentId() > 6)
+          return DebugUtils::errored(kErrorInvalidSegment);
+
+        // Validate AVX-512 broadcast {1tox}.
+        if (m.hasBroadcast()) {
+          if (memSize != 0) {
+            // If the size is specified it has to match the broadcast size.
+            if (ASMJIT_UNLIKELY(commonInfo.hasAvx512B32() && memSize != 4))
+              return DebugUtils::errored(kErrorInvalidBroadcast);
+
+            if (ASMJIT_UNLIKELY(commonInfo.hasAvx512B64() && memSize != 8))
+              return DebugUtils::errored(kErrorInvalidBroadcast);
+          }
+          else {
+            // If there is no size we implicitly calculate it so we can validate N in {1toN} properly.
+            memSize = commonInfo.hasAvx512B32() ? 4 : 8;
+          }
+
+          memSize <<= m.getBroadcast();
+        }
+
+        if (baseType != 0 && baseType > Label::kLabelTag) {
+          uint32_t baseId = m.baseId();
+
+          if (m.isRegHome()) {
+            // Home address of a virtual register. In such case we don't want to
+            // validate the type of the base register as it will always be patched
+            // to ESP|RSP.
+          }
+          else {
+            if (ASMJIT_UNLIKELY((vd->allowedMemBaseRegs & (1u << baseType)) == 0))
+              return DebugUtils::errored(kErrorInvalidAddress);
+          }
+
+          // Create information that will be validated only if this is an implicit
+          // memory operand. Basically only usable for string instructions and other
+          // instructions where memory operand is implicit and has 'seg:[reg]' form.
+          if (baseId < Operand::kVirtIdMin) {
+            if (ASMJIT_UNLIKELY(baseId >= 32))
+              return DebugUtils::errored(kErrorInvalidPhysId);
+
+            // Physical base id.
+            regMask = Support::bitMask(baseId);
+            combinedRegMask |= regMask;
+          }
+          else {
+            // Virtual base id - fill the whole mask for implicit mem validation.
+            // The register is not assigned yet, so we cannot predict the phys id.
+            if (!(validationFlags & InstAPI::kValidationFlagVirtRegs))
+              return DebugUtils::errored(kErrorIllegalVirtReg);
+            regMask = 0xFFFFFFFFu;
+          }
+
+          if (!indexType && !m.offsetLo32())
+            memFlags |= InstDB::kMemOpBaseOnly;
+        }
+        else if (baseType == Label::kLabelTag) {
+          // [Label] - there is no need to validate the base as it's label.
+        }
+        else {
+          // Base is a 64-bit address.
+          int64_t offset = m.offset();
+          if (!Support::isInt32(offset)) {
+            if (mode == InstDB::kModeX86) {
+              // 32-bit mode: Make sure that the address is either `int32_t` or `uint32_t`.
+              if (!Support::isUInt32(offset))
+                return DebugUtils::errored(kErrorInvalidAddress64Bit);
+            }
+            else {
+              // 64-bit mode: Zero extension is allowed if the address has 32-bit index
+              // register or the address has no index register (it's still encodable).
+              if (indexType) {
+                if (!Support::isUInt32(offset))
+                  return DebugUtils::errored(kErrorInvalidAddress64Bit);
+
+                if (indexType != Reg::kTypeGpd)
+                  return DebugUtils::errored(kErrorInvalidAddress64BitZeroExtension);
+              }
+              else {
+                // We don't validate absolute 64-bit addresses without an index register
+                // as this also depends on the target's base address. We don't have the
+                // information to do it at this moment.
+              }
+            }
+          }
+        }
+
+        if (indexType) {
+          if (ASMJIT_UNLIKELY((vd->allowedMemIndexRegs & (1u << indexType)) == 0))
+            return DebugUtils::errored(kErrorInvalidAddress);
+
+          if (indexType == Reg::kTypeXmm) {
+            opFlags |= InstDB::kOpVm;
+            memFlags |= InstDB::kMemOpVm32x | InstDB::kMemOpVm64x;
+          }
+          else if (indexType == Reg::kTypeYmm) {
+            opFlags |= InstDB::kOpVm;
+            memFlags |= InstDB::kMemOpVm32y | InstDB::kMemOpVm64y;
+          }
+          else if (indexType == Reg::kTypeZmm) {
+            opFlags |= InstDB::kOpVm;
+            memFlags |= InstDB::kMemOpVm32z | InstDB::kMemOpVm64z;
+          }
+          else {
+            opFlags |= InstDB::kOpMem;
+            if (baseType)
+              memFlags |= InstDB::kMemOpMib;
+          }
+
+          // [RIP + {XMM|YMM|ZMM}] is not allowed.
+          if (baseType == Reg::kTypeRip && (opFlags & InstDB::kOpVm))
+            return DebugUtils::errored(kErrorInvalidAddress);
+
+          uint32_t indexId = m.indexId();
+          if (indexId < Operand::kVirtIdMin) {
+            if (ASMJIT_UNLIKELY(indexId >= 32))
+              return DebugUtils::errored(kErrorInvalidPhysId);
+
+            combinedRegMask |= Support::bitMask(indexId);
+          }
+          else {
+            if (!(validationFlags & InstAPI::kValidationFlagVirtRegs))
+              return DebugUtils::errored(kErrorIllegalVirtReg);
+          }
+
+          // Only used for implicit memory operands having 'seg:[reg]' form, so clear it.
+          regMask = 0;
+        }
+        else {
+          opFlags |= InstDB::kOpMem;
+        }
+
+        switch (memSize) {
+          case  0: memFlags |= InstDB::kMemOpAny ; break;
+          case  1: memFlags |= InstDB::kMemOpM8  ; break;
+          case  2: memFlags |= InstDB::kMemOpM16 ; break;
+          case  4: memFlags |= InstDB::kMemOpM32 ; break;
+          case  6: memFlags |= InstDB::kMemOpM48 ; break;
+          case  8: memFlags |= InstDB::kMemOpM64 ; break;
+          case 10: memFlags |= InstDB::kMemOpM80 ; break;
+          case 16: memFlags |= InstDB::kMemOpM128; break;
+          case 32: memFlags |= InstDB::kMemOpM256; break;
+          case 64: memFlags |= InstDB::kMemOpM512; break;
+          default:
+            return DebugUtils::errored(kErrorInvalidOperandSize);
+        }
+
+        break;
+      }
+
+      case Operand::kOpImm: {
+        uint64_t immValue = op.as<Imm>().valueAs<uint64_t>();
+        uint32_t immFlags = 0;
+
+        if (int64_t(immValue) >= 0) {
+          if (immValue <= 0x7u)
+            immFlags = InstDB::kOpI64 | InstDB::kOpU64 | InstDB::kOpI32 | InstDB::kOpU32 |
+                       InstDB::kOpI16 | InstDB::kOpU16 | InstDB::kOpI8  | InstDB::kOpU8  |
+                       InstDB::kOpI4  | InstDB::kOpU4  ;
+          else if (immValue <= 0xFu)
+            immFlags = InstDB::kOpI64 | InstDB::kOpU64 | InstDB::kOpI32 | InstDB::kOpU32 |
+                       InstDB::kOpI16 | InstDB::kOpU16 | InstDB::kOpI8  | InstDB::kOpU8  |
+                       InstDB::kOpU4  ;
+          else if (immValue <= 0x7Fu)
+            immFlags = InstDB::kOpI64 | InstDB::kOpU64 | InstDB::kOpI32 | InstDB::kOpU32 |
+                       InstDB::kOpI16 | InstDB::kOpU16 | InstDB::kOpI8  | InstDB::kOpU8  ;
+          else if (immValue <= 0xFFu)
+            immFlags = InstDB::kOpI64 | InstDB::kOpU64 | InstDB::kOpI32 | InstDB::kOpU32 |
+                       InstDB::kOpI16 | InstDB::kOpU16 | InstDB::kOpU8  ;
+          else if (immValue <= 0x7FFFu)
+            immFlags = InstDB::kOpI64 | InstDB::kOpU64 | InstDB::kOpI32 | InstDB::kOpU32 |
+                       InstDB::kOpI16 | InstDB::kOpU16 ;
+          else if (immValue <= 0xFFFFu)
+            immFlags = InstDB::kOpI64 | InstDB::kOpU64 | InstDB::kOpI32 | InstDB::kOpU32 |
+                       InstDB::kOpU16 ;
+          else if (immValue <= 0x7FFFFFFFu)
+            immFlags = InstDB::kOpI64 | InstDB::kOpU64 | InstDB::kOpI32 | InstDB::kOpU32;
+          else if (immValue <= 0xFFFFFFFFu)
+            immFlags = InstDB::kOpI64 | InstDB::kOpU64 | InstDB::kOpU32;
+          else if (immValue <= 0x7FFFFFFFFFFFFFFFu)
+            immFlags = InstDB::kOpI64 | InstDB::kOpU64;
+          else
+            immFlags = InstDB::kOpU64;
+        }
+        else {
+          immValue = Support::neg(immValue);
+          if (immValue <= 0x8u)
+            immFlags = InstDB::kOpI64 | InstDB::kOpI32 | InstDB::kOpI16 | InstDB::kOpI8 | InstDB::kOpI4;
+          else if (immValue <= 0x80u)
+            immFlags = InstDB::kOpI64 | InstDB::kOpI32 | InstDB::kOpI16 | InstDB::kOpI8;
+          else if (immValue <= 0x8000u)
+            immFlags = InstDB::kOpI64 | InstDB::kOpI32 | InstDB::kOpI16;
+          else if (immValue <= 0x80000000u)
+            immFlags = InstDB::kOpI64 | InstDB::kOpI32;
+          else
+            immFlags = InstDB::kOpI64;
+        }
+        opFlags |= immFlags;
+        break;
+      }
+
+      case Operand::kOpLabel: {
+        opFlags |= InstDB::kOpRel8 | InstDB::kOpRel32;
+        break;
+      }
+
+      default:
+        return DebugUtils::errored(kErrorInvalidState);
+    }
+
+    InstDB::OpSignature& oSigDst = oSigTranslated[i];
+    oSigDst.opFlags = opFlags;
+    oSigDst.memFlags = uint16_t(memFlags);
+    oSigDst.regMask = uint8_t(regMask & 0xFFu);
+    combinedOpFlags |= opFlags;
+  }
+
+  // Decrease the number of operands of those that are none. This is important
+  // as Assembler and Compiler may just pass more operands padded with none
+  // (which means that no operand is given at that index). However, validate
+  // that there are no gaps (like [reg, none, reg] or [none, reg]).
+  if (i < opCount) {
+    while (--opCount > i)
+      if (ASMJIT_UNLIKELY(!operands[opCount].isNone()))
+        return DebugUtils::errored(kErrorInvalidInstruction);
+  }
+
+  // Validate X86 and X64 specific cases.
+  if (mode == InstDB::kModeX86) {
+    // Illegal use of 64-bit register in 32-bit mode.
+    if (ASMJIT_UNLIKELY((combinedOpFlags & InstDB::kOpGpq) != 0))
+      return DebugUtils::errored(kErrorInvalidUseOfGpq);
+  }
+  else {
+    // Illegal use of a high 8-bit register with REX prefix.
+    bool hasREX = inst.hasOption(Inst::kOptionRex) ||
+                  ((combinedRegMask & 0xFFFFFF00u) != 0);
+    if (ASMJIT_UNLIKELY(hasREX && (combinedOpFlags & InstDB::kOpGpbHi) != 0))
+      return DebugUtils::errored(kErrorInvalidUseOfGpbHi);
+  }
+
+  // --------------------------------------------------------------------------
+  // [Validate Instruction Signature by Comparing Against All `iSig` Rows]
+  // --------------------------------------------------------------------------
+
+  const InstDB::InstSignature* iSig = InstDB::_instSignatureTable + commonInfo._iSignatureIndex;
+  const InstDB::InstSignature* iEnd = iSig + commonInfo._iSignatureCount;
+
+  if (iSig != iEnd) {
+    const InstDB::OpSignature* opSignatureTable = InstDB::_opSignatureTable;
+
+    // If set it means that we matched a signature where only immediate value
+    // was out of bounds. We can return a more descriptive error if we know this.
+    bool globalImmOutOfRange = false;
+
+    do {
+      // Check if the architecture is compatible.
+      if ((iSig->modes & mode) == 0)
+        continue;
+
+      // Compare the operands table with reference operands.
+      uint32_t j = 0;
+      uint32_t iSigCount = iSig->opCount;
+      bool localImmOutOfRange = false;
+
+      if (iSigCount == opCount) {
+        for (j = 0; j < opCount; j++)
+          if (!x86CheckOSig(oSigTranslated[j], opSignatureTable[iSig->operands[j]], localImmOutOfRange))
+            break;
+      }
+      else if (iSigCount - iSig->implicit == opCount) {
+        uint32_t r = 0;
+        for (j = 0; j < opCount && r < iSigCount; j++, r++) {
+          const InstDB::OpSignature* oChk = oSigTranslated + j;
+          const InstDB::OpSignature* oRef;
+Next:
+          oRef = opSignatureTable + iSig->operands[r];
+          // Skip implicit.
+          if ((oRef->opFlags & InstDB::kOpImplicit) != 0) {
+            if (++r >= iSigCount)
+              break;
+            else
+              goto Next;
+          }
+
+          if (!x86CheckOSig(*oChk, *oRef, localImmOutOfRange))
+            break;
+        }
+      }
+
+      if (j == opCount) {
+        if (!localImmOutOfRange) {
+          // Match, must clear possible `globalImmOutOfRange`.
+          globalImmOutOfRange = false;
+          break;
+        }
+        globalImmOutOfRange = localImmOutOfRange;
+      }
+    } while (++iSig != iEnd);
+
+    if (iSig == iEnd) {
+      if (globalImmOutOfRange)
+        return DebugUtils::errored(kErrorInvalidImmediate);
+      else
+        return DebugUtils::errored(kErrorInvalidInstruction);
+    }
+  }
+
+  // --------------------------------------------------------------------------
+  // [Validate AVX512 Options]
+  // --------------------------------------------------------------------------
+
+  const RegOnly& extraReg = inst.extraReg();
+  const uint32_t kAvx512Options = Inst::kOptionZMask   |
+                                  Inst::kOptionER      |
+                                  Inst::kOptionSAE     ;
+
+  if (options & kAvx512Options) {
+    if (commonInfo.hasFlag(InstDB::kFlagEvex)) {
+      // Validate AVX-512 {z}.
+      if ((options & Inst::kOptionZMask)) {
+        if (ASMJIT_UNLIKELY((options & Inst::kOptionZMask) != 0 && !commonInfo.hasAvx512Z()))
+          return DebugUtils::errored(kErrorInvalidKZeroUse);
+      }
+
+      // Validate AVX-512 {sae} and {er}.
+      if (options & (Inst::kOptionSAE | Inst::kOptionER)) {
+        // Rounding control is impossible if the instruction is not reg-to-reg.
+        if (ASMJIT_UNLIKELY(memOp))
+          return DebugUtils::errored(kErrorInvalidEROrSAE);
+
+        // Check if {sae} or {er} is supported by the instruction.
+        if (options & Inst::kOptionER) {
+          // NOTE: if both {sae} and {er} are set, we don't care, as {sae} is implied.
+          if (ASMJIT_UNLIKELY(!commonInfo.hasAvx512ER()))
+            return DebugUtils::errored(kErrorInvalidEROrSAE);
+        }
+        else {
+          if (ASMJIT_UNLIKELY(!commonInfo.hasAvx512SAE()))
+            return DebugUtils::errored(kErrorInvalidEROrSAE);
+        }
+
+        // {sae} and {er} are defined for either scalar ops or vector ops that
+        // require LL to be 10 (512-bit vector operations). We don't need any
+        // more bits in the instruction database to be able to validate this, as
+        // each AVX512 instruction that has broadcast is vector instruction (in
+        // this case we require zmm registers), otherwise it's a scalar instruction,
+        // which is valid.
+        if (commonInfo.hasAvx512B()) {
+          // Supports broadcast, thus we require LL to be '10', which means there
+          // have to be ZMM registers used. We don't calculate LL here, but we know
+          // that it would be '10' if there is at least one ZMM register used.
+
+          // There is no {er}/{sae}-enabled instruction with less than two operands.
+          ASMJIT_ASSERT(opCount >= 2);
+          if (ASMJIT_UNLIKELY(!x86IsZmmOrM512(operands[0]) && !x86IsZmmOrM512(operands[1])))
+            return DebugUtils::errored(kErrorInvalidEROrSAE);
+        }
+      }
+    }
+    else {
+      // Not AVX512 instruction - maybe OpExtra is xCX register used by REP/REPNE
+      // prefix. Otherwise the instruction is invalid.
+      if ((options & kAvx512Options) || (options & kRepAny) == 0)
+        return DebugUtils::errored(kErrorInvalidInstruction);
+    }
+  }
+
+  // --------------------------------------------------------------------------
+  // [Validate {Extra} Register]
+  // --------------------------------------------------------------------------
+
+  if (extraReg.isReg()) {
+    if (options & kRepAny) {
+      // Validate REP|REPNE {cx|ecx|rcx}.
+      if (ASMJIT_UNLIKELY(iFlags & InstDB::kFlagRepIgnored))
+        return DebugUtils::errored(kErrorInvalidExtraReg);
+
+      if (extraReg.isPhysReg()) {
+        if (ASMJIT_UNLIKELY(extraReg.id() != Gp::kIdCx))
+          return DebugUtils::errored(kErrorInvalidExtraReg);
+      }
+
+      // The type of the {...} register must match the type of the base register
+      // of memory operand. So if the memory operand uses 32-bit register the
+      // count register must also be 32-bit, etc...
+      if (ASMJIT_UNLIKELY(!memOp || extraReg.type() != memOp->baseType()))
+        return DebugUtils::errored(kErrorInvalidExtraReg);
+    }
+    else if (commonInfo.hasFlag(InstDB::kFlagEvex)) {
+      // Validate AVX-512 {k}.
+      if (ASMJIT_UNLIKELY(extraReg.type() != Reg::kTypeKReg))
+        return DebugUtils::errored(kErrorInvalidExtraReg);
+
+      if (ASMJIT_UNLIKELY(extraReg.id() == 0 || !commonInfo.hasAvx512K()))
+        return DebugUtils::errored(kErrorInvalidKMaskUse);
+    }
+    else {
+      return DebugUtils::errored(kErrorInvalidExtraReg);
+    }
+  }
+
+  return kErrorOk;
+}
+#endif // !ASMJIT_NO_VALIDATION
+
+// ============================================================================
+// [asmjit::x86::InstInternal - QueryRWInfo]
+// ============================================================================
+
+#ifndef ASMJIT_NO_INTROSPECTION
+static const uint64_t rwRegGroupByteMask[Reg::kGroupCount] = {
+  0x00000000000000FFu, // GP.
+  0xFFFFFFFFFFFFFFFFu, // XMM|YMM|ZMM.
+  0x00000000000000FFu, // MM.
+  0x00000000000000FFu, // KReg.
+  0x0000000000000003u, // SReg.
+  0x00000000000000FFu, // CReg.
+  0x00000000000000FFu, // DReg.
+  0x00000000000003FFu, // St().
+  0x000000000000FFFFu, // BND.
+  0x00000000000000FFu  // RIP.
+};
+
+static ASMJIT_INLINE void rwZeroExtendGp(OpRWInfo& opRwInfo, const Gp& reg, uint32_t nativeGpSize) noexcept {
+  ASMJIT_ASSERT(BaseReg::isGp(reg.as<Operand>()));
+  if (reg.size() + 4 == nativeGpSize) {
+    opRwInfo.addOpFlags(OpRWInfo::kZExt);
+    opRwInfo.setExtendByteMask(~opRwInfo.writeByteMask() & 0xFFu);
+  }
+}
+
+static ASMJIT_INLINE void rwZeroExtendAvxVec(OpRWInfo& opRwInfo, const Vec& reg) noexcept {
+  DebugUtils::unused(reg);
+
+  uint64_t msk = ~Support::fillTrailingBits(opRwInfo.writeByteMask());
+  if (msk) {
+    opRwInfo.addOpFlags(OpRWInfo::kZExt);
+    opRwInfo.setExtendByteMask(msk);
+  }
+}
+
+static ASMJIT_INLINE void rwZeroExtendNonVec(OpRWInfo& opRwInfo, const Reg& reg) noexcept {
+  uint64_t msk = ~Support::fillTrailingBits(opRwInfo.writeByteMask()) & rwRegGroupByteMask[reg.group()];
+  if (msk) {
+    opRwInfo.addOpFlags(OpRWInfo::kZExt);
+    opRwInfo.setExtendByteMask(msk);
+  }
+}
+
+Error InstInternal::queryRWInfo(uint32_t arch, const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept {
+  using namespace Status;
+
+  // Only called when `arch` matches X86 family.
+  ASMJIT_ASSERT(Environment::isFamilyX86(arch));
+
+  // Get the instruction data.
+  uint32_t instId = inst.id();
+  if (ASMJIT_UNLIKELY(!Inst::isDefinedId(instId)))
+    return DebugUtils::errored(kErrorInvalidInstruction);
+
+  // Read/Write flags.
+  const InstDB::CommonInfoTableB& tabB = InstDB::_commonInfoTableB[InstDB::_instInfoTable[instId]._commonInfoIndexB];
+  const InstDB::RWFlagsInfoTable& rwFlags = InstDB::_rwFlagsInfoTable[tabB._rwFlagsIndex];
+
+
+  // There are two data tables, one for `opCount == 2` and the second for
+  // `opCount != 2`. There are two reasons for that:
+  //   - There are instructions that share the same name that have both 2
+  //     or 3 operands, which have different RW information / semantics.
+  //   - There must be 2 tables otherwise the lookup index won't fit into
+  //     8 bits (there is more than 256 records of combined rwInfo A and B).
+  const InstDB::RWInfo& instRwInfo = opCount == 2 ? InstDB::rwInfoA[InstDB::rwInfoIndexA[instId]]
+                                                  : InstDB::rwInfoB[InstDB::rwInfoIndexB[instId]];
+  const InstDB::RWInfoRm& instRmInfo = InstDB::rwInfoRm[instRwInfo.rmInfo];
+
+  out->_instFlags = 0;
+  out->_opCount = uint8_t(opCount);
+  out->_rmFeature = instRmInfo.rmFeature;
+  out->_extraReg.reset();
+  out->_readFlags = rwFlags.readFlags;
+  out->_writeFlags = rwFlags.writeFlags;
+
+  uint32_t nativeGpSize = Environment::registerSizeFromArch(arch);
+
+  constexpr uint32_t R = OpRWInfo::kRead;
+  constexpr uint32_t W = OpRWInfo::kWrite;
+  constexpr uint32_t X = OpRWInfo::kRW;
+  constexpr uint32_t RegM = OpRWInfo::kRegMem;
+  constexpr uint32_t RegPhys = OpRWInfo::kRegPhysId;
+  constexpr uint32_t MibRead = OpRWInfo::kMemBaseRead | OpRWInfo::kMemIndexRead;
+
+  if (instRwInfo.category == InstDB::RWInfo::kCategoryGeneric) {
+    uint32_t i;
+    uint32_t rmOpsMask = 0;
+    uint32_t rmMaxSize = 0;
+
+    for (i = 0; i < opCount; i++) {
+      OpRWInfo& op = out->_operands[i];
+      const Operand_& srcOp = operands[i];
+      const InstDB::RWInfoOp& rwOpData = InstDB::rwInfoOp[instRwInfo.opInfoIndex[i]];
+
+      if (!srcOp.isRegOrMem()) {
+        op.reset();
+        continue;
+      }
+
+      op._opFlags = rwOpData.flags & ~(OpRWInfo::kZExt);
+      op._physId = rwOpData.physId;
+      op._rmSize = 0;
+      op._resetReserved();
+
+      uint64_t rByteMask = rwOpData.rByteMask;
+      uint64_t wByteMask = rwOpData.wByteMask;
+
+      if (op.isRead()  && !rByteMask) rByteMask = Support::lsbMask<uint64_t>(srcOp.size());
+      if (op.isWrite() && !wByteMask) wByteMask = Support::lsbMask<uint64_t>(srcOp.size());
+
+      op._readByteMask = rByteMask;
+      op._writeByteMask = wByteMask;
+      op._extendByteMask = 0;
+
+      if (srcOp.isReg()) {
+        // Zero extension.
+        if (op.isWrite()) {
+          if (srcOp.as<Reg>().isGp()) {
+            // GP registers on X64 are special:
+            //   - 8-bit and 16-bit writes aren't zero extended.
+            //   - 32-bit writes ARE zero extended.
+            rwZeroExtendGp(op, srcOp.as<Gp>(), nativeGpSize);
+          }
+          else if (rwOpData.flags & OpRWInfo::kZExt) {
+            // Otherwise follow ZExt.
+            rwZeroExtendNonVec(op, srcOp.as<Gp>());
+          }
+        }
+
+        // Aggregate values required to calculate valid Reg/M info.
+        rmMaxSize  = Support::max(rmMaxSize, srcOp.size());
+        rmOpsMask |= Support::bitMask<uint32_t>(i);
+      }
+      else {
+        const x86::Mem& memOp = srcOp.as<x86::Mem>();
+        // The RW flags of BASE+INDEX are either provided by the data, which means
+        // that the instruction is border-case, or they are deduced from the operand.
+        if (memOp.hasBaseReg() && !(op.opFlags() & OpRWInfo::kMemBaseRW))
+          op.addOpFlags(OpRWInfo::kMemBaseRead);
+        if (memOp.hasIndexReg() && !(op.opFlags() & OpRWInfo::kMemIndexRW))
+          op.addOpFlags(OpRWInfo::kMemIndexRead);
+      }
+    }
+
+    rmOpsMask &= instRmInfo.rmOpsMask;
+    if (rmOpsMask) {
+      Support::BitWordIterator<uint32_t> it(rmOpsMask);
+      do {
+        i = it.next();
+
+        OpRWInfo& op = out->_operands[i];
+        op.addOpFlags(RegM);
+
+        switch (instRmInfo.category) {
+          case InstDB::RWInfoRm::kCategoryFixed:
+            op.setRmSize(instRmInfo.fixedSize);
+            break;
+          case InstDB::RWInfoRm::kCategoryConsistent:
+            op.setRmSize(operands[i].size());
+            break;
+          case InstDB::RWInfoRm::kCategoryHalf:
+            op.setRmSize(rmMaxSize / 2u);
+            break;
+          case InstDB::RWInfoRm::kCategoryQuarter:
+            op.setRmSize(rmMaxSize / 4u);
+            break;
+          case InstDB::RWInfoRm::kCategoryEighth:
+            op.setRmSize(rmMaxSize / 8u);
+            break;
+        }
+      } while (it.hasNext());
+    }
+
+    return kErrorOk;
+  }
+
+  switch (instRwInfo.category) {
+    case InstDB::RWInfo::kCategoryMov: {
+      // Special case for 'movhpd' instruction. Here there are some variants that
+      // we have to handle as mov can be used to move between GP, segment, control
+      // and debug registers. Moving between GP registers also allow to use memory
+      // operand.
+
+      if (opCount == 2) {
+        if (operands[0].isReg() && operands[1].isReg()) {
+          const Reg& o0 = operands[0].as<Reg>();
+          const Reg& o1 = operands[1].as<Reg>();
+
+          if (o0.isGp() && o1.isGp()) {
+            out->_operands[0].reset(W | RegM, operands[0].size());
+            out->_operands[1].reset(R | RegM, operands[1].size());
+
+            rwZeroExtendGp(out->_operands[0], operands[0].as<Gp>(), nativeGpSize);
+            return kErrorOk;
+          }
+
+          if (o0.isGp() && o1.isSReg()) {
+            out->_operands[0].reset(W | RegM, nativeGpSize);
+            out->_operands[0].setRmSize(2);
+            out->_operands[1].reset(R, 2);
+            return kErrorOk;
+          }
+
+          if (o0.isSReg() && o1.isGp()) {
+            out->_operands[0].reset(W, 2);
+            out->_operands[1].reset(R | RegM, 2);
+            out->_operands[1].setRmSize(2);
+            return kErrorOk;
+          }
+
+          if (o0.isGp() && (o1.isCReg() || o1.isDReg())) {
+            out->_operands[0].reset(W, nativeGpSize);
+            out->_operands[1].reset(R, nativeGpSize);
+            out->_writeFlags = kOF | kSF | kZF | kAF | kPF | kCF;
+            return kErrorOk;
+          }
+
+          if ((o0.isCReg() || o0.isDReg()) && o1.isGp()) {
+            out->_operands[0].reset(W, nativeGpSize);
+            out->_operands[1].reset(R, nativeGpSize);
+            out->_writeFlags = kOF | kSF | kZF | kAF | kPF | kCF;
+            return kErrorOk;
+          }
+        }
+
+        if (operands[0].isReg() && operands[1].isMem()) {
+          const Reg& o0 = operands[0].as<Reg>();
+          const Mem& o1 = operands[1].as<Mem>();
+
+          if (o0.isGp()) {
+            if (!o1.isOffset64Bit())
+              out->_operands[0].reset(W, o0.size());
+            else
+              out->_operands[0].reset(W | RegPhys, o0.size(), Gp::kIdAx);
+
+            out->_operands[1].reset(R | MibRead, o0.size());
+            rwZeroExtendGp(out->_operands[0], operands[0].as<Gp>(), nativeGpSize);
+            return kErrorOk;
+          }
+
+          if (o0.isSReg()) {
+            out->_operands[0].reset(W, 2);
+            out->_operands[1].reset(R, 2);
+            return kErrorOk;
+          }
+        }
+
+        if (operands[0].isMem() && operands[1].isReg()) {
+          const Mem& o0 = operands[0].as<Mem>();
+          const Reg& o1 = operands[1].as<Reg>();
+
+          if (o1.isGp()) {
+            out->_operands[0].reset(W | MibRead, o1.size());
+            if (!o0.isOffset64Bit())
+              out->_operands[1].reset(R, o1.size());
+            else
+              out->_operands[1].reset(R | RegPhys, o1.size(), Gp::kIdAx);
+            return kErrorOk;
+          }
+
+          if (o1.isSReg()) {
+            out->_operands[0].reset(W | MibRead, 2);
+            out->_operands[1].reset(R, 2);
+            return kErrorOk;
+          }
+        }
+
+        if (Reg::isGp(operands[0]) && operands[1].isImm()) {
+          const Reg& o0 = operands[0].as<Reg>();
+          out->_operands[0].reset(W | RegM, o0.size());
+          out->_operands[1].reset();
+
+          rwZeroExtendGp(out->_operands[0], operands[0].as<Gp>(), nativeGpSize);
+          return kErrorOk;
+        }
+
+        if (operands[0].isMem() && operands[1].isImm()) {
+          const Reg& o0 = operands[0].as<Reg>();
+          out->_operands[0].reset(W | MibRead, o0.size());
+          out->_operands[1].reset();
+          return kErrorOk;
+        }
+      }
+      break;
+    }
+
+    case InstDB::RWInfo::kCategoryImul: {
+      // Special case for 'imul' instruction.
+      //
+      // There are 3 variants in general:
+      //
+      //   1. Standard multiplication: 'A = A * B'.
+      //   2. Multiplication with imm: 'A = B * C'.
+      //   3. Extended multiplication: 'A:B = B * C'.
+
+      if (opCount == 2) {
+        if (operands[0].isReg() && operands[1].isImm()) {
+          out->_operands[0].reset(X, operands[0].size());
+          out->_operands[1].reset();
+
+          rwZeroExtendGp(out->_operands[0], operands[0].as<Gp>(), nativeGpSize);
+          return kErrorOk;
+        }
+
+        if (Reg::isGpw(operands[0]) && operands[1].size() == 1) {
+          // imul ax, r8/m8 <- AX = AL * r8/m8
+          out->_operands[0].reset(X | RegPhys, 2, Gp::kIdAx);
+          out->_operands[0].setReadByteMask(Support::lsbMask<uint64_t>(1));
+          out->_operands[1].reset(R | RegM, 1);
+        }
+        else {
+          // imul r?, r?/m?
+          out->_operands[0].reset(X, operands[0].size());
+          out->_operands[1].reset(R | RegM, operands[0].size());
+          rwZeroExtendGp(out->_operands[0], operands[0].as<Gp>(), nativeGpSize);
+        }
+
+        if (operands[1].isMem())
+          out->_operands[1].addOpFlags(MibRead);
+        return kErrorOk;
+      }
+
+      if (opCount == 3) {
+        if (operands[2].isImm()) {
+          out->_operands[0].reset(W, operands[0].size());
+          out->_operands[1].reset(R | RegM, operands[1].size());
+          out->_operands[2].reset();
+
+          rwZeroExtendGp(out->_operands[0], operands[0].as<Gp>(), nativeGpSize);
+          if (operands[1].isMem())
+            out->_operands[1].addOpFlags(MibRead);
+          return kErrorOk;
+        }
+        else {
+          out->_operands[0].reset(W | RegPhys, operands[0].size(), Gp::kIdDx);
+          out->_operands[1].reset(X | RegPhys, operands[1].size(), Gp::kIdAx);
+          out->_operands[2].reset(R | RegM, operands[2].size());
+
+          rwZeroExtendGp(out->_operands[0], operands[0].as<Gp>(), nativeGpSize);
+          rwZeroExtendGp(out->_operands[1], operands[1].as<Gp>(), nativeGpSize);
+          if (operands[2].isMem())
+            out->_operands[2].addOpFlags(MibRead);
+          return kErrorOk;
+        }
+      }
+      break;
+    }
+
+    case InstDB::RWInfo::kCategoryMovh64: {
+      // Special case for 'movhpd|movhps' instructions. Note that this is only
+      // required for legacy (non-AVX) variants as AVX instructions use either
+      // 2 or 3 operands that are use `kCategoryGeneric`.
+      if (opCount == 2) {
+        if (BaseReg::isVec(operands[0]) && operands[1].isMem()) {
+          out->_operands[0].reset(W, 8);
+          out->_operands[0].setWriteByteMask(Support::lsbMask<uint64_t>(8) << 8);
+          out->_operands[1].reset(R | MibRead, 8);
+          return kErrorOk;
+        }
+
+        if (operands[0].isMem() && BaseReg::isVec(operands[1])) {
+          out->_operands[0].reset(W | MibRead, 8);
+          out->_operands[1].reset(R, 8);
+          out->_operands[1].setReadByteMask(Support::lsbMask<uint64_t>(8) << 8);
+          return kErrorOk;
+        }
+      }
+      break;
+    }
+
+    case InstDB::RWInfo::kCategoryVmaskmov: {
+      // Special case for 'vmaskmovpd|vmaskmovps|vpmaskmovd|vpmaskmovq' instructions.
+      if (opCount == 3) {
+        if (BaseReg::isVec(operands[0]) && BaseReg::isVec(operands[1]) && operands[2].isMem()) {
+          out->_operands[0].reset(W, operands[0].size());
+          out->_operands[1].reset(R, operands[1].size());
+          out->_operands[2].reset(R | MibRead, operands[1].size());
+
+          rwZeroExtendAvxVec(out->_operands[0], operands[0].as<Vec>());
+          return kErrorOk;
+        }
+
+        if (operands[0].isMem() && BaseReg::isVec(operands[1]) && BaseReg::isVec(operands[2])) {
+          out->_operands[0].reset(X | MibRead, operands[1].size());
+          out->_operands[1].reset(R, operands[1].size());
+          out->_operands[2].reset(R, operands[2].size());
+          return kErrorOk;
+        }
+      }
+      break;
+    }
+
+    case InstDB::RWInfo::kCategoryVmovddup: {
+      // Special case for 'vmovddup' instruction. This instruction has an
+      // interesting semantic as 128-bit XMM version only uses 64-bit memory
+      // operand (m64), however, 256/512-bit versions use 256/512-bit memory
+      // operand, respectively.
+      if (opCount == 2) {
+        if (BaseReg::isVec(operands[0]) && BaseReg::isVec(operands[1])) {
+          uint32_t o0Size = operands[0].size();
+          uint32_t o1Size = o0Size == 16 ? 8 : o0Size;
+
+          out->_operands[0].reset(W, o0Size);
+          out->_operands[1].reset(R | RegM, o1Size);
+          out->_operands[1]._readByteMask &= 0x00FF00FF00FF00FFu;
+
+          rwZeroExtendAvxVec(out->_operands[0], operands[0].as<Vec>());
+          return kErrorOk;
+        }
+
+        if (BaseReg::isVec(operands[0]) && operands[1].isMem()) {
+          uint32_t o0Size = operands[0].size();
+          uint32_t o1Size = o0Size == 16 ? 8 : o0Size;
+
+          out->_operands[0].reset(W, o0Size);
+          out->_operands[1].reset(R | MibRead, o1Size);
+
+          rwZeroExtendAvxVec(out->_operands[0], operands[0].as<Vec>());
+          return kErrorOk;
+        }
+      }
+      break;
+    }
+
+    case InstDB::RWInfo::kCategoryVmovmskpd:
+    case InstDB::RWInfo::kCategoryVmovmskps: {
+      // Special case for 'vmovmskpd|vmovmskps' instructions.
+      if (opCount == 2) {
+        if (BaseReg::isGp(operands[0]) && BaseReg::isVec(operands[1])) {
+          out->_operands[0].reset(W, 1);
+          out->_operands[0].setExtendByteMask(Support::lsbMask<uint32_t>(nativeGpSize - 1) << 1);
+          out->_operands[1].reset(R, operands[1].size());
+          return kErrorOk;
+        }
+      }
+      break;
+    }
+
+    case InstDB::RWInfo::kCategoryVmov1_2:
+    case InstDB::RWInfo::kCategoryVmov1_4:
+    case InstDB::RWInfo::kCategoryVmov1_8: {
+      // Special case for instructions where the destination is 1:N (narrowing).
+      //
+      // Vmov1_2:
+      //   vcvtpd2dq|vcvttpd2dq
+      //   vcvtpd2udq|vcvttpd2udq
+      //   vcvtpd2ps|vcvtps2ph
+      //   vcvtqq2ps|vcvtuqq2ps
+      //   vpmovwb|vpmovswb|vpmovuswb
+      //   vpmovdw|vpmovsdw|vpmovusdw
+      //   vpmovqd|vpmovsqd|vpmovusqd
+      //
+      // Vmov1_4:
+      //   vpmovdb|vpmovsdb|vpmovusdb
+      //   vpmovqw|vpmovsqw|vpmovusqw
+      //
+      // Vmov1_8:
+      //   pmovmskb|vpmovmskb
+      //   vpmovqb|vpmovsqb|vpmovusqb
+      uint32_t shift = instRwInfo.category - InstDB::RWInfo::kCategoryVmov1_2 + 1;
+
+      if (opCount >= 2) {
+        if (opCount >= 3) {
+          if (opCount > 3)
+            return DebugUtils::errored(kErrorInvalidInstruction);
+          out->_operands[2].reset();
+        }
+
+        if (operands[0].isReg() && operands[1].isReg()) {
+          uint32_t size1 = operands[1].size();
+          uint32_t size0 = size1 >> shift;
+
+          out->_operands[0].reset(W, size0);
+          out->_operands[1].reset(R, size1);
+
+          if (instRmInfo.rmOpsMask & 0x1) {
+            out->_operands[0].addOpFlags(RegM);
+            out->_operands[0].setRmSize(size0);
+          }
+
+          if (instRmInfo.rmOpsMask & 0x2) {
+            out->_operands[1].addOpFlags(RegM);
+            out->_operands[1].setRmSize(size1);
+          }
+
+          // Handle 'pmovmskb|vpmovmskb'.
+          if (BaseReg::isGp(operands[0]))
+            rwZeroExtendGp(out->_operands[0], operands[0].as<Gp>(), nativeGpSize);
+
+          if (BaseReg::isVec(operands[0]))
+            rwZeroExtendAvxVec(out->_operands[0], operands[0].as<Vec>());
+
+          return kErrorOk;
+        }
+
+        if (operands[0].isReg() && operands[1].isMem()) {
+          uint32_t size1 = operands[1].size() ? operands[1].size() : uint32_t(16);
+          uint32_t size0 = size1 >> shift;
+
+          out->_operands[0].reset(W, size0);
+          out->_operands[1].reset(R | MibRead, size1);
+          return kErrorOk;
+        }
+
+        if (operands[0].isMem() && operands[1].isReg()) {
+          uint32_t size1 = operands[1].size();
+          uint32_t size0 = size1 >> shift;
+
+          out->_operands[0].reset(W | MibRead, size0);
+          out->_operands[1].reset(R, size1);
+          return kErrorOk;
+        }
+      }
+      break;
+    }
+
+    case InstDB::RWInfo::kCategoryVmov2_1:
+    case InstDB::RWInfo::kCategoryVmov4_1:
+    case InstDB::RWInfo::kCategoryVmov8_1: {
+      // Special case for instructions where the destination is N:1 (widening).
+      //
+      // Vmov2_1:
+      //   vcvtdq2pd|vcvtudq2pd
+      //   vcvtps2pd|vcvtph2ps
+      //   vcvtps2qq|vcvtps2uqq
+      //   vcvttps2qq|vcvttps2uqq
+      //   vpmovsxbw|vpmovzxbw
+      //   vpmovsxwd|vpmovzxwd
+      //   vpmovsxdq|vpmovzxdq
+      //
+      // Vmov4_1:
+      //   vpmovsxbd|vpmovzxbd
+      //   vpmovsxwq|vpmovzxwq
+      //
+      // Vmov8_1:
+      //   vpmovsxbq|vpmovzxbq
+      uint32_t shift = instRwInfo.category - InstDB::RWInfo::kCategoryVmov2_1 + 1;
+
+      if (opCount >= 2) {
+        if (opCount >= 3) {
+          if (opCount > 3)
+            return DebugUtils::errored(kErrorInvalidInstruction);
+          out->_operands[2].reset();
+        }
+
+        uint32_t size0 = operands[0].size();
+        uint32_t size1 = size0 >> shift;
+
+        out->_operands[0].reset(W, size0);
+        out->_operands[1].reset(R, size1);
+
+        if (operands[0].isReg() && operands[1].isReg()) {
+          if (instRmInfo.rmOpsMask & 0x1) {
+            out->_operands[0].addOpFlags(RegM);
+            out->_operands[0].setRmSize(size0);
+          }
+
+          if (instRmInfo.rmOpsMask & 0x2) {
+            out->_operands[1].addOpFlags(RegM);
+            out->_operands[1].setRmSize(size1);
+          }
+          return kErrorOk;
+        }
+
+        if (operands[0].isReg() && operands[1].isMem()) {
+          out->_operands[1].addOpFlags(MibRead);
+          return kErrorOk;
+        }
+      }
+      break;
+    }
+  }
+
+  return DebugUtils::errored(kErrorInvalidInstruction);
+}
+#endif // !ASMJIT_NO_INTROSPECTION
+
+// ============================================================================
+// [asmjit::x86::InstInternal - QueryFeatures]
+// ============================================================================
+
+#ifndef ASMJIT_NO_INTROSPECTION
+struct RegAnalysis {
+  uint32_t regTypeMask;
+  uint32_t highVecUsed;
+
+  inline bool hasRegType(uint32_t regType) const noexcept {
+    return Support::bitTest(regTypeMask, regType);
+  }
+};
+
+static RegAnalysis InstInternal_regAnalysis(const Operand_* operands, size_t opCount) noexcept {
+  uint32_t mask = 0;
+  uint32_t highVecUsed = 0;
+
+  for (uint32_t i = 0; i < opCount; i++) {
+    const Operand_& op = operands[i];
+    if (op.isReg()) {
+      const BaseReg& reg = op.as<BaseReg>();
+      mask |= Support::bitMask(reg.type());
+      if (reg.isVec())
+        highVecUsed |= uint32_t(reg.id() >= 16 && reg.id() < 32);
+    }
+    else if (op.isMem()) {
+      const BaseMem& mem = op.as<BaseMem>();
+      if (mem.hasBaseReg()) mask |= Support::bitMask(mem.baseType());
+      if (mem.hasIndexReg()) {
+        mask |= Support::bitMask(mem.indexType());
+        highVecUsed |= uint32_t(mem.indexId() >= 16 && mem.indexId() < 32);
+      }
+    }
+  }
+
+  return RegAnalysis { mask, highVecUsed };
+}
+
+Error InstInternal::queryFeatures(uint32_t arch, const BaseInst& inst, const Operand_* operands, size_t opCount, BaseFeatures* out) noexcept {
+  // Only called when `arch` matches X86 family.
+  DebugUtils::unused(arch);
+  ASMJIT_ASSERT(Environment::isFamilyX86(arch));
+
+  // Get the instruction data.
+  uint32_t instId = inst.id();
+  uint32_t options = inst.options();
+
+  if (ASMJIT_UNLIKELY(!Inst::isDefinedId(instId)))
+    return DebugUtils::errored(kErrorInvalidInstruction);
+
+  const InstDB::InstInfo& instInfo = InstDB::infoById(instId);
+  const InstDB::CommonInfoTableB& tableB = InstDB::_commonInfoTableB[instInfo._commonInfoIndexB];
+
+  const uint8_t* fData = tableB.featuresBegin();
+  const uint8_t* fEnd = tableB.featuresEnd();
+
+  // Copy all features to `out`.
+  out->reset();
+  do {
+    uint32_t feature = fData[0];
+    if (!feature)
+      break;
+    out->add(feature);
+  } while (++fData != fEnd);
+
+  // Since AsmJit aggregates instructions that share the same name we have to
+  // deal with some special cases and also with MMX/SSE and AVX/AVX2 overlaps.
+  if (fData != tableB.featuresBegin()) {
+    RegAnalysis regAnalysis = InstInternal_regAnalysis(operands, opCount);
+
+    // Handle MMX vs SSE overlap.
+    if (out->has(Features::kMMX) || out->has(Features::kMMX2)) {
+      // Only instructions defined by SSE and SSE2 overlap. Instructions
+      // introduced by newer instruction sets like SSE3+ don't state MMX as
+      // they require SSE3+.
+      if (out->has(Features::kSSE) || out->has(Features::kSSE2)) {
+        if (!regAnalysis.hasRegType(Reg::kTypeXmm)) {
+          // The instruction doesn't use XMM register(s), thus it's MMX/MMX2 only.
+          out->remove(Features::kSSE);
+          out->remove(Features::kSSE2);
+        }
+        else {
+          out->remove(Features::kMMX);
+          out->remove(Features::kMMX2);
+        }
+
+        // Special case: PEXTRW instruction is MMX/SSE2 instruction. However,
+        // MMX/SSE version cannot access memory (only register to register
+        // extract) so when SSE4.1 introduced the whole family of PEXTR/PINSR
+        // instructions they also introduced PEXTRW with a new opcode 0x15 that
+        // can extract directly to memory. This instruction is, of course, not
+        // compatible with MMX/SSE2 and would #UD if SSE4.1 is not supported.
+        if (instId == Inst::kIdPextrw) {
+          ASMJIT_ASSERT(out->has(Features::kSSE2));
+          ASMJIT_ASSERT(out->has(Features::kSSE4_1));
+
+          if (opCount >= 1 && operands[0].isMem())
+            out->remove(Features::kSSE2);
+          else
+            out->remove(Features::kSSE4_1);
+        }
+      }
+    }
+
+    // Handle PCLMULQDQ vs VPCLMULQDQ.
+    if (out->has(Features::kVPCLMULQDQ)) {
+      if (regAnalysis.hasRegType(Reg::kTypeZmm) || Support::bitTest(options, Inst::kOptionEvex)) {
+        // AVX512_F & VPCLMULQDQ.
+        out->remove(Features::kAVX, Features::kPCLMULQDQ);
+      }
+      else if (regAnalysis.hasRegType(Reg::kTypeYmm)) {
+        out->remove(Features::kAVX512_F, Features::kAVX512_VL);
+      }
+      else {
+        // AVX & PCLMULQDQ.
+        out->remove(Features::kAVX512_F, Features::kAVX512_VL, Features::kVPCLMULQDQ);
+      }
+    }
+
+    // Handle AVX vs AVX2 overlap.
+    if (out->has(Features::kAVX) && out->has(Features::kAVX2)) {
+      bool isAVX2 = true;
+      // Special case: VBROADCASTSS and VBROADCASTSD were introduced in AVX, but
+      // only version that uses memory as a source operand. AVX2 then added support
+      // for register source operand.
+      if (instId == Inst::kIdVbroadcastss || instId == Inst::kIdVbroadcastsd) {
+        if (opCount > 1 && operands[1].isMem())
+          isAVX2 = false;
+      }
+      else {
+        // AVX instruction set doesn't support integer operations on YMM registers
+        // as these were later introcuced by AVX2. In our case we have to check if
+        // YMM register(s) are in use and if that is the case this is an AVX2 instruction.
+        if (!(regAnalysis.regTypeMask & Support::bitMask(Reg::kTypeYmm, Reg::kTypeZmm)))
+          isAVX2 = false;
+      }
+
+      if (isAVX2)
+        out->remove(Features::kAVX);
+      else
+        out->remove(Features::kAVX2);
+    }
+
+    // Handle AVX|AVX2|FMA|F16C vs AVX512 overlap.
+    if (out->has(Features::kAVX) || out->has(Features::kAVX2) || out->has(Features::kFMA) || out->has(Features::kF16C)) {
+      // Only AVX512-F|BW|DQ allow to encode AVX/AVX2/FMA/F16C instructions
+      if (out->has(Features::kAVX512_F) || out->has(Features::kAVX512_BW) || out->has(Features::kAVX512_DQ)) {
+        uint32_t hasEvex = options & (Inst::kOptionEvex | Inst::_kOptionAvx512Mask);
+        uint32_t hasKMask = inst.extraReg().type() == Reg::kTypeKReg;
+        uint32_t hasKOrZmm = regAnalysis.regTypeMask & Support::bitMask(Reg::kTypeZmm, Reg::kTypeKReg);
+
+        uint32_t mustUseEvex = 0;
+
+        switch (instId) {
+          // Special case: VPSLLDQ and VPSRLDQ instructions only allow `reg, reg. imm`
+          // combination in AVX|AVX2 mode, then AVX-512 introduced `reg, reg/mem, imm`
+          // combination that uses EVEX prefix. This means that if the second operand
+          // is memory then this is AVX-512_BW instruction and not AVX/AVX2 instruction.
+          case Inst::kIdVpslldq:
+          case Inst::kIdVpsrldq:
+            mustUseEvex = opCount >= 2 && operands[1].isMem();
+            break;
+
+          // Special case: VPBROADCAST[B|D|Q|W] only supports r32/r64 with EVEX prefix.
+          case Inst::kIdVpbroadcastb:
+          case Inst::kIdVpbroadcastd:
+          case Inst::kIdVpbroadcastq:
+          case Inst::kIdVpbroadcastw:
+            mustUseEvex = opCount >= 2 && x86::Reg::isGp(operands[1]);
+            break;
+
+          // Special case: VPERMPD only supports YMM predicate in AVX mode, immediate
+          // precicate is only supported by AVX512-F and newer.
+          case Inst::kIdVpermpd:
+            mustUseEvex = opCount >= 3 && !operands[2].isImm();
+            break;
+        }
+
+        if (!(hasEvex | mustUseEvex | hasKMask | hasKOrZmm | regAnalysis.highVecUsed))
+          out->remove(Features::kAVX512_F, Features::kAVX512_BW, Features::kAVX512_DQ, Features::kAVX512_VL);
+        else
+          out->remove(Features::kAVX, Features::kAVX2, Features::kFMA, Features::kF16C);
+      }
+    }
+
+    // Clear AVX512_VL if ZMM register is used.
+    if (regAnalysis.hasRegType(Reg::kTypeZmm))
+      out->remove(Features::kAVX512_VL);
+  }
+
+  return kErrorOk;
+}
+#endif // !ASMJIT_NO_INTROSPECTION
+
+// ============================================================================
+// [asmjit::x86::InstInternal - Unit]
+// ============================================================================
+
+#if defined(ASMJIT_TEST)
+UNIT(x86_inst_api_text) {
+  // All known instructions should be matched.
+  INFO("Matching all X86 instructions");
+  for (uint32_t a = 1; a < Inst::_kIdCount; a++) {
+    StringTmp<128> aName;
+    EXPECT(InstInternal::instIdToString(0, a, aName) == kErrorOk,
+           "Failed to get the name of instruction #%u", a);
+
+    uint32_t b = InstInternal::stringToInstId(0, aName.data(), aName.size());
+    StringTmp<128> bName;
+    InstInternal::instIdToString(0, b, bName);
+
+    EXPECT(a == b,
+           "Instructions do not match \"%s\" (#%u) != \"%s\" (#%u)", aName.data(), a, bName.data(), b);
+  }
+}
+#endif
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86
diff --git a/client/asmjit/x86/x86instapi_p.h b/client/asmjit/x86/x86instapi_p.h
new file mode 100644
index 0000000..83b3f77
--- /dev/null
+++ b/client/asmjit/x86/x86instapi_p.h
@@ -0,0 +1,59 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86INSTAPI_P_H_INCLUDED
+#define ASMJIT_X86_X86INSTAPI_P_H_INCLUDED
+
+#include "../core/inst.h"
+#include "../core/operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_x86
+//! \{
+
+namespace InstInternal {
+
+#ifndef ASMJIT_NO_TEXT
+Error instIdToString(uint32_t arch, uint32_t instId, String& output) noexcept;
+uint32_t stringToInstId(uint32_t arch, const char* s, size_t len) noexcept;
+#endif // !ASMJIT_NO_TEXT
+
+#ifndef ASMJIT_NO_VALIDATION
+Error validate(uint32_t arch, const BaseInst& inst, const Operand_* operands, size_t opCount, uint32_t validationFlags) noexcept;
+#endif // !ASMJIT_NO_VALIDATION
+
+#ifndef ASMJIT_NO_INTROSPECTION
+Error queryRWInfo(uint32_t arch, const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept;
+Error queryFeatures(uint32_t arch, const BaseInst& inst, const Operand_* operands, size_t opCount, BaseFeatures* out) noexcept;
+#endif // !ASMJIT_NO_INTROSPECTION
+
+} // {InstInternal}
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86INSTAPI_P_H_INCLUDED
diff --git a/client/asmjit/x86/x86instdb.cpp b/client/asmjit/x86/x86instdb.cpp
new file mode 100644
index 0000000..911682b
--- /dev/null
+++ b/client/asmjit/x86/x86instdb.cpp
@@ -0,0 +1,4138 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+// ----------------------------------------------------------------------------
+// IMPORTANT: AsmJit now uses an external instruction database to populate
+// static tables within this file. Perform the following steps to regenerate
+// all tables enclosed by ${...}:
+//
+//   1. Install node.js environment <https://nodejs.org>
+//   2. Go to asmjit/tools directory
+//   3. Get the latest asmdb from <https://github.com/asmjit/asmdb> and
+//      copy/link the `asmdb` directory to `asmjit/tools/asmdb`.
+//   4. Execute `node tablegen-x86.js`
+//
+// Instruction encoding and opcodes were added to the `x86inst.cpp` database
+// manually in the past and they are not updated by the script as it became
+// tricky. However, everything else is updated including instruction operands
+// and tables required to validate them, instruction read/write information
+// (including registers and flags), and all indexes to all tables.
+// ----------------------------------------------------------------------------
+
+#include "../core/api-build_p.h"
+#ifdef ASMJIT_BUILD_X86
+
+#include "../core/cpuinfo.h"
+#include "../core/misc_p.h"
+#include "../core/support.h"
+#include "../x86/x86features.h"
+#include "../x86/x86instdb_p.h"
+#include "../x86/x86opcode_p.h"
+#include "../x86/x86operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::x86::InstDB - InstInfo]
+// ============================================================================
+
+// Instruction opcode definitions:
+//   - `O` encodes X86|MMX|SSE instructions.
+//   - `V` encodes VEX|XOP|EVEX instructions.
+//   - `E` encodes EVEX instructions only.
+#define O_ENCODE(VEX, PREFIX, OPCODE, O, L, W, EvexW, N, TT) \
+  ((PREFIX) | (OPCODE) | (O) | (L) | (W) | (EvexW) | (N) | (TT) | \
+   (VEX && ((PREFIX) & Opcode::kMM_Mask) != Opcode::kMM_0F ? int(Opcode::kMM_ForceVex3) : 0))
+
+#define O(PREFIX, OPCODE, ModO, LL, W, EvexW, N, ModRM) (O_ENCODE(0, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kModO_##ModO, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kModRM_##ModRM))
+#define V(PREFIX, OPCODE, ModO, LL, W, EvexW, N, TT) (O_ENCODE(1, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kModO_##ModO, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kCDTT_##TT))
+#define E(PREFIX, OPCODE, ModO, LL, W, EvexW, N, TT) (O_ENCODE(1, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kModO_##ModO, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kCDTT_##TT) | Opcode::kMM_ForceEvex)
+#define O_FPU(PREFIX, OPCODE, ModO) (Opcode::kFPU_##PREFIX | (0x##OPCODE & 0xFFu) | ((0x##OPCODE >> 8) << Opcode::kFPU_2B_Shift) | Opcode::kModO_##ModO)
+
+// Don't store `_nameDataIndex` if instruction names are disabled. Since some
+// APIs can use `_nameDataIndex` it's much safer if it's zero if it's not defined.
+#ifndef ASMJIT_NO_TEXT
+  #define NAME_DATA_INDEX(Index) Index
+#else
+  #define NAME_DATA_INDEX(Index) 0
+#endif
+
+// Defines an X86 instruction.
+#define INST(id, encoding, opcode0, opcode1, mainOpcodeIndex, altOpcodeIndex, nameDataIndex, commomInfoIndexA, commomInfoIndexB) { \
+  uint32_t(NAME_DATA_INDEX(nameDataIndex)), \
+  uint32_t(commomInfoIndexA),               \
+  uint32_t(commomInfoIndexB),               \
+  uint8_t(InstDB::kEncoding##encoding),     \
+  uint8_t((opcode0) & 0xFFu),               \
+  uint8_t(mainOpcodeIndex),                 \
+  uint8_t(altOpcodeIndex)                   \
+}
+
+const InstDB::InstInfo InstDB::_instInfoTable[] = {
+  /*--------------------+--------------------+------------------+--------+------------------+--------+----+----+------+----+----+
+  |    Instruction      |    Instruction     |    Main Opcode   |  EVEX  |Alternative Opcode|  EVEX  |Op0X|Op1X|Name-X|IdxA|IdxB|
+  |     Id & Name       |      Encoding      |  (pp+mmm|op/o|L|w|W|N|TT.)|--(pp+mmm|op/o|L|w|W|N|TT.)|     (auto-generated)     |
+  +---------------------+--------------------+---------+----+-+-+-+-+----+---------+----+-+-+-+-+----+----+----+------+----+---*/
+  // ${InstInfo:Begin}
+  INST(None             , None               , 0                         , 0                         , 0  , 0  , 0    , 0  , 0  ), // #0
+  INST(Aaa              , X86Op_xAX          , O(000000,37,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1    , 1  , 1  ), // #1
+  INST(Aad              , X86I_xAX           , O(000000,D5,_,_,_,_,_,_  ), 0                         , 0  , 0  , 5    , 2  , 1  ), // #2
+  INST(Aam              , X86I_xAX           , O(000000,D4,_,_,_,_,_,_  ), 0                         , 0  , 0  , 9    , 2  , 1  ), // #3
+  INST(Aas              , X86Op_xAX          , O(000000,3F,_,_,_,_,_,_  ), 0                         , 0  , 0  , 13   , 1  , 1  ), // #4
+  INST(Adc              , X86Arith           , O(000000,10,2,_,x,_,_,_  ), 0                         , 1  , 0  , 17   , 3  , 2  ), // #5
+  INST(Adcx             , X86Rm              , O(660F38,F6,_,_,x,_,_,_  ), 0                         , 2  , 0  , 21   , 4  , 3  ), // #6
+  INST(Add              , X86Arith           , O(000000,00,0,_,x,_,_,_  ), 0                         , 0  , 0  , 3112 , 3  , 1  ), // #7
+  INST(Addpd            , ExtRm              , O(660F00,58,_,_,_,_,_,_  ), 0                         , 3  , 0  , 5102 , 5  , 4  ), // #8
+  INST(Addps            , ExtRm              , O(000F00,58,_,_,_,_,_,_  ), 0                         , 4  , 0  , 5114 , 5  , 5  ), // #9
+  INST(Addsd            , ExtRm              , O(F20F00,58,_,_,_,_,_,_  ), 0                         , 5  , 0  , 5336 , 6  , 4  ), // #10
+  INST(Addss            , ExtRm              , O(F30F00,58,_,_,_,_,_,_  ), 0                         , 6  , 0  , 3243 , 7  , 5  ), // #11
+  INST(Addsubpd         , ExtRm              , O(660F00,D0,_,_,_,_,_,_  ), 0                         , 3  , 0  , 4841 , 5  , 6  ), // #12
+  INST(Addsubps         , ExtRm              , O(F20F00,D0,_,_,_,_,_,_  ), 0                         , 5  , 0  , 4853 , 5  , 6  ), // #13
+  INST(Adox             , X86Rm              , O(F30F38,F6,_,_,x,_,_,_  ), 0                         , 7  , 0  , 26   , 4  , 7  ), // #14
+  INST(Aesdec           , ExtRm              , O(660F38,DE,_,_,_,_,_,_  ), 0                         , 2  , 0  , 3298 , 5  , 8  ), // #15
+  INST(Aesdeclast       , ExtRm              , O(660F38,DF,_,_,_,_,_,_  ), 0                         , 2  , 0  , 3306 , 5  , 8  ), // #16
+  INST(Aesenc           , ExtRm              , O(660F38,DC,_,_,_,_,_,_  ), 0                         , 2  , 0  , 3318 , 5  , 8  ), // #17
+  INST(Aesenclast       , ExtRm              , O(660F38,DD,_,_,_,_,_,_  ), 0                         , 2  , 0  , 3326 , 5  , 8  ), // #18
+  INST(Aesimc           , ExtRm              , O(660F38,DB,_,_,_,_,_,_  ), 0                         , 2  , 0  , 3338 , 5  , 8  ), // #19
+  INST(Aeskeygenassist  , ExtRmi             , O(660F3A,DF,_,_,_,_,_,_  ), 0                         , 8  , 0  , 3346 , 8  , 8  ), // #20
+  INST(And              , X86Arith           , O(000000,20,4,_,x,_,_,_  ), 0                         , 9  , 0  , 2510 , 9  , 1  ), // #21
+  INST(Andn             , VexRvm_Wx          , V(000F38,F2,_,0,x,_,_,_  ), 0                         , 10 , 0  , 6810 , 10 , 9  ), // #22
+  INST(Andnpd           , ExtRm              , O(660F00,55,_,_,_,_,_,_  ), 0                         , 3  , 0  , 3379 , 5  , 4  ), // #23
+  INST(Andnps           , ExtRm              , O(000F00,55,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3387 , 5  , 5  ), // #24
+  INST(Andpd            , ExtRm              , O(660F00,54,_,_,_,_,_,_  ), 0                         , 3  , 0  , 4355 , 11 , 4  ), // #25
+  INST(Andps            , ExtRm              , O(000F00,54,_,_,_,_,_,_  ), 0                         , 4  , 0  , 4365 , 11 , 5  ), // #26
+  INST(Arpl             , X86Mr_NoSize       , O(000000,63,_,_,_,_,_,_  ), 0                         , 0  , 0  , 31   , 12 , 10 ), // #27
+  INST(Bextr            , VexRmv_Wx          , V(000F38,F7,_,0,x,_,_,_  ), 0                         , 10 , 0  , 36   , 13 , 9  ), // #28
+  INST(Blcfill          , VexVm_Wx           , V(XOP_M9,01,1,0,x,_,_,_  ), 0                         , 11 , 0  , 42   , 14 , 11 ), // #29
+  INST(Blci             , VexVm_Wx           , V(XOP_M9,02,6,0,x,_,_,_  ), 0                         , 12 , 0  , 50   , 14 , 11 ), // #30
+  INST(Blcic            , VexVm_Wx           , V(XOP_M9,01,5,0,x,_,_,_  ), 0                         , 13 , 0  , 55   , 14 , 11 ), // #31
+  INST(Blcmsk           , VexVm_Wx           , V(XOP_M9,02,1,0,x,_,_,_  ), 0                         , 11 , 0  , 61   , 14 , 11 ), // #32
+  INST(Blcs             , VexVm_Wx           , V(XOP_M9,01,3,0,x,_,_,_  ), 0                         , 14 , 0  , 68   , 14 , 11 ), // #33
+  INST(Blendpd          , ExtRmi             , O(660F3A,0D,_,_,_,_,_,_  ), 0                         , 8  , 0  , 3465 , 8  , 12 ), // #34
+  INST(Blendps          , ExtRmi             , O(660F3A,0C,_,_,_,_,_,_  ), 0                         , 8  , 0  , 3474 , 8  , 12 ), // #35
+  INST(Blendvpd         , ExtRm_XMM0         , O(660F38,15,_,_,_,_,_,_  ), 0                         , 2  , 0  , 3483 , 15 , 12 ), // #36
+  INST(Blendvps         , ExtRm_XMM0         , O(660F38,14,_,_,_,_,_,_  ), 0                         , 2  , 0  , 3493 , 15 , 12 ), // #37
+  INST(Blsfill          , VexVm_Wx           , V(XOP_M9,01,2,0,x,_,_,_  ), 0                         , 15 , 0  , 73   , 14 , 11 ), // #38
+  INST(Blsi             , VexVm_Wx           , V(000F38,F3,3,0,x,_,_,_  ), 0                         , 16 , 0  , 81   , 14 , 9  ), // #39
+  INST(Blsic            , VexVm_Wx           , V(XOP_M9,01,6,0,x,_,_,_  ), 0                         , 12 , 0  , 86   , 14 , 11 ), // #40
+  INST(Blsmsk           , VexVm_Wx           , V(000F38,F3,2,0,x,_,_,_  ), 0                         , 17 , 0  , 92   , 14 , 9  ), // #41
+  INST(Blsr             , VexVm_Wx           , V(000F38,F3,1,0,x,_,_,_  ), 0                         , 18 , 0  , 99   , 14 , 9  ), // #42
+  INST(Bndcl            , X86Rm              , O(F30F00,1A,_,_,_,_,_,_  ), 0                         , 6  , 0  , 104  , 16 , 13 ), // #43
+  INST(Bndcn            , X86Rm              , O(F20F00,1B,_,_,_,_,_,_  ), 0                         , 5  , 0  , 110  , 16 , 13 ), // #44
+  INST(Bndcu            , X86Rm              , O(F20F00,1A,_,_,_,_,_,_  ), 0                         , 5  , 0  , 116  , 16 , 13 ), // #45
+  INST(Bndldx           , X86Rm              , O(000F00,1A,_,_,_,_,_,_  ), 0                         , 4  , 0  , 122  , 17 , 13 ), // #46
+  INST(Bndmk            , X86Rm              , O(F30F00,1B,_,_,_,_,_,_  ), 0                         , 6  , 0  , 129  , 18 , 13 ), // #47
+  INST(Bndmov           , X86Bndmov          , O(660F00,1A,_,_,_,_,_,_  ), O(660F00,1B,_,_,_,_,_,_  ), 3  , 1  , 135  , 19 , 13 ), // #48
+  INST(Bndstx           , X86Mr              , O(000F00,1B,_,_,_,_,_,_  ), 0                         , 4  , 0  , 142  , 20 , 13 ), // #49
+  INST(Bound            , X86Rm              , O(000000,62,_,_,_,_,_,_  ), 0                         , 0  , 0  , 149  , 21 , 0  ), // #50
+  INST(Bsf              , X86Rm              , O(000F00,BC,_,_,x,_,_,_  ), 0                         , 4  , 0  , 155  , 22 , 1  ), // #51
+  INST(Bsr              , X86Rm              , O(000F00,BD,_,_,x,_,_,_  ), 0                         , 4  , 0  , 159  , 22 , 1  ), // #52
+  INST(Bswap            , X86Bswap           , O(000F00,C8,_,_,x,_,_,_  ), 0                         , 4  , 0  , 163  , 23 , 0  ), // #53
+  INST(Bt               , X86Bt              , O(000F00,A3,_,_,x,_,_,_  ), O(000F00,BA,4,_,x,_,_,_  ), 4  , 2  , 169  , 24 , 14 ), // #54
+  INST(Btc              , X86Bt              , O(000F00,BB,_,_,x,_,_,_  ), O(000F00,BA,7,_,x,_,_,_  ), 4  , 3  , 172  , 25 , 14 ), // #55
+  INST(Btr              , X86Bt              , O(000F00,B3,_,_,x,_,_,_  ), O(000F00,BA,6,_,x,_,_,_  ), 4  , 4  , 176  , 25 , 14 ), // #56
+  INST(Bts              , X86Bt              , O(000F00,AB,_,_,x,_,_,_  ), O(000F00,BA,5,_,x,_,_,_  ), 4  , 5  , 180  , 25 , 14 ), // #57
+  INST(Bzhi             , VexRmv_Wx          , V(000F38,F5,_,0,x,_,_,_  ), 0                         , 10 , 0  , 184  , 13 , 15 ), // #58
+  INST(Call             , X86Call            , O(000000,FF,2,_,_,_,_,_  ), 0                         , 1  , 0  , 3009 , 26 , 1  ), // #59
+  INST(Cbw              , X86Op_xAX          , O(660000,98,_,_,_,_,_,_  ), 0                         , 19 , 0  , 189  , 27 , 0  ), // #60
+  INST(Cdq              , X86Op_xDX_xAX      , O(000000,99,_,_,_,_,_,_  ), 0                         , 0  , 0  , 193  , 28 , 0  ), // #61
+  INST(Cdqe             , X86Op_xAX          , O(000000,98,_,_,1,_,_,_  ), 0                         , 20 , 0  , 197  , 29 , 0  ), // #62
+  INST(Clac             , X86Op              , O(000F01,CA,_,_,_,_,_,_  ), 0                         , 21 , 0  , 202  , 30 , 16 ), // #63
+  INST(Clc              , X86Op              , O(000000,F8,_,_,_,_,_,_  ), 0                         , 0  , 0  , 207  , 30 , 17 ), // #64
+  INST(Cld              , X86Op              , O(000000,FC,_,_,_,_,_,_  ), 0                         , 0  , 0  , 211  , 30 , 18 ), // #65
+  INST(Cldemote         , X86M_Only          , O(000F00,1C,0,_,_,_,_,_  ), 0                         , 4  , 0  , 215  , 31 , 19 ), // #66
+  INST(Clflush          , X86M_Only          , O(000F00,AE,7,_,_,_,_,_  ), 0                         , 22 , 0  , 224  , 31 , 20 ), // #67
+  INST(Clflushopt       , X86M_Only          , O(660F00,AE,7,_,_,_,_,_  ), 0                         , 23 , 0  , 232  , 31 , 21 ), // #68
+  INST(Clgi             , X86Op              , O(000F01,DD,_,_,_,_,_,_  ), 0                         , 21 , 0  , 243  , 30 , 22 ), // #69
+  INST(Cli              , X86Op              , O(000000,FA,_,_,_,_,_,_  ), 0                         , 0  , 0  , 248  , 30 , 23 ), // #70
+  INST(Clrssbsy         , X86M               , O(F30F00,AE,6,_,_,_,_,_  ), 0                         , 24 , 0  , 252  , 32 , 24 ), // #71
+  INST(Clts             , X86Op              , O(000F00,06,_,_,_,_,_,_  ), 0                         , 4  , 0  , 261  , 30 , 0  ), // #72
+  INST(Clwb             , X86M_Only          , O(660F00,AE,6,_,_,_,_,_  ), 0                         , 25 , 0  , 266  , 31 , 25 ), // #73
+  INST(Clzero           , X86Op_MemZAX       , O(000F01,FC,_,_,_,_,_,_  ), 0                         , 21 , 0  , 271  , 33 , 26 ), // #74
+  INST(Cmc              , X86Op              , O(000000,F5,_,_,_,_,_,_  ), 0                         , 0  , 0  , 278  , 30 , 27 ), // #75
+  INST(Cmova            , X86Rm              , O(000F00,47,_,_,x,_,_,_  ), 0                         , 4  , 0  , 282  , 22 , 28 ), // #76
+  INST(Cmovae           , X86Rm              , O(000F00,43,_,_,x,_,_,_  ), 0                         , 4  , 0  , 288  , 22 , 29 ), // #77
+  INST(Cmovb            , X86Rm              , O(000F00,42,_,_,x,_,_,_  ), 0                         , 4  , 0  , 643  , 22 , 29 ), // #78
+  INST(Cmovbe           , X86Rm              , O(000F00,46,_,_,x,_,_,_  ), 0                         , 4  , 0  , 650  , 22 , 28 ), // #79
+  INST(Cmovc            , X86Rm              , O(000F00,42,_,_,x,_,_,_  ), 0                         , 4  , 0  , 295  , 22 , 29 ), // #80
+  INST(Cmove            , X86Rm              , O(000F00,44,_,_,x,_,_,_  ), 0                         , 4  , 0  , 658  , 22 , 30 ), // #81
+  INST(Cmovg            , X86Rm              , O(000F00,4F,_,_,x,_,_,_  ), 0                         , 4  , 0  , 301  , 22 , 31 ), // #82
+  INST(Cmovge           , X86Rm              , O(000F00,4D,_,_,x,_,_,_  ), 0                         , 4  , 0  , 307  , 22 , 32 ), // #83
+  INST(Cmovl            , X86Rm              , O(000F00,4C,_,_,x,_,_,_  ), 0                         , 4  , 0  , 314  , 22 , 32 ), // #84
+  INST(Cmovle           , X86Rm              , O(000F00,4E,_,_,x,_,_,_  ), 0                         , 4  , 0  , 320  , 22 , 31 ), // #85
+  INST(Cmovna           , X86Rm              , O(000F00,46,_,_,x,_,_,_  ), 0                         , 4  , 0  , 327  , 22 , 28 ), // #86
+  INST(Cmovnae          , X86Rm              , O(000F00,42,_,_,x,_,_,_  ), 0                         , 4  , 0  , 334  , 22 , 29 ), // #87
+  INST(Cmovnb           , X86Rm              , O(000F00,43,_,_,x,_,_,_  ), 0                         , 4  , 0  , 665  , 22 , 29 ), // #88
+  INST(Cmovnbe          , X86Rm              , O(000F00,47,_,_,x,_,_,_  ), 0                         , 4  , 0  , 673  , 22 , 28 ), // #89
+  INST(Cmovnc           , X86Rm              , O(000F00,43,_,_,x,_,_,_  ), 0                         , 4  , 0  , 342  , 22 , 29 ), // #90
+  INST(Cmovne           , X86Rm              , O(000F00,45,_,_,x,_,_,_  ), 0                         , 4  , 0  , 682  , 22 , 30 ), // #91
+  INST(Cmovng           , X86Rm              , O(000F00,4E,_,_,x,_,_,_  ), 0                         , 4  , 0  , 349  , 22 , 31 ), // #92
+  INST(Cmovnge          , X86Rm              , O(000F00,4C,_,_,x,_,_,_  ), 0                         , 4  , 0  , 356  , 22 , 32 ), // #93
+  INST(Cmovnl           , X86Rm              , O(000F00,4D,_,_,x,_,_,_  ), 0                         , 4  , 0  , 364  , 22 , 32 ), // #94
+  INST(Cmovnle          , X86Rm              , O(000F00,4F,_,_,x,_,_,_  ), 0                         , 4  , 0  , 371  , 22 , 31 ), // #95
+  INST(Cmovno           , X86Rm              , O(000F00,41,_,_,x,_,_,_  ), 0                         , 4  , 0  , 379  , 22 , 33 ), // #96
+  INST(Cmovnp           , X86Rm              , O(000F00,4B,_,_,x,_,_,_  ), 0                         , 4  , 0  , 386  , 22 , 34 ), // #97
+  INST(Cmovns           , X86Rm              , O(000F00,49,_,_,x,_,_,_  ), 0                         , 4  , 0  , 393  , 22 , 35 ), // #98
+  INST(Cmovnz           , X86Rm              , O(000F00,45,_,_,x,_,_,_  ), 0                         , 4  , 0  , 400  , 22 , 30 ), // #99
+  INST(Cmovo            , X86Rm              , O(000F00,40,_,_,x,_,_,_  ), 0                         , 4  , 0  , 407  , 22 , 33 ), // #100
+  INST(Cmovp            , X86Rm              , O(000F00,4A,_,_,x,_,_,_  ), 0                         , 4  , 0  , 413  , 22 , 34 ), // #101
+  INST(Cmovpe           , X86Rm              , O(000F00,4A,_,_,x,_,_,_  ), 0                         , 4  , 0  , 419  , 22 , 34 ), // #102
+  INST(Cmovpo           , X86Rm              , O(000F00,4B,_,_,x,_,_,_  ), 0                         , 4  , 0  , 426  , 22 , 34 ), // #103
+  INST(Cmovs            , X86Rm              , O(000F00,48,_,_,x,_,_,_  ), 0                         , 4  , 0  , 433  , 22 , 35 ), // #104
+  INST(Cmovz            , X86Rm              , O(000F00,44,_,_,x,_,_,_  ), 0                         , 4  , 0  , 439  , 22 , 30 ), // #105
+  INST(Cmp              , X86Arith           , O(000000,38,7,_,x,_,_,_  ), 0                         , 26 , 0  , 445  , 34 , 1  ), // #106
+  INST(Cmppd            , ExtRmi             , O(660F00,C2,_,_,_,_,_,_  ), 0                         , 3  , 0  , 3719 , 8  , 4  ), // #107
+  INST(Cmpps            , ExtRmi             , O(000F00,C2,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3726 , 8  , 5  ), // #108
+  INST(Cmps             , X86StrMm           , O(000000,A6,_,_,_,_,_,_  ), 0                         , 0  , 0  , 449  , 35 , 36 ), // #109
+  INST(Cmpsd            , ExtRmi             , O(F20F00,C2,_,_,_,_,_,_  ), 0                         , 5  , 0  , 3733 , 36 , 4  ), // #110
+  INST(Cmpss            , ExtRmi             , O(F30F00,C2,_,_,_,_,_,_  ), 0                         , 6  , 0  , 3740 , 37 , 5  ), // #111
+  INST(Cmpxchg          , X86Cmpxchg         , O(000F00,B0,_,_,x,_,_,_  ), 0                         , 4  , 0  , 454  , 38 , 37 ), // #112
+  INST(Cmpxchg16b       , X86Cmpxchg8b_16b   , O(000F00,C7,1,_,1,_,_,_  ), 0                         , 27 , 0  , 462  , 39 , 38 ), // #113
+  INST(Cmpxchg8b        , X86Cmpxchg8b_16b   , O(000F00,C7,1,_,_,_,_,_  ), 0                         , 28 , 0  , 473  , 40 , 39 ), // #114
+  INST(Comisd           , ExtRm              , O(660F00,2F,_,_,_,_,_,_  ), 0                         , 3  , 0  , 10246, 6  , 40 ), // #115
+  INST(Comiss           , ExtRm              , O(000F00,2F,_,_,_,_,_,_  ), 0                         , 4  , 0  , 10255, 7  , 41 ), // #116
+  INST(Cpuid            , X86Op              , O(000F00,A2,_,_,_,_,_,_  ), 0                         , 4  , 0  , 483  , 41 , 42 ), // #117
+  INST(Cqo              , X86Op_xDX_xAX      , O(000000,99,_,_,1,_,_,_  ), 0                         , 20 , 0  , 489  , 42 , 0  ), // #118
+  INST(Crc32            , X86Crc             , O(F20F38,F0,_,_,x,_,_,_  ), 0                         , 29 , 0  , 493  , 43 , 43 ), // #119
+  INST(Cvtdq2pd         , ExtRm              , O(F30F00,E6,_,_,_,_,_,_  ), 0                         , 6  , 0  , 3787 , 6  , 4  ), // #120
+  INST(Cvtdq2ps         , ExtRm              , O(000F00,5B,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3797 , 5  , 4  ), // #121
+  INST(Cvtpd2dq         , ExtRm              , O(F20F00,E6,_,_,_,_,_,_  ), 0                         , 5  , 0  , 3836 , 5  , 4  ), // #122
+  INST(Cvtpd2pi         , ExtRm              , O(660F00,2D,_,_,_,_,_,_  ), 0                         , 3  , 0  , 499  , 44 , 4  ), // #123
+  INST(Cvtpd2ps         , ExtRm              , O(660F00,5A,_,_,_,_,_,_  ), 0                         , 3  , 0  , 3846 , 5  , 4  ), // #124
+  INST(Cvtpi2pd         , ExtRm              , O(660F00,2A,_,_,_,_,_,_  ), 0                         , 3  , 0  , 508  , 45 , 4  ), // #125
+  INST(Cvtpi2ps         , ExtRm              , O(000F00,2A,_,_,_,_,_,_  ), 0                         , 4  , 0  , 517  , 45 , 5  ), // #126
+  INST(Cvtps2dq         , ExtRm              , O(660F00,5B,_,_,_,_,_,_  ), 0                         , 3  , 0  , 3898 , 5  , 4  ), // #127
+  INST(Cvtps2pd         , ExtRm              , O(000F00,5A,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3908 , 6  , 4  ), // #128
+  INST(Cvtps2pi         , ExtRm              , O(000F00,2D,_,_,_,_,_,_  ), 0                         , 4  , 0  , 526  , 46 , 5  ), // #129
+  INST(Cvtsd2si         , ExtRm_Wx           , O(F20F00,2D,_,_,x,_,_,_  ), 0                         , 5  , 0  , 3980 , 47 , 4  ), // #130
+  INST(Cvtsd2ss         , ExtRm              , O(F20F00,5A,_,_,_,_,_,_  ), 0                         , 5  , 0  , 3990 , 6  , 4  ), // #131
+  INST(Cvtsi2sd         , ExtRm_Wx           , O(F20F00,2A,_,_,x,_,_,_  ), 0                         , 5  , 0  , 4011 , 48 , 4  ), // #132
+  INST(Cvtsi2ss         , ExtRm_Wx           , O(F30F00,2A,_,_,x,_,_,_  ), 0                         , 6  , 0  , 4021 , 48 , 5  ), // #133
+  INST(Cvtss2sd         , ExtRm              , O(F30F00,5A,_,_,_,_,_,_  ), 0                         , 6  , 0  , 4031 , 7  , 4  ), // #134
+  INST(Cvtss2si         , ExtRm_Wx           , O(F30F00,2D,_,_,x,_,_,_  ), 0                         , 6  , 0  , 4041 , 49 , 5  ), // #135
+  INST(Cvttpd2dq        , ExtRm              , O(660F00,E6,_,_,_,_,_,_  ), 0                         , 3  , 0  , 4062 , 5  , 4  ), // #136
+  INST(Cvttpd2pi        , ExtRm              , O(660F00,2C,_,_,_,_,_,_  ), 0                         , 3  , 0  , 535  , 44 , 4  ), // #137
+  INST(Cvttps2dq        , ExtRm              , O(F30F00,5B,_,_,_,_,_,_  ), 0                         , 6  , 0  , 4108 , 5  , 4  ), // #138
+  INST(Cvttps2pi        , ExtRm              , O(000F00,2C,_,_,_,_,_,_  ), 0                         , 4  , 0  , 545  , 46 , 5  ), // #139
+  INST(Cvttsd2si        , ExtRm_Wx           , O(F20F00,2C,_,_,x,_,_,_  ), 0                         , 5  , 0  , 4154 , 47 , 4  ), // #140
+  INST(Cvttss2si        , ExtRm_Wx           , O(F30F00,2C,_,_,x,_,_,_  ), 0                         , 6  , 0  , 4177 , 49 , 5  ), // #141
+  INST(Cwd              , X86Op_xDX_xAX      , O(660000,99,_,_,_,_,_,_  ), 0                         , 19 , 0  , 555  , 50 , 0  ), // #142
+  INST(Cwde             , X86Op_xAX          , O(000000,98,_,_,_,_,_,_  ), 0                         , 0  , 0  , 559  , 51 , 0  ), // #143
+  INST(Daa              , X86Op              , O(000000,27,_,_,_,_,_,_  ), 0                         , 0  , 0  , 564  , 1  , 1  ), // #144
+  INST(Das              , X86Op              , O(000000,2F,_,_,_,_,_,_  ), 0                         , 0  , 0  , 568  , 1  , 1  ), // #145
+  INST(Dec              , X86IncDec          , O(000000,FE,1,_,x,_,_,_  ), O(000000,48,_,_,x,_,_,_  ), 30 , 6  , 3301 , 52 , 44 ), // #146
+  INST(Div              , X86M_GPB_MulDiv    , O(000000,F6,6,_,x,_,_,_  ), 0                         , 31 , 0  , 805  , 53 , 1  ), // #147
+  INST(Divpd            , ExtRm              , O(660F00,5E,_,_,_,_,_,_  ), 0                         , 3  , 0  , 4276 , 5  , 4  ), // #148
+  INST(Divps            , ExtRm              , O(000F00,5E,_,_,_,_,_,_  ), 0                         , 4  , 0  , 4283 , 5  , 5  ), // #149
+  INST(Divsd            , ExtRm              , O(F20F00,5E,_,_,_,_,_,_  ), 0                         , 5  , 0  , 4290 , 6  , 4  ), // #150
+  INST(Divss            , ExtRm              , O(F30F00,5E,_,_,_,_,_,_  ), 0                         , 6  , 0  , 4297 , 7  , 5  ), // #151
+  INST(Dppd             , ExtRmi             , O(660F3A,41,_,_,_,_,_,_  ), 0                         , 8  , 0  , 4314 , 8  , 12 ), // #152
+  INST(Dpps             , ExtRmi             , O(660F3A,40,_,_,_,_,_,_  ), 0                         , 8  , 0  , 4320 , 8  , 12 ), // #153
+  INST(Emms             , X86Op              , O(000F00,77,_,_,_,_,_,_  ), 0                         , 4  , 0  , 773  , 54 , 45 ), // #154
+  INST(Endbr32          , X86Op_Mod11RM      , O(F30F00,FB,7,_,_,_,_,3  ), 0                         , 32 , 0  , 572  , 30 , 46 ), // #155
+  INST(Endbr64          , X86Op_Mod11RM      , O(F30F00,FA,7,_,_,_,_,2  ), 0                         , 33 , 0  , 580  , 30 , 46 ), // #156
+  INST(Enqcmd           , X86EnqcmdMovdir64b , O(F20F38,F8,_,_,_,_,_,_  ), 0                         , 29 , 0  , 588  , 55 , 47 ), // #157
+  INST(Enqcmds          , X86EnqcmdMovdir64b , O(F30F38,F8,_,_,_,_,_,_  ), 0                         , 7  , 0  , 595  , 55 , 47 ), // #158
+  INST(Enter            , X86Enter           , O(000000,C8,_,_,_,_,_,_  ), 0                         , 0  , 0  , 3017 , 56 , 0  ), // #159
+  INST(Extractps        , ExtExtract         , O(660F3A,17,_,_,_,_,_,_  ), 0                         , 8  , 0  , 4510 , 57 , 12 ), // #160
+  INST(Extrq            , ExtExtrq           , O(660F00,79,_,_,_,_,_,_  ), O(660F00,78,0,_,_,_,_,_  ), 3  , 7  , 7606 , 58 , 48 ), // #161
+  INST(F2xm1            , FpuOp              , O_FPU(00,D9F0,_)          , 0                         , 34 , 0  , 603  , 30 , 0  ), // #162
+  INST(Fabs             , FpuOp              , O_FPU(00,D9E1,_)          , 0                         , 34 , 0  , 609  , 30 , 0  ), // #163
+  INST(Fadd             , FpuArith           , O_FPU(00,C0C0,0)          , 0                         , 35 , 0  , 2106 , 59 , 0  ), // #164
+  INST(Faddp            , FpuRDef            , O_FPU(00,DEC0,_)          , 0                         , 36 , 0  , 614  , 60 , 0  ), // #165
+  INST(Fbld             , X86M_Only          , O_FPU(00,00DF,4)          , 0                         , 37 , 0  , 620  , 61 , 0  ), // #166
+  INST(Fbstp            , X86M_Only          , O_FPU(00,00DF,6)          , 0                         , 38 , 0  , 625  , 61 , 0  ), // #167
+  INST(Fchs             , FpuOp              , O_FPU(00,D9E0,_)          , 0                         , 34 , 0  , 631  , 30 , 0  ), // #168
+  INST(Fclex            , FpuOp              , O_FPU(9B,DBE2,_)          , 0                         , 39 , 0  , 636  , 30 , 0  ), // #169
+  INST(Fcmovb           , FpuR               , O_FPU(00,DAC0,_)          , 0                         , 40 , 0  , 642  , 62 , 29 ), // #170
+  INST(Fcmovbe          , FpuR               , O_FPU(00,DAD0,_)          , 0                         , 40 , 0  , 649  , 62 , 28 ), // #171
+  INST(Fcmove           , FpuR               , O_FPU(00,DAC8,_)          , 0                         , 40 , 0  , 657  , 62 , 30 ), // #172
+  INST(Fcmovnb          , FpuR               , O_FPU(00,DBC0,_)          , 0                         , 41 , 0  , 664  , 62 , 29 ), // #173
+  INST(Fcmovnbe         , FpuR               , O_FPU(00,DBD0,_)          , 0                         , 41 , 0  , 672  , 62 , 28 ), // #174
+  INST(Fcmovne          , FpuR               , O_FPU(00,DBC8,_)          , 0                         , 41 , 0  , 681  , 62 , 30 ), // #175
+  INST(Fcmovnu          , FpuR               , O_FPU(00,DBD8,_)          , 0                         , 41 , 0  , 689  , 62 , 34 ), // #176
+  INST(Fcmovu           , FpuR               , O_FPU(00,DAD8,_)          , 0                         , 40 , 0  , 697  , 62 , 34 ), // #177
+  INST(Fcom             , FpuCom             , O_FPU(00,D0D0,2)          , 0                         , 42 , 0  , 704  , 63 , 0  ), // #178
+  INST(Fcomi            , FpuR               , O_FPU(00,DBF0,_)          , 0                         , 41 , 0  , 709  , 62 , 49 ), // #179
+  INST(Fcomip           , FpuR               , O_FPU(00,DFF0,_)          , 0                         , 43 , 0  , 715  , 62 , 49 ), // #180
+  INST(Fcomp            , FpuCom             , O_FPU(00,D8D8,3)          , 0                         , 44 , 0  , 722  , 63 , 0  ), // #181
+  INST(Fcompp           , FpuOp              , O_FPU(00,DED9,_)          , 0                         , 36 , 0  , 728  , 30 , 0  ), // #182
+  INST(Fcos             , FpuOp              , O_FPU(00,D9FF,_)          , 0                         , 34 , 0  , 735  , 30 , 0  ), // #183
+  INST(Fdecstp          , FpuOp              , O_FPU(00,D9F6,_)          , 0                         , 34 , 0  , 740  , 30 , 0  ), // #184
+  INST(Fdiv             , FpuArith           , O_FPU(00,F0F8,6)          , 0                         , 45 , 0  , 748  , 59 , 0  ), // #185
+  INST(Fdivp            , FpuRDef            , O_FPU(00,DEF8,_)          , 0                         , 36 , 0  , 753  , 60 , 0  ), // #186
+  INST(Fdivr            , FpuArith           , O_FPU(00,F8F0,7)          , 0                         , 46 , 0  , 759  , 59 , 0  ), // #187
+  INST(Fdivrp           , FpuRDef            , O_FPU(00,DEF0,_)          , 0                         , 36 , 0  , 765  , 60 , 0  ), // #188
+  INST(Femms            , X86Op              , O(000F00,0E,_,_,_,_,_,_  ), 0                         , 4  , 0  , 772  , 30 , 50 ), // #189
+  INST(Ffree            , FpuR               , O_FPU(00,DDC0,_)          , 0                         , 47 , 0  , 778  , 62 , 0  ), // #190
+  INST(Fiadd            , FpuM               , O_FPU(00,00DA,0)          , 0                         , 48 , 0  , 784  , 64 , 0  ), // #191
+  INST(Ficom            , FpuM               , O_FPU(00,00DA,2)          , 0                         , 49 , 0  , 790  , 64 , 0  ), // #192
+  INST(Ficomp           , FpuM               , O_FPU(00,00DA,3)          , 0                         , 50 , 0  , 796  , 64 , 0  ), // #193
+  INST(Fidiv            , FpuM               , O_FPU(00,00DA,6)          , 0                         , 38 , 0  , 803  , 64 , 0  ), // #194
+  INST(Fidivr           , FpuM               , O_FPU(00,00DA,7)          , 0                         , 51 , 0  , 809  , 64 , 0  ), // #195
+  INST(Fild             , FpuM               , O_FPU(00,00DB,0)          , O_FPU(00,00DF,5)          , 48 , 8  , 816  , 65 , 0  ), // #196
+  INST(Fimul            , FpuM               , O_FPU(00,00DA,1)          , 0                         , 52 , 0  , 821  , 64 , 0  ), // #197
+  INST(Fincstp          , FpuOp              , O_FPU(00,D9F7,_)          , 0                         , 34 , 0  , 827  , 30 , 0  ), // #198
+  INST(Finit            , FpuOp              , O_FPU(9B,DBE3,_)          , 0                         , 39 , 0  , 835  , 30 , 0  ), // #199
+  INST(Fist             , FpuM               , O_FPU(00,00DB,2)          , 0                         , 49 , 0  , 841  , 64 , 0  ), // #200
+  INST(Fistp            , FpuM               , O_FPU(00,00DB,3)          , O_FPU(00,00DF,7)          , 50 , 9  , 846  , 65 , 0  ), // #201
+  INST(Fisttp           , FpuM               , O_FPU(00,00DB,1)          , O_FPU(00,00DD,1)          , 52 , 10 , 852  , 65 , 6  ), // #202
+  INST(Fisub            , FpuM               , O_FPU(00,00DA,4)          , 0                         , 37 , 0  , 859  , 64 , 0  ), // #203
+  INST(Fisubr           , FpuM               , O_FPU(00,00DA,5)          , 0                         , 53 , 0  , 865  , 64 , 0  ), // #204
+  INST(Fld              , FpuFldFst          , O_FPU(00,00D9,0)          , O_FPU(00,00DB,5)          , 48 , 11 , 872  , 66 , 0  ), // #205
+  INST(Fld1             , FpuOp              , O_FPU(00,D9E8,_)          , 0                         , 34 , 0  , 876  , 30 , 0  ), // #206
+  INST(Fldcw            , X86M_Only          , O_FPU(00,00D9,5)          , 0                         , 53 , 0  , 881  , 67 , 0  ), // #207
+  INST(Fldenv           , X86M_Only          , O_FPU(00,00D9,4)          , 0                         , 37 , 0  , 887  , 31 , 0  ), // #208
+  INST(Fldl2e           , FpuOp              , O_FPU(00,D9EA,_)          , 0                         , 34 , 0  , 894  , 30 , 0  ), // #209
+  INST(Fldl2t           , FpuOp              , O_FPU(00,D9E9,_)          , 0                         , 34 , 0  , 901  , 30 , 0  ), // #210
+  INST(Fldlg2           , FpuOp              , O_FPU(00,D9EC,_)          , 0                         , 34 , 0  , 908  , 30 , 0  ), // #211
+  INST(Fldln2           , FpuOp              , O_FPU(00,D9ED,_)          , 0                         , 34 , 0  , 915  , 30 , 0  ), // #212
+  INST(Fldpi            , FpuOp              , O_FPU(00,D9EB,_)          , 0                         , 34 , 0  , 922  , 30 , 0  ), // #213
+  INST(Fldz             , FpuOp              , O_FPU(00,D9EE,_)          , 0                         , 34 , 0  , 928  , 30 , 0  ), // #214
+  INST(Fmul             , FpuArith           , O_FPU(00,C8C8,1)          , 0                         , 54 , 0  , 2148 , 59 , 0  ), // #215
+  INST(Fmulp            , FpuRDef            , O_FPU(00,DEC8,_)          , 0                         , 36 , 0  , 933  , 60 , 0  ), // #216
+  INST(Fnclex           , FpuOp              , O_FPU(00,DBE2,_)          , 0                         , 41 , 0  , 939  , 30 , 0  ), // #217
+  INST(Fninit           , FpuOp              , O_FPU(00,DBE3,_)          , 0                         , 41 , 0  , 946  , 30 , 0  ), // #218
+  INST(Fnop             , FpuOp              , O_FPU(00,D9D0,_)          , 0                         , 34 , 0  , 953  , 30 , 0  ), // #219
+  INST(Fnsave           , X86M_Only          , O_FPU(00,00DD,6)          , 0                         , 38 , 0  , 958  , 31 , 0  ), // #220
+  INST(Fnstcw           , X86M_Only          , O_FPU(00,00D9,7)          , 0                         , 51 , 0  , 965  , 67 , 0  ), // #221
+  INST(Fnstenv          , X86M_Only          , O_FPU(00,00D9,6)          , 0                         , 38 , 0  , 972  , 31 , 0  ), // #222
+  INST(Fnstsw           , FpuStsw            , O_FPU(00,00DD,7)          , O_FPU(00,DFE0,_)          , 51 , 12 , 980  , 68 , 0  ), // #223
+  INST(Fpatan           , FpuOp              , O_FPU(00,D9F3,_)          , 0                         , 34 , 0  , 987  , 30 , 0  ), // #224
+  INST(Fprem            , FpuOp              , O_FPU(00,D9F8,_)          , 0                         , 34 , 0  , 994  , 30 , 0  ), // #225
+  INST(Fprem1           , FpuOp              , O_FPU(00,D9F5,_)          , 0                         , 34 , 0  , 1000 , 30 , 0  ), // #226
+  INST(Fptan            , FpuOp              , O_FPU(00,D9F2,_)          , 0                         , 34 , 0  , 1007 , 30 , 0  ), // #227
+  INST(Frndint          , FpuOp              , O_FPU(00,D9FC,_)          , 0                         , 34 , 0  , 1013 , 30 , 0  ), // #228
+  INST(Frstor           , X86M_Only          , O_FPU(00,00DD,4)          , 0                         , 37 , 0  , 1021 , 31 , 0  ), // #229
+  INST(Fsave            , X86M_Only          , O_FPU(9B,00DD,6)          , 0                         , 55 , 0  , 1028 , 31 , 0  ), // #230
+  INST(Fscale           , FpuOp              , O_FPU(00,D9FD,_)          , 0                         , 34 , 0  , 1034 , 30 , 0  ), // #231
+  INST(Fsin             , FpuOp              , O_FPU(00,D9FE,_)          , 0                         , 34 , 0  , 1041 , 30 , 0  ), // #232
+  INST(Fsincos          , FpuOp              , O_FPU(00,D9FB,_)          , 0                         , 34 , 0  , 1046 , 30 , 0  ), // #233
+  INST(Fsqrt            , FpuOp              , O_FPU(00,D9FA,_)          , 0                         , 34 , 0  , 1054 , 30 , 0  ), // #234
+  INST(Fst              , FpuFldFst          , O_FPU(00,00D9,2)          , 0                         , 49 , 0  , 1060 , 69 , 0  ), // #235
+  INST(Fstcw            , X86M_Only          , O_FPU(9B,00D9,7)          , 0                         , 56 , 0  , 1064 , 67 , 0  ), // #236
+  INST(Fstenv           , X86M_Only          , O_FPU(9B,00D9,6)          , 0                         , 55 , 0  , 1070 , 31 , 0  ), // #237
+  INST(Fstp             , FpuFldFst          , O_FPU(00,00D9,3)          , O(000000,DB,7,_,_,_,_,_  ), 50 , 13 , 1077 , 66 , 0  ), // #238
+  INST(Fstsw            , FpuStsw            , O_FPU(9B,00DD,7)          , O_FPU(9B,DFE0,_)          , 56 , 14 , 1082 , 68 , 0  ), // #239
+  INST(Fsub             , FpuArith           , O_FPU(00,E0E8,4)          , 0                         , 57 , 0  , 2226 , 59 , 0  ), // #240
+  INST(Fsubp            , FpuRDef            , O_FPU(00,DEE8,_)          , 0                         , 36 , 0  , 1088 , 60 , 0  ), // #241
+  INST(Fsubr            , FpuArith           , O_FPU(00,E8E0,5)          , 0                         , 58 , 0  , 2232 , 59 , 0  ), // #242
+  INST(Fsubrp           , FpuRDef            , O_FPU(00,DEE0,_)          , 0                         , 36 , 0  , 1094 , 60 , 0  ), // #243
+  INST(Ftst             , FpuOp              , O_FPU(00,D9E4,_)          , 0                         , 34 , 0  , 1101 , 30 , 0  ), // #244
+  INST(Fucom            , FpuRDef            , O_FPU(00,DDE0,_)          , 0                         , 47 , 0  , 1106 , 60 , 0  ), // #245
+  INST(Fucomi           , FpuR               , O_FPU(00,DBE8,_)          , 0                         , 41 , 0  , 1112 , 62 , 49 ), // #246
+  INST(Fucomip          , FpuR               , O_FPU(00,DFE8,_)          , 0                         , 43 , 0  , 1119 , 62 , 49 ), // #247
+  INST(Fucomp           , FpuRDef            , O_FPU(00,DDE8,_)          , 0                         , 47 , 0  , 1127 , 60 , 0  ), // #248
+  INST(Fucompp          , FpuOp              , O_FPU(00,DAE9,_)          , 0                         , 40 , 0  , 1134 , 30 , 0  ), // #249
+  INST(Fwait            , X86Op              , O_FPU(00,009B,_)          , 0                         , 59 , 0  , 1142 , 30 , 0  ), // #250
+  INST(Fxam             , FpuOp              , O_FPU(00,D9E5,_)          , 0                         , 34 , 0  , 1148 , 30 , 0  ), // #251
+  INST(Fxch             , FpuR               , O_FPU(00,D9C8,_)          , 0                         , 34 , 0  , 1153 , 60 , 0  ), // #252
+  INST(Fxrstor          , X86M_Only          , O(000F00,AE,1,_,_,_,_,_  ), 0                         , 28 , 0  , 1158 , 31 , 51 ), // #253
+  INST(Fxrstor64        , X86M_Only          , O(000F00,AE,1,_,1,_,_,_  ), 0                         , 27 , 0  , 1166 , 70 , 51 ), // #254
+  INST(Fxsave           , X86M_Only          , O(000F00,AE,0,_,_,_,_,_  ), 0                         , 4  , 0  , 1176 , 31 , 51 ), // #255
+  INST(Fxsave64         , X86M_Only          , O(000F00,AE,0,_,1,_,_,_  ), 0                         , 60 , 0  , 1183 , 70 , 51 ), // #256
+  INST(Fxtract          , FpuOp              , O_FPU(00,D9F4,_)          , 0                         , 34 , 0  , 1192 , 30 , 0  ), // #257
+  INST(Fyl2x            , FpuOp              , O_FPU(00,D9F1,_)          , 0                         , 34 , 0  , 1200 , 30 , 0  ), // #258
+  INST(Fyl2xp1          , FpuOp              , O_FPU(00,D9F9,_)          , 0                         , 34 , 0  , 1206 , 30 , 0  ), // #259
+  INST(Getsec           , X86Op              , O(000F00,37,_,_,_,_,_,_  ), 0                         , 4  , 0  , 1214 , 30 , 52 ), // #260
+  INST(Gf2p8affineinvqb , ExtRmi             , O(660F3A,CF,_,_,_,_,_,_  ), 0                         , 8  , 0  , 5865 , 8  , 53 ), // #261
+  INST(Gf2p8affineqb    , ExtRmi             , O(660F3A,CE,_,_,_,_,_,_  ), 0                         , 8  , 0  , 5883 , 8  , 53 ), // #262
+  INST(Gf2p8mulb        , ExtRm              , O(660F38,CF,_,_,_,_,_,_  ), 0                         , 2  , 0  , 5898 , 5  , 53 ), // #263
+  INST(Haddpd           , ExtRm              , O(660F00,7C,_,_,_,_,_,_  ), 0                         , 3  , 0  , 5909 , 5  , 6  ), // #264
+  INST(Haddps           , ExtRm              , O(F20F00,7C,_,_,_,_,_,_  ), 0                         , 5  , 0  , 5917 , 5  , 6  ), // #265
+  INST(Hlt              , X86Op              , O(000000,F4,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1221 , 30 , 0  ), // #266
+  INST(Hsubpd           , ExtRm              , O(660F00,7D,_,_,_,_,_,_  ), 0                         , 3  , 0  , 5925 , 5  , 6  ), // #267
+  INST(Hsubps           , ExtRm              , O(F20F00,7D,_,_,_,_,_,_  ), 0                         , 5  , 0  , 5933 , 5  , 6  ), // #268
+  INST(Idiv             , X86M_GPB_MulDiv    , O(000000,F6,7,_,x,_,_,_  ), 0                         , 26 , 0  , 804  , 53 , 1  ), // #269
+  INST(Imul             , X86Imul            , O(000000,F6,5,_,x,_,_,_  ), 0                         , 61 , 0  , 822  , 71 , 1  ), // #270
+  INST(In               , X86In              , O(000000,EC,_,_,_,_,_,_  ), O(000000,E4,_,_,_,_,_,_  ), 0  , 15 , 10418, 72 , 0  ), // #271
+  INST(Inc              , X86IncDec          , O(000000,FE,0,_,x,_,_,_  ), O(000000,40,_,_,x,_,_,_  ), 0  , 16 , 1225 , 52 , 44 ), // #272
+  INST(Incsspd          , X86M               , O(F30F00,AE,5,_,0,_,_,_  ), 0                         , 62 , 0  , 1229 , 73 , 54 ), // #273
+  INST(Incsspq          , X86M               , O(F30F00,AE,5,_,1,_,_,_  ), 0                         , 63 , 0  , 1237 , 74 , 54 ), // #274
+  INST(Ins              , X86Ins             , O(000000,6C,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1908 , 75 , 0  ), // #275
+  INST(Insertps         , ExtRmi             , O(660F3A,21,_,_,_,_,_,_  ), 0                         , 8  , 0  , 6069 , 37 , 12 ), // #276
+  INST(Insertq          , ExtInsertq         , O(F20F00,79,_,_,_,_,_,_  ), O(F20F00,78,_,_,_,_,_,_  ), 5  , 17 , 1245 , 76 , 48 ), // #277
+  INST(Int              , X86Int             , O(000000,CD,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1017 , 77 , 0  ), // #278
+  INST(Int3             , X86Op              , O(000000,CC,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1253 , 30 , 0  ), // #279
+  INST(Into             , X86Op              , O(000000,CE,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1258 , 78 , 55 ), // #280
+  INST(Invd             , X86Op              , O(000F00,08,_,_,_,_,_,_  ), 0                         , 4  , 0  , 10347, 30 , 42 ), // #281
+  INST(Invept           , X86Rm_NoSize       , O(660F38,80,_,_,_,_,_,_  ), 0                         , 2  , 0  , 1263 , 79 , 56 ), // #282
+  INST(Invlpg           , X86M_Only          , O(000F00,01,7,_,_,_,_,_  ), 0                         , 22 , 0  , 1270 , 31 , 42 ), // #283
+  INST(Invlpga          , X86Op_xAddr        , O(000F01,DF,_,_,_,_,_,_  ), 0                         , 21 , 0  , 1277 , 80 , 22 ), // #284
+  INST(Invpcid          , X86Rm_NoSize       , O(660F38,82,_,_,_,_,_,_  ), 0                         , 2  , 0  , 1285 , 79 , 42 ), // #285
+  INST(Invvpid          , X86Rm_NoSize       , O(660F38,81,_,_,_,_,_,_  ), 0                         , 2  , 0  , 1293 , 79 , 56 ), // #286
+  INST(Iret             , X86Op              , O(000000,CF,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1301 , 81 , 1  ), // #287
+  INST(Iretd            , X86Op              , O(000000,CF,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1306 , 81 , 1  ), // #288
+  INST(Iretq            , X86Op              , O(000000,CF,_,_,1,_,_,_  ), 0                         , 20 , 0  , 1312 , 82 , 1  ), // #289
+  INST(Iretw            , X86Op              , O(660000,CF,_,_,_,_,_,_  ), 0                         , 19 , 0  , 1318 , 81 , 1  ), // #290
+  INST(Ja               , X86Jcc             , O(000F00,87,_,_,_,_,_,_  ), O(000000,77,_,_,_,_,_,_  ), 4  , 18 , 1324 , 83 , 57 ), // #291
+  INST(Jae              , X86Jcc             , O(000F00,83,_,_,_,_,_,_  ), O(000000,73,_,_,_,_,_,_  ), 4  , 19 , 1327 , 83 , 58 ), // #292
+  INST(Jb               , X86Jcc             , O(000F00,82,_,_,_,_,_,_  ), O(000000,72,_,_,_,_,_,_  ), 4  , 20 , 1331 , 83 , 58 ), // #293
+  INST(Jbe              , X86Jcc             , O(000F00,86,_,_,_,_,_,_  ), O(000000,76,_,_,_,_,_,_  ), 4  , 21 , 1334 , 83 , 57 ), // #294
+  INST(Jc               , X86Jcc             , O(000F00,82,_,_,_,_,_,_  ), O(000000,72,_,_,_,_,_,_  ), 4  , 20 , 1338 , 83 , 58 ), // #295
+  INST(Je               , X86Jcc             , O(000F00,84,_,_,_,_,_,_  ), O(000000,74,_,_,_,_,_,_  ), 4  , 22 , 1341 , 83 , 59 ), // #296
+  INST(Jecxz            , X86JecxzLoop       , 0                         , O(000000,E3,_,_,_,_,_,_  ), 0  , 23 , 1344 , 84 , 0  ), // #297
+  INST(Jg               , X86Jcc             , O(000F00,8F,_,_,_,_,_,_  ), O(000000,7F,_,_,_,_,_,_  ), 4  , 24 , 1350 , 83 , 60 ), // #298
+  INST(Jge              , X86Jcc             , O(000F00,8D,_,_,_,_,_,_  ), O(000000,7D,_,_,_,_,_,_  ), 4  , 25 , 1353 , 83 , 61 ), // #299
+  INST(Jl               , X86Jcc             , O(000F00,8C,_,_,_,_,_,_  ), O(000000,7C,_,_,_,_,_,_  ), 4  , 26 , 1357 , 83 , 61 ), // #300
+  INST(Jle              , X86Jcc             , O(000F00,8E,_,_,_,_,_,_  ), O(000000,7E,_,_,_,_,_,_  ), 4  , 27 , 1360 , 83 , 60 ), // #301
+  INST(Jmp              , X86Jmp             , O(000000,FF,4,_,_,_,_,_  ), O(000000,EB,_,_,_,_,_,_  ), 9  , 28 , 1364 , 85 , 0  ), // #302
+  INST(Jna              , X86Jcc             , O(000F00,86,_,_,_,_,_,_  ), O(000000,76,_,_,_,_,_,_  ), 4  , 21 , 1368 , 83 , 57 ), // #303
+  INST(Jnae             , X86Jcc             , O(000F00,82,_,_,_,_,_,_  ), O(000000,72,_,_,_,_,_,_  ), 4  , 20 , 1372 , 83 , 58 ), // #304
+  INST(Jnb              , X86Jcc             , O(000F00,83,_,_,_,_,_,_  ), O(000000,73,_,_,_,_,_,_  ), 4  , 19 , 1377 , 83 , 58 ), // #305
+  INST(Jnbe             , X86Jcc             , O(000F00,87,_,_,_,_,_,_  ), O(000000,77,_,_,_,_,_,_  ), 4  , 18 , 1381 , 83 , 57 ), // #306
+  INST(Jnc              , X86Jcc             , O(000F00,83,_,_,_,_,_,_  ), O(000000,73,_,_,_,_,_,_  ), 4  , 19 , 1386 , 83 , 58 ), // #307
+  INST(Jne              , X86Jcc             , O(000F00,85,_,_,_,_,_,_  ), O(000000,75,_,_,_,_,_,_  ), 4  , 29 , 1390 , 83 , 59 ), // #308
+  INST(Jng              , X86Jcc             , O(000F00,8E,_,_,_,_,_,_  ), O(000000,7E,_,_,_,_,_,_  ), 4  , 27 , 1394 , 83 , 60 ), // #309
+  INST(Jnge             , X86Jcc             , O(000F00,8C,_,_,_,_,_,_  ), O(000000,7C,_,_,_,_,_,_  ), 4  , 26 , 1398 , 83 , 61 ), // #310
+  INST(Jnl              , X86Jcc             , O(000F00,8D,_,_,_,_,_,_  ), O(000000,7D,_,_,_,_,_,_  ), 4  , 25 , 1403 , 83 , 61 ), // #311
+  INST(Jnle             , X86Jcc             , O(000F00,8F,_,_,_,_,_,_  ), O(000000,7F,_,_,_,_,_,_  ), 4  , 24 , 1407 , 83 , 60 ), // #312
+  INST(Jno              , X86Jcc             , O(000F00,81,_,_,_,_,_,_  ), O(000000,71,_,_,_,_,_,_  ), 4  , 30 , 1412 , 83 , 55 ), // #313
+  INST(Jnp              , X86Jcc             , O(000F00,8B,_,_,_,_,_,_  ), O(000000,7B,_,_,_,_,_,_  ), 4  , 31 , 1416 , 83 , 62 ), // #314
+  INST(Jns              , X86Jcc             , O(000F00,89,_,_,_,_,_,_  ), O(000000,79,_,_,_,_,_,_  ), 4  , 32 , 1420 , 83 , 63 ), // #315
+  INST(Jnz              , X86Jcc             , O(000F00,85,_,_,_,_,_,_  ), O(000000,75,_,_,_,_,_,_  ), 4  , 29 , 1424 , 83 , 59 ), // #316
+  INST(Jo               , X86Jcc             , O(000F00,80,_,_,_,_,_,_  ), O(000000,70,_,_,_,_,_,_  ), 4  , 33 , 1428 , 83 , 55 ), // #317
+  INST(Jp               , X86Jcc             , O(000F00,8A,_,_,_,_,_,_  ), O(000000,7A,_,_,_,_,_,_  ), 4  , 34 , 1431 , 83 , 62 ), // #318
+  INST(Jpe              , X86Jcc             , O(000F00,8A,_,_,_,_,_,_  ), O(000000,7A,_,_,_,_,_,_  ), 4  , 34 , 1434 , 83 , 62 ), // #319
+  INST(Jpo              , X86Jcc             , O(000F00,8B,_,_,_,_,_,_  ), O(000000,7B,_,_,_,_,_,_  ), 4  , 31 , 1438 , 83 , 62 ), // #320
+  INST(Js               , X86Jcc             , O(000F00,88,_,_,_,_,_,_  ), O(000000,78,_,_,_,_,_,_  ), 4  , 35 , 1442 , 83 , 63 ), // #321
+  INST(Jz               , X86Jcc             , O(000F00,84,_,_,_,_,_,_  ), O(000000,74,_,_,_,_,_,_  ), 4  , 22 , 1445 , 83 , 59 ), // #322
+  INST(Kaddb            , VexRvm             , V(660F00,4A,_,1,0,_,_,_  ), 0                         , 64 , 0  , 1448 , 86 , 64 ), // #323
+  INST(Kaddd            , VexRvm             , V(660F00,4A,_,1,1,_,_,_  ), 0                         , 65 , 0  , 1454 , 86 , 65 ), // #324
+  INST(Kaddq            , VexRvm             , V(000F00,4A,_,1,1,_,_,_  ), 0                         , 66 , 0  , 1460 , 86 , 65 ), // #325
+  INST(Kaddw            , VexRvm             , V(000F00,4A,_,1,0,_,_,_  ), 0                         , 67 , 0  , 1466 , 86 , 64 ), // #326
+  INST(Kandb            , VexRvm             , V(660F00,41,_,1,0,_,_,_  ), 0                         , 64 , 0  , 1472 , 86 , 64 ), // #327
+  INST(Kandd            , VexRvm             , V(660F00,41,_,1,1,_,_,_  ), 0                         , 65 , 0  , 1478 , 86 , 65 ), // #328
+  INST(Kandnb           , VexRvm             , V(660F00,42,_,1,0,_,_,_  ), 0                         , 64 , 0  , 1484 , 86 , 64 ), // #329
+  INST(Kandnd           , VexRvm             , V(660F00,42,_,1,1,_,_,_  ), 0                         , 65 , 0  , 1491 , 86 , 65 ), // #330
+  INST(Kandnq           , VexRvm             , V(000F00,42,_,1,1,_,_,_  ), 0                         , 66 , 0  , 1498 , 86 , 65 ), // #331
+  INST(Kandnw           , VexRvm             , V(000F00,42,_,1,0,_,_,_  ), 0                         , 67 , 0  , 1505 , 86 , 66 ), // #332
+  INST(Kandq            , VexRvm             , V(000F00,41,_,1,1,_,_,_  ), 0                         , 66 , 0  , 1512 , 86 , 65 ), // #333
+  INST(Kandw            , VexRvm             , V(000F00,41,_,1,0,_,_,_  ), 0                         , 67 , 0  , 1518 , 86 , 66 ), // #334
+  INST(Kmovb            , VexKmov            , V(660F00,90,_,0,0,_,_,_  ), V(660F00,92,_,0,0,_,_,_  ), 68 , 36 , 1524 , 87 , 64 ), // #335
+  INST(Kmovd            , VexKmov            , V(660F00,90,_,0,1,_,_,_  ), V(F20F00,92,_,0,0,_,_,_  ), 69 , 37 , 8086 , 88 , 65 ), // #336
+  INST(Kmovq            , VexKmov            , V(000F00,90,_,0,1,_,_,_  ), V(F20F00,92,_,0,1,_,_,_  ), 70 , 38 , 8097 , 89 , 65 ), // #337
+  INST(Kmovw            , VexKmov            , V(000F00,90,_,0,0,_,_,_  ), V(000F00,92,_,0,0,_,_,_  ), 71 , 39 , 1530 , 90 , 66 ), // #338
+  INST(Knotb            , VexRm              , V(660F00,44,_,0,0,_,_,_  ), 0                         , 68 , 0  , 1536 , 91 , 64 ), // #339
+  INST(Knotd            , VexRm              , V(660F00,44,_,0,1,_,_,_  ), 0                         , 69 , 0  , 1542 , 91 , 65 ), // #340
+  INST(Knotq            , VexRm              , V(000F00,44,_,0,1,_,_,_  ), 0                         , 70 , 0  , 1548 , 91 , 65 ), // #341
+  INST(Knotw            , VexRm              , V(000F00,44,_,0,0,_,_,_  ), 0                         , 71 , 0  , 1554 , 91 , 66 ), // #342
+  INST(Korb             , VexRvm             , V(660F00,45,_,1,0,_,_,_  ), 0                         , 64 , 0  , 1560 , 86 , 64 ), // #343
+  INST(Kord             , VexRvm             , V(660F00,45,_,1,1,_,_,_  ), 0                         , 65 , 0  , 1565 , 86 , 65 ), // #344
+  INST(Korq             , VexRvm             , V(000F00,45,_,1,1,_,_,_  ), 0                         , 66 , 0  , 1570 , 86 , 65 ), // #345
+  INST(Kortestb         , VexRm              , V(660F00,98,_,0,0,_,_,_  ), 0                         , 68 , 0  , 1575 , 91 , 67 ), // #346
+  INST(Kortestd         , VexRm              , V(660F00,98,_,0,1,_,_,_  ), 0                         , 69 , 0  , 1584 , 91 , 68 ), // #347
+  INST(Kortestq         , VexRm              , V(000F00,98,_,0,1,_,_,_  ), 0                         , 70 , 0  , 1593 , 91 , 68 ), // #348
+  INST(Kortestw         , VexRm              , V(000F00,98,_,0,0,_,_,_  ), 0                         , 71 , 0  , 1602 , 91 , 69 ), // #349
+  INST(Korw             , VexRvm             , V(000F00,45,_,1,0,_,_,_  ), 0                         , 67 , 0  , 1611 , 86 , 66 ), // #350
+  INST(Kshiftlb         , VexRmi             , V(660F3A,32,_,0,0,_,_,_  ), 0                         , 72 , 0  , 1616 , 92 , 64 ), // #351
+  INST(Kshiftld         , VexRmi             , V(660F3A,33,_,0,0,_,_,_  ), 0                         , 72 , 0  , 1625 , 92 , 65 ), // #352
+  INST(Kshiftlq         , VexRmi             , V(660F3A,33,_,0,1,_,_,_  ), 0                         , 73 , 0  , 1634 , 92 , 65 ), // #353
+  INST(Kshiftlw         , VexRmi             , V(660F3A,32,_,0,1,_,_,_  ), 0                         , 73 , 0  , 1643 , 92 , 66 ), // #354
+  INST(Kshiftrb         , VexRmi             , V(660F3A,30,_,0,0,_,_,_  ), 0                         , 72 , 0  , 1652 , 92 , 64 ), // #355
+  INST(Kshiftrd         , VexRmi             , V(660F3A,31,_,0,0,_,_,_  ), 0                         , 72 , 0  , 1661 , 92 , 65 ), // #356
+  INST(Kshiftrq         , VexRmi             , V(660F3A,31,_,0,1,_,_,_  ), 0                         , 73 , 0  , 1670 , 92 , 65 ), // #357
+  INST(Kshiftrw         , VexRmi             , V(660F3A,30,_,0,1,_,_,_  ), 0                         , 73 , 0  , 1679 , 92 , 66 ), // #358
+  INST(Ktestb           , VexRm              , V(660F00,99,_,0,0,_,_,_  ), 0                         , 68 , 0  , 1688 , 91 , 67 ), // #359
+  INST(Ktestd           , VexRm              , V(660F00,99,_,0,1,_,_,_  ), 0                         , 69 , 0  , 1695 , 91 , 68 ), // #360
+  INST(Ktestq           , VexRm              , V(000F00,99,_,0,1,_,_,_  ), 0                         , 70 , 0  , 1702 , 91 , 68 ), // #361
+  INST(Ktestw           , VexRm              , V(000F00,99,_,0,0,_,_,_  ), 0                         , 71 , 0  , 1709 , 91 , 67 ), // #362
+  INST(Kunpckbw         , VexRvm             , V(660F00,4B,_,1,0,_,_,_  ), 0                         , 64 , 0  , 1716 , 86 , 66 ), // #363
+  INST(Kunpckdq         , VexRvm             , V(000F00,4B,_,1,1,_,_,_  ), 0                         , 66 , 0  , 1725 , 86 , 65 ), // #364
+  INST(Kunpckwd         , VexRvm             , V(000F00,4B,_,1,0,_,_,_  ), 0                         , 67 , 0  , 1734 , 86 , 65 ), // #365
+  INST(Kxnorb           , VexRvm             , V(660F00,46,_,1,0,_,_,_  ), 0                         , 64 , 0  , 1743 , 86 , 64 ), // #366
+  INST(Kxnord           , VexRvm             , V(660F00,46,_,1,1,_,_,_  ), 0                         , 65 , 0  , 1750 , 86 , 65 ), // #367
+  INST(Kxnorq           , VexRvm             , V(000F00,46,_,1,1,_,_,_  ), 0                         , 66 , 0  , 1757 , 86 , 65 ), // #368
+  INST(Kxnorw           , VexRvm             , V(000F00,46,_,1,0,_,_,_  ), 0                         , 67 , 0  , 1764 , 86 , 66 ), // #369
+  INST(Kxorb            , VexRvm             , V(660F00,47,_,1,0,_,_,_  ), 0                         , 64 , 0  , 1771 , 86 , 64 ), // #370
+  INST(Kxord            , VexRvm             , V(660F00,47,_,1,1,_,_,_  ), 0                         , 65 , 0  , 1777 , 86 , 65 ), // #371
+  INST(Kxorq            , VexRvm             , V(000F00,47,_,1,1,_,_,_  ), 0                         , 66 , 0  , 1783 , 86 , 65 ), // #372
+  INST(Kxorw            , VexRvm             , V(000F00,47,_,1,0,_,_,_  ), 0                         , 67 , 0  , 1789 , 86 , 66 ), // #373
+  INST(Lahf             , X86Op              , O(000000,9F,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1795 , 93 , 70 ), // #374
+  INST(Lar              , X86Rm              , O(000F00,02,_,_,_,_,_,_  ), 0                         , 4  , 0  , 1800 , 94 , 10 ), // #375
+  INST(Lddqu            , ExtRm              , O(F20F00,F0,_,_,_,_,_,_  ), 0                         , 5  , 0  , 6079 , 95 , 6  ), // #376
+  INST(Ldmxcsr          , X86M_Only          , O(000F00,AE,2,_,_,_,_,_  ), 0                         , 74 , 0  , 6086 , 96 , 5  ), // #377
+  INST(Lds              , X86Rm              , O(000000,C5,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1804 , 97 , 0  ), // #378
+  INST(Ldtilecfg        , AmxCfg             , V(000F38,49,_,0,0,_,_,_  ), 0                         , 10 , 0  , 1808 , 98 , 71 ), // #379
+  INST(Lea              , X86Lea             , O(000000,8D,_,_,x,_,_,_  ), 0                         , 0  , 0  , 1818 , 99 , 0  ), // #380
+  INST(Leave            , X86Op              , O(000000,C9,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1822 , 30 , 0  ), // #381
+  INST(Les              , X86Rm              , O(000000,C4,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1828 , 97 , 0  ), // #382
+  INST(Lfence           , X86Fence           , O(000F00,AE,5,_,_,_,_,_  ), 0                         , 75 , 0  , 1832 , 30 , 4  ), // #383
+  INST(Lfs              , X86Rm              , O(000F00,B4,_,_,_,_,_,_  ), 0                         , 4  , 0  , 1839 , 100, 0  ), // #384
+  INST(Lgdt             , X86M_Only          , O(000F00,01,2,_,_,_,_,_  ), 0                         , 74 , 0  , 1843 , 31 , 0  ), // #385
+  INST(Lgs              , X86Rm              , O(000F00,B5,_,_,_,_,_,_  ), 0                         , 4  , 0  , 1848 , 100, 0  ), // #386
+  INST(Lidt             , X86M_Only          , O(000F00,01,3,_,_,_,_,_  ), 0                         , 76 , 0  , 1852 , 31 , 0  ), // #387
+  INST(Lldt             , X86M_NoSize        , O(000F00,00,2,_,_,_,_,_  ), 0                         , 74 , 0  , 1857 , 101, 0  ), // #388
+  INST(Llwpcb           , VexR_Wx            , V(XOP_M9,12,0,0,x,_,_,_  ), 0                         , 77 , 0  , 1862 , 102, 72 ), // #389
+  INST(Lmsw             , X86M_NoSize        , O(000F00,01,6,_,_,_,_,_  ), 0                         , 78 , 0  , 1869 , 101, 0  ), // #390
+  INST(Lods             , X86StrRm           , O(000000,AC,_,_,_,_,_,_  ), 0                         , 0  , 0  , 1874 , 103, 73 ), // #391
+  INST(Loop             , X86JecxzLoop       , 0                         , O(000000,E2,_,_,_,_,_,_  ), 0  , 40 , 1879 , 104, 0  ), // #392
+  INST(Loope            , X86JecxzLoop       , 0                         , O(000000,E1,_,_,_,_,_,_  ), 0  , 41 , 1884 , 104, 59 ), // #393
+  INST(Loopne           , X86JecxzLoop       , 0                         , O(000000,E0,_,_,_,_,_,_  ), 0  , 42 , 1890 , 104, 59 ), // #394
+  INST(Lsl              , X86Rm              , O(000F00,03,_,_,_,_,_,_  ), 0                         , 4  , 0  , 1897 , 105, 10 ), // #395
+  INST(Lss              , X86Rm              , O(000F00,B2,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6577 , 100, 0  ), // #396
+  INST(Ltr              , X86M_NoSize        , O(000F00,00,3,_,_,_,_,_  ), 0                         , 76 , 0  , 1901 , 101, 0  ), // #397
+  INST(Lwpins           , VexVmi4_Wx         , V(XOP_MA,12,0,0,x,_,_,_  ), 0                         , 79 , 0  , 1905 , 106, 72 ), // #398
+  INST(Lwpval           , VexVmi4_Wx         , V(XOP_MA,12,1,0,x,_,_,_  ), 0                         , 80 , 0  , 1912 , 106, 72 ), // #399
+  INST(Lzcnt            , X86Rm_Raw66H       , O(F30F00,BD,_,_,x,_,_,_  ), 0                         , 6  , 0  , 1919 , 22 , 74 ), // #400
+  INST(Maskmovdqu       , ExtRm_ZDI          , O(660F00,57,_,_,_,_,_,_  ), 0                         , 3  , 0  , 6095 , 107, 4  ), // #401
+  INST(Maskmovq         , ExtRm_ZDI          , O(000F00,F7,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8094 , 108, 75 ), // #402
+  INST(Maxpd            , ExtRm              , O(660F00,5F,_,_,_,_,_,_  ), 0                         , 3  , 0  , 6129 , 5  , 4  ), // #403
+  INST(Maxps            , ExtRm              , O(000F00,5F,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6136 , 5  , 5  ), // #404
+  INST(Maxsd            , ExtRm              , O(F20F00,5F,_,_,_,_,_,_  ), 0                         , 5  , 0  , 8113 , 6  , 4  ), // #405
+  INST(Maxss            , ExtRm              , O(F30F00,5F,_,_,_,_,_,_  ), 0                         , 6  , 0  , 6150 , 7  , 5  ), // #406
+  INST(Mcommit          , X86Op              , O(F30F01,FA,_,_,_,_,_,_  ), 0                         , 81 , 0  , 1925 , 30 , 76 ), // #407
+  INST(Mfence           , X86Fence           , O(000F00,AE,6,_,_,_,_,_  ), 0                         , 78 , 0  , 1933 , 30 , 4  ), // #408
+  INST(Minpd            , ExtRm              , O(660F00,5D,_,_,_,_,_,_  ), 0                         , 3  , 0  , 6179 , 5  , 4  ), // #409
+  INST(Minps            , ExtRm              , O(000F00,5D,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6186 , 5  , 5  ), // #410
+  INST(Minsd            , ExtRm              , O(F20F00,5D,_,_,_,_,_,_  ), 0                         , 5  , 0  , 8177 , 6  , 4  ), // #411
+  INST(Minss            , ExtRm              , O(F30F00,5D,_,_,_,_,_,_  ), 0                         , 6  , 0  , 6200 , 7  , 5  ), // #412
+  INST(Monitor          , X86Op              , O(000F01,C8,_,_,_,_,_,_  ), 0                         , 21 , 0  , 3192 , 109, 77 ), // #413
+  INST(Monitorx         , X86Op              , O(000F01,FA,_,_,_,_,_,_  ), 0                         , 21 , 0  , 1940 , 109, 78 ), // #414
+  INST(Mov              , X86Mov             , 0                         , 0                         , 0  , 0  , 138  , 110, 0  ), // #415
+  INST(Movapd           , ExtMov             , O(660F00,28,_,_,_,_,_,_  ), O(660F00,29,_,_,_,_,_,_  ), 3  , 43 , 6231 , 111, 4  ), // #416
+  INST(Movaps           , ExtMov             , O(000F00,28,_,_,_,_,_,_  ), O(000F00,29,_,_,_,_,_,_  ), 4  , 44 , 6239 , 111, 5  ), // #417
+  INST(Movbe            , ExtMovbe           , O(000F38,F0,_,_,x,_,_,_  ), O(000F38,F1,_,_,x,_,_,_  ), 82 , 45 , 651  , 112, 79 ), // #418
+  INST(Movd             , ExtMovd            , O(000F00,6E,_,_,_,_,_,_  ), O(000F00,7E,_,_,_,_,_,_  ), 4  , 46 , 8087 , 113, 80 ), // #419
+  INST(Movddup          , ExtMov             , O(F20F00,12,_,_,_,_,_,_  ), 0                         , 5  , 0  , 6253 , 6  , 6  ), // #420
+  INST(Movdir64b        , X86EnqcmdMovdir64b , O(660F38,F8,_,_,_,_,_,_  ), 0                         , 2  , 0  , 1949 , 114, 81 ), // #421
+  INST(Movdiri          , X86MovntiMovdiri   , O(000F38,F9,_,_,_,_,_,_  ), 0                         , 82 , 0  , 1959 , 115, 82 ), // #422
+  INST(Movdq2q          , ExtMov             , O(F20F00,D6,_,_,_,_,_,_  ), 0                         , 5  , 0  , 1967 , 116, 4  ), // #423
+  INST(Movdqa           , ExtMov             , O(660F00,6F,_,_,_,_,_,_  ), O(660F00,7F,_,_,_,_,_,_  ), 3  , 47 , 6262 , 111, 4  ), // #424
+  INST(Movdqu           , ExtMov             , O(F30F00,6F,_,_,_,_,_,_  ), O(F30F00,7F,_,_,_,_,_,_  ), 6  , 48 , 6099 , 111, 4  ), // #425
+  INST(Movhlps          , ExtMov             , O(000F00,12,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6337 , 117, 5  ), // #426
+  INST(Movhpd           , ExtMov             , O(660F00,16,_,_,_,_,_,_  ), O(660F00,17,_,_,_,_,_,_  ), 3  , 49 , 6346 , 118, 4  ), // #427
+  INST(Movhps           , ExtMov             , O(000F00,16,_,_,_,_,_,_  ), O(000F00,17,_,_,_,_,_,_  ), 4  , 50 , 6354 , 118, 5  ), // #428
+  INST(Movlhps          , ExtMov             , O(000F00,16,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6362 , 117, 5  ), // #429
+  INST(Movlpd           , ExtMov             , O(660F00,12,_,_,_,_,_,_  ), O(660F00,13,_,_,_,_,_,_  ), 3  , 51 , 6371 , 118, 4  ), // #430
+  INST(Movlps           , ExtMov             , O(000F00,12,_,_,_,_,_,_  ), O(000F00,13,_,_,_,_,_,_  ), 4  , 52 , 6379 , 118, 5  ), // #431
+  INST(Movmskpd         , ExtMov             , O(660F00,50,_,_,_,_,_,_  ), 0                         , 3  , 0  , 6387 , 119, 4  ), // #432
+  INST(Movmskps         , ExtMov             , O(000F00,50,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6397 , 119, 5  ), // #433
+  INST(Movntdq          , ExtMov             , 0                         , O(660F00,E7,_,_,_,_,_,_  ), 0  , 53 , 6407 , 120, 4  ), // #434
+  INST(Movntdqa         , ExtMov             , O(660F38,2A,_,_,_,_,_,_  ), 0                         , 2  , 0  , 6416 , 95 , 12 ), // #435
+  INST(Movnti           , X86MovntiMovdiri   , O(000F00,C3,_,_,x,_,_,_  ), 0                         , 4  , 0  , 1975 , 115, 4  ), // #436
+  INST(Movntpd          , ExtMov             , 0                         , O(660F00,2B,_,_,_,_,_,_  ), 0  , 54 , 6426 , 120, 4  ), // #437
+  INST(Movntps          , ExtMov             , 0                         , O(000F00,2B,_,_,_,_,_,_  ), 0  , 55 , 6435 , 120, 5  ), // #438
+  INST(Movntq           , ExtMov             , 0                         , O(000F00,E7,_,_,_,_,_,_  ), 0  , 56 , 1982 , 121, 75 ), // #439
+  INST(Movntsd          , ExtMov             , 0                         , O(F20F00,2B,_,_,_,_,_,_  ), 0  , 57 , 1989 , 122, 48 ), // #440
+  INST(Movntss          , ExtMov             , 0                         , O(F30F00,2B,_,_,_,_,_,_  ), 0  , 58 , 1997 , 123, 48 ), // #441
+  INST(Movq             , ExtMovq            , O(000F00,6E,_,_,x,_,_,_  ), O(000F00,7E,_,_,x,_,_,_  ), 4  , 59 , 8098 , 124, 80 ), // #442
+  INST(Movq2dq          , ExtRm              , O(F30F00,D6,_,_,_,_,_,_  ), 0                         , 6  , 0  , 2005 , 125, 4  ), // #443
+  INST(Movs             , X86StrMm           , O(000000,A4,_,_,_,_,_,_  ), 0                         , 0  , 0  , 434  , 126, 73 ), // #444
+  INST(Movsd            , ExtMov             , O(F20F00,10,_,_,_,_,_,_  ), O(F20F00,11,_,_,_,_,_,_  ), 5  , 60 , 6450 , 127, 4  ), // #445
+  INST(Movshdup         , ExtRm              , O(F30F00,16,_,_,_,_,_,_  ), 0                         , 6  , 0  , 6457 , 5  , 6  ), // #446
+  INST(Movsldup         , ExtRm              , O(F30F00,12,_,_,_,_,_,_  ), 0                         , 6  , 0  , 6467 , 5  , 6  ), // #447
+  INST(Movss            , ExtMov             , O(F30F00,10,_,_,_,_,_,_  ), O(F30F00,11,_,_,_,_,_,_  ), 6  , 61 , 6477 , 128, 5  ), // #448
+  INST(Movsx            , X86MovsxMovzx      , O(000F00,BE,_,_,x,_,_,_  ), 0                         , 4  , 0  , 2013 , 129, 0  ), // #449
+  INST(Movsxd           , X86Rm              , O(000000,63,_,_,x,_,_,_  ), 0                         , 0  , 0  , 2019 , 130, 0  ), // #450
+  INST(Movupd           , ExtMov             , O(660F00,10,_,_,_,_,_,_  ), O(660F00,11,_,_,_,_,_,_  ), 3  , 62 , 6484 , 111, 4  ), // #451
+  INST(Movups           , ExtMov             , O(000F00,10,_,_,_,_,_,_  ), O(000F00,11,_,_,_,_,_,_  ), 4  , 63 , 6492 , 111, 5  ), // #452
+  INST(Movzx            , X86MovsxMovzx      , O(000F00,B6,_,_,x,_,_,_  ), 0                         , 4  , 0  , 2026 , 129, 0  ), // #453
+  INST(Mpsadbw          , ExtRmi             , O(660F3A,42,_,_,_,_,_,_  ), 0                         , 8  , 0  , 6500 , 8  , 12 ), // #454
+  INST(Mul              , X86M_GPB_MulDiv    , O(000000,F6,4,_,x,_,_,_  ), 0                         , 9  , 0  , 823  , 53 , 1  ), // #455
+  INST(Mulpd            , ExtRm              , O(660F00,59,_,_,_,_,_,_  ), 0                         , 3  , 0  , 6554 , 5  , 4  ), // #456
+  INST(Mulps            , ExtRm              , O(000F00,59,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6561 , 5  , 5  ), // #457
+  INST(Mulsd            , ExtRm              , O(F20F00,59,_,_,_,_,_,_  ), 0                         , 5  , 0  , 6568 , 6  , 4  ), // #458
+  INST(Mulss            , ExtRm              , O(F30F00,59,_,_,_,_,_,_  ), 0                         , 6  , 0  , 6575 , 7  , 5  ), // #459
+  INST(Mulx             , VexRvm_ZDX_Wx      , V(F20F38,F6,_,0,x,_,_,_  ), 0                         , 83 , 0  , 2032 , 131, 83 ), // #460
+  INST(Mwait            , X86Op              , O(000F01,C9,_,_,_,_,_,_  ), 0                         , 21 , 0  , 3201 , 132, 77 ), // #461
+  INST(Mwaitx           , X86Op              , O(000F01,FB,_,_,_,_,_,_  ), 0                         , 21 , 0  , 2037 , 133, 78 ), // #462
+  INST(Neg              , X86M_GPB           , O(000000,F6,3,_,x,_,_,_  ), 0                         , 84 , 0  , 2044 , 134, 1  ), // #463
+  INST(Nop              , X86M_Nop           , O(000000,90,_,_,_,_,_,_  ), 0                         , 0  , 0  , 954  , 135, 0  ), // #464
+  INST(Not              , X86M_GPB           , O(000000,F6,2,_,x,_,_,_  ), 0                         , 1  , 0  , 2048 , 134, 0  ), // #465
+  INST(Or               , X86Arith           , O(000000,08,1,_,x,_,_,_  ), 0                         , 30 , 0  , 3197 , 136, 1  ), // #466
+  INST(Orpd             , ExtRm              , O(660F00,56,_,_,_,_,_,_  ), 0                         , 3  , 0  , 10304, 11 , 4  ), // #467
+  INST(Orps             , ExtRm              , O(000F00,56,_,_,_,_,_,_  ), 0                         , 4  , 0  , 10311, 11 , 5  ), // #468
+  INST(Out              , X86Out             , O(000000,EE,_,_,_,_,_,_  ), O(000000,E6,_,_,_,_,_,_  ), 0  , 64 , 2052 , 137, 0  ), // #469
+  INST(Outs             , X86Outs            , O(000000,6E,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2056 , 138, 0  ), // #470
+  INST(Pabsb            , ExtRm_P            , O(000F38,1C,_,_,_,_,_,_  ), 0                         , 82 , 0  , 6657 , 139, 84 ), // #471
+  INST(Pabsd            , ExtRm_P            , O(000F38,1E,_,_,_,_,_,_  ), 0                         , 82 , 0  , 6664 , 139, 84 ), // #472
+  INST(Pabsw            , ExtRm_P            , O(000F38,1D,_,_,_,_,_,_  ), 0                         , 82 , 0  , 6678 , 139, 84 ), // #473
+  INST(Packssdw         , ExtRm_P            , O(000F00,6B,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6685 , 139, 80 ), // #474
+  INST(Packsswb         , ExtRm_P            , O(000F00,63,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6695 , 139, 80 ), // #475
+  INST(Packusdw         , ExtRm              , O(660F38,2B,_,_,_,_,_,_  ), 0                         , 2  , 0  , 6705 , 5  , 12 ), // #476
+  INST(Packuswb         , ExtRm_P            , O(000F00,67,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6715 , 139, 80 ), // #477
+  INST(Paddb            , ExtRm_P            , O(000F00,FC,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6725 , 139, 80 ), // #478
+  INST(Paddd            , ExtRm_P            , O(000F00,FE,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6732 , 139, 80 ), // #479
+  INST(Paddq            , ExtRm_P            , O(000F00,D4,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6739 , 139, 4  ), // #480
+  INST(Paddsb           , ExtRm_P            , O(000F00,EC,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6746 , 139, 80 ), // #481
+  INST(Paddsw           , ExtRm_P            , O(000F00,ED,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6754 , 139, 80 ), // #482
+  INST(Paddusb          , ExtRm_P            , O(000F00,DC,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6762 , 139, 80 ), // #483
+  INST(Paddusw          , ExtRm_P            , O(000F00,DD,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6771 , 139, 80 ), // #484
+  INST(Paddw            , ExtRm_P            , O(000F00,FD,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6780 , 139, 80 ), // #485
+  INST(Palignr          , ExtRmi_P           , O(000F3A,0F,_,_,_,_,_,_  ), 0                         , 85 , 0  , 6787 , 140, 6  ), // #486
+  INST(Pand             , ExtRm_P            , O(000F00,DB,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6796 , 141, 80 ), // #487
+  INST(Pandn            , ExtRm_P            , O(000F00,DF,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6809 , 142, 80 ), // #488
+  INST(Pause            , X86Op              , O(F30000,90,_,_,_,_,_,_  ), 0                         , 86 , 0  , 3161 , 30 , 0  ), // #489
+  INST(Pavgb            , ExtRm_P            , O(000F00,E0,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6839 , 139, 85 ), // #490
+  INST(Pavgusb          , Ext3dNow           , O(000F0F,BF,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2061 , 143, 50 ), // #491
+  INST(Pavgw            , ExtRm_P            , O(000F00,E3,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6846 , 139, 85 ), // #492
+  INST(Pblendvb         , ExtRm_XMM0         , O(660F38,10,_,_,_,_,_,_  ), 0                         , 2  , 0  , 6862 , 15 , 12 ), // #493
+  INST(Pblendw          , ExtRmi             , O(660F3A,0E,_,_,_,_,_,_  ), 0                         , 8  , 0  , 6872 , 8  , 12 ), // #494
+  INST(Pclmulqdq        , ExtRmi             , O(660F3A,44,_,_,_,_,_,_  ), 0                         , 8  , 0  , 6965 , 8  , 86 ), // #495
+  INST(Pcmpeqb          , ExtRm_P            , O(000F00,74,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6997 , 142, 80 ), // #496
+  INST(Pcmpeqd          , ExtRm_P            , O(000F00,76,_,_,_,_,_,_  ), 0                         , 4  , 0  , 7006 , 142, 80 ), // #497
+  INST(Pcmpeqq          , ExtRm              , O(660F38,29,_,_,_,_,_,_  ), 0                         , 2  , 0  , 7015 , 144, 12 ), // #498
+  INST(Pcmpeqw          , ExtRm_P            , O(000F00,75,_,_,_,_,_,_  ), 0                         , 4  , 0  , 7024 , 142, 80 ), // #499
+  INST(Pcmpestri        , ExtRmi             , O(660F3A,61,_,_,_,_,_,_  ), 0                         , 8  , 0  , 7033 , 145, 87 ), // #500
+  INST(Pcmpestrm        , ExtRmi             , O(660F3A,60,_,_,_,_,_,_  ), 0                         , 8  , 0  , 7044 , 146, 87 ), // #501
+  INST(Pcmpgtb          , ExtRm_P            , O(000F00,64,_,_,_,_,_,_  ), 0                         , 4  , 0  , 7055 , 142, 80 ), // #502
+  INST(Pcmpgtd          , ExtRm_P            , O(000F00,66,_,_,_,_,_,_  ), 0                         , 4  , 0  , 7064 , 142, 80 ), // #503
+  INST(Pcmpgtq          , ExtRm              , O(660F38,37,_,_,_,_,_,_  ), 0                         , 2  , 0  , 7073 , 144, 43 ), // #504
+  INST(Pcmpgtw          , ExtRm_P            , O(000F00,65,_,_,_,_,_,_  ), 0                         , 4  , 0  , 7082 , 142, 80 ), // #505
+  INST(Pcmpistri        , ExtRmi             , O(660F3A,63,_,_,_,_,_,_  ), 0                         , 8  , 0  , 7091 , 147, 87 ), // #506
+  INST(Pcmpistrm        , ExtRmi             , O(660F3A,62,_,_,_,_,_,_  ), 0                         , 8  , 0  , 7102 , 148, 87 ), // #507
+  INST(Pconfig          , X86Op              , O(000F01,C5,_,_,_,_,_,_  ), 0                         , 21 , 0  , 2069 , 30 , 88 ), // #508
+  INST(Pdep             , VexRvm_Wx          , V(F20F38,F5,_,0,x,_,_,_  ), 0                         , 83 , 0  , 2077 , 10 , 83 ), // #509
+  INST(Pext             , VexRvm_Wx          , V(F30F38,F5,_,0,x,_,_,_  ), 0                         , 88 , 0  , 2082 , 10 , 83 ), // #510
+  INST(Pextrb           , ExtExtract         , O(000F3A,14,_,_,_,_,_,_  ), 0                         , 85 , 0  , 7589 , 149, 12 ), // #511
+  INST(Pextrd           , ExtExtract         , O(000F3A,16,_,_,_,_,_,_  ), 0                         , 85 , 0  , 7597 , 57 , 12 ), // #512
+  INST(Pextrq           , ExtExtract         , O(000F3A,16,_,_,1,_,_,_  ), 0                         , 89 , 0  , 7605 , 150, 12 ), // #513
+  INST(Pextrw           , ExtPextrw          , O(000F00,C5,_,_,_,_,_,_  ), O(000F3A,15,_,_,_,_,_,_  ), 4  , 65 , 7613 , 151, 89 ), // #514
+  INST(Pf2id            , Ext3dNow           , O(000F0F,1D,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2087 , 143, 50 ), // #515
+  INST(Pf2iw            , Ext3dNow           , O(000F0F,1C,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2093 , 143, 90 ), // #516
+  INST(Pfacc            , Ext3dNow           , O(000F0F,AE,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2099 , 143, 50 ), // #517
+  INST(Pfadd            , Ext3dNow           , O(000F0F,9E,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2105 , 143, 50 ), // #518
+  INST(Pfcmpeq          , Ext3dNow           , O(000F0F,B0,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2111 , 143, 50 ), // #519
+  INST(Pfcmpge          , Ext3dNow           , O(000F0F,90,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2119 , 143, 50 ), // #520
+  INST(Pfcmpgt          , Ext3dNow           , O(000F0F,A0,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2127 , 143, 50 ), // #521
+  INST(Pfmax            , Ext3dNow           , O(000F0F,A4,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2135 , 143, 50 ), // #522
+  INST(Pfmin            , Ext3dNow           , O(000F0F,94,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2141 , 143, 50 ), // #523
+  INST(Pfmul            , Ext3dNow           , O(000F0F,B4,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2147 , 143, 50 ), // #524
+  INST(Pfnacc           , Ext3dNow           , O(000F0F,8A,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2153 , 143, 90 ), // #525
+  INST(Pfpnacc          , Ext3dNow           , O(000F0F,8E,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2160 , 143, 90 ), // #526
+  INST(Pfrcp            , Ext3dNow           , O(000F0F,96,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2168 , 143, 50 ), // #527
+  INST(Pfrcpit1         , Ext3dNow           , O(000F0F,A6,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2174 , 143, 50 ), // #528
+  INST(Pfrcpit2         , Ext3dNow           , O(000F0F,B6,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2183 , 143, 50 ), // #529
+  INST(Pfrcpv           , Ext3dNow           , O(000F0F,86,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2192 , 143, 91 ), // #530
+  INST(Pfrsqit1         , Ext3dNow           , O(000F0F,A7,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2199 , 143, 50 ), // #531
+  INST(Pfrsqrt          , Ext3dNow           , O(000F0F,97,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2208 , 143, 50 ), // #532
+  INST(Pfrsqrtv         , Ext3dNow           , O(000F0F,87,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2216 , 143, 91 ), // #533
+  INST(Pfsub            , Ext3dNow           , O(000F0F,9A,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2225 , 143, 50 ), // #534
+  INST(Pfsubr           , Ext3dNow           , O(000F0F,AA,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2231 , 143, 50 ), // #535
+  INST(Phaddd           , ExtRm_P            , O(000F38,02,_,_,_,_,_,_  ), 0                         , 82 , 0  , 7692 , 139, 84 ), // #536
+  INST(Phaddsw          , ExtRm_P            , O(000F38,03,_,_,_,_,_,_  ), 0                         , 82 , 0  , 7709 , 139, 84 ), // #537
+  INST(Phaddw           , ExtRm_P            , O(000F38,01,_,_,_,_,_,_  ), 0                         , 82 , 0  , 7778 , 139, 84 ), // #538
+  INST(Phminposuw       , ExtRm              , O(660F38,41,_,_,_,_,_,_  ), 0                         , 2  , 0  , 7804 , 5  , 12 ), // #539
+  INST(Phsubd           , ExtRm_P            , O(000F38,06,_,_,_,_,_,_  ), 0                         , 82 , 0  , 7825 , 139, 84 ), // #540
+  INST(Phsubsw          , ExtRm_P            , O(000F38,07,_,_,_,_,_,_  ), 0                         , 82 , 0  , 7842 , 139, 84 ), // #541
+  INST(Phsubw           , ExtRm_P            , O(000F38,05,_,_,_,_,_,_  ), 0                         , 82 , 0  , 7851 , 139, 84 ), // #542
+  INST(Pi2fd            , Ext3dNow           , O(000F0F,0D,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2238 , 143, 50 ), // #543
+  INST(Pi2fw            , Ext3dNow           , O(000F0F,0C,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2244 , 143, 90 ), // #544
+  INST(Pinsrb           , ExtRmi             , O(660F3A,20,_,_,_,_,_,_  ), 0                         , 8  , 0  , 7868 , 152, 12 ), // #545
+  INST(Pinsrd           , ExtRmi             , O(660F3A,22,_,_,_,_,_,_  ), 0                         , 8  , 0  , 7876 , 153, 12 ), // #546
+  INST(Pinsrq           , ExtRmi             , O(660F3A,22,_,_,1,_,_,_  ), 0                         , 90 , 0  , 7884 , 154, 12 ), // #547
+  INST(Pinsrw           , ExtRmi_P           , O(000F00,C4,_,_,_,_,_,_  ), 0                         , 4  , 0  , 7892 , 155, 85 ), // #548
+  INST(Pmaddubsw        , ExtRm_P            , O(000F38,04,_,_,_,_,_,_  ), 0                         , 82 , 0  , 8062 , 139, 84 ), // #549
+  INST(Pmaddwd          , ExtRm_P            , O(000F00,F5,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8073 , 139, 80 ), // #550
+  INST(Pmaxsb           , ExtRm              , O(660F38,3C,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8104 , 11 , 12 ), // #551
+  INST(Pmaxsd           , ExtRm              , O(660F38,3D,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8112 , 11 , 12 ), // #552
+  INST(Pmaxsw           , ExtRm_P            , O(000F00,EE,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8128 , 141, 85 ), // #553
+  INST(Pmaxub           , ExtRm_P            , O(000F00,DE,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8136 , 141, 85 ), // #554
+  INST(Pmaxud           , ExtRm              , O(660F38,3F,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8144 , 11 , 12 ), // #555
+  INST(Pmaxuw           , ExtRm              , O(660F38,3E,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8160 , 11 , 12 ), // #556
+  INST(Pminsb           , ExtRm              , O(660F38,38,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8168 , 11 , 12 ), // #557
+  INST(Pminsd           , ExtRm              , O(660F38,39,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8176 , 11 , 12 ), // #558
+  INST(Pminsw           , ExtRm_P            , O(000F00,EA,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8192 , 141, 85 ), // #559
+  INST(Pminub           , ExtRm_P            , O(000F00,DA,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8200 , 141, 85 ), // #560
+  INST(Pminud           , ExtRm              , O(660F38,3B,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8208 , 11 , 12 ), // #561
+  INST(Pminuw           , ExtRm              , O(660F38,3A,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8224 , 11 , 12 ), // #562
+  INST(Pmovmskb         , ExtRm_P            , O(000F00,D7,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8302 , 156, 85 ), // #563
+  INST(Pmovsxbd         , ExtRm              , O(660F38,21,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8399 , 7  , 12 ), // #564
+  INST(Pmovsxbq         , ExtRm              , O(660F38,22,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8409 , 157, 12 ), // #565
+  INST(Pmovsxbw         , ExtRm              , O(660F38,20,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8419 , 6  , 12 ), // #566
+  INST(Pmovsxdq         , ExtRm              , O(660F38,25,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8429 , 6  , 12 ), // #567
+  INST(Pmovsxwd         , ExtRm              , O(660F38,23,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8439 , 6  , 12 ), // #568
+  INST(Pmovsxwq         , ExtRm              , O(660F38,24,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8449 , 7  , 12 ), // #569
+  INST(Pmovzxbd         , ExtRm              , O(660F38,31,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8536 , 7  , 12 ), // #570
+  INST(Pmovzxbq         , ExtRm              , O(660F38,32,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8546 , 157, 12 ), // #571
+  INST(Pmovzxbw         , ExtRm              , O(660F38,30,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8556 , 6  , 12 ), // #572
+  INST(Pmovzxdq         , ExtRm              , O(660F38,35,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8566 , 6  , 12 ), // #573
+  INST(Pmovzxwd         , ExtRm              , O(660F38,33,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8576 , 6  , 12 ), // #574
+  INST(Pmovzxwq         , ExtRm              , O(660F38,34,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8586 , 7  , 12 ), // #575
+  INST(Pmuldq           , ExtRm              , O(660F38,28,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8596 , 5  , 12 ), // #576
+  INST(Pmulhrsw         , ExtRm_P            , O(000F38,0B,_,_,_,_,_,_  ), 0                         , 82 , 0  , 8604 , 139, 84 ), // #577
+  INST(Pmulhrw          , Ext3dNow           , O(000F0F,B7,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2250 , 143, 50 ), // #578
+  INST(Pmulhuw          , ExtRm_P            , O(000F00,E4,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8614 , 139, 85 ), // #579
+  INST(Pmulhw           , ExtRm_P            , O(000F00,E5,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8623 , 139, 80 ), // #580
+  INST(Pmulld           , ExtRm              , O(660F38,40,_,_,_,_,_,_  ), 0                         , 2  , 0  , 8631 , 5  , 12 ), // #581
+  INST(Pmullw           , ExtRm_P            , O(000F00,D5,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8647 , 139, 80 ), // #582
+  INST(Pmuludq          , ExtRm_P            , O(000F00,F4,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8670 , 139, 4  ), // #583
+  INST(Pop              , X86Pop             , O(000000,8F,0,_,_,_,_,_  ), O(000000,58,_,_,_,_,_,_  ), 0  , 66 , 2258 , 158, 0  ), // #584
+  INST(Popa             , X86Op              , O(660000,61,_,_,_,_,_,_  ), 0                         , 19 , 0  , 2262 , 78 , 0  ), // #585
+  INST(Popad            , X86Op              , O(000000,61,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2267 , 78 , 0  ), // #586
+  INST(Popcnt           , X86Rm_Raw66H       , O(F30F00,B8,_,_,x,_,_,_  ), 0                         , 6  , 0  , 2273 , 22 , 92 ), // #587
+  INST(Popf             , X86Op              , O(660000,9D,_,_,_,_,_,_  ), 0                         , 19 , 0  , 2280 , 30 , 93 ), // #588
+  INST(Popfd            , X86Op              , O(000000,9D,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2285 , 78 , 93 ), // #589
+  INST(Popfq            , X86Op              , O(000000,9D,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2291 , 159, 93 ), // #590
+  INST(Por              , ExtRm_P            , O(000F00,EB,_,_,_,_,_,_  ), 0                         , 4  , 0  , 8715 , 141, 80 ), // #591
+  INST(Prefetch         , X86M_Only          , O(000F00,0D,0,_,_,_,_,_  ), 0                         , 4  , 0  , 2297 , 31 , 50 ), // #592
+  INST(Prefetchnta      , X86M_Only          , O(000F00,18,0,_,_,_,_,_  ), 0                         , 4  , 0  , 2306 , 31 , 75 ), // #593
+  INST(Prefetcht0       , X86M_Only          , O(000F00,18,1,_,_,_,_,_  ), 0                         , 28 , 0  , 2318 , 31 , 75 ), // #594
+  INST(Prefetcht1       , X86M_Only          , O(000F00,18,2,_,_,_,_,_  ), 0                         , 74 , 0  , 2329 , 31 , 75 ), // #595
+  INST(Prefetcht2       , X86M_Only          , O(000F00,18,3,_,_,_,_,_  ), 0                         , 76 , 0  , 2340 , 31 , 75 ), // #596
+  INST(Prefetchw        , X86M_Only          , O(000F00,0D,1,_,_,_,_,_  ), 0                         , 28 , 0  , 2351 , 31 , 94 ), // #597
+  INST(Prefetchwt1      , X86M_Only          , O(000F00,0D,2,_,_,_,_,_  ), 0                         , 74 , 0  , 2361 , 31 , 95 ), // #598
+  INST(Psadbw           , ExtRm_P            , O(000F00,F6,_,_,_,_,_,_  ), 0                         , 4  , 0  , 4268 , 139, 85 ), // #599
+  INST(Pshufb           , ExtRm_P            , O(000F38,00,_,_,_,_,_,_  ), 0                         , 82 , 0  , 9041 , 139, 84 ), // #600
+  INST(Pshufd           , ExtRmi             , O(660F00,70,_,_,_,_,_,_  ), 0                         , 3  , 0  , 9062 , 8  , 4  ), // #601
+  INST(Pshufhw          , ExtRmi             , O(F30F00,70,_,_,_,_,_,_  ), 0                         , 6  , 0  , 9070 , 8  , 4  ), // #602
+  INST(Pshuflw          , ExtRmi             , O(F20F00,70,_,_,_,_,_,_  ), 0                         , 5  , 0  , 9079 , 8  , 4  ), // #603
+  INST(Pshufw           , ExtRmi_P           , O(000F00,70,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2373 , 160, 75 ), // #604
+  INST(Psignb           , ExtRm_P            , O(000F38,08,_,_,_,_,_,_  ), 0                         , 82 , 0  , 9088 , 139, 84 ), // #605
+  INST(Psignd           , ExtRm_P            , O(000F38,0A,_,_,_,_,_,_  ), 0                         , 82 , 0  , 9096 , 139, 84 ), // #606
+  INST(Psignw           , ExtRm_P            , O(000F38,09,_,_,_,_,_,_  ), 0                         , 82 , 0  , 9104 , 139, 84 ), // #607
+  INST(Pslld            , ExtRmRi_P          , O(000F00,F2,_,_,_,_,_,_  ), O(000F00,72,6,_,_,_,_,_  ), 4  , 67 , 9112 , 161, 80 ), // #608
+  INST(Pslldq           , ExtRmRi            , 0                         , O(660F00,73,7,_,_,_,_,_  ), 0  , 68 , 9119 , 162, 4  ), // #609
+  INST(Psllq            , ExtRmRi_P          , O(000F00,F3,_,_,_,_,_,_  ), O(000F00,73,6,_,_,_,_,_  ), 4  , 69 , 9127 , 161, 80 ), // #610
+  INST(Psllw            , ExtRmRi_P          , O(000F00,F1,_,_,_,_,_,_  ), O(000F00,71,6,_,_,_,_,_  ), 4  , 70 , 9158 , 161, 80 ), // #611
+  INST(Psmash           , X86Op              , O(F30F01,FF,_,_,_,_,_,_  ), 0                         , 81 , 0  , 2380 , 159, 96 ), // #612
+  INST(Psrad            , ExtRmRi_P          , O(000F00,E2,_,_,_,_,_,_  ), O(000F00,72,4,_,_,_,_,_  ), 4  , 71 , 9165 , 161, 80 ), // #613
+  INST(Psraw            , ExtRmRi_P          , O(000F00,E1,_,_,_,_,_,_  ), O(000F00,71,4,_,_,_,_,_  ), 4  , 72 , 9203 , 161, 80 ), // #614
+  INST(Psrld            , ExtRmRi_P          , O(000F00,D2,_,_,_,_,_,_  ), O(000F00,72,2,_,_,_,_,_  ), 4  , 73 , 9210 , 161, 80 ), // #615
+  INST(Psrldq           , ExtRmRi            , 0                         , O(660F00,73,3,_,_,_,_,_  ), 0  , 74 , 9217 , 162, 4  ), // #616
+  INST(Psrlq            , ExtRmRi_P          , O(000F00,D3,_,_,_,_,_,_  ), O(000F00,73,2,_,_,_,_,_  ), 4  , 75 , 9225 , 161, 80 ), // #617
+  INST(Psrlw            , ExtRmRi_P          , O(000F00,D1,_,_,_,_,_,_  ), O(000F00,71,2,_,_,_,_,_  ), 4  , 76 , 9256 , 161, 80 ), // #618
+  INST(Psubb            , ExtRm_P            , O(000F00,F8,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9263 , 142, 80 ), // #619
+  INST(Psubd            , ExtRm_P            , O(000F00,FA,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9270 , 142, 80 ), // #620
+  INST(Psubq            , ExtRm_P            , O(000F00,FB,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9277 , 142, 4  ), // #621
+  INST(Psubsb           , ExtRm_P            , O(000F00,E8,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9284 , 142, 80 ), // #622
+  INST(Psubsw           , ExtRm_P            , O(000F00,E9,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9292 , 142, 80 ), // #623
+  INST(Psubusb          , ExtRm_P            , O(000F00,D8,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9300 , 142, 80 ), // #624
+  INST(Psubusw          , ExtRm_P            , O(000F00,D9,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9309 , 142, 80 ), // #625
+  INST(Psubw            , ExtRm_P            , O(000F00,F9,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9318 , 142, 80 ), // #626
+  INST(Pswapd           , Ext3dNow           , O(000F0F,BB,_,_,_,_,_,_  ), 0                         , 87 , 0  , 2387 , 143, 90 ), // #627
+  INST(Ptest            , ExtRm              , O(660F38,17,_,_,_,_,_,_  ), 0                         , 2  , 0  , 9347 , 5  , 97 ), // #628
+  INST(Ptwrite          , X86M               , O(F30F00,AE,4,_,_,_,_,_  ), 0                         , 91 , 0  , 2394 , 163, 98 ), // #629
+  INST(Punpckhbw        , ExtRm_P            , O(000F00,68,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9430 , 139, 80 ), // #630
+  INST(Punpckhdq        , ExtRm_P            , O(000F00,6A,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9441 , 139, 80 ), // #631
+  INST(Punpckhqdq       , ExtRm              , O(660F00,6D,_,_,_,_,_,_  ), 0                         , 3  , 0  , 9452 , 5  , 4  ), // #632
+  INST(Punpckhwd        , ExtRm_P            , O(000F00,69,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9464 , 139, 80 ), // #633
+  INST(Punpcklbw        , ExtRm_P            , O(000F00,60,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9475 , 139, 80 ), // #634
+  INST(Punpckldq        , ExtRm_P            , O(000F00,62,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9486 , 139, 80 ), // #635
+  INST(Punpcklqdq       , ExtRm              , O(660F00,6C,_,_,_,_,_,_  ), 0                         , 3  , 0  , 9497 , 5  , 4  ), // #636
+  INST(Punpcklwd        , ExtRm_P            , O(000F00,61,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9509 , 139, 80 ), // #637
+  INST(Push             , X86Push            , O(000000,FF,6,_,_,_,_,_  ), O(000000,50,_,_,_,_,_,_  ), 31 , 77 , 2402 , 164, 0  ), // #638
+  INST(Pusha            , X86Op              , O(660000,60,_,_,_,_,_,_  ), 0                         , 19 , 0  , 2407 , 78 , 0  ), // #639
+  INST(Pushad           , X86Op              , O(000000,60,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2413 , 78 , 0  ), // #640
+  INST(Pushf            , X86Op              , O(660000,9C,_,_,_,_,_,_  ), 0                         , 19 , 0  , 2420 , 30 , 99 ), // #641
+  INST(Pushfd           , X86Op              , O(000000,9C,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2426 , 78 , 99 ), // #642
+  INST(Pushfq           , X86Op              , O(000000,9C,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2433 , 159, 99 ), // #643
+  INST(Pvalidate        , X86Op              , O(F20F01,FF,_,_,_,_,_,_  ), 0                         , 92 , 0  , 2440 , 30 , 100), // #644
+  INST(Pxor             , ExtRm_P            , O(000F00,EF,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9520 , 142, 80 ), // #645
+  INST(Rcl              , X86Rot             , O(000000,D0,2,_,x,_,_,_  ), 0                         , 1  , 0  , 2450 , 165, 101), // #646
+  INST(Rcpps            , ExtRm              , O(000F00,53,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9648 , 5  , 5  ), // #647
+  INST(Rcpss            , ExtRm              , O(F30F00,53,_,_,_,_,_,_  ), 0                         , 6  , 0  , 9655 , 7  , 5  ), // #648
+  INST(Rcr              , X86Rot             , O(000000,D0,3,_,x,_,_,_  ), 0                         , 84 , 0  , 2454 , 165, 101), // #649
+  INST(Rdfsbase         , X86M               , O(F30F00,AE,0,_,x,_,_,_  ), 0                         , 6  , 0  , 2458 , 166, 102), // #650
+  INST(Rdgsbase         , X86M               , O(F30F00,AE,1,_,x,_,_,_  ), 0                         , 93 , 0  , 2467 , 166, 102), // #651
+  INST(Rdmsr            , X86Op              , O(000F00,32,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2476 , 167, 103), // #652
+  INST(Rdpid            , X86R_Native        , O(F30F00,C7,7,_,_,_,_,_  ), 0                         , 94 , 0  , 2482 , 168, 104), // #653
+  INST(Rdpkru           , X86Op              , O(000F01,EE,_,_,_,_,_,_  ), 0                         , 21 , 0  , 2488 , 167, 105), // #654
+  INST(Rdpmc            , X86Op              , O(000F00,33,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2495 , 167, 0  ), // #655
+  INST(Rdpru            , X86Op              , O(000F01,FD,_,_,_,_,_,_  ), 0                         , 21 , 0  , 2501 , 167, 106), // #656
+  INST(Rdrand           , X86M               , O(000F00,C7,6,_,x,_,_,_  ), 0                         , 78 , 0  , 2507 , 23 , 107), // #657
+  INST(Rdseed           , X86M               , O(000F00,C7,7,_,x,_,_,_  ), 0                         , 22 , 0  , 2514 , 23 , 108), // #658
+  INST(Rdsspd           , X86M               , O(F30F00,1E,1,_,_,_,_,_  ), 0                         , 93 , 0  , 2521 , 73 , 54 ), // #659
+  INST(Rdsspq           , X86M               , O(F30F00,1E,1,_,_,_,_,_  ), 0                         , 93 , 0  , 2528 , 74 , 54 ), // #660
+  INST(Rdtsc            , X86Op              , O(000F00,31,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2535 , 28 , 109), // #661
+  INST(Rdtscp           , X86Op              , O(000F01,F9,_,_,_,_,_,_  ), 0                         , 21 , 0  , 2541 , 167, 110), // #662
+  INST(Ret              , X86Ret             , O(000000,C2,_,_,_,_,_,_  ), 0                         , 0  , 0  , 3044 , 169, 0  ), // #663
+  INST(Rmpadjust        , X86Op              , O(F30F01,FE,_,_,_,_,_,_  ), 0                         , 81 , 0  , 2548 , 159, 96 ), // #664
+  INST(Rmpupdate        , X86Op              , O(F20F01,FE,_,_,_,_,_,_  ), 0                         , 92 , 0  , 2558 , 159, 96 ), // #665
+  INST(Rol              , X86Rot             , O(000000,D0,0,_,x,_,_,_  ), 0                         , 0  , 0  , 2568 , 165, 111), // #666
+  INST(Ror              , X86Rot             , O(000000,D0,1,_,x,_,_,_  ), 0                         , 30 , 0  , 2572 , 165, 111), // #667
+  INST(Rorx             , VexRmi_Wx          , V(F20F3A,F0,_,0,x,_,_,_  ), 0                         , 95 , 0  , 2576 , 170, 83 ), // #668
+  INST(Roundpd          , ExtRmi             , O(660F3A,09,_,_,_,_,_,_  ), 0                         , 8  , 0  , 9750 , 8  , 12 ), // #669
+  INST(Roundps          , ExtRmi             , O(660F3A,08,_,_,_,_,_,_  ), 0                         , 8  , 0  , 9759 , 8  , 12 ), // #670
+  INST(Roundsd          , ExtRmi             , O(660F3A,0B,_,_,_,_,_,_  ), 0                         , 8  , 0  , 9768 , 36 , 12 ), // #671
+  INST(Roundss          , ExtRmi             , O(660F3A,0A,_,_,_,_,_,_  ), 0                         , 8  , 0  , 9777 , 37 , 12 ), // #672
+  INST(Rsm              , X86Op              , O(000F00,AA,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2581 , 78 , 1  ), // #673
+  INST(Rsqrtps          , ExtRm              , O(000F00,52,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9874 , 5  , 5  ), // #674
+  INST(Rsqrtss          , ExtRm              , O(F30F00,52,_,_,_,_,_,_  ), 0                         , 6  , 0  , 9883 , 7  , 5  ), // #675
+  INST(Rstorssp         , X86M               , O(F30F00,01,5,_,_,_,_,_  ), 0                         , 62 , 0  , 2585 , 32 , 24 ), // #676
+  INST(Sahf             , X86Op              , O(000000,9E,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2594 , 93 , 112), // #677
+  INST(Sal              , X86Rot             , O(000000,D0,4,_,x,_,_,_  ), 0                         , 9  , 0  , 2599 , 165, 1  ), // #678
+  INST(Sar              , X86Rot             , O(000000,D0,7,_,x,_,_,_  ), 0                         , 26 , 0  , 2603 , 165, 1  ), // #679
+  INST(Sarx             , VexRmv_Wx          , V(F30F38,F7,_,0,x,_,_,_  ), 0                         , 88 , 0  , 2607 , 13 , 83 ), // #680
+  INST(Saveprevssp      , X86Op              , O(F30F01,EA,_,_,_,_,_,_  ), 0                         , 81 , 0  , 2612 , 30 , 24 ), // #681
+  INST(Sbb              , X86Arith           , O(000000,18,3,_,x,_,_,_  ), 0                         , 84 , 0  , 2624 , 171, 2  ), // #682
+  INST(Scas             , X86StrRm           , O(000000,AE,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2628 , 172, 36 ), // #683
+  INST(Serialize        , X86Op              , O(000F01,E8,_,_,_,_,_,_  ), 0                         , 21 , 0  , 2633 , 30 , 113), // #684
+  INST(Seta             , X86Set             , O(000F00,97,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2643 , 173, 57 ), // #685
+  INST(Setae            , X86Set             , O(000F00,93,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2648 , 173, 58 ), // #686
+  INST(Setb             , X86Set             , O(000F00,92,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2654 , 173, 58 ), // #687
+  INST(Setbe            , X86Set             , O(000F00,96,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2659 , 173, 57 ), // #688
+  INST(Setc             , X86Set             , O(000F00,92,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2665 , 173, 58 ), // #689
+  INST(Sete             , X86Set             , O(000F00,94,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2670 , 173, 59 ), // #690
+  INST(Setg             , X86Set             , O(000F00,9F,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2675 , 173, 60 ), // #691
+  INST(Setge            , X86Set             , O(000F00,9D,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2680 , 173, 61 ), // #692
+  INST(Setl             , X86Set             , O(000F00,9C,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2686 , 173, 61 ), // #693
+  INST(Setle            , X86Set             , O(000F00,9E,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2691 , 173, 60 ), // #694
+  INST(Setna            , X86Set             , O(000F00,96,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2697 , 173, 57 ), // #695
+  INST(Setnae           , X86Set             , O(000F00,92,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2703 , 173, 58 ), // #696
+  INST(Setnb            , X86Set             , O(000F00,93,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2710 , 173, 58 ), // #697
+  INST(Setnbe           , X86Set             , O(000F00,97,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2716 , 173, 57 ), // #698
+  INST(Setnc            , X86Set             , O(000F00,93,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2723 , 173, 58 ), // #699
+  INST(Setne            , X86Set             , O(000F00,95,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2729 , 173, 59 ), // #700
+  INST(Setng            , X86Set             , O(000F00,9E,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2735 , 173, 60 ), // #701
+  INST(Setnge           , X86Set             , O(000F00,9C,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2741 , 173, 61 ), // #702
+  INST(Setnl            , X86Set             , O(000F00,9D,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2748 , 173, 61 ), // #703
+  INST(Setnle           , X86Set             , O(000F00,9F,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2754 , 173, 60 ), // #704
+  INST(Setno            , X86Set             , O(000F00,91,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2761 , 173, 55 ), // #705
+  INST(Setnp            , X86Set             , O(000F00,9B,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2767 , 173, 62 ), // #706
+  INST(Setns            , X86Set             , O(000F00,99,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2773 , 173, 63 ), // #707
+  INST(Setnz            , X86Set             , O(000F00,95,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2779 , 173, 59 ), // #708
+  INST(Seto             , X86Set             , O(000F00,90,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2785 , 173, 55 ), // #709
+  INST(Setp             , X86Set             , O(000F00,9A,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2790 , 173, 62 ), // #710
+  INST(Setpe            , X86Set             , O(000F00,9A,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2795 , 173, 62 ), // #711
+  INST(Setpo            , X86Set             , O(000F00,9B,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2801 , 173, 62 ), // #712
+  INST(Sets             , X86Set             , O(000F00,98,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2807 , 173, 63 ), // #713
+  INST(Setssbsy         , X86Op              , O(F30F01,E8,_,_,_,_,_,_  ), 0                         , 81 , 0  , 2812 , 30 , 54 ), // #714
+  INST(Setz             , X86Set             , O(000F00,94,_,_,_,_,_,_  ), 0                         , 4  , 0  , 2821 , 173, 59 ), // #715
+  INST(Sfence           , X86Fence           , O(000F00,AE,7,_,_,_,_,_  ), 0                         , 22 , 0  , 2826 , 30 , 75 ), // #716
+  INST(Sgdt             , X86M_Only          , O(000F00,01,0,_,_,_,_,_  ), 0                         , 4  , 0  , 2833 , 31 , 0  ), // #717
+  INST(Sha1msg1         , ExtRm              , O(000F38,C9,_,_,_,_,_,_  ), 0                         , 82 , 0  , 2838 , 5  , 114), // #718
+  INST(Sha1msg2         , ExtRm              , O(000F38,CA,_,_,_,_,_,_  ), 0                         , 82 , 0  , 2847 , 5  , 114), // #719
+  INST(Sha1nexte        , ExtRm              , O(000F38,C8,_,_,_,_,_,_  ), 0                         , 82 , 0  , 2856 , 5  , 114), // #720
+  INST(Sha1rnds4        , ExtRmi             , O(000F3A,CC,_,_,_,_,_,_  ), 0                         , 85 , 0  , 2866 , 8  , 114), // #721
+  INST(Sha256msg1       , ExtRm              , O(000F38,CC,_,_,_,_,_,_  ), 0                         , 82 , 0  , 2876 , 5  , 114), // #722
+  INST(Sha256msg2       , ExtRm              , O(000F38,CD,_,_,_,_,_,_  ), 0                         , 82 , 0  , 2887 , 5  , 114), // #723
+  INST(Sha256rnds2      , ExtRm_XMM0         , O(000F38,CB,_,_,_,_,_,_  ), 0                         , 82 , 0  , 2898 , 15 , 114), // #724
+  INST(Shl              , X86Rot             , O(000000,D0,4,_,x,_,_,_  ), 0                         , 9  , 0  , 2910 , 165, 1  ), // #725
+  INST(Shld             , X86ShldShrd        , O(000F00,A4,_,_,x,_,_,_  ), 0                         , 4  , 0  , 8919 , 174, 1  ), // #726
+  INST(Shlx             , VexRmv_Wx          , V(660F38,F7,_,0,x,_,_,_  ), 0                         , 96 , 0  , 2914 , 13 , 83 ), // #727
+  INST(Shr              , X86Rot             , O(000000,D0,5,_,x,_,_,_  ), 0                         , 61 , 0  , 2919 , 165, 1  ), // #728
+  INST(Shrd             , X86ShldShrd        , O(000F00,AC,_,_,x,_,_,_  ), 0                         , 4  , 0  , 2923 , 174, 1  ), // #729
+  INST(Shrx             , VexRmv_Wx          , V(F20F38,F7,_,0,x,_,_,_  ), 0                         , 83 , 0  , 2928 , 13 , 83 ), // #730
+  INST(Shufpd           , ExtRmi             , O(660F00,C6,_,_,_,_,_,_  ), 0                         , 3  , 0  , 10144, 8  , 4  ), // #731
+  INST(Shufps           , ExtRmi             , O(000F00,C6,_,_,_,_,_,_  ), 0                         , 4  , 0  , 10152, 8  , 5  ), // #732
+  INST(Sidt             , X86M_Only          , O(000F00,01,1,_,_,_,_,_  ), 0                         , 28 , 0  , 2933 , 31 , 0  ), // #733
+  INST(Skinit           , X86Op_xAX          , O(000F01,DE,_,_,_,_,_,_  ), 0                         , 21 , 0  , 2938 , 51 , 115), // #734
+  INST(Sldt             , X86M               , O(000F00,00,0,_,_,_,_,_  ), 0                         , 4  , 0  , 2945 , 175, 0  ), // #735
+  INST(Slwpcb           , VexR_Wx            , V(XOP_M9,12,1,0,x,_,_,_  ), 0                         , 11 , 0  , 2950 , 102, 72 ), // #736
+  INST(Smsw             , X86M               , O(000F00,01,4,_,_,_,_,_  ), 0                         , 97 , 0  , 2957 , 175, 0  ), // #737
+  INST(Sqrtpd           , ExtRm              , O(660F00,51,_,_,_,_,_,_  ), 0                         , 3  , 0  , 10160, 5  , 4  ), // #738
+  INST(Sqrtps           , ExtRm              , O(000F00,51,_,_,_,_,_,_  ), 0                         , 4  , 0  , 9875 , 5  , 5  ), // #739
+  INST(Sqrtsd           , ExtRm              , O(F20F00,51,_,_,_,_,_,_  ), 0                         , 5  , 0  , 10176, 6  , 4  ), // #740
+  INST(Sqrtss           , ExtRm              , O(F30F00,51,_,_,_,_,_,_  ), 0                         , 6  , 0  , 9884 , 7  , 5  ), // #741
+  INST(Stac             , X86Op              , O(000F01,CB,_,_,_,_,_,_  ), 0                         , 21 , 0  , 2962 , 30 , 16 ), // #742
+  INST(Stc              , X86Op              , O(000000,F9,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2967 , 30 , 17 ), // #743
+  INST(Std              , X86Op              , O(000000,FD,_,_,_,_,_,_  ), 0                         , 0  , 0  , 6902 , 30 , 18 ), // #744
+  INST(Stgi             , X86Op              , O(000F01,DC,_,_,_,_,_,_  ), 0                         , 21 , 0  , 2971 , 30 , 115), // #745
+  INST(Sti              , X86Op              , O(000000,FB,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2976 , 30 , 23 ), // #746
+  INST(Stmxcsr          , X86M_Only          , O(000F00,AE,3,_,_,_,_,_  ), 0                         , 76 , 0  , 10192, 96 , 5  ), // #747
+  INST(Stos             , X86StrMr           , O(000000,AA,_,_,_,_,_,_  ), 0                         , 0  , 0  , 2980 , 176, 73 ), // #748
+  INST(Str              , X86M               , O(000F00,00,1,_,_,_,_,_  ), 0                         , 28 , 0  , 2985 , 175, 0  ), // #749
+  INST(Sttilecfg        , AmxCfg             , V(660F38,49,_,0,0,_,_,_  ), 0                         , 96 , 0  , 2989 , 98 , 71 ), // #750
+  INST(Sub              , X86Arith           , O(000000,28,5,_,x,_,_,_  ), 0                         , 61 , 0  , 861  , 171, 1  ), // #751
+  INST(Subpd            , ExtRm              , O(660F00,5C,_,_,_,_,_,_  ), 0                         , 3  , 0  , 4844 , 5  , 4  ), // #752
+  INST(Subps            , ExtRm              , O(000F00,5C,_,_,_,_,_,_  ), 0                         , 4  , 0  , 4856 , 5  , 5  ), // #753
+  INST(Subsd            , ExtRm              , O(F20F00,5C,_,_,_,_,_,_  ), 0                         , 5  , 0  , 5532 , 6  , 4  ), // #754
+  INST(Subss            , ExtRm              , O(F30F00,5C,_,_,_,_,_,_  ), 0                         , 6  , 0  , 5542 , 7  , 5  ), // #755
+  INST(Swapgs           , X86Op              , O(000F01,F8,_,_,_,_,_,_  ), 0                         , 21 , 0  , 2999 , 159, 0  ), // #756
+  INST(Syscall          , X86Op              , O(000F00,05,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3006 , 159, 0  ), // #757
+  INST(Sysenter         , X86Op              , O(000F00,34,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3014 , 30 , 0  ), // #758
+  INST(Sysexit          , X86Op              , O(000F00,35,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3023 , 30 , 0  ), // #759
+  INST(Sysexit64        , X86Op              , O(000F00,35,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3031 , 30 , 0  ), // #760
+  INST(Sysret           , X86Op              , O(000F00,07,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3041 , 159, 0  ), // #761
+  INST(Sysret64         , X86Op              , O(000F00,07,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3048 , 159, 0  ), // #762
+  INST(T1mskc           , VexVm_Wx           , V(XOP_M9,01,7,0,x,_,_,_  ), 0                         , 98 , 0  , 3057 , 14 , 11 ), // #763
+  INST(Tdpbf16ps        , AmxRmv             , V(F30F38,5C,_,0,0,_,_,_  ), 0                         , 88 , 0  , 3064 , 177, 116), // #764
+  INST(Tdpbssd          , AmxRmv             , V(F20F38,5E,_,0,0,_,_,_  ), 0                         , 83 , 0  , 3074 , 177, 117), // #765
+  INST(Tdpbsud          , AmxRmv             , V(F30F38,5E,_,0,0,_,_,_  ), 0                         , 88 , 0  , 3082 , 177, 117), // #766
+  INST(Tdpbusd          , AmxRmv             , V(660F38,5E,_,0,0,_,_,_  ), 0                         , 96 , 0  , 3090 , 177, 117), // #767
+  INST(Tdpbuud          , AmxRmv             , V(000F38,5E,_,0,0,_,_,_  ), 0                         , 10 , 0  , 3098 , 177, 117), // #768
+  INST(Test             , X86Test            , O(000000,84,_,_,x,_,_,_  ), O(000000,F6,_,_,x,_,_,_  ), 0  , 78 , 9348 , 178, 1  ), // #769
+  INST(Tileloadd        , AmxRm              , V(F20F38,4B,_,0,0,_,_,_  ), 0                         , 83 , 0  , 3106 , 179, 71 ), // #770
+  INST(Tileloaddt1      , AmxRm              , V(660F38,4B,_,0,0,_,_,_  ), 0                         , 96 , 0  , 3116 , 179, 71 ), // #771
+  INST(Tilerelease      , VexOpMod           , V(000F38,49,0,0,0,_,_,_  ), 0                         , 10 , 0  , 3128 , 180, 71 ), // #772
+  INST(Tilestored       , AmxMr              , V(F30F38,4B,_,0,0,_,_,_  ), 0                         , 88 , 0  , 3140 , 181, 71 ), // #773
+  INST(Tilezero         , AmxR               , V(F20F38,49,_,0,0,_,_,_  ), 0                         , 83 , 0  , 3151 , 182, 71 ), // #774
+  INST(Tpause           , X86R32_EDX_EAX     , O(660F00,AE,6,_,_,_,_,_  ), 0                         , 25 , 0  , 3160 , 183, 118), // #775
+  INST(Tzcnt            , X86Rm_Raw66H       , O(F30F00,BC,_,_,x,_,_,_  ), 0                         , 6  , 0  , 3167 , 22 , 9  ), // #776
+  INST(Tzmsk            , VexVm_Wx           , V(XOP_M9,01,4,0,x,_,_,_  ), 0                         , 99 , 0  , 3173 , 14 , 11 ), // #777
+  INST(Ucomisd          , ExtRm              , O(660F00,2E,_,_,_,_,_,_  ), 0                         , 3  , 0  , 10245, 6  , 40 ), // #778
+  INST(Ucomiss          , ExtRm              , O(000F00,2E,_,_,_,_,_,_  ), 0                         , 4  , 0  , 10254, 7  , 41 ), // #779
+  INST(Ud0              , X86M               , O(000F00,FF,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3179 , 184, 0  ), // #780
+  INST(Ud1              , X86M               , O(000F00,B9,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3183 , 184, 0  ), // #781
+  INST(Ud2              , X86Op              , O(000F00,0B,_,_,_,_,_,_  ), 0                         , 4  , 0  , 3187 , 30 , 0  ), // #782
+  INST(Umonitor         , X86R_FromM         , O(F30F00,AE,6,_,_,_,_,_  ), 0                         , 24 , 0  , 3191 , 185, 119), // #783
+  INST(Umwait           , X86R32_EDX_EAX     , O(F20F00,AE,6,_,_,_,_,_  ), 0                         , 100, 0  , 3200 , 183, 118), // #784
+  INST(Unpckhpd         , ExtRm              , O(660F00,15,_,_,_,_,_,_  ), 0                         , 3  , 0  , 10263, 5  , 4  ), // #785
+  INST(Unpckhps         , ExtRm              , O(000F00,15,_,_,_,_,_,_  ), 0                         , 4  , 0  , 10273, 5  , 5  ), // #786
+  INST(Unpcklpd         , ExtRm              , O(660F00,14,_,_,_,_,_,_  ), 0                         , 3  , 0  , 10283, 5  , 4  ), // #787
+  INST(Unpcklps         , ExtRm              , O(000F00,14,_,_,_,_,_,_  ), 0                         , 4  , 0  , 10293, 5  , 5  ), // #788
+  INST(V4fmaddps        , VexRm_T1_4X        , E(F20F38,9A,_,2,_,0,2,T4X), 0                         , 101, 0  , 3207 , 186, 120), // #789
+  INST(V4fmaddss        , VexRm_T1_4X        , E(F20F38,9B,_,2,_,0,2,T4X), 0                         , 101, 0  , 3217 , 187, 120), // #790
+  INST(V4fnmaddps       , VexRm_T1_4X        , E(F20F38,AA,_,2,_,0,2,T4X), 0                         , 101, 0  , 3227 , 186, 120), // #791
+  INST(V4fnmaddss       , VexRm_T1_4X        , E(F20F38,AB,_,2,_,0,2,T4X), 0                         , 101, 0  , 3238 , 187, 120), // #792
+  INST(Vaddpd           , VexRvm_Lx          , V(660F00,58,_,x,I,1,4,FV ), 0                         , 102, 0  , 3249 , 188, 121), // #793
+  INST(Vaddps           , VexRvm_Lx          , V(000F00,58,_,x,I,0,4,FV ), 0                         , 103, 0  , 3256 , 189, 121), // #794
+  INST(Vaddsd           , VexRvm             , V(F20F00,58,_,I,I,1,3,T1S), 0                         , 104, 0  , 3263 , 190, 122), // #795
+  INST(Vaddss           , VexRvm             , V(F30F00,58,_,I,I,0,2,T1S), 0                         , 105, 0  , 3270 , 191, 122), // #796
+  INST(Vaddsubpd        , VexRvm_Lx          , V(660F00,D0,_,x,I,_,_,_  ), 0                         , 68 , 0  , 3277 , 192, 123), // #797
+  INST(Vaddsubps        , VexRvm_Lx          , V(F20F00,D0,_,x,I,_,_,_  ), 0                         , 106, 0  , 3287 , 192, 123), // #798
+  INST(Vaesdec          , VexRvm_Lx          , V(660F38,DE,_,x,I,_,4,FVM), 0                         , 107, 0  , 3297 , 193, 124), // #799
+  INST(Vaesdeclast      , VexRvm_Lx          , V(660F38,DF,_,x,I,_,4,FVM), 0                         , 107, 0  , 3305 , 193, 124), // #800
+  INST(Vaesenc          , VexRvm_Lx          , V(660F38,DC,_,x,I,_,4,FVM), 0                         , 107, 0  , 3317 , 193, 124), // #801
+  INST(Vaesenclast      , VexRvm_Lx          , V(660F38,DD,_,x,I,_,4,FVM), 0                         , 107, 0  , 3325 , 193, 124), // #802
+  INST(Vaesimc          , VexRm              , V(660F38,DB,_,0,I,_,_,_  ), 0                         , 96 , 0  , 3337 , 194, 125), // #803
+  INST(Vaeskeygenassist , VexRmi             , V(660F3A,DF,_,0,I,_,_,_  ), 0                         , 72 , 0  , 3345 , 195, 125), // #804
+  INST(Valignd          , VexRvmi_Lx         , E(660F3A,03,_,x,_,0,4,FV ), 0                         , 108, 0  , 3362 , 196, 126), // #805
+  INST(Valignq          , VexRvmi_Lx         , E(660F3A,03,_,x,_,1,4,FV ), 0                         , 109, 0  , 3370 , 197, 126), // #806
+  INST(Vandnpd          , VexRvm_Lx          , V(660F00,55,_,x,I,1,4,FV ), 0                         , 102, 0  , 3378 , 198, 127), // #807
+  INST(Vandnps          , VexRvm_Lx          , V(000F00,55,_,x,I,0,4,FV ), 0                         , 103, 0  , 3386 , 199, 127), // #808
+  INST(Vandpd           , VexRvm_Lx          , V(660F00,54,_,x,I,1,4,FV ), 0                         , 102, 0  , 3394 , 200, 127), // #809
+  INST(Vandps           , VexRvm_Lx          , V(000F00,54,_,x,I,0,4,FV ), 0                         , 103, 0  , 3401 , 201, 127), // #810
+  INST(Vblendmb         , VexRvm_Lx          , E(660F38,66,_,x,_,0,4,FVM), 0                         , 110, 0  , 3408 , 202, 128), // #811
+  INST(Vblendmd         , VexRvm_Lx          , E(660F38,64,_,x,_,0,4,FV ), 0                         , 111, 0  , 3417 , 203, 126), // #812
+  INST(Vblendmpd        , VexRvm_Lx          , E(660F38,65,_,x,_,1,4,FV ), 0                         , 112, 0  , 3426 , 204, 126), // #813
+  INST(Vblendmps        , VexRvm_Lx          , E(660F38,65,_,x,_,0,4,FV ), 0                         , 111, 0  , 3436 , 203, 126), // #814
+  INST(Vblendmq         , VexRvm_Lx          , E(660F38,64,_,x,_,1,4,FV ), 0                         , 112, 0  , 3446 , 204, 126), // #815
+  INST(Vblendmw         , VexRvm_Lx          , E(660F38,66,_,x,_,1,4,FVM), 0                         , 113, 0  , 3455 , 202, 128), // #816
+  INST(Vblendpd         , VexRvmi_Lx         , V(660F3A,0D,_,x,I,_,_,_  ), 0                         , 72 , 0  , 3464 , 205, 123), // #817
+  INST(Vblendps         , VexRvmi_Lx         , V(660F3A,0C,_,x,I,_,_,_  ), 0                         , 72 , 0  , 3473 , 205, 123), // #818
+  INST(Vblendvpd        , VexRvmr_Lx         , V(660F3A,4B,_,x,0,_,_,_  ), 0                         , 72 , 0  , 3482 , 206, 123), // #819
+  INST(Vblendvps        , VexRvmr_Lx         , V(660F3A,4A,_,x,0,_,_,_  ), 0                         , 72 , 0  , 3492 , 206, 123), // #820
+  INST(Vbroadcastf128   , VexRm              , V(660F38,1A,_,1,0,_,_,_  ), 0                         , 114, 0  , 3502 , 207, 123), // #821
+  INST(Vbroadcastf32x2  , VexRm_Lx           , E(660F38,19,_,x,_,0,3,T2 ), 0                         , 115, 0  , 3517 , 208, 129), // #822
+  INST(Vbroadcastf32x4  , VexRm_Lx           , E(660F38,1A,_,x,_,0,4,T4 ), 0                         , 116, 0  , 3533 , 209, 66 ), // #823
+  INST(Vbroadcastf32x8  , VexRm              , E(660F38,1B,_,2,_,0,5,T8 ), 0                         , 117, 0  , 3549 , 210, 64 ), // #824
+  INST(Vbroadcastf64x2  , VexRm_Lx           , E(660F38,1A,_,x,_,1,4,T2 ), 0                         , 118, 0  , 3565 , 209, 129), // #825
+  INST(Vbroadcastf64x4  , VexRm              , E(660F38,1B,_,2,_,1,5,T4 ), 0                         , 119, 0  , 3581 , 210, 66 ), // #826
+  INST(Vbroadcasti128   , VexRm              , V(660F38,5A,_,1,0,_,_,_  ), 0                         , 114, 0  , 3597 , 207, 130), // #827
+  INST(Vbroadcasti32x2  , VexRm_Lx           , E(660F38,59,_,x,_,0,3,T2 ), 0                         , 115, 0  , 3612 , 211, 129), // #828
+  INST(Vbroadcasti32x4  , VexRm_Lx           , E(660F38,5A,_,x,_,0,4,T4 ), 0                         , 116, 0  , 3628 , 209, 126), // #829
+  INST(Vbroadcasti32x8  , VexRm              , E(660F38,5B,_,2,_,0,5,T8 ), 0                         , 117, 0  , 3644 , 210, 64 ), // #830
+  INST(Vbroadcasti64x2  , VexRm_Lx           , E(660F38,5A,_,x,_,1,4,T2 ), 0                         , 118, 0  , 3660 , 209, 129), // #831
+  INST(Vbroadcasti64x4  , VexRm              , E(660F38,5B,_,2,_,1,5,T4 ), 0                         , 119, 0  , 3676 , 210, 66 ), // #832
+  INST(Vbroadcastsd     , VexRm_Lx           , V(660F38,19,_,x,0,1,3,T1S), 0                         , 120, 0  , 3692 , 212, 131), // #833
+  INST(Vbroadcastss     , VexRm_Lx           , V(660F38,18,_,x,0,0,2,T1S), 0                         , 121, 0  , 3705 , 213, 131), // #834
+  INST(Vcmppd           , VexRvmi_Lx         , V(660F00,C2,_,x,I,1,4,FV ), 0                         , 102, 0  , 3718 , 214, 121), // #835
+  INST(Vcmpps           , VexRvmi_Lx         , V(000F00,C2,_,x,I,0,4,FV ), 0                         , 103, 0  , 3725 , 215, 121), // #836
+  INST(Vcmpsd           , VexRvmi            , V(F20F00,C2,_,I,I,1,3,T1S), 0                         , 104, 0  , 3732 , 216, 122), // #837
+  INST(Vcmpss           , VexRvmi            , V(F30F00,C2,_,I,I,0,2,T1S), 0                         , 105, 0  , 3739 , 217, 122), // #838
+  INST(Vcomisd          , VexRm              , V(660F00,2F,_,I,I,1,3,T1S), 0                         , 122, 0  , 3746 , 218, 132), // #839
+  INST(Vcomiss          , VexRm              , V(000F00,2F,_,I,I,0,2,T1S), 0                         , 123, 0  , 3754 , 219, 132), // #840
+  INST(Vcompresspd      , VexMr_Lx           , E(660F38,8A,_,x,_,1,3,T1S), 0                         , 124, 0  , 3762 , 220, 126), // #841
+  INST(Vcompressps      , VexMr_Lx           , E(660F38,8A,_,x,_,0,2,T1S), 0                         , 125, 0  , 3774 , 220, 126), // #842
+  INST(Vcvtdq2pd        , VexRm_Lx           , V(F30F00,E6,_,x,I,0,3,HV ), 0                         , 126, 0  , 3786 , 221, 121), // #843
+  INST(Vcvtdq2ps        , VexRm_Lx           , V(000F00,5B,_,x,I,0,4,FV ), 0                         , 103, 0  , 3796 , 222, 121), // #844
+  INST(Vcvtne2ps2bf16   , VexRvm             , E(F20F38,72,_,_,_,0,_,_  ), 0                         , 127, 0  , 3806 , 203, 133), // #845
+  INST(Vcvtneps2bf16    , VexRm              , E(F30F38,72,_,_,_,0,_,_  ), 0                         , 128, 0  , 3821 , 223, 133), // #846
+  INST(Vcvtpd2dq        , VexRm_Lx           , V(F20F00,E6,_,x,I,1,4,FV ), 0                         , 129, 0  , 3835 , 224, 121), // #847
+  INST(Vcvtpd2ps        , VexRm_Lx           , V(660F00,5A,_,x,I,1,4,FV ), 0                         , 102, 0  , 3845 , 224, 121), // #848
+  INST(Vcvtpd2qq        , VexRm_Lx           , E(660F00,7B,_,x,_,1,4,FV ), 0                         , 130, 0  , 3855 , 225, 129), // #849
+  INST(Vcvtpd2udq       , VexRm_Lx           , E(000F00,79,_,x,_,1,4,FV ), 0                         , 131, 0  , 3865 , 226, 126), // #850
+  INST(Vcvtpd2uqq       , VexRm_Lx           , E(660F00,79,_,x,_,1,4,FV ), 0                         , 130, 0  , 3876 , 225, 129), // #851
+  INST(Vcvtph2ps        , VexRm_Lx           , V(660F38,13,_,x,0,0,3,HVM), 0                         , 132, 0  , 3887 , 227, 134), // #852
+  INST(Vcvtps2dq        , VexRm_Lx           , V(660F00,5B,_,x,I,0,4,FV ), 0                         , 133, 0  , 3897 , 222, 121), // #853
+  INST(Vcvtps2pd        , VexRm_Lx           , V(000F00,5A,_,x,I,0,4,HV ), 0                         , 134, 0  , 3907 , 228, 121), // #854
+  INST(Vcvtps2ph        , VexMri_Lx          , V(660F3A,1D,_,x,0,0,3,HVM), 0                         , 135, 0  , 3917 , 229, 134), // #855
+  INST(Vcvtps2qq        , VexRm_Lx           , E(660F00,7B,_,x,_,0,3,HV ), 0                         , 136, 0  , 3927 , 230, 129), // #856
+  INST(Vcvtps2udq       , VexRm_Lx           , E(000F00,79,_,x,_,0,4,FV ), 0                         , 137, 0  , 3937 , 231, 126), // #857
+  INST(Vcvtps2uqq       , VexRm_Lx           , E(660F00,79,_,x,_,0,3,HV ), 0                         , 136, 0  , 3948 , 230, 129), // #858
+  INST(Vcvtqq2pd        , VexRm_Lx           , E(F30F00,E6,_,x,_,1,4,FV ), 0                         , 138, 0  , 3959 , 225, 129), // #859
+  INST(Vcvtqq2ps        , VexRm_Lx           , E(000F00,5B,_,x,_,1,4,FV ), 0                         , 131, 0  , 3969 , 226, 129), // #860
+  INST(Vcvtsd2si        , VexRm_Wx           , V(F20F00,2D,_,I,x,x,3,T1F), 0                         , 139, 0  , 3979 , 232, 122), // #861
+  INST(Vcvtsd2ss        , VexRvm             , V(F20F00,5A,_,I,I,1,3,T1S), 0                         , 104, 0  , 3989 , 190, 122), // #862
+  INST(Vcvtsd2usi       , VexRm_Wx           , E(F20F00,79,_,I,_,x,3,T1F), 0                         , 140, 0  , 3999 , 233, 66 ), // #863
+  INST(Vcvtsi2sd        , VexRvm_Wx          , V(F20F00,2A,_,I,x,x,2,T1W), 0                         , 141, 0  , 4010 , 234, 122), // #864
+  INST(Vcvtsi2ss        , VexRvm_Wx          , V(F30F00,2A,_,I,x,x,2,T1W), 0                         , 142, 0  , 4020 , 234, 122), // #865
+  INST(Vcvtss2sd        , VexRvm             , V(F30F00,5A,_,I,I,0,2,T1S), 0                         , 105, 0  , 4030 , 235, 122), // #866
+  INST(Vcvtss2si        , VexRm_Wx           , V(F30F00,2D,_,I,x,x,2,T1F), 0                         , 143, 0  , 4040 , 236, 122), // #867
+  INST(Vcvtss2usi       , VexRm_Wx           , E(F30F00,79,_,I,_,x,2,T1F), 0                         , 144, 0  , 4050 , 237, 66 ), // #868
+  INST(Vcvttpd2dq       , VexRm_Lx           , V(660F00,E6,_,x,I,1,4,FV ), 0                         , 102, 0  , 4061 , 238, 121), // #869
+  INST(Vcvttpd2qq       , VexRm_Lx           , E(660F00,7A,_,x,_,1,4,FV ), 0                         , 130, 0  , 4072 , 239, 126), // #870
+  INST(Vcvttpd2udq      , VexRm_Lx           , E(000F00,78,_,x,_,1,4,FV ), 0                         , 131, 0  , 4083 , 240, 126), // #871
+  INST(Vcvttpd2uqq      , VexRm_Lx           , E(660F00,78,_,x,_,1,4,FV ), 0                         , 130, 0  , 4095 , 239, 129), // #872
+  INST(Vcvttps2dq       , VexRm_Lx           , V(F30F00,5B,_,x,I,0,4,FV ), 0                         , 145, 0  , 4107 , 241, 121), // #873
+  INST(Vcvttps2qq       , VexRm_Lx           , E(660F00,7A,_,x,_,0,3,HV ), 0                         , 136, 0  , 4118 , 242, 129), // #874
+  INST(Vcvttps2udq      , VexRm_Lx           , E(000F00,78,_,x,_,0,4,FV ), 0                         , 137, 0  , 4129 , 243, 126), // #875
+  INST(Vcvttps2uqq      , VexRm_Lx           , E(660F00,78,_,x,_,0,3,HV ), 0                         , 136, 0  , 4141 , 242, 129), // #876
+  INST(Vcvttsd2si       , VexRm_Wx           , V(F20F00,2C,_,I,x,x,3,T1F), 0                         , 139, 0  , 4153 , 244, 122), // #877
+  INST(Vcvttsd2usi      , VexRm_Wx           , E(F20F00,78,_,I,_,x,3,T1F), 0                         , 140, 0  , 4164 , 245, 66 ), // #878
+  INST(Vcvttss2si       , VexRm_Wx           , V(F30F00,2C,_,I,x,x,2,T1F), 0                         , 143, 0  , 4176 , 246, 122), // #879
+  INST(Vcvttss2usi      , VexRm_Wx           , E(F30F00,78,_,I,_,x,2,T1F), 0                         , 144, 0  , 4187 , 247, 66 ), // #880
+  INST(Vcvtudq2pd       , VexRm_Lx           , E(F30F00,7A,_,x,_,0,3,HV ), 0                         , 146, 0  , 4199 , 248, 126), // #881
+  INST(Vcvtudq2ps       , VexRm_Lx           , E(F20F00,7A,_,x,_,0,4,FV ), 0                         , 147, 0  , 4210 , 231, 126), // #882
+  INST(Vcvtuqq2pd       , VexRm_Lx           , E(F30F00,7A,_,x,_,1,4,FV ), 0                         , 138, 0  , 4221 , 225, 129), // #883
+  INST(Vcvtuqq2ps       , VexRm_Lx           , E(F20F00,7A,_,x,_,1,4,FV ), 0                         , 148, 0  , 4232 , 226, 129), // #884
+  INST(Vcvtusi2sd       , VexRvm_Wx          , E(F20F00,7B,_,I,_,x,2,T1W), 0                         , 149, 0  , 4243 , 249, 66 ), // #885
+  INST(Vcvtusi2ss       , VexRvm_Wx          , E(F30F00,7B,_,I,_,x,2,T1W), 0                         , 150, 0  , 4254 , 249, 66 ), // #886
+  INST(Vdbpsadbw        , VexRvmi_Lx         , E(660F3A,42,_,x,_,0,4,FVM), 0                         , 151, 0  , 4265 , 250, 128), // #887
+  INST(Vdivpd           , VexRvm_Lx          , V(660F00,5E,_,x,I,1,4,FV ), 0                         , 102, 0  , 4275 , 188, 121), // #888
+  INST(Vdivps           , VexRvm_Lx          , V(000F00,5E,_,x,I,0,4,FV ), 0                         , 103, 0  , 4282 , 189, 121), // #889
+  INST(Vdivsd           , VexRvm             , V(F20F00,5E,_,I,I,1,3,T1S), 0                         , 104, 0  , 4289 , 190, 122), // #890
+  INST(Vdivss           , VexRvm             , V(F30F00,5E,_,I,I,0,2,T1S), 0                         , 105, 0  , 4296 , 191, 122), // #891
+  INST(Vdpbf16ps        , VexRvm             , E(F30F38,52,_,_,_,0,_,_  ), 0                         , 128, 0  , 4303 , 203, 133), // #892
+  INST(Vdppd            , VexRvmi_Lx         , V(660F3A,41,_,x,I,_,_,_  ), 0                         , 72 , 0  , 4313 , 251, 123), // #893
+  INST(Vdpps            , VexRvmi_Lx         , V(660F3A,40,_,x,I,_,_,_  ), 0                         , 72 , 0  , 4319 , 205, 123), // #894
+  INST(Verr             , X86M_NoSize        , O(000F00,00,4,_,_,_,_,_  ), 0                         , 97 , 0  , 4325 , 101, 10 ), // #895
+  INST(Verw             , X86M_NoSize        , O(000F00,00,5,_,_,_,_,_  ), 0                         , 75 , 0  , 4330 , 101, 10 ), // #896
+  INST(Vexp2pd          , VexRm              , E(660F38,C8,_,2,_,1,4,FV ), 0                         , 152, 0  , 4335 , 252, 135), // #897
+  INST(Vexp2ps          , VexRm              , E(660F38,C8,_,2,_,0,4,FV ), 0                         , 153, 0  , 4343 , 253, 135), // #898
+  INST(Vexpandpd        , VexRm_Lx           , E(660F38,88,_,x,_,1,3,T1S), 0                         , 124, 0  , 4351 , 254, 126), // #899
+  INST(Vexpandps        , VexRm_Lx           , E(660F38,88,_,x,_,0,2,T1S), 0                         , 125, 0  , 4361 , 254, 126), // #900
+  INST(Vextractf128     , VexMri             , V(660F3A,19,_,1,0,_,_,_  ), 0                         , 154, 0  , 4371 , 255, 123), // #901
+  INST(Vextractf32x4    , VexMri_Lx          , E(660F3A,19,_,x,_,0,4,T4 ), 0                         , 155, 0  , 4384 , 256, 126), // #902
+  INST(Vextractf32x8    , VexMri             , E(660F3A,1B,_,2,_,0,5,T8 ), 0                         , 156, 0  , 4398 , 257, 64 ), // #903
+  INST(Vextractf64x2    , VexMri_Lx          , E(660F3A,19,_,x,_,1,4,T2 ), 0                         , 157, 0  , 4412 , 256, 129), // #904
+  INST(Vextractf64x4    , VexMri             , E(660F3A,1B,_,2,_,1,5,T4 ), 0                         , 158, 0  , 4426 , 257, 66 ), // #905
+  INST(Vextracti128     , VexMri             , V(660F3A,39,_,1,0,_,_,_  ), 0                         , 154, 0  , 4440 , 255, 130), // #906
+  INST(Vextracti32x4    , VexMri_Lx          , E(660F3A,39,_,x,_,0,4,T4 ), 0                         , 155, 0  , 4453 , 256, 126), // #907
+  INST(Vextracti32x8    , VexMri             , E(660F3A,3B,_,2,_,0,5,T8 ), 0                         , 156, 0  , 4467 , 257, 64 ), // #908
+  INST(Vextracti64x2    , VexMri_Lx          , E(660F3A,39,_,x,_,1,4,T2 ), 0                         , 157, 0  , 4481 , 256, 129), // #909
+  INST(Vextracti64x4    , VexMri             , E(660F3A,3B,_,2,_,1,5,T4 ), 0                         , 158, 0  , 4495 , 257, 66 ), // #910
+  INST(Vextractps       , VexMri             , V(660F3A,17,_,0,I,I,2,T1S), 0                         , 159, 0  , 4509 , 258, 122), // #911
+  INST(Vfixupimmpd      , VexRvmi_Lx         , E(660F3A,54,_,x,_,1,4,FV ), 0                         , 109, 0  , 4520 , 259, 126), // #912
+  INST(Vfixupimmps      , VexRvmi_Lx         , E(660F3A,54,_,x,_,0,4,FV ), 0                         , 108, 0  , 4532 , 260, 126), // #913
+  INST(Vfixupimmsd      , VexRvmi            , E(660F3A,55,_,I,_,1,3,T1S), 0                         , 160, 0  , 4544 , 261, 66 ), // #914
+  INST(Vfixupimmss      , VexRvmi            , E(660F3A,55,_,I,_,0,2,T1S), 0                         , 161, 0  , 4556 , 262, 66 ), // #915
+  INST(Vfmadd132pd      , VexRvm_Lx          , V(660F38,98,_,x,1,1,4,FV ), 0                         , 162, 0  , 4568 , 188, 136), // #916
+  INST(Vfmadd132ps      , VexRvm_Lx          , V(660F38,98,_,x,0,0,4,FV ), 0                         , 163, 0  , 4580 , 189, 136), // #917
+  INST(Vfmadd132sd      , VexRvm             , V(660F38,99,_,I,1,1,3,T1S), 0                         , 164, 0  , 4592 , 190, 137), // #918
+  INST(Vfmadd132ss      , VexRvm             , V(660F38,99,_,I,0,0,2,T1S), 0                         , 121, 0  , 4604 , 191, 137), // #919
+  INST(Vfmadd213pd      , VexRvm_Lx          , V(660F38,A8,_,x,1,1,4,FV ), 0                         , 162, 0  , 4616 , 188, 136), // #920
+  INST(Vfmadd213ps      , VexRvm_Lx          , V(660F38,A8,_,x,0,0,4,FV ), 0                         , 163, 0  , 4628 , 189, 136), // #921
+  INST(Vfmadd213sd      , VexRvm             , V(660F38,A9,_,I,1,1,3,T1S), 0                         , 164, 0  , 4640 , 190, 137), // #922
+  INST(Vfmadd213ss      , VexRvm             , V(660F38,A9,_,I,0,0,2,T1S), 0                         , 121, 0  , 4652 , 191, 137), // #923
+  INST(Vfmadd231pd      , VexRvm_Lx          , V(660F38,B8,_,x,1,1,4,FV ), 0                         , 162, 0  , 4664 , 188, 136), // #924
+  INST(Vfmadd231ps      , VexRvm_Lx          , V(660F38,B8,_,x,0,0,4,FV ), 0                         , 163, 0  , 4676 , 189, 136), // #925
+  INST(Vfmadd231sd      , VexRvm             , V(660F38,B9,_,I,1,1,3,T1S), 0                         , 164, 0  , 4688 , 190, 137), // #926
+  INST(Vfmadd231ss      , VexRvm             , V(660F38,B9,_,I,0,0,2,T1S), 0                         , 121, 0  , 4700 , 191, 137), // #927
+  INST(Vfmaddpd         , Fma4_Lx            , V(660F3A,69,_,x,x,_,_,_  ), 0                         , 72 , 0  , 4712 , 263, 138), // #928
+  INST(Vfmaddps         , Fma4_Lx            , V(660F3A,68,_,x,x,_,_,_  ), 0                         , 72 , 0  , 4721 , 263, 138), // #929
+  INST(Vfmaddsd         , Fma4               , V(660F3A,6B,_,0,x,_,_,_  ), 0                         , 72 , 0  , 4730 , 264, 138), // #930
+  INST(Vfmaddss         , Fma4               , V(660F3A,6A,_,0,x,_,_,_  ), 0                         , 72 , 0  , 4739 , 265, 138), // #931
+  INST(Vfmaddsub132pd   , VexRvm_Lx          , V(660F38,96,_,x,1,1,4,FV ), 0                         , 162, 0  , 4748 , 188, 136), // #932
+  INST(Vfmaddsub132ps   , VexRvm_Lx          , V(660F38,96,_,x,0,0,4,FV ), 0                         , 163, 0  , 4763 , 189, 136), // #933
+  INST(Vfmaddsub213pd   , VexRvm_Lx          , V(660F38,A6,_,x,1,1,4,FV ), 0                         , 162, 0  , 4778 , 188, 136), // #934
+  INST(Vfmaddsub213ps   , VexRvm_Lx          , V(660F38,A6,_,x,0,0,4,FV ), 0                         , 163, 0  , 4793 , 189, 136), // #935
+  INST(Vfmaddsub231pd   , VexRvm_Lx          , V(660F38,B6,_,x,1,1,4,FV ), 0                         , 162, 0  , 4808 , 188, 136), // #936
+  INST(Vfmaddsub231ps   , VexRvm_Lx          , V(660F38,B6,_,x,0,0,4,FV ), 0                         , 163, 0  , 4823 , 189, 136), // #937
+  INST(Vfmaddsubpd      , Fma4_Lx            , V(660F3A,5D,_,x,x,_,_,_  ), 0                         , 72 , 0  , 4838 , 263, 138), // #938
+  INST(Vfmaddsubps      , Fma4_Lx            , V(660F3A,5C,_,x,x,_,_,_  ), 0                         , 72 , 0  , 4850 , 263, 138), // #939
+  INST(Vfmsub132pd      , VexRvm_Lx          , V(660F38,9A,_,x,1,1,4,FV ), 0                         , 162, 0  , 4862 , 188, 136), // #940
+  INST(Vfmsub132ps      , VexRvm_Lx          , V(660F38,9A,_,x,0,0,4,FV ), 0                         , 163, 0  , 4874 , 189, 136), // #941
+  INST(Vfmsub132sd      , VexRvm             , V(660F38,9B,_,I,1,1,3,T1S), 0                         , 164, 0  , 4886 , 190, 137), // #942
+  INST(Vfmsub132ss      , VexRvm             , V(660F38,9B,_,I,0,0,2,T1S), 0                         , 121, 0  , 4898 , 191, 137), // #943
+  INST(Vfmsub213pd      , VexRvm_Lx          , V(660F38,AA,_,x,1,1,4,FV ), 0                         , 162, 0  , 4910 , 188, 136), // #944
+  INST(Vfmsub213ps      , VexRvm_Lx          , V(660F38,AA,_,x,0,0,4,FV ), 0                         , 163, 0  , 4922 , 189, 136), // #945
+  INST(Vfmsub213sd      , VexRvm             , V(660F38,AB,_,I,1,1,3,T1S), 0                         , 164, 0  , 4934 , 190, 137), // #946
+  INST(Vfmsub213ss      , VexRvm             , V(660F38,AB,_,I,0,0,2,T1S), 0                         , 121, 0  , 4946 , 191, 137), // #947
+  INST(Vfmsub231pd      , VexRvm_Lx          , V(660F38,BA,_,x,1,1,4,FV ), 0                         , 162, 0  , 4958 , 188, 136), // #948
+  INST(Vfmsub231ps      , VexRvm_Lx          , V(660F38,BA,_,x,0,0,4,FV ), 0                         , 163, 0  , 4970 , 189, 136), // #949
+  INST(Vfmsub231sd      , VexRvm             , V(660F38,BB,_,I,1,1,3,T1S), 0                         , 164, 0  , 4982 , 190, 137), // #950
+  INST(Vfmsub231ss      , VexRvm             , V(660F38,BB,_,I,0,0,2,T1S), 0                         , 121, 0  , 4994 , 191, 137), // #951
+  INST(Vfmsubadd132pd   , VexRvm_Lx          , V(660F38,97,_,x,1,1,4,FV ), 0                         , 162, 0  , 5006 , 188, 136), // #952
+  INST(Vfmsubadd132ps   , VexRvm_Lx          , V(660F38,97,_,x,0,0,4,FV ), 0                         , 163, 0  , 5021 , 189, 136), // #953
+  INST(Vfmsubadd213pd   , VexRvm_Lx          , V(660F38,A7,_,x,1,1,4,FV ), 0                         , 162, 0  , 5036 , 188, 136), // #954
+  INST(Vfmsubadd213ps   , VexRvm_Lx          , V(660F38,A7,_,x,0,0,4,FV ), 0                         , 163, 0  , 5051 , 189, 136), // #955
+  INST(Vfmsubadd231pd   , VexRvm_Lx          , V(660F38,B7,_,x,1,1,4,FV ), 0                         , 162, 0  , 5066 , 188, 136), // #956
+  INST(Vfmsubadd231ps   , VexRvm_Lx          , V(660F38,B7,_,x,0,0,4,FV ), 0                         , 163, 0  , 5081 , 189, 136), // #957
+  INST(Vfmsubaddpd      , Fma4_Lx            , V(660F3A,5F,_,x,x,_,_,_  ), 0                         , 72 , 0  , 5096 , 263, 138), // #958
+  INST(Vfmsubaddps      , Fma4_Lx            , V(660F3A,5E,_,x,x,_,_,_  ), 0                         , 72 , 0  , 5108 , 263, 138), // #959
+  INST(Vfmsubpd         , Fma4_Lx            , V(660F3A,6D,_,x,x,_,_,_  ), 0                         , 72 , 0  , 5120 , 263, 138), // #960
+  INST(Vfmsubps         , Fma4_Lx            , V(660F3A,6C,_,x,x,_,_,_  ), 0                         , 72 , 0  , 5129 , 263, 138), // #961
+  INST(Vfmsubsd         , Fma4               , V(660F3A,6F,_,0,x,_,_,_  ), 0                         , 72 , 0  , 5138 , 264, 138), // #962
+  INST(Vfmsubss         , Fma4               , V(660F3A,6E,_,0,x,_,_,_  ), 0                         , 72 , 0  , 5147 , 265, 138), // #963
+  INST(Vfnmadd132pd     , VexRvm_Lx          , V(660F38,9C,_,x,1,1,4,FV ), 0                         , 162, 0  , 5156 , 188, 136), // #964
+  INST(Vfnmadd132ps     , VexRvm_Lx          , V(660F38,9C,_,x,0,0,4,FV ), 0                         , 163, 0  , 5169 , 189, 136), // #965
+  INST(Vfnmadd132sd     , VexRvm             , V(660F38,9D,_,I,1,1,3,T1S), 0                         , 164, 0  , 5182 , 190, 137), // #966
+  INST(Vfnmadd132ss     , VexRvm             , V(660F38,9D,_,I,0,0,2,T1S), 0                         , 121, 0  , 5195 , 191, 137), // #967
+  INST(Vfnmadd213pd     , VexRvm_Lx          , V(660F38,AC,_,x,1,1,4,FV ), 0                         , 162, 0  , 5208 , 188, 136), // #968
+  INST(Vfnmadd213ps     , VexRvm_Lx          , V(660F38,AC,_,x,0,0,4,FV ), 0                         , 163, 0  , 5221 , 189, 136), // #969
+  INST(Vfnmadd213sd     , VexRvm             , V(660F38,AD,_,I,1,1,3,T1S), 0                         , 164, 0  , 5234 , 190, 137), // #970
+  INST(Vfnmadd213ss     , VexRvm             , V(660F38,AD,_,I,0,0,2,T1S), 0                         , 121, 0  , 5247 , 191, 137), // #971
+  INST(Vfnmadd231pd     , VexRvm_Lx          , V(660F38,BC,_,x,1,1,4,FV ), 0                         , 162, 0  , 5260 , 188, 136), // #972
+  INST(Vfnmadd231ps     , VexRvm_Lx          , V(660F38,BC,_,x,0,0,4,FV ), 0                         , 163, 0  , 5273 , 189, 136), // #973
+  INST(Vfnmadd231sd     , VexRvm             , V(660F38,BC,_,I,1,1,3,T1S), 0                         , 164, 0  , 5286 , 190, 137), // #974
+  INST(Vfnmadd231ss     , VexRvm             , V(660F38,BC,_,I,0,0,2,T1S), 0                         , 121, 0  , 5299 , 191, 137), // #975
+  INST(Vfnmaddpd        , Fma4_Lx            , V(660F3A,79,_,x,x,_,_,_  ), 0                         , 72 , 0  , 5312 , 263, 138), // #976
+  INST(Vfnmaddps        , Fma4_Lx            , V(660F3A,78,_,x,x,_,_,_  ), 0                         , 72 , 0  , 5322 , 263, 138), // #977
+  INST(Vfnmaddsd        , Fma4               , V(660F3A,7B,_,0,x,_,_,_  ), 0                         , 72 , 0  , 5332 , 264, 138), // #978
+  INST(Vfnmaddss        , Fma4               , V(660F3A,7A,_,0,x,_,_,_  ), 0                         , 72 , 0  , 5342 , 265, 138), // #979
+  INST(Vfnmsub132pd     , VexRvm_Lx          , V(660F38,9E,_,x,1,1,4,FV ), 0                         , 162, 0  , 5352 , 188, 136), // #980
+  INST(Vfnmsub132ps     , VexRvm_Lx          , V(660F38,9E,_,x,0,0,4,FV ), 0                         , 163, 0  , 5365 , 189, 136), // #981
+  INST(Vfnmsub132sd     , VexRvm             , V(660F38,9F,_,I,1,1,3,T1S), 0                         , 164, 0  , 5378 , 190, 137), // #982
+  INST(Vfnmsub132ss     , VexRvm             , V(660F38,9F,_,I,0,0,2,T1S), 0                         , 121, 0  , 5391 , 191, 137), // #983
+  INST(Vfnmsub213pd     , VexRvm_Lx          , V(660F38,AE,_,x,1,1,4,FV ), 0                         , 162, 0  , 5404 , 188, 136), // #984
+  INST(Vfnmsub213ps     , VexRvm_Lx          , V(660F38,AE,_,x,0,0,4,FV ), 0                         , 163, 0  , 5417 , 189, 136), // #985
+  INST(Vfnmsub213sd     , VexRvm             , V(660F38,AF,_,I,1,1,3,T1S), 0                         , 164, 0  , 5430 , 190, 137), // #986
+  INST(Vfnmsub213ss     , VexRvm             , V(660F38,AF,_,I,0,0,2,T1S), 0                         , 121, 0  , 5443 , 191, 137), // #987
+  INST(Vfnmsub231pd     , VexRvm_Lx          , V(660F38,BE,_,x,1,1,4,FV ), 0                         , 162, 0  , 5456 , 188, 136), // #988
+  INST(Vfnmsub231ps     , VexRvm_Lx          , V(660F38,BE,_,x,0,0,4,FV ), 0                         , 163, 0  , 5469 , 189, 136), // #989
+  INST(Vfnmsub231sd     , VexRvm             , V(660F38,BF,_,I,1,1,3,T1S), 0                         , 164, 0  , 5482 , 190, 137), // #990
+  INST(Vfnmsub231ss     , VexRvm             , V(660F38,BF,_,I,0,0,2,T1S), 0                         , 121, 0  , 5495 , 191, 137), // #991
+  INST(Vfnmsubpd        , Fma4_Lx            , V(660F3A,7D,_,x,x,_,_,_  ), 0                         , 72 , 0  , 5508 , 263, 138), // #992
+  INST(Vfnmsubps        , Fma4_Lx            , V(660F3A,7C,_,x,x,_,_,_  ), 0                         , 72 , 0  , 5518 , 263, 138), // #993
+  INST(Vfnmsubsd        , Fma4               , V(660F3A,7F,_,0,x,_,_,_  ), 0                         , 72 , 0  , 5528 , 264, 138), // #994
+  INST(Vfnmsubss        , Fma4               , V(660F3A,7E,_,0,x,_,_,_  ), 0                         , 72 , 0  , 5538 , 265, 138), // #995
+  INST(Vfpclasspd       , VexRmi_Lx          , E(660F3A,66,_,x,_,1,4,FV ), 0                         , 109, 0  , 5548 , 266, 129), // #996
+  INST(Vfpclassps       , VexRmi_Lx          , E(660F3A,66,_,x,_,0,4,FV ), 0                         , 108, 0  , 5559 , 267, 129), // #997
+  INST(Vfpclasssd       , VexRmi_Lx          , E(660F3A,67,_,I,_,1,3,T1S), 0                         , 160, 0  , 5570 , 268, 64 ), // #998
+  INST(Vfpclassss       , VexRmi_Lx          , E(660F3A,67,_,I,_,0,2,T1S), 0                         , 161, 0  , 5581 , 269, 64 ), // #999
+  INST(Vfrczpd          , VexRm_Lx           , V(XOP_M9,81,_,x,0,_,_,_  ), 0                         , 77 , 0  , 5592 , 270, 139), // #1000
+  INST(Vfrczps          , VexRm_Lx           , V(XOP_M9,80,_,x,0,_,_,_  ), 0                         , 77 , 0  , 5600 , 270, 139), // #1001
+  INST(Vfrczsd          , VexRm              , V(XOP_M9,83,_,0,0,_,_,_  ), 0                         , 77 , 0  , 5608 , 271, 139), // #1002
+  INST(Vfrczss          , VexRm              , V(XOP_M9,82,_,0,0,_,_,_  ), 0                         , 77 , 0  , 5616 , 272, 139), // #1003
+  INST(Vgatherdpd       , VexRmvRm_VM        , V(660F38,92,_,x,1,_,_,_  ), V(660F38,92,_,x,_,1,3,T1S), 165, 79 , 5624 , 273, 140), // #1004
+  INST(Vgatherdps       , VexRmvRm_VM        , V(660F38,92,_,x,0,_,_,_  ), V(660F38,92,_,x,_,0,2,T1S), 96 , 80 , 5635 , 274, 140), // #1005
+  INST(Vgatherpf0dpd    , VexM_VM            , E(660F38,C6,1,2,_,1,3,T1S), 0                         , 166, 0  , 5646 , 275, 141), // #1006
+  INST(Vgatherpf0dps    , VexM_VM            , E(660F38,C6,1,2,_,0,2,T1S), 0                         , 167, 0  , 5660 , 276, 141), // #1007
+  INST(Vgatherpf0qpd    , VexM_VM            , E(660F38,C7,1,2,_,1,3,T1S), 0                         , 166, 0  , 5674 , 277, 141), // #1008
+  INST(Vgatherpf0qps    , VexM_VM            , E(660F38,C7,1,2,_,0,2,T1S), 0                         , 167, 0  , 5688 , 277, 141), // #1009
+  INST(Vgatherpf1dpd    , VexM_VM            , E(660F38,C6,2,2,_,1,3,T1S), 0                         , 168, 0  , 5702 , 275, 141), // #1010
+  INST(Vgatherpf1dps    , VexM_VM            , E(660F38,C6,2,2,_,0,2,T1S), 0                         , 169, 0  , 5716 , 276, 141), // #1011
+  INST(Vgatherpf1qpd    , VexM_VM            , E(660F38,C7,2,2,_,1,3,T1S), 0                         , 168, 0  , 5730 , 277, 141), // #1012
+  INST(Vgatherpf1qps    , VexM_VM            , E(660F38,C7,2,2,_,0,2,T1S), 0                         , 169, 0  , 5744 , 277, 141), // #1013
+  INST(Vgatherqpd       , VexRmvRm_VM        , V(660F38,93,_,x,1,_,_,_  ), V(660F38,93,_,x,_,1,3,T1S), 165, 81 , 5758 , 278, 140), // #1014
+  INST(Vgatherqps       , VexRmvRm_VM        , V(660F38,93,_,x,0,_,_,_  ), V(660F38,93,_,x,_,0,2,T1S), 96 , 82 , 5769 , 279, 140), // #1015
+  INST(Vgetexppd        , VexRm_Lx           , E(660F38,42,_,x,_,1,4,FV ), 0                         , 112, 0  , 5780 , 239, 126), // #1016
+  INST(Vgetexpps        , VexRm_Lx           , E(660F38,42,_,x,_,0,4,FV ), 0                         , 111, 0  , 5790 , 243, 126), // #1017
+  INST(Vgetexpsd        , VexRvm             , E(660F38,43,_,I,_,1,3,T1S), 0                         , 124, 0  , 5800 , 280, 66 ), // #1018
+  INST(Vgetexpss        , VexRvm             , E(660F38,43,_,I,_,0,2,T1S), 0                         , 125, 0  , 5810 , 281, 66 ), // #1019
+  INST(Vgetmantpd       , VexRmi_Lx          , E(660F3A,26,_,x,_,1,4,FV ), 0                         , 109, 0  , 5820 , 282, 126), // #1020
+  INST(Vgetmantps       , VexRmi_Lx          , E(660F3A,26,_,x,_,0,4,FV ), 0                         , 108, 0  , 5831 , 283, 126), // #1021
+  INST(Vgetmantsd       , VexRvmi            , E(660F3A,27,_,I,_,1,3,T1S), 0                         , 160, 0  , 5842 , 261, 66 ), // #1022
+  INST(Vgetmantss       , VexRvmi            , E(660F3A,27,_,I,_,0,2,T1S), 0                         , 161, 0  , 5853 , 262, 66 ), // #1023
+  INST(Vgf2p8affineinvqb, VexRvmi_Lx         , V(660F3A,CF,_,x,1,1,4,FV ), 0                         , 170, 0  , 5864 , 284, 142), // #1024
+  INST(Vgf2p8affineqb   , VexRvmi_Lx         , V(660F3A,CE,_,x,1,1,4,FV ), 0                         , 170, 0  , 5882 , 284, 142), // #1025
+  INST(Vgf2p8mulb       , VexRvm_Lx          , V(660F38,CF,_,x,0,0,4,FV ), 0                         , 163, 0  , 5897 , 285, 142), // #1026
+  INST(Vhaddpd          , VexRvm_Lx          , V(660F00,7C,_,x,I,_,_,_  ), 0                         , 68 , 0  , 5908 , 192, 123), // #1027
+  INST(Vhaddps          , VexRvm_Lx          , V(F20F00,7C,_,x,I,_,_,_  ), 0                         , 106, 0  , 5916 , 192, 123), // #1028
+  INST(Vhsubpd          , VexRvm_Lx          , V(660F00,7D,_,x,I,_,_,_  ), 0                         , 68 , 0  , 5924 , 192, 123), // #1029
+  INST(Vhsubps          , VexRvm_Lx          , V(F20F00,7D,_,x,I,_,_,_  ), 0                         , 106, 0  , 5932 , 192, 123), // #1030
+  INST(Vinsertf128      , VexRvmi            , V(660F3A,18,_,1,0,_,_,_  ), 0                         , 154, 0  , 5940 , 286, 123), // #1031
+  INST(Vinsertf32x4     , VexRvmi_Lx         , E(660F3A,18,_,x,_,0,4,T4 ), 0                         , 155, 0  , 5952 , 287, 126), // #1032
+  INST(Vinsertf32x8     , VexRvmi            , E(660F3A,1A,_,2,_,0,5,T8 ), 0                         , 156, 0  , 5965 , 288, 64 ), // #1033
+  INST(Vinsertf64x2     , VexRvmi_Lx         , E(660F3A,18,_,x,_,1,4,T2 ), 0                         , 157, 0  , 5978 , 287, 129), // #1034
+  INST(Vinsertf64x4     , VexRvmi            , E(660F3A,1A,_,2,_,1,5,T4 ), 0                         , 158, 0  , 5991 , 288, 66 ), // #1035
+  INST(Vinserti128      , VexRvmi            , V(660F3A,38,_,1,0,_,_,_  ), 0                         , 154, 0  , 6004 , 286, 130), // #1036
+  INST(Vinserti32x4     , VexRvmi_Lx         , E(660F3A,38,_,x,_,0,4,T4 ), 0                         , 155, 0  , 6016 , 287, 126), // #1037
+  INST(Vinserti32x8     , VexRvmi            , E(660F3A,3A,_,2,_,0,5,T8 ), 0                         , 156, 0  , 6029 , 288, 64 ), // #1038
+  INST(Vinserti64x2     , VexRvmi_Lx         , E(660F3A,38,_,x,_,1,4,T2 ), 0                         , 157, 0  , 6042 , 287, 129), // #1039
+  INST(Vinserti64x4     , VexRvmi            , E(660F3A,3A,_,2,_,1,5,T4 ), 0                         , 158, 0  , 6055 , 288, 66 ), // #1040
+  INST(Vinsertps        , VexRvmi            , V(660F3A,21,_,0,I,0,2,T1S), 0                         , 159, 0  , 6068 , 289, 122), // #1041
+  INST(Vlddqu           , VexRm_Lx           , V(F20F00,F0,_,x,I,_,_,_  ), 0                         , 106, 0  , 6078 , 290, 123), // #1042
+  INST(Vldmxcsr         , VexM               , V(000F00,AE,2,0,I,_,_,_  ), 0                         , 171, 0  , 6085 , 291, 123), // #1043
+  INST(Vmaskmovdqu      , VexRm_ZDI          , V(660F00,F7,_,0,I,_,_,_  ), 0                         , 68 , 0  , 6094 , 292, 123), // #1044
+  INST(Vmaskmovpd       , VexRvmMvr_Lx       , V(660F38,2D,_,x,0,_,_,_  ), V(660F38,2F,_,x,0,_,_,_  ), 96 , 83 , 6106 , 293, 123), // #1045
+  INST(Vmaskmovps       , VexRvmMvr_Lx       , V(660F38,2C,_,x,0,_,_,_  ), V(660F38,2E,_,x,0,_,_,_  ), 96 , 84 , 6117 , 293, 123), // #1046
+  INST(Vmaxpd           , VexRvm_Lx          , V(660F00,5F,_,x,I,1,4,FV ), 0                         , 102, 0  , 6128 , 294, 121), // #1047
+  INST(Vmaxps           , VexRvm_Lx          , V(000F00,5F,_,x,I,0,4,FV ), 0                         , 103, 0  , 6135 , 295, 121), // #1048
+  INST(Vmaxsd           , VexRvm             , V(F20F00,5F,_,I,I,1,3,T1S), 0                         , 104, 0  , 6142 , 296, 121), // #1049
+  INST(Vmaxss           , VexRvm             , V(F30F00,5F,_,I,I,0,2,T1S), 0                         , 105, 0  , 6149 , 235, 121), // #1050
+  INST(Vmcall           , X86Op              , O(000F01,C1,_,_,_,_,_,_  ), 0                         , 21 , 0  , 6156 , 30 , 56 ), // #1051
+  INST(Vmclear          , X86M_Only          , O(660F00,C7,6,_,_,_,_,_  ), 0                         , 25 , 0  , 6163 , 32 , 56 ), // #1052
+  INST(Vmfunc           , X86Op              , O(000F01,D4,_,_,_,_,_,_  ), 0                         , 21 , 0  , 6171 , 30 , 56 ), // #1053
+  INST(Vminpd           , VexRvm_Lx          , V(660F00,5D,_,x,I,1,4,FV ), 0                         , 102, 0  , 6178 , 294, 121), // #1054
+  INST(Vminps           , VexRvm_Lx          , V(000F00,5D,_,x,I,0,4,FV ), 0                         , 103, 0  , 6185 , 295, 121), // #1055
+  INST(Vminsd           , VexRvm             , V(F20F00,5D,_,I,I,1,3,T1S), 0                         , 104, 0  , 6192 , 296, 121), // #1056
+  INST(Vminss           , VexRvm             , V(F30F00,5D,_,I,I,0,2,T1S), 0                         , 105, 0  , 6199 , 235, 121), // #1057
+  INST(Vmlaunch         , X86Op              , O(000F01,C2,_,_,_,_,_,_  ), 0                         , 21 , 0  , 6206 , 30 , 56 ), // #1058
+  INST(Vmload           , X86Op_xAX          , O(000F01,DA,_,_,_,_,_,_  ), 0                         , 21 , 0  , 6215 , 297, 22 ), // #1059
+  INST(Vmmcall          , X86Op              , O(000F01,D9,_,_,_,_,_,_  ), 0                         , 21 , 0  , 6222 , 30 , 22 ), // #1060
+  INST(Vmovapd          , VexRmMr_Lx         , V(660F00,28,_,x,I,1,4,FVM), V(660F00,29,_,x,I,1,4,FVM), 172, 85 , 6230 , 298, 121), // #1061
+  INST(Vmovaps          , VexRmMr_Lx         , V(000F00,28,_,x,I,0,4,FVM), V(000F00,29,_,x,I,0,4,FVM), 173, 86 , 6238 , 298, 121), // #1062
+  INST(Vmovd            , VexMovdMovq        , V(660F00,6E,_,0,0,0,2,T1S), V(660F00,7E,_,0,0,0,2,T1S), 174, 87 , 6246 , 299, 122), // #1063
+  INST(Vmovddup         , VexRm_Lx           , V(F20F00,12,_,x,I,1,3,DUP), 0                         , 175, 0  , 6252 , 300, 121), // #1064
+  INST(Vmovdqa          , VexRmMr_Lx         , V(660F00,6F,_,x,I,_,_,_  ), V(660F00,7F,_,x,I,_,_,_  ), 68 , 88 , 6261 , 301, 123), // #1065
+  INST(Vmovdqa32        , VexRmMr_Lx         , E(660F00,6F,_,x,_,0,4,FVM), E(660F00,7F,_,x,_,0,4,FVM), 176, 89 , 6269 , 302, 126), // #1066
+  INST(Vmovdqa64        , VexRmMr_Lx         , E(660F00,6F,_,x,_,1,4,FVM), E(660F00,7F,_,x,_,1,4,FVM), 177, 90 , 6279 , 302, 126), // #1067
+  INST(Vmovdqu          , VexRmMr_Lx         , V(F30F00,6F,_,x,I,_,_,_  ), V(F30F00,7F,_,x,I,_,_,_  ), 178, 91 , 6289 , 301, 123), // #1068
+  INST(Vmovdqu16        , VexRmMr_Lx         , E(F20F00,6F,_,x,_,1,4,FVM), E(F20F00,7F,_,x,_,1,4,FVM), 179, 92 , 6297 , 302, 128), // #1069
+  INST(Vmovdqu32        , VexRmMr_Lx         , E(F30F00,6F,_,x,_,0,4,FVM), E(F30F00,7F,_,x,_,0,4,FVM), 180, 93 , 6307 , 302, 126), // #1070
+  INST(Vmovdqu64        , VexRmMr_Lx         , E(F30F00,6F,_,x,_,1,4,FVM), E(F30F00,7F,_,x,_,1,4,FVM), 181, 94 , 6317 , 302, 126), // #1071
+  INST(Vmovdqu8         , VexRmMr_Lx         , E(F20F00,6F,_,x,_,0,4,FVM), E(F20F00,7F,_,x,_,0,4,FVM), 182, 95 , 6327 , 302, 128), // #1072
+  INST(Vmovhlps         , VexRvm             , V(000F00,12,_,0,I,0,_,_  ), 0                         , 71 , 0  , 6336 , 303, 122), // #1073
+  INST(Vmovhpd          , VexRvmMr           , V(660F00,16,_,0,I,1,3,T1S), V(660F00,17,_,0,I,1,3,T1S), 122, 96 , 6345 , 304, 122), // #1074
+  INST(Vmovhps          , VexRvmMr           , V(000F00,16,_,0,I,0,3,T2 ), V(000F00,17,_,0,I,0,3,T2 ), 183, 97 , 6353 , 304, 122), // #1075
+  INST(Vmovlhps         , VexRvm             , V(000F00,16,_,0,I,0,_,_  ), 0                         , 71 , 0  , 6361 , 303, 122), // #1076
+  INST(Vmovlpd          , VexRvmMr           , V(660F00,12,_,0,I,1,3,T1S), V(660F00,13,_,0,I,1,3,T1S), 122, 98 , 6370 , 304, 122), // #1077
+  INST(Vmovlps          , VexRvmMr           , V(000F00,12,_,0,I,0,3,T2 ), V(000F00,13,_,0,I,0,3,T2 ), 183, 99 , 6378 , 304, 122), // #1078
+  INST(Vmovmskpd        , VexRm_Lx           , V(660F00,50,_,x,I,_,_,_  ), 0                         , 68 , 0  , 6386 , 305, 123), // #1079
+  INST(Vmovmskps        , VexRm_Lx           , V(000F00,50,_,x,I,_,_,_  ), 0                         , 71 , 0  , 6396 , 305, 123), // #1080
+  INST(Vmovntdq         , VexMr_Lx           , V(660F00,E7,_,x,I,0,4,FVM), 0                         , 184, 0  , 6406 , 306, 121), // #1081
+  INST(Vmovntdqa        , VexRm_Lx           , V(660F38,2A,_,x,I,0,4,FVM), 0                         , 107, 0  , 6415 , 307, 131), // #1082
+  INST(Vmovntpd         , VexMr_Lx           , V(660F00,2B,_,x,I,1,4,FVM), 0                         , 172, 0  , 6425 , 306, 121), // #1083
+  INST(Vmovntps         , VexMr_Lx           , V(000F00,2B,_,x,I,0,4,FVM), 0                         , 173, 0  , 6434 , 306, 121), // #1084
+  INST(Vmovq            , VexMovdMovq        , V(660F00,6E,_,0,I,1,3,T1S), V(660F00,7E,_,0,I,1,3,T1S), 122, 100, 6443 , 308, 122), // #1085
+  INST(Vmovsd           , VexMovssMovsd      , V(F20F00,10,_,I,I,1,3,T1S), V(F20F00,11,_,I,I,1,3,T1S), 104, 101, 6449 , 309, 122), // #1086
+  INST(Vmovshdup        , VexRm_Lx           , V(F30F00,16,_,x,I,0,4,FVM), 0                         , 185, 0  , 6456 , 310, 121), // #1087
+  INST(Vmovsldup        , VexRm_Lx           , V(F30F00,12,_,x,I,0,4,FVM), 0                         , 185, 0  , 6466 , 310, 121), // #1088
+  INST(Vmovss           , VexMovssMovsd      , V(F30F00,10,_,I,I,0,2,T1S), V(F30F00,11,_,I,I,0,2,T1S), 105, 102, 6476 , 311, 122), // #1089
+  INST(Vmovupd          , VexRmMr_Lx         , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 172, 103, 6483 , 298, 121), // #1090
+  INST(Vmovups          , VexRmMr_Lx         , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 173, 104, 6491 , 298, 121), // #1091
+  INST(Vmpsadbw         , VexRvmi_Lx         , V(660F3A,42,_,x,I,_,_,_  ), 0                         , 72 , 0  , 6499 , 205, 143), // #1092
+  INST(Vmptrld          , X86M_Only          , O(000F00,C7,6,_,_,_,_,_  ), 0                         , 78 , 0  , 6508 , 32 , 56 ), // #1093
+  INST(Vmptrst          , X86M_Only          , O(000F00,C7,7,_,_,_,_,_  ), 0                         , 22 , 0  , 6516 , 32 , 56 ), // #1094
+  INST(Vmread           , X86Mr_NoSize       , O(000F00,78,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6524 , 312, 56 ), // #1095
+  INST(Vmresume         , X86Op              , O(000F01,C3,_,_,_,_,_,_  ), 0                         , 21 , 0  , 6531 , 30 , 56 ), // #1096
+  INST(Vmrun            , X86Op_xAX          , O(000F01,D8,_,_,_,_,_,_  ), 0                         , 21 , 0  , 6540 , 297, 22 ), // #1097
+  INST(Vmsave           , X86Op_xAX          , O(000F01,DB,_,_,_,_,_,_  ), 0                         , 21 , 0  , 6546 , 297, 22 ), // #1098
+  INST(Vmulpd           , VexRvm_Lx          , V(660F00,59,_,x,I,1,4,FV ), 0                         , 102, 0  , 6553 , 188, 121), // #1099
+  INST(Vmulps           , VexRvm_Lx          , V(000F00,59,_,x,I,0,4,FV ), 0                         , 103, 0  , 6560 , 189, 121), // #1100
+  INST(Vmulsd           , VexRvm_Lx          , V(F20F00,59,_,I,I,1,3,T1S), 0                         , 104, 0  , 6567 , 190, 122), // #1101
+  INST(Vmulss           , VexRvm_Lx          , V(F30F00,59,_,I,I,0,2,T1S), 0                         , 105, 0  , 6574 , 191, 122), // #1102
+  INST(Vmwrite          , X86Rm_NoSize       , O(000F00,79,_,_,_,_,_,_  ), 0                         , 4  , 0  , 6581 , 313, 56 ), // #1103
+  INST(Vmxon            , X86M_Only          , O(F30F00,C7,6,_,_,_,_,_  ), 0                         , 24 , 0  , 6589 , 32 , 56 ), // #1104
+  INST(Vorpd            , VexRvm_Lx          , V(660F00,56,_,x,I,1,4,FV ), 0                         , 102, 0  , 6595 , 200, 127), // #1105
+  INST(Vorps            , VexRvm_Lx          , V(000F00,56,_,x,I,0,4,FV ), 0                         , 103, 0  , 6601 , 201, 127), // #1106
+  INST(Vp2intersectd    , VexRvm_Lx_2xK      , E(F20F38,68,_,_,_,0,4,FV ), 0                         , 186, 0  , 6607 , 314, 144), // #1107
+  INST(Vp2intersectq    , VexRvm_Lx_2xK      , E(F20F38,68,_,_,_,1,4,FV ), 0                         , 187, 0  , 6621 , 315, 144), // #1108
+  INST(Vp4dpwssd        , VexRm_T1_4X        , E(F20F38,52,_,2,_,0,2,T4X), 0                         , 101, 0  , 6635 , 186, 145), // #1109
+  INST(Vp4dpwssds       , VexRm_T1_4X        , E(F20F38,53,_,2,_,0,2,T4X), 0                         , 101, 0  , 6645 , 186, 145), // #1110
+  INST(Vpabsb           , VexRm_Lx           , V(660F38,1C,_,x,I,_,4,FVM), 0                         , 107, 0  , 6656 , 310, 146), // #1111
+  INST(Vpabsd           , VexRm_Lx           , V(660F38,1E,_,x,I,0,4,FV ), 0                         , 163, 0  , 6663 , 310, 131), // #1112
+  INST(Vpabsq           , VexRm_Lx           , E(660F38,1F,_,x,_,1,4,FV ), 0                         , 112, 0  , 6670 , 254, 126), // #1113
+  INST(Vpabsw           , VexRm_Lx           , V(660F38,1D,_,x,I,_,4,FVM), 0                         , 107, 0  , 6677 , 310, 146), // #1114
+  INST(Vpackssdw        , VexRvm_Lx          , V(660F00,6B,_,x,I,0,4,FV ), 0                         , 133, 0  , 6684 , 199, 146), // #1115
+  INST(Vpacksswb        , VexRvm_Lx          , V(660F00,63,_,x,I,I,4,FVM), 0                         , 184, 0  , 6694 , 285, 146), // #1116
+  INST(Vpackusdw        , VexRvm_Lx          , V(660F38,2B,_,x,I,0,4,FV ), 0                         , 163, 0  , 6704 , 199, 146), // #1117
+  INST(Vpackuswb        , VexRvm_Lx          , V(660F00,67,_,x,I,I,4,FVM), 0                         , 184, 0  , 6714 , 285, 146), // #1118
+  INST(Vpaddb           , VexRvm_Lx          , V(660F00,FC,_,x,I,I,4,FVM), 0                         , 184, 0  , 6724 , 285, 146), // #1119
+  INST(Vpaddd           , VexRvm_Lx          , V(660F00,FE,_,x,I,0,4,FV ), 0                         , 133, 0  , 6731 , 199, 131), // #1120
+  INST(Vpaddq           , VexRvm_Lx          , V(660F00,D4,_,x,I,1,4,FV ), 0                         , 102, 0  , 6738 , 198, 131), // #1121
+  INST(Vpaddsb          , VexRvm_Lx          , V(660F00,EC,_,x,I,I,4,FVM), 0                         , 184, 0  , 6745 , 285, 146), // #1122
+  INST(Vpaddsw          , VexRvm_Lx          , V(660F00,ED,_,x,I,I,4,FVM), 0                         , 184, 0  , 6753 , 285, 146), // #1123
+  INST(Vpaddusb         , VexRvm_Lx          , V(660F00,DC,_,x,I,I,4,FVM), 0                         , 184, 0  , 6761 , 285, 146), // #1124
+  INST(Vpaddusw         , VexRvm_Lx          , V(660F00,DD,_,x,I,I,4,FVM), 0                         , 184, 0  , 6770 , 285, 146), // #1125
+  INST(Vpaddw           , VexRvm_Lx          , V(660F00,FD,_,x,I,I,4,FVM), 0                         , 184, 0  , 6779 , 285, 146), // #1126
+  INST(Vpalignr         , VexRvmi_Lx         , V(660F3A,0F,_,x,I,I,4,FVM), 0                         , 188, 0  , 6786 , 284, 146), // #1127
+  INST(Vpand            , VexRvm_Lx          , V(660F00,DB,_,x,I,_,_,_  ), 0                         , 68 , 0  , 6795 , 316, 143), // #1128
+  INST(Vpandd           , VexRvm_Lx          , E(660F00,DB,_,x,_,0,4,FV ), 0                         , 189, 0  , 6801 , 317, 126), // #1129
+  INST(Vpandn           , VexRvm_Lx          , V(660F00,DF,_,x,I,_,_,_  ), 0                         , 68 , 0  , 6808 , 318, 143), // #1130
+  INST(Vpandnd          , VexRvm_Lx          , E(660F00,DF,_,x,_,0,4,FV ), 0                         , 189, 0  , 6815 , 319, 126), // #1131
+  INST(Vpandnq          , VexRvm_Lx          , E(660F00,DF,_,x,_,1,4,FV ), 0                         , 130, 0  , 6823 , 320, 126), // #1132
+  INST(Vpandq           , VexRvm_Lx          , E(660F00,DB,_,x,_,1,4,FV ), 0                         , 130, 0  , 6831 , 321, 126), // #1133
+  INST(Vpavgb           , VexRvm_Lx          , V(660F00,E0,_,x,I,I,4,FVM), 0                         , 184, 0  , 6838 , 285, 146), // #1134
+  INST(Vpavgw           , VexRvm_Lx          , V(660F00,E3,_,x,I,I,4,FVM), 0                         , 184, 0  , 6845 , 285, 146), // #1135
+  INST(Vpblendd         , VexRvmi_Lx         , V(660F3A,02,_,x,0,_,_,_  ), 0                         , 72 , 0  , 6852 , 205, 130), // #1136
+  INST(Vpblendvb        , VexRvmr            , V(660F3A,4C,_,x,0,_,_,_  ), 0                         , 72 , 0  , 6861 , 206, 143), // #1137
+  INST(Vpblendw         , VexRvmi_Lx         , V(660F3A,0E,_,x,I,_,_,_  ), 0                         , 72 , 0  , 6871 , 205, 143), // #1138
+  INST(Vpbroadcastb     , VexRm_Lx_Bcst      , V(660F38,78,_,x,0,0,0,T1S), E(660F38,7A,_,x,0,0,0,T1S), 190, 105, 6880 , 322, 147), // #1139
+  INST(Vpbroadcastd     , VexRm_Lx_Bcst      , V(660F38,58,_,x,0,0,2,T1S), E(660F38,7C,_,x,0,0,0,T1S), 121, 106, 6893 , 323, 140), // #1140
+  INST(Vpbroadcastmb2d  , VexRm_Lx           , E(F30F38,3A,_,x,_,0,_,_  ), 0                         , 128, 0  , 6906 , 324, 148), // #1141
+  INST(Vpbroadcastmb2q  , VexRm_Lx           , E(F30F38,2A,_,x,_,1,_,_  ), 0                         , 191, 0  , 6922 , 324, 148), // #1142
+  INST(Vpbroadcastq     , VexRm_Lx_Bcst      , V(660F38,59,_,x,0,1,3,T1S), E(660F38,7C,_,x,0,1,0,T1S), 120, 107, 6938 , 325, 140), // #1143
+  INST(Vpbroadcastw     , VexRm_Lx_Bcst      , V(660F38,79,_,x,0,0,1,T1S), E(660F38,7B,_,x,0,0,0,T1S), 192, 108, 6951 , 326, 147), // #1144
+  INST(Vpclmulqdq       , VexRvmi_Lx         , V(660F3A,44,_,x,I,_,4,FVM), 0                         , 188, 0  , 6964 , 327, 149), // #1145
+  INST(Vpcmov           , VexRvrmRvmr_Lx     , V(XOP_M8,A2,_,x,x,_,_,_  ), 0                         , 193, 0  , 6975 , 263, 139), // #1146
+  INST(Vpcmpb           , VexRvmi_Lx         , E(660F3A,3F,_,x,_,0,4,FVM), 0                         , 151, 0  , 6982 , 328, 128), // #1147
+  INST(Vpcmpd           , VexRvmi_Lx         , E(660F3A,1F,_,x,_,0,4,FV ), 0                         , 108, 0  , 6989 , 329, 126), // #1148
+  INST(Vpcmpeqb         , VexRvm_Lx          , V(660F00,74,_,x,I,I,4,FV ), 0                         , 133, 0  , 6996 , 330, 146), // #1149
+  INST(Vpcmpeqd         , VexRvm_Lx          , V(660F00,76,_,x,I,0,4,FVM), 0                         , 184, 0  , 7005 , 331, 131), // #1150
+  INST(Vpcmpeqq         , VexRvm_Lx          , V(660F38,29,_,x,I,1,4,FVM), 0                         , 194, 0  , 7014 , 332, 131), // #1151
+  INST(Vpcmpeqw         , VexRvm_Lx          , V(660F00,75,_,x,I,I,4,FV ), 0                         , 133, 0  , 7023 , 330, 146), // #1152
+  INST(Vpcmpestri       , VexRmi             , V(660F3A,61,_,0,I,_,_,_  ), 0                         , 72 , 0  , 7032 , 333, 150), // #1153
+  INST(Vpcmpestrm       , VexRmi             , V(660F3A,60,_,0,I,_,_,_  ), 0                         , 72 , 0  , 7043 , 334, 150), // #1154
+  INST(Vpcmpgtb         , VexRvm_Lx          , V(660F00,64,_,x,I,I,4,FV ), 0                         , 133, 0  , 7054 , 330, 146), // #1155
+  INST(Vpcmpgtd         , VexRvm_Lx          , V(660F00,66,_,x,I,0,4,FVM), 0                         , 184, 0  , 7063 , 331, 131), // #1156
+  INST(Vpcmpgtq         , VexRvm_Lx          , V(660F38,37,_,x,I,1,4,FVM), 0                         , 194, 0  , 7072 , 332, 131), // #1157
+  INST(Vpcmpgtw         , VexRvm_Lx          , V(660F00,65,_,x,I,I,4,FV ), 0                         , 133, 0  , 7081 , 330, 146), // #1158
+  INST(Vpcmpistri       , VexRmi             , V(660F3A,63,_,0,I,_,_,_  ), 0                         , 72 , 0  , 7090 , 335, 150), // #1159
+  INST(Vpcmpistrm       , VexRmi             , V(660F3A,62,_,0,I,_,_,_  ), 0                         , 72 , 0  , 7101 , 336, 150), // #1160
+  INST(Vpcmpq           , VexRvmi_Lx         , E(660F3A,1F,_,x,_,1,4,FV ), 0                         , 109, 0  , 7112 , 337, 126), // #1161
+  INST(Vpcmpub          , VexRvmi_Lx         , E(660F3A,3E,_,x,_,0,4,FVM), 0                         , 151, 0  , 7119 , 328, 128), // #1162
+  INST(Vpcmpud          , VexRvmi_Lx         , E(660F3A,1E,_,x,_,0,4,FV ), 0                         , 108, 0  , 7127 , 329, 126), // #1163
+  INST(Vpcmpuq          , VexRvmi_Lx         , E(660F3A,1E,_,x,_,1,4,FV ), 0                         , 109, 0  , 7135 , 337, 126), // #1164
+  INST(Vpcmpuw          , VexRvmi_Lx         , E(660F3A,3E,_,x,_,1,4,FVM), 0                         , 195, 0  , 7143 , 337, 128), // #1165
+  INST(Vpcmpw           , VexRvmi_Lx         , E(660F3A,3F,_,x,_,1,4,FVM), 0                         , 195, 0  , 7151 , 337, 128), // #1166
+  INST(Vpcomb           , VexRvmi            , V(XOP_M8,CC,_,0,0,_,_,_  ), 0                         , 193, 0  , 7158 , 251, 139), // #1167
+  INST(Vpcomd           , VexRvmi            , V(XOP_M8,CE,_,0,0,_,_,_  ), 0                         , 193, 0  , 7165 , 251, 139), // #1168
+  INST(Vpcompressb      , VexMr_Lx           , E(660F38,63,_,x,_,0,0,T1S), 0                         , 196, 0  , 7172 , 220, 151), // #1169
+  INST(Vpcompressd      , VexMr_Lx           , E(660F38,8B,_,x,_,0,2,T1S), 0                         , 125, 0  , 7184 , 220, 126), // #1170
+  INST(Vpcompressq      , VexMr_Lx           , E(660F38,8B,_,x,_,1,3,T1S), 0                         , 124, 0  , 7196 , 220, 126), // #1171
+  INST(Vpcompressw      , VexMr_Lx           , E(660F38,63,_,x,_,1,1,T1S), 0                         , 197, 0  , 7208 , 220, 151), // #1172
+  INST(Vpcomq           , VexRvmi            , V(XOP_M8,CF,_,0,0,_,_,_  ), 0                         , 193, 0  , 7220 , 251, 139), // #1173
+  INST(Vpcomub          , VexRvmi            , V(XOP_M8,EC,_,0,0,_,_,_  ), 0                         , 193, 0  , 7227 , 251, 139), // #1174
+  INST(Vpcomud          , VexRvmi            , V(XOP_M8,EE,_,0,0,_,_,_  ), 0                         , 193, 0  , 7235 , 251, 139), // #1175
+  INST(Vpcomuq          , VexRvmi            , V(XOP_M8,EF,_,0,0,_,_,_  ), 0                         , 193, 0  , 7243 , 251, 139), // #1176
+  INST(Vpcomuw          , VexRvmi            , V(XOP_M8,ED,_,0,0,_,_,_  ), 0                         , 193, 0  , 7251 , 251, 139), // #1177
+  INST(Vpcomw           , VexRvmi            , V(XOP_M8,CD,_,0,0,_,_,_  ), 0                         , 193, 0  , 7259 , 251, 139), // #1178
+  INST(Vpconflictd      , VexRm_Lx           , E(660F38,C4,_,x,_,0,4,FV ), 0                         , 111, 0  , 7266 , 338, 148), // #1179
+  INST(Vpconflictq      , VexRm_Lx           , E(660F38,C4,_,x,_,1,4,FV ), 0                         , 112, 0  , 7278 , 338, 148), // #1180
+  INST(Vpdpbusd         , VexRvm_Lx          , E(660F38,50,_,x,_,0,4,FV ), 0                         , 111, 0  , 7290 , 203, 152), // #1181
+  INST(Vpdpbusds        , VexRvm_Lx          , E(660F38,51,_,x,_,0,4,FV ), 0                         , 111, 0  , 7299 , 203, 152), // #1182
+  INST(Vpdpwssd         , VexRvm_Lx          , E(660F38,52,_,x,_,0,4,FV ), 0                         , 111, 0  , 7309 , 203, 152), // #1183
+  INST(Vpdpwssds        , VexRvm_Lx          , E(660F38,53,_,x,_,0,4,FV ), 0                         , 111, 0  , 7318 , 203, 152), // #1184
+  INST(Vperm2f128       , VexRvmi            , V(660F3A,06,_,1,0,_,_,_  ), 0                         , 154, 0  , 7328 , 339, 123), // #1185
+  INST(Vperm2i128       , VexRvmi            , V(660F3A,46,_,1,0,_,_,_  ), 0                         , 154, 0  , 7339 , 339, 130), // #1186
+  INST(Vpermb           , VexRvm_Lx          , E(660F38,8D,_,x,_,0,4,FVM), 0                         , 110, 0  , 7350 , 202, 153), // #1187
+  INST(Vpermd           , VexRvm_Lx          , V(660F38,36,_,x,0,0,4,FV ), 0                         , 163, 0  , 7357 , 340, 140), // #1188
+  INST(Vpermi2b         , VexRvm_Lx          , E(660F38,75,_,x,_,0,4,FVM), 0                         , 110, 0  , 7364 , 202, 153), // #1189
+  INST(Vpermi2d         , VexRvm_Lx          , E(660F38,76,_,x,_,0,4,FV ), 0                         , 111, 0  , 7373 , 203, 126), // #1190
+  INST(Vpermi2pd        , VexRvm_Lx          , E(660F38,77,_,x,_,1,4,FV ), 0                         , 112, 0  , 7382 , 204, 126), // #1191
+  INST(Vpermi2ps        , VexRvm_Lx          , E(660F38,77,_,x,_,0,4,FV ), 0                         , 111, 0  , 7392 , 203, 126), // #1192
+  INST(Vpermi2q         , VexRvm_Lx          , E(660F38,76,_,x,_,1,4,FV ), 0                         , 112, 0  , 7402 , 204, 126), // #1193
+  INST(Vpermi2w         , VexRvm_Lx          , E(660F38,75,_,x,_,1,4,FVM), 0                         , 113, 0  , 7411 , 202, 128), // #1194
+  INST(Vpermil2pd       , VexRvrmiRvmri_Lx   , V(660F3A,49,_,x,x,_,_,_  ), 0                         , 72 , 0  , 7420 , 341, 139), // #1195
+  INST(Vpermil2ps       , VexRvrmiRvmri_Lx   , V(660F3A,48,_,x,x,_,_,_  ), 0                         , 72 , 0  , 7431 , 341, 139), // #1196
+  INST(Vpermilpd        , VexRvmRmi_Lx       , V(660F38,0D,_,x,0,1,4,FV ), V(660F3A,05,_,x,0,1,4,FV ), 198, 109, 7442 , 342, 121), // #1197
+  INST(Vpermilps        , VexRvmRmi_Lx       , V(660F38,0C,_,x,0,0,4,FV ), V(660F3A,04,_,x,0,0,4,FV ), 163, 110, 7452 , 342, 121), // #1198
+  INST(Vpermpd          , VexRvmRmi_Lx       , E(660F38,16,_,x,1,1,4,FV ), V(660F3A,01,_,x,1,1,4,FV ), 199, 111, 7462 , 343, 140), // #1199
+  INST(Vpermps          , VexRvm_Lx          , V(660F38,16,_,x,0,0,4,FV ), 0                         , 163, 0  , 7470 , 340, 140), // #1200
+  INST(Vpermq           , VexRvmRmi_Lx       , V(660F38,36,_,x,_,1,4,FV ), V(660F3A,00,_,x,1,1,4,FV ), 198, 112, 7478 , 343, 140), // #1201
+  INST(Vpermt2b         , VexRvm_Lx          , E(660F38,7D,_,x,_,0,4,FVM), 0                         , 110, 0  , 7485 , 202, 153), // #1202
+  INST(Vpermt2d         , VexRvm_Lx          , E(660F38,7E,_,x,_,0,4,FV ), 0                         , 111, 0  , 7494 , 203, 126), // #1203
+  INST(Vpermt2pd        , VexRvm_Lx          , E(660F38,7F,_,x,_,1,4,FV ), 0                         , 112, 0  , 7503 , 204, 126), // #1204
+  INST(Vpermt2ps        , VexRvm_Lx          , E(660F38,7F,_,x,_,0,4,FV ), 0                         , 111, 0  , 7513 , 203, 126), // #1205
+  INST(Vpermt2q         , VexRvm_Lx          , E(660F38,7E,_,x,_,1,4,FV ), 0                         , 112, 0  , 7523 , 204, 126), // #1206
+  INST(Vpermt2w         , VexRvm_Lx          , E(660F38,7D,_,x,_,1,4,FVM), 0                         , 113, 0  , 7532 , 202, 128), // #1207
+  INST(Vpermw           , VexRvm_Lx          , E(660F38,8D,_,x,_,1,4,FVM), 0                         , 113, 0  , 7541 , 202, 128), // #1208
+  INST(Vpexpandb        , VexRm_Lx           , E(660F38,62,_,x,_,0,0,T1S), 0                         , 196, 0  , 7548 , 254, 151), // #1209
+  INST(Vpexpandd        , VexRm_Lx           , E(660F38,89,_,x,_,0,2,T1S), 0                         , 125, 0  , 7558 , 254, 126), // #1210
+  INST(Vpexpandq        , VexRm_Lx           , E(660F38,89,_,x,_,1,3,T1S), 0                         , 124, 0  , 7568 , 254, 126), // #1211
+  INST(Vpexpandw        , VexRm_Lx           , E(660F38,62,_,x,_,1,1,T1S), 0                         , 197, 0  , 7578 , 254, 151), // #1212
+  INST(Vpextrb          , VexMri             , V(660F3A,14,_,0,0,I,0,T1S), 0                         , 200, 0  , 7588 , 344, 154), // #1213
+  INST(Vpextrd          , VexMri             , V(660F3A,16,_,0,0,0,2,T1S), 0                         , 159, 0  , 7596 , 258, 155), // #1214
+  INST(Vpextrq          , VexMri             , V(660F3A,16,_,0,1,1,3,T1S), 0                         , 201, 0  , 7604 , 345, 155), // #1215
+  INST(Vpextrw          , VexMri             , V(660F3A,15,_,0,0,I,1,T1S), 0                         , 202, 0  , 7612 , 346, 154), // #1216
+  INST(Vpgatherdd       , VexRmvRm_VM        , V(660F38,90,_,x,0,_,_,_  ), V(660F38,90,_,x,_,0,2,T1S), 96 , 113, 7620 , 274, 140), // #1217
+  INST(Vpgatherdq       , VexRmvRm_VM        , V(660F38,90,_,x,1,_,_,_  ), V(660F38,90,_,x,_,1,3,T1S), 165, 114, 7631 , 273, 140), // #1218
+  INST(Vpgatherqd       , VexRmvRm_VM        , V(660F38,91,_,x,0,_,_,_  ), V(660F38,91,_,x,_,0,2,T1S), 96 , 115, 7642 , 279, 140), // #1219
+  INST(Vpgatherqq       , VexRmvRm_VM        , V(660F38,91,_,x,1,_,_,_  ), V(660F38,91,_,x,_,1,3,T1S), 165, 116, 7653 , 278, 140), // #1220
+  INST(Vphaddbd         , VexRm              , V(XOP_M9,C2,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7664 , 194, 139), // #1221
+  INST(Vphaddbq         , VexRm              , V(XOP_M9,C3,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7673 , 194, 139), // #1222
+  INST(Vphaddbw         , VexRm              , V(XOP_M9,C1,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7682 , 194, 139), // #1223
+  INST(Vphaddd          , VexRvm_Lx          , V(660F38,02,_,x,I,_,_,_  ), 0                         , 96 , 0  , 7691 , 192, 143), // #1224
+  INST(Vphadddq         , VexRm              , V(XOP_M9,CB,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7699 , 194, 139), // #1225
+  INST(Vphaddsw         , VexRvm_Lx          , V(660F38,03,_,x,I,_,_,_  ), 0                         , 96 , 0  , 7708 , 192, 143), // #1226
+  INST(Vphaddubd        , VexRm              , V(XOP_M9,D2,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7717 , 194, 139), // #1227
+  INST(Vphaddubq        , VexRm              , V(XOP_M9,D3,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7727 , 194, 139), // #1228
+  INST(Vphaddubw        , VexRm              , V(XOP_M9,D1,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7737 , 194, 139), // #1229
+  INST(Vphaddudq        , VexRm              , V(XOP_M9,DB,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7747 , 194, 139), // #1230
+  INST(Vphadduwd        , VexRm              , V(XOP_M9,D6,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7757 , 194, 139), // #1231
+  INST(Vphadduwq        , VexRm              , V(XOP_M9,D7,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7767 , 194, 139), // #1232
+  INST(Vphaddw          , VexRvm_Lx          , V(660F38,01,_,x,I,_,_,_  ), 0                         , 96 , 0  , 7777 , 192, 143), // #1233
+  INST(Vphaddwd         , VexRm              , V(XOP_M9,C6,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7785 , 194, 139), // #1234
+  INST(Vphaddwq         , VexRm              , V(XOP_M9,C7,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7794 , 194, 139), // #1235
+  INST(Vphminposuw      , VexRm              , V(660F38,41,_,0,I,_,_,_  ), 0                         , 96 , 0  , 7803 , 194, 123), // #1236
+  INST(Vphsubbw         , VexRm              , V(XOP_M9,E1,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7815 , 194, 139), // #1237
+  INST(Vphsubd          , VexRvm_Lx          , V(660F38,06,_,x,I,_,_,_  ), 0                         , 96 , 0  , 7824 , 192, 143), // #1238
+  INST(Vphsubdq         , VexRm              , V(XOP_M9,E3,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7832 , 194, 139), // #1239
+  INST(Vphsubsw         , VexRvm_Lx          , V(660F38,07,_,x,I,_,_,_  ), 0                         , 96 , 0  , 7841 , 192, 143), // #1240
+  INST(Vphsubw          , VexRvm_Lx          , V(660F38,05,_,x,I,_,_,_  ), 0                         , 96 , 0  , 7850 , 192, 143), // #1241
+  INST(Vphsubwd         , VexRm              , V(XOP_M9,E2,_,0,0,_,_,_  ), 0                         , 77 , 0  , 7858 , 194, 139), // #1242
+  INST(Vpinsrb          , VexRvmi            , V(660F3A,20,_,0,0,I,0,T1S), 0                         , 200, 0  , 7867 , 347, 154), // #1243
+  INST(Vpinsrd          , VexRvmi            , V(660F3A,22,_,0,0,0,2,T1S), 0                         , 159, 0  , 7875 , 348, 155), // #1244
+  INST(Vpinsrq          , VexRvmi            , V(660F3A,22,_,0,1,1,3,T1S), 0                         , 201, 0  , 7883 , 349, 155), // #1245
+  INST(Vpinsrw          , VexRvmi            , V(660F00,C4,_,0,0,I,1,T1S), 0                         , 203, 0  , 7891 , 350, 154), // #1246
+  INST(Vplzcntd         , VexRm_Lx           , E(660F38,44,_,x,_,0,4,FV ), 0                         , 111, 0  , 7899 , 338, 148), // #1247
+  INST(Vplzcntq         , VexRm_Lx           , E(660F38,44,_,x,_,1,4,FV ), 0                         , 112, 0  , 7908 , 351, 148), // #1248
+  INST(Vpmacsdd         , VexRvmr            , V(XOP_M8,9E,_,0,0,_,_,_  ), 0                         , 193, 0  , 7917 , 352, 139), // #1249
+  INST(Vpmacsdqh        , VexRvmr            , V(XOP_M8,9F,_,0,0,_,_,_  ), 0                         , 193, 0  , 7926 , 352, 139), // #1250
+  INST(Vpmacsdql        , VexRvmr            , V(XOP_M8,97,_,0,0,_,_,_  ), 0                         , 193, 0  , 7936 , 352, 139), // #1251
+  INST(Vpmacssdd        , VexRvmr            , V(XOP_M8,8E,_,0,0,_,_,_  ), 0                         , 193, 0  , 7946 , 352, 139), // #1252
+  INST(Vpmacssdqh       , VexRvmr            , V(XOP_M8,8F,_,0,0,_,_,_  ), 0                         , 193, 0  , 7956 , 352, 139), // #1253
+  INST(Vpmacssdql       , VexRvmr            , V(XOP_M8,87,_,0,0,_,_,_  ), 0                         , 193, 0  , 7967 , 352, 139), // #1254
+  INST(Vpmacsswd        , VexRvmr            , V(XOP_M8,86,_,0,0,_,_,_  ), 0                         , 193, 0  , 7978 , 352, 139), // #1255
+  INST(Vpmacssww        , VexRvmr            , V(XOP_M8,85,_,0,0,_,_,_  ), 0                         , 193, 0  , 7988 , 352, 139), // #1256
+  INST(Vpmacswd         , VexRvmr            , V(XOP_M8,96,_,0,0,_,_,_  ), 0                         , 193, 0  , 7998 , 352, 139), // #1257
+  INST(Vpmacsww         , VexRvmr            , V(XOP_M8,95,_,0,0,_,_,_  ), 0                         , 193, 0  , 8007 , 352, 139), // #1258
+  INST(Vpmadcsswd       , VexRvmr            , V(XOP_M8,A6,_,0,0,_,_,_  ), 0                         , 193, 0  , 8016 , 352, 139), // #1259
+  INST(Vpmadcswd        , VexRvmr            , V(XOP_M8,B6,_,0,0,_,_,_  ), 0                         , 193, 0  , 8027 , 352, 139), // #1260
+  INST(Vpmadd52huq      , VexRvm_Lx          , E(660F38,B5,_,x,_,1,4,FV ), 0                         , 112, 0  , 8037 , 204, 156), // #1261
+  INST(Vpmadd52luq      , VexRvm_Lx          , E(660F38,B4,_,x,_,1,4,FV ), 0                         , 112, 0  , 8049 , 204, 156), // #1262
+  INST(Vpmaddubsw       , VexRvm_Lx          , V(660F38,04,_,x,I,I,4,FVM), 0                         , 107, 0  , 8061 , 285, 146), // #1263
+  INST(Vpmaddwd         , VexRvm_Lx          , V(660F00,F5,_,x,I,I,4,FVM), 0                         , 184, 0  , 8072 , 285, 146), // #1264
+  INST(Vpmaskmovd       , VexRvmMvr_Lx       , V(660F38,8C,_,x,0,_,_,_  ), V(660F38,8E,_,x,0,_,_,_  ), 96 , 117, 8081 , 293, 130), // #1265
+  INST(Vpmaskmovq       , VexRvmMvr_Lx       , V(660F38,8C,_,x,1,_,_,_  ), V(660F38,8E,_,x,1,_,_,_  ), 165, 118, 8092 , 293, 130), // #1266
+  INST(Vpmaxsb          , VexRvm_Lx          , V(660F38,3C,_,x,I,I,4,FVM), 0                         , 107, 0  , 8103 , 353, 146), // #1267
+  INST(Vpmaxsd          , VexRvm_Lx          , V(660F38,3D,_,x,I,0,4,FV ), 0                         , 163, 0  , 8111 , 201, 131), // #1268
+  INST(Vpmaxsq          , VexRvm_Lx          , E(660F38,3D,_,x,_,1,4,FV ), 0                         , 112, 0  , 8119 , 204, 126), // #1269
+  INST(Vpmaxsw          , VexRvm_Lx          , V(660F00,EE,_,x,I,I,4,FVM), 0                         , 184, 0  , 8127 , 353, 146), // #1270
+  INST(Vpmaxub          , VexRvm_Lx          , V(660F00,DE,_,x,I,I,4,FVM), 0                         , 184, 0  , 8135 , 353, 146), // #1271
+  INST(Vpmaxud          , VexRvm_Lx          , V(660F38,3F,_,x,I,0,4,FV ), 0                         , 163, 0  , 8143 , 201, 131), // #1272
+  INST(Vpmaxuq          , VexRvm_Lx          , E(660F38,3F,_,x,_,1,4,FV ), 0                         , 112, 0  , 8151 , 204, 126), // #1273
+  INST(Vpmaxuw          , VexRvm_Lx          , V(660F38,3E,_,x,I,I,4,FVM), 0                         , 107, 0  , 8159 , 353, 146), // #1274
+  INST(Vpminsb          , VexRvm_Lx          , V(660F38,38,_,x,I,I,4,FVM), 0                         , 107, 0  , 8167 , 353, 146), // #1275
+  INST(Vpminsd          , VexRvm_Lx          , V(660F38,39,_,x,I,0,4,FV ), 0                         , 163, 0  , 8175 , 201, 131), // #1276
+  INST(Vpminsq          , VexRvm_Lx          , E(660F38,39,_,x,_,1,4,FV ), 0                         , 112, 0  , 8183 , 204, 126), // #1277
+  INST(Vpminsw          , VexRvm_Lx          , V(660F00,EA,_,x,I,I,4,FVM), 0                         , 184, 0  , 8191 , 353, 146), // #1278
+  INST(Vpminub          , VexRvm_Lx          , V(660F00,DA,_,x,I,_,4,FVM), 0                         , 184, 0  , 8199 , 353, 146), // #1279
+  INST(Vpminud          , VexRvm_Lx          , V(660F38,3B,_,x,I,0,4,FV ), 0                         , 163, 0  , 8207 , 201, 131), // #1280
+  INST(Vpminuq          , VexRvm_Lx          , E(660F38,3B,_,x,_,1,4,FV ), 0                         , 112, 0  , 8215 , 204, 126), // #1281
+  INST(Vpminuw          , VexRvm_Lx          , V(660F38,3A,_,x,I,_,4,FVM), 0                         , 107, 0  , 8223 , 353, 146), // #1282
+  INST(Vpmovb2m         , VexRm_Lx           , E(F30F38,29,_,x,_,0,_,_  ), 0                         , 128, 0  , 8231 , 354, 128), // #1283
+  INST(Vpmovd2m         , VexRm_Lx           , E(F30F38,39,_,x,_,0,_,_  ), 0                         , 128, 0  , 8240 , 354, 129), // #1284
+  INST(Vpmovdb          , VexMr_Lx           , E(F30F38,31,_,x,_,0,2,QVM), 0                         , 204, 0  , 8249 , 355, 126), // #1285
+  INST(Vpmovdw          , VexMr_Lx           , E(F30F38,33,_,x,_,0,3,HVM), 0                         , 205, 0  , 8257 , 356, 126), // #1286
+  INST(Vpmovm2b         , VexRm_Lx           , E(F30F38,28,_,x,_,0,_,_  ), 0                         , 128, 0  , 8265 , 324, 128), // #1287
+  INST(Vpmovm2d         , VexRm_Lx           , E(F30F38,38,_,x,_,0,_,_  ), 0                         , 128, 0  , 8274 , 324, 129), // #1288
+  INST(Vpmovm2q         , VexRm_Lx           , E(F30F38,38,_,x,_,1,_,_  ), 0                         , 191, 0  , 8283 , 324, 129), // #1289
+  INST(Vpmovm2w         , VexRm_Lx           , E(F30F38,28,_,x,_,1,_,_  ), 0                         , 191, 0  , 8292 , 324, 128), // #1290
+  INST(Vpmovmskb        , VexRm_Lx           , V(660F00,D7,_,x,I,_,_,_  ), 0                         , 68 , 0  , 8301 , 305, 143), // #1291
+  INST(Vpmovq2m         , VexRm_Lx           , E(F30F38,39,_,x,_,1,_,_  ), 0                         , 191, 0  , 8311 , 354, 129), // #1292
+  INST(Vpmovqb          , VexMr_Lx           , E(F30F38,32,_,x,_,0,1,OVM), 0                         , 206, 0  , 8320 , 357, 126), // #1293
+  INST(Vpmovqd          , VexMr_Lx           , E(F30F38,35,_,x,_,0,3,HVM), 0                         , 205, 0  , 8328 , 356, 126), // #1294
+  INST(Vpmovqw          , VexMr_Lx           , E(F30F38,34,_,x,_,0,2,QVM), 0                         , 204, 0  , 8336 , 355, 126), // #1295
+  INST(Vpmovsdb         , VexMr_Lx           , E(F30F38,21,_,x,_,0,2,QVM), 0                         , 204, 0  , 8344 , 355, 126), // #1296
+  INST(Vpmovsdw         , VexMr_Lx           , E(F30F38,23,_,x,_,0,3,HVM), 0                         , 205, 0  , 8353 , 356, 126), // #1297
+  INST(Vpmovsqb         , VexMr_Lx           , E(F30F38,22,_,x,_,0,1,OVM), 0                         , 206, 0  , 8362 , 357, 126), // #1298
+  INST(Vpmovsqd         , VexMr_Lx           , E(F30F38,25,_,x,_,0,3,HVM), 0                         , 205, 0  , 8371 , 356, 126), // #1299
+  INST(Vpmovsqw         , VexMr_Lx           , E(F30F38,24,_,x,_,0,2,QVM), 0                         , 204, 0  , 8380 , 355, 126), // #1300
+  INST(Vpmovswb         , VexMr_Lx           , E(F30F38,20,_,x,_,0,3,HVM), 0                         , 205, 0  , 8389 , 356, 128), // #1301
+  INST(Vpmovsxbd        , VexRm_Lx           , V(660F38,21,_,x,I,I,2,QVM), 0                         , 207, 0  , 8398 , 358, 131), // #1302
+  INST(Vpmovsxbq        , VexRm_Lx           , V(660F38,22,_,x,I,I,1,OVM), 0                         , 208, 0  , 8408 , 359, 131), // #1303
+  INST(Vpmovsxbw        , VexRm_Lx           , V(660F38,20,_,x,I,I,3,HVM), 0                         , 132, 0  , 8418 , 360, 146), // #1304
+  INST(Vpmovsxdq        , VexRm_Lx           , V(660F38,25,_,x,I,0,3,HVM), 0                         , 132, 0  , 8428 , 360, 131), // #1305
+  INST(Vpmovsxwd        , VexRm_Lx           , V(660F38,23,_,x,I,I,3,HVM), 0                         , 132, 0  , 8438 , 360, 131), // #1306
+  INST(Vpmovsxwq        , VexRm_Lx           , V(660F38,24,_,x,I,I,2,QVM), 0                         , 207, 0  , 8448 , 358, 131), // #1307
+  INST(Vpmovusdb        , VexMr_Lx           , E(F30F38,11,_,x,_,0,2,QVM), 0                         , 204, 0  , 8458 , 355, 126), // #1308
+  INST(Vpmovusdw        , VexMr_Lx           , E(F30F38,13,_,x,_,0,3,HVM), 0                         , 205, 0  , 8468 , 356, 126), // #1309
+  INST(Vpmovusqb        , VexMr_Lx           , E(F30F38,12,_,x,_,0,1,OVM), 0                         , 206, 0  , 8478 , 357, 126), // #1310
+  INST(Vpmovusqd        , VexMr_Lx           , E(F30F38,15,_,x,_,0,3,HVM), 0                         , 205, 0  , 8488 , 356, 126), // #1311
+  INST(Vpmovusqw        , VexMr_Lx           , E(F30F38,14,_,x,_,0,2,QVM), 0                         , 204, 0  , 8498 , 355, 126), // #1312
+  INST(Vpmovuswb        , VexMr_Lx           , E(F30F38,10,_,x,_,0,3,HVM), 0                         , 205, 0  , 8508 , 356, 128), // #1313
+  INST(Vpmovw2m         , VexRm_Lx           , E(F30F38,29,_,x,_,1,_,_  ), 0                         , 191, 0  , 8518 , 354, 128), // #1314
+  INST(Vpmovwb          , VexMr_Lx           , E(F30F38,30,_,x,_,0,3,HVM), 0                         , 205, 0  , 8527 , 356, 128), // #1315
+  INST(Vpmovzxbd        , VexRm_Lx           , V(660F38,31,_,x,I,I,2,QVM), 0                         , 207, 0  , 8535 , 358, 131), // #1316
+  INST(Vpmovzxbq        , VexRm_Lx           , V(660F38,32,_,x,I,I,1,OVM), 0                         , 208, 0  , 8545 , 359, 131), // #1317
+  INST(Vpmovzxbw        , VexRm_Lx           , V(660F38,30,_,x,I,I,3,HVM), 0                         , 132, 0  , 8555 , 360, 146), // #1318
+  INST(Vpmovzxdq        , VexRm_Lx           , V(660F38,35,_,x,I,0,3,HVM), 0                         , 132, 0  , 8565 , 360, 131), // #1319
+  INST(Vpmovzxwd        , VexRm_Lx           , V(660F38,33,_,x,I,I,3,HVM), 0                         , 132, 0  , 8575 , 360, 131), // #1320
+  INST(Vpmovzxwq        , VexRm_Lx           , V(660F38,34,_,x,I,I,2,QVM), 0                         , 207, 0  , 8585 , 358, 131), // #1321
+  INST(Vpmuldq          , VexRvm_Lx          , V(660F38,28,_,x,I,1,4,FV ), 0                         , 198, 0  , 8595 , 198, 131), // #1322
+  INST(Vpmulhrsw        , VexRvm_Lx          , V(660F38,0B,_,x,I,I,4,FVM), 0                         , 107, 0  , 8603 , 285, 146), // #1323
+  INST(Vpmulhuw         , VexRvm_Lx          , V(660F00,E4,_,x,I,I,4,FVM), 0                         , 184, 0  , 8613 , 285, 146), // #1324
+  INST(Vpmulhw          , VexRvm_Lx          , V(660F00,E5,_,x,I,I,4,FVM), 0                         , 184, 0  , 8622 , 285, 146), // #1325
+  INST(Vpmulld          , VexRvm_Lx          , V(660F38,40,_,x,I,0,4,FV ), 0                         , 163, 0  , 8630 , 199, 131), // #1326
+  INST(Vpmullq          , VexRvm_Lx          , E(660F38,40,_,x,_,1,4,FV ), 0                         , 112, 0  , 8638 , 204, 129), // #1327
+  INST(Vpmullw          , VexRvm_Lx          , V(660F00,D5,_,x,I,I,4,FVM), 0                         , 184, 0  , 8646 , 285, 146), // #1328
+  INST(Vpmultishiftqb   , VexRvm_Lx          , E(660F38,83,_,x,_,1,4,FV ), 0                         , 112, 0  , 8654 , 204, 153), // #1329
+  INST(Vpmuludq         , VexRvm_Lx          , V(660F00,F4,_,x,I,1,4,FV ), 0                         , 102, 0  , 8669 , 198, 131), // #1330
+  INST(Vpopcntb         , VexRm_Lx           , E(660F38,54,_,x,_,0,4,FV ), 0                         , 111, 0  , 8678 , 254, 157), // #1331
+  INST(Vpopcntd         , VexRm_Lx           , E(660F38,55,_,x,_,0,4,FVM), 0                         , 110, 0  , 8687 , 338, 158), // #1332
+  INST(Vpopcntq         , VexRm_Lx           , E(660F38,55,_,x,_,1,4,FVM), 0                         , 113, 0  , 8696 , 351, 158), // #1333
+  INST(Vpopcntw         , VexRm_Lx           , E(660F38,54,_,x,_,1,4,FV ), 0                         , 112, 0  , 8705 , 254, 157), // #1334
+  INST(Vpor             , VexRvm_Lx          , V(660F00,EB,_,x,I,_,_,_  ), 0                         , 68 , 0  , 8714 , 316, 143), // #1335
+  INST(Vpord            , VexRvm_Lx          , E(660F00,EB,_,x,_,0,4,FV ), 0                         , 189, 0  , 8719 , 317, 126), // #1336
+  INST(Vporq            , VexRvm_Lx          , E(660F00,EB,_,x,_,1,4,FV ), 0                         , 130, 0  , 8725 , 321, 126), // #1337
+  INST(Vpperm           , VexRvrmRvmr        , V(XOP_M8,A3,_,0,x,_,_,_  ), 0                         , 193, 0  , 8731 , 361, 139), // #1338
+  INST(Vprold           , VexVmi_Lx          , E(660F00,72,1,x,_,0,4,FV ), 0                         , 209, 0  , 8738 , 362, 126), // #1339
+  INST(Vprolq           , VexVmi_Lx          , E(660F00,72,1,x,_,1,4,FV ), 0                         , 210, 0  , 8745 , 363, 126), // #1340
+  INST(Vprolvd          , VexRvm_Lx          , E(660F38,15,_,x,_,0,4,FV ), 0                         , 111, 0  , 8752 , 203, 126), // #1341
+  INST(Vprolvq          , VexRvm_Lx          , E(660F38,15,_,x,_,1,4,FV ), 0                         , 112, 0  , 8760 , 204, 126), // #1342
+  INST(Vprord           , VexVmi_Lx          , E(660F00,72,0,x,_,0,4,FV ), 0                         , 189, 0  , 8768 , 362, 126), // #1343
+  INST(Vprorq           , VexVmi_Lx          , E(660F00,72,0,x,_,1,4,FV ), 0                         , 130, 0  , 8775 , 363, 126), // #1344
+  INST(Vprorvd          , VexRvm_Lx          , E(660F38,14,_,x,_,0,4,FV ), 0                         , 111, 0  , 8782 , 203, 126), // #1345
+  INST(Vprorvq          , VexRvm_Lx          , E(660F38,14,_,x,_,1,4,FV ), 0                         , 112, 0  , 8790 , 204, 126), // #1346
+  INST(Vprotb           , VexRvmRmvRmi       , V(XOP_M9,90,_,0,x,_,_,_  ), V(XOP_M8,C0,_,0,x,_,_,_  ), 77 , 119, 8798 , 364, 139), // #1347
+  INST(Vprotd           , VexRvmRmvRmi       , V(XOP_M9,92,_,0,x,_,_,_  ), V(XOP_M8,C2,_,0,x,_,_,_  ), 77 , 120, 8805 , 364, 139), // #1348
+  INST(Vprotq           , VexRvmRmvRmi       , V(XOP_M9,93,_,0,x,_,_,_  ), V(XOP_M8,C3,_,0,x,_,_,_  ), 77 , 121, 8812 , 364, 139), // #1349
+  INST(Vprotw           , VexRvmRmvRmi       , V(XOP_M9,91,_,0,x,_,_,_  ), V(XOP_M8,C1,_,0,x,_,_,_  ), 77 , 122, 8819 , 364, 139), // #1350
+  INST(Vpsadbw          , VexRvm_Lx          , V(660F00,F6,_,x,I,I,4,FVM), 0                         , 184, 0  , 8826 , 193, 146), // #1351
+  INST(Vpscatterdd      , VexMr_VM           , E(660F38,A0,_,x,_,0,2,T1S), 0                         , 125, 0  , 8834 , 365, 126), // #1352
+  INST(Vpscatterdq      , VexMr_VM           , E(660F38,A0,_,x,_,1,3,T1S), 0                         , 124, 0  , 8846 , 365, 126), // #1353
+  INST(Vpscatterqd      , VexMr_VM           , E(660F38,A1,_,x,_,0,2,T1S), 0                         , 125, 0  , 8858 , 366, 126), // #1354
+  INST(Vpscatterqq      , VexMr_VM           , E(660F38,A1,_,x,_,1,3,T1S), 0                         , 124, 0  , 8870 , 367, 126), // #1355
+  INST(Vpshab           , VexRvmRmv          , V(XOP_M9,98,_,0,x,_,_,_  ), 0                         , 77 , 0  , 8882 , 368, 139), // #1356
+  INST(Vpshad           , VexRvmRmv          , V(XOP_M9,9A,_,0,x,_,_,_  ), 0                         , 77 , 0  , 8889 , 368, 139), // #1357
+  INST(Vpshaq           , VexRvmRmv          , V(XOP_M9,9B,_,0,x,_,_,_  ), 0                         , 77 , 0  , 8896 , 368, 139), // #1358
+  INST(Vpshaw           , VexRvmRmv          , V(XOP_M9,99,_,0,x,_,_,_  ), 0                         , 77 , 0  , 8903 , 368, 139), // #1359
+  INST(Vpshlb           , VexRvmRmv          , V(XOP_M9,94,_,0,x,_,_,_  ), 0                         , 77 , 0  , 8910 , 368, 139), // #1360
+  INST(Vpshld           , VexRvmRmv          , V(XOP_M9,96,_,0,x,_,_,_  ), 0                         , 77 , 0  , 8917 , 368, 139), // #1361
+  INST(Vpshldd          , VexRvmi_Lx         , E(660F3A,71,_,x,_,0,4,FV ), 0                         , 108, 0  , 8924 , 196, 151), // #1362
+  INST(Vpshldq          , VexRvmi_Lx         , E(660F3A,71,_,x,_,1,4,FV ), 0                         , 109, 0  , 8932 , 197, 151), // #1363
+  INST(Vpshldvd         , VexRvm_Lx          , E(660F38,71,_,x,_,0,4,FV ), 0                         , 111, 0  , 8940 , 203, 151), // #1364
+  INST(Vpshldvq         , VexRvm_Lx          , E(660F38,71,_,x,_,1,4,FV ), 0                         , 112, 0  , 8949 , 204, 151), // #1365
+  INST(Vpshldvw         , VexRvm_Lx          , E(660F38,70,_,x,_,0,4,FVM), 0                         , 110, 0  , 8958 , 202, 151), // #1366
+  INST(Vpshldw          , VexRvmi_Lx         , E(660F3A,70,_,x,_,0,4,FVM), 0                         , 151, 0  , 8967 , 250, 151), // #1367
+  INST(Vpshlq           , VexRvmRmv          , V(XOP_M9,97,_,0,x,_,_,_  ), 0                         , 77 , 0  , 8975 , 368, 139), // #1368
+  INST(Vpshlw           , VexRvmRmv          , V(XOP_M9,95,_,0,x,_,_,_  ), 0                         , 77 , 0  , 8982 , 368, 139), // #1369
+  INST(Vpshrdd          , VexRvmi_Lx         , E(660F3A,73,_,x,_,0,4,FV ), 0                         , 108, 0  , 8989 , 196, 151), // #1370
+  INST(Vpshrdq          , VexRvmi_Lx         , E(660F3A,73,_,x,_,1,4,FV ), 0                         , 109, 0  , 8997 , 197, 151), // #1371
+  INST(Vpshrdvd         , VexRvm_Lx          , E(660F38,73,_,x,_,0,4,FV ), 0                         , 111, 0  , 9005 , 203, 151), // #1372
+  INST(Vpshrdvq         , VexRvm_Lx          , E(660F38,73,_,x,_,1,4,FV ), 0                         , 112, 0  , 9014 , 204, 151), // #1373
+  INST(Vpshrdvw         , VexRvm_Lx          , E(660F38,72,_,x,_,0,4,FVM), 0                         , 110, 0  , 9023 , 202, 151), // #1374
+  INST(Vpshrdw          , VexRvmi_Lx         , E(660F3A,72,_,x,_,0,4,FVM), 0                         , 151, 0  , 9032 , 250, 151), // #1375
+  INST(Vpshufb          , VexRvm_Lx          , V(660F38,00,_,x,I,I,4,FVM), 0                         , 107, 0  , 9040 , 285, 146), // #1376
+  INST(Vpshufbitqmb     , VexRvm_Lx          , E(660F38,8F,_,x,0,0,4,FVM), 0                         , 110, 0  , 9048 , 369, 157), // #1377
+  INST(Vpshufd          , VexRmi_Lx          , V(660F00,70,_,x,I,0,4,FV ), 0                         , 133, 0  , 9061 , 370, 131), // #1378
+  INST(Vpshufhw         , VexRmi_Lx          , V(F30F00,70,_,x,I,I,4,FVM), 0                         , 185, 0  , 9069 , 371, 146), // #1379
+  INST(Vpshuflw         , VexRmi_Lx          , V(F20F00,70,_,x,I,I,4,FVM), 0                         , 211, 0  , 9078 , 371, 146), // #1380
+  INST(Vpsignb          , VexRvm_Lx          , V(660F38,08,_,x,I,_,_,_  ), 0                         , 96 , 0  , 9087 , 192, 143), // #1381
+  INST(Vpsignd          , VexRvm_Lx          , V(660F38,0A,_,x,I,_,_,_  ), 0                         , 96 , 0  , 9095 , 192, 143), // #1382
+  INST(Vpsignw          , VexRvm_Lx          , V(660F38,09,_,x,I,_,_,_  ), 0                         , 96 , 0  , 9103 , 192, 143), // #1383
+  INST(Vpslld           , VexRvmVmi_Lx       , V(660F00,F2,_,x,I,0,4,128), V(660F00,72,6,x,I,0,4,FV ), 212, 123, 9111 , 372, 131), // #1384
+  INST(Vpslldq          , VexEvexVmi_Lx      , V(660F00,73,7,x,I,I,4,FVM), 0                         , 213, 0  , 9118 , 373, 146), // #1385
+  INST(Vpsllq           , VexRvmVmi_Lx       , V(660F00,F3,_,x,I,1,4,128), V(660F00,73,6,x,I,1,4,FV ), 214, 124, 9126 , 374, 131), // #1386
+  INST(Vpsllvd          , VexRvm_Lx          , V(660F38,47,_,x,0,0,4,FV ), 0                         , 163, 0  , 9133 , 199, 140), // #1387
+  INST(Vpsllvq          , VexRvm_Lx          , V(660F38,47,_,x,1,1,4,FV ), 0                         , 162, 0  , 9141 , 198, 140), // #1388
+  INST(Vpsllvw          , VexRvm_Lx          , E(660F38,12,_,x,_,1,4,FVM), 0                         , 113, 0  , 9149 , 202, 128), // #1389
+  INST(Vpsllw           , VexRvmVmi_Lx       , V(660F00,F1,_,x,I,I,4,FVM), V(660F00,71,6,x,I,I,4,FVM), 184, 125, 9157 , 375, 146), // #1390
+  INST(Vpsrad           , VexRvmVmi_Lx       , V(660F00,E2,_,x,I,0,4,128), V(660F00,72,4,x,I,0,4,FV ), 212, 126, 9164 , 372, 131), // #1391
+  INST(Vpsraq           , VexRvmVmi_Lx       , E(660F00,E2,_,x,_,1,4,128), E(660F00,72,4,x,_,1,4,FV ), 215, 127, 9171 , 376, 126), // #1392
+  INST(Vpsravd          , VexRvm_Lx          , V(660F38,46,_,x,0,0,4,FV ), 0                         , 163, 0  , 9178 , 199, 140), // #1393
+  INST(Vpsravq          , VexRvm_Lx          , E(660F38,46,_,x,_,1,4,FV ), 0                         , 112, 0  , 9186 , 204, 126), // #1394
+  INST(Vpsravw          , VexRvm_Lx          , E(660F38,11,_,x,_,1,4,FVM), 0                         , 113, 0  , 9194 , 202, 128), // #1395
+  INST(Vpsraw           , VexRvmVmi_Lx       , V(660F00,E1,_,x,I,I,4,128), V(660F00,71,4,x,I,I,4,FVM), 212, 128, 9202 , 375, 146), // #1396
+  INST(Vpsrld           , VexRvmVmi_Lx       , V(660F00,D2,_,x,I,0,4,128), V(660F00,72,2,x,I,0,4,FV ), 212, 129, 9209 , 372, 131), // #1397
+  INST(Vpsrldq          , VexEvexVmi_Lx      , V(660F00,73,3,x,I,I,4,FVM), 0                         , 216, 0  , 9216 , 373, 146), // #1398
+  INST(Vpsrlq           , VexRvmVmi_Lx       , V(660F00,D3,_,x,I,1,4,128), V(660F00,73,2,x,I,1,4,FV ), 214, 130, 9224 , 374, 131), // #1399
+  INST(Vpsrlvd          , VexRvm_Lx          , V(660F38,45,_,x,0,0,4,FV ), 0                         , 163, 0  , 9231 , 199, 140), // #1400
+  INST(Vpsrlvq          , VexRvm_Lx          , V(660F38,45,_,x,1,1,4,FV ), 0                         , 162, 0  , 9239 , 198, 140), // #1401
+  INST(Vpsrlvw          , VexRvm_Lx          , E(660F38,10,_,x,_,1,4,FVM), 0                         , 113, 0  , 9247 , 202, 128), // #1402
+  INST(Vpsrlw           , VexRvmVmi_Lx       , V(660F00,D1,_,x,I,I,4,128), V(660F00,71,2,x,I,I,4,FVM), 212, 131, 9255 , 375, 146), // #1403
+  INST(Vpsubb           , VexRvm_Lx          , V(660F00,F8,_,x,I,I,4,FVM), 0                         , 184, 0  , 9262 , 377, 146), // #1404
+  INST(Vpsubd           , VexRvm_Lx          , V(660F00,FA,_,x,I,0,4,FV ), 0                         , 133, 0  , 9269 , 378, 131), // #1405
+  INST(Vpsubq           , VexRvm_Lx          , V(660F00,FB,_,x,I,1,4,FV ), 0                         , 102, 0  , 9276 , 379, 131), // #1406
+  INST(Vpsubsb          , VexRvm_Lx          , V(660F00,E8,_,x,I,I,4,FVM), 0                         , 184, 0  , 9283 , 377, 146), // #1407
+  INST(Vpsubsw          , VexRvm_Lx          , V(660F00,E9,_,x,I,I,4,FVM), 0                         , 184, 0  , 9291 , 377, 146), // #1408
+  INST(Vpsubusb         , VexRvm_Lx          , V(660F00,D8,_,x,I,I,4,FVM), 0                         , 184, 0  , 9299 , 377, 146), // #1409
+  INST(Vpsubusw         , VexRvm_Lx          , V(660F00,D9,_,x,I,I,4,FVM), 0                         , 184, 0  , 9308 , 377, 146), // #1410
+  INST(Vpsubw           , VexRvm_Lx          , V(660F00,F9,_,x,I,I,4,FVM), 0                         , 184, 0  , 9317 , 377, 146), // #1411
+  INST(Vpternlogd       , VexRvmi_Lx         , E(660F3A,25,_,x,_,0,4,FV ), 0                         , 108, 0  , 9324 , 196, 126), // #1412
+  INST(Vpternlogq       , VexRvmi_Lx         , E(660F3A,25,_,x,_,1,4,FV ), 0                         , 109, 0  , 9335 , 197, 126), // #1413
+  INST(Vptest           , VexRm_Lx           , V(660F38,17,_,x,I,_,_,_  ), 0                         , 96 , 0  , 9346 , 270, 150), // #1414
+  INST(Vptestmb         , VexRvm_Lx          , E(660F38,26,_,x,_,0,4,FVM), 0                         , 110, 0  , 9353 , 369, 128), // #1415
+  INST(Vptestmd         , VexRvm_Lx          , E(660F38,27,_,x,_,0,4,FV ), 0                         , 111, 0  , 9362 , 380, 126), // #1416
+  INST(Vptestmq         , VexRvm_Lx          , E(660F38,27,_,x,_,1,4,FV ), 0                         , 112, 0  , 9371 , 381, 126), // #1417
+  INST(Vptestmw         , VexRvm_Lx          , E(660F38,26,_,x,_,1,4,FVM), 0                         , 113, 0  , 9380 , 369, 128), // #1418
+  INST(Vptestnmb        , VexRvm_Lx          , E(F30F38,26,_,x,_,0,4,FVM), 0                         , 217, 0  , 9389 , 369, 128), // #1419
+  INST(Vptestnmd        , VexRvm_Lx          , E(F30F38,27,_,x,_,0,4,FV ), 0                         , 218, 0  , 9399 , 380, 126), // #1420
+  INST(Vptestnmq        , VexRvm_Lx          , E(F30F38,27,_,x,_,1,4,FV ), 0                         , 219, 0  , 9409 , 381, 126), // #1421
+  INST(Vptestnmw        , VexRvm_Lx          , E(F30F38,26,_,x,_,1,4,FVM), 0                         , 220, 0  , 9419 , 369, 128), // #1422
+  INST(Vpunpckhbw       , VexRvm_Lx          , V(660F00,68,_,x,I,I,4,FVM), 0                         , 184, 0  , 9429 , 285, 146), // #1423
+  INST(Vpunpckhdq       , VexRvm_Lx          , V(660F00,6A,_,x,I,0,4,FV ), 0                         , 133, 0  , 9440 , 199, 131), // #1424
+  INST(Vpunpckhqdq      , VexRvm_Lx          , V(660F00,6D,_,x,I,1,4,FV ), 0                         , 102, 0  , 9451 , 198, 131), // #1425
+  INST(Vpunpckhwd       , VexRvm_Lx          , V(660F00,69,_,x,I,I,4,FVM), 0                         , 184, 0  , 9463 , 285, 146), // #1426
+  INST(Vpunpcklbw       , VexRvm_Lx          , V(660F00,60,_,x,I,I,4,FVM), 0                         , 184, 0  , 9474 , 285, 146), // #1427
+  INST(Vpunpckldq       , VexRvm_Lx          , V(660F00,62,_,x,I,0,4,FV ), 0                         , 133, 0  , 9485 , 199, 131), // #1428
+  INST(Vpunpcklqdq      , VexRvm_Lx          , V(660F00,6C,_,x,I,1,4,FV ), 0                         , 102, 0  , 9496 , 198, 131), // #1429
+  INST(Vpunpcklwd       , VexRvm_Lx          , V(660F00,61,_,x,I,I,4,FVM), 0                         , 184, 0  , 9508 , 285, 146), // #1430
+  INST(Vpxor            , VexRvm_Lx          , V(660F00,EF,_,x,I,_,_,_  ), 0                         , 68 , 0  , 9519 , 318, 143), // #1431
+  INST(Vpxord           , VexRvm_Lx          , E(660F00,EF,_,x,_,0,4,FV ), 0                         , 189, 0  , 9525 , 319, 126), // #1432
+  INST(Vpxorq           , VexRvm_Lx          , E(660F00,EF,_,x,_,1,4,FV ), 0                         , 130, 0  , 9532 , 320, 126), // #1433
+  INST(Vrangepd         , VexRvmi_Lx         , E(660F3A,50,_,x,_,1,4,FV ), 0                         , 109, 0  , 9539 , 259, 129), // #1434
+  INST(Vrangeps         , VexRvmi_Lx         , E(660F3A,50,_,x,_,0,4,FV ), 0                         , 108, 0  , 9548 , 260, 129), // #1435
+  INST(Vrangesd         , VexRvmi            , E(660F3A,51,_,I,_,1,3,T1S), 0                         , 160, 0  , 9557 , 261, 64 ), // #1436
+  INST(Vrangess         , VexRvmi            , E(660F3A,51,_,I,_,0,2,T1S), 0                         , 161, 0  , 9566 , 262, 64 ), // #1437
+  INST(Vrcp14pd         , VexRm_Lx           , E(660F38,4C,_,x,_,1,4,FV ), 0                         , 112, 0  , 9575 , 351, 126), // #1438
+  INST(Vrcp14ps         , VexRm_Lx           , E(660F38,4C,_,x,_,0,4,FV ), 0                         , 111, 0  , 9584 , 338, 126), // #1439
+  INST(Vrcp14sd         , VexRvm             , E(660F38,4D,_,I,_,1,3,T1S), 0                         , 124, 0  , 9593 , 382, 66 ), // #1440
+  INST(Vrcp14ss         , VexRvm             , E(660F38,4D,_,I,_,0,2,T1S), 0                         , 125, 0  , 9602 , 383, 66 ), // #1441
+  INST(Vrcp28pd         , VexRm              , E(660F38,CA,_,2,_,1,4,FV ), 0                         , 152, 0  , 9611 , 252, 135), // #1442
+  INST(Vrcp28ps         , VexRm              , E(660F38,CA,_,2,_,0,4,FV ), 0                         , 153, 0  , 9620 , 253, 135), // #1443
+  INST(Vrcp28sd         , VexRvm             , E(660F38,CB,_,I,_,1,3,T1S), 0                         , 124, 0  , 9629 , 280, 135), // #1444
+  INST(Vrcp28ss         , VexRvm             , E(660F38,CB,_,I,_,0,2,T1S), 0                         , 125, 0  , 9638 , 281, 135), // #1445
+  INST(Vrcpps           , VexRm_Lx           , V(000F00,53,_,x,I,_,_,_  ), 0                         , 71 , 0  , 9647 , 270, 123), // #1446
+  INST(Vrcpss           , VexRvm             , V(F30F00,53,_,I,I,_,_,_  ), 0                         , 178, 0  , 9654 , 384, 123), // #1447
+  INST(Vreducepd        , VexRmi_Lx          , E(660F3A,56,_,x,_,1,4,FV ), 0                         , 109, 0  , 9661 , 363, 129), // #1448
+  INST(Vreduceps        , VexRmi_Lx          , E(660F3A,56,_,x,_,0,4,FV ), 0                         , 108, 0  , 9671 , 362, 129), // #1449
+  INST(Vreducesd        , VexRvmi            , E(660F3A,57,_,I,_,1,3,T1S), 0                         , 160, 0  , 9681 , 385, 64 ), // #1450
+  INST(Vreducess        , VexRvmi            , E(660F3A,57,_,I,_,0,2,T1S), 0                         , 161, 0  , 9691 , 386, 64 ), // #1451
+  INST(Vrndscalepd      , VexRmi_Lx          , E(660F3A,09,_,x,_,1,4,FV ), 0                         , 109, 0  , 9701 , 282, 126), // #1452
+  INST(Vrndscaleps      , VexRmi_Lx          , E(660F3A,08,_,x,_,0,4,FV ), 0                         , 108, 0  , 9713 , 283, 126), // #1453
+  INST(Vrndscalesd      , VexRvmi            , E(660F3A,0B,_,I,_,1,3,T1S), 0                         , 160, 0  , 9725 , 261, 66 ), // #1454
+  INST(Vrndscaless      , VexRvmi            , E(660F3A,0A,_,I,_,0,2,T1S), 0                         , 161, 0  , 9737 , 262, 66 ), // #1455
+  INST(Vroundpd         , VexRmi_Lx          , V(660F3A,09,_,x,I,_,_,_  ), 0                         , 72 , 0  , 9749 , 387, 123), // #1456
+  INST(Vroundps         , VexRmi_Lx          , V(660F3A,08,_,x,I,_,_,_  ), 0                         , 72 , 0  , 9758 , 387, 123), // #1457
+  INST(Vroundsd         , VexRvmi            , V(660F3A,0B,_,I,I,_,_,_  ), 0                         , 72 , 0  , 9767 , 388, 123), // #1458
+  INST(Vroundss         , VexRvmi            , V(660F3A,0A,_,I,I,_,_,_  ), 0                         , 72 , 0  , 9776 , 389, 123), // #1459
+  INST(Vrsqrt14pd       , VexRm_Lx           , E(660F38,4E,_,x,_,1,4,FV ), 0                         , 112, 0  , 9785 , 351, 126), // #1460
+  INST(Vrsqrt14ps       , VexRm_Lx           , E(660F38,4E,_,x,_,0,4,FV ), 0                         , 111, 0  , 9796 , 338, 126), // #1461
+  INST(Vrsqrt14sd       , VexRvm             , E(660F38,4F,_,I,_,1,3,T1S), 0                         , 124, 0  , 9807 , 382, 66 ), // #1462
+  INST(Vrsqrt14ss       , VexRvm             , E(660F38,4F,_,I,_,0,2,T1S), 0                         , 125, 0  , 9818 , 383, 66 ), // #1463
+  INST(Vrsqrt28pd       , VexRm              , E(660F38,CC,_,2,_,1,4,FV ), 0                         , 152, 0  , 9829 , 252, 135), // #1464
+  INST(Vrsqrt28ps       , VexRm              , E(660F38,CC,_,2,_,0,4,FV ), 0                         , 153, 0  , 9840 , 253, 135), // #1465
+  INST(Vrsqrt28sd       , VexRvm             , E(660F38,CD,_,I,_,1,3,T1S), 0                         , 124, 0  , 9851 , 280, 135), // #1466
+  INST(Vrsqrt28ss       , VexRvm             , E(660F38,CD,_,I,_,0,2,T1S), 0                         , 125, 0  , 9862 , 281, 135), // #1467
+  INST(Vrsqrtps         , VexRm_Lx           , V(000F00,52,_,x,I,_,_,_  ), 0                         , 71 , 0  , 9873 , 270, 123), // #1468
+  INST(Vrsqrtss         , VexRvm             , V(F30F00,52,_,I,I,_,_,_  ), 0                         , 178, 0  , 9882 , 384, 123), // #1469
+  INST(Vscalefpd        , VexRvm_Lx          , E(660F38,2C,_,x,_,1,4,FV ), 0                         , 112, 0  , 9891 , 390, 126), // #1470
+  INST(Vscalefps        , VexRvm_Lx          , E(660F38,2C,_,x,_,0,4,FV ), 0                         , 111, 0  , 9901 , 391, 126), // #1471
+  INST(Vscalefsd        , VexRvm             , E(660F38,2D,_,I,_,1,3,T1S), 0                         , 124, 0  , 9911 , 392, 66 ), // #1472
+  INST(Vscalefss        , VexRvm             , E(660F38,2D,_,I,_,0,2,T1S), 0                         , 125, 0  , 9921 , 393, 66 ), // #1473
+  INST(Vscatterdpd      , VexMr_Lx           , E(660F38,A2,_,x,_,1,3,T1S), 0                         , 124, 0  , 9931 , 394, 126), // #1474
+  INST(Vscatterdps      , VexMr_Lx           , E(660F38,A2,_,x,_,0,2,T1S), 0                         , 125, 0  , 9943 , 365, 126), // #1475
+  INST(Vscatterpf0dpd   , VexM_VM            , E(660F38,C6,5,2,_,1,3,T1S), 0                         , 221, 0  , 9955 , 275, 141), // #1476
+  INST(Vscatterpf0dps   , VexM_VM            , E(660F38,C6,5,2,_,0,2,T1S), 0                         , 222, 0  , 9970 , 276, 141), // #1477
+  INST(Vscatterpf0qpd   , VexM_VM            , E(660F38,C7,5,2,_,1,3,T1S), 0                         , 221, 0  , 9985 , 277, 141), // #1478
+  INST(Vscatterpf0qps   , VexM_VM            , E(660F38,C7,5,2,_,0,2,T1S), 0                         , 222, 0  , 10000, 277, 141), // #1479
+  INST(Vscatterpf1dpd   , VexM_VM            , E(660F38,C6,6,2,_,1,3,T1S), 0                         , 223, 0  , 10015, 275, 141), // #1480
+  INST(Vscatterpf1dps   , VexM_VM            , E(660F38,C6,6,2,_,0,2,T1S), 0                         , 224, 0  , 10030, 276, 141), // #1481
+  INST(Vscatterpf1qpd   , VexM_VM            , E(660F38,C7,6,2,_,1,3,T1S), 0                         , 223, 0  , 10045, 277, 141), // #1482
+  INST(Vscatterpf1qps   , VexM_VM            , E(660F38,C7,6,2,_,0,2,T1S), 0                         , 224, 0  , 10060, 277, 141), // #1483
+  INST(Vscatterqpd      , VexMr_Lx           , E(660F38,A3,_,x,_,1,3,T1S), 0                         , 124, 0  , 10075, 367, 126), // #1484
+  INST(Vscatterqps      , VexMr_Lx           , E(660F38,A3,_,x,_,0,2,T1S), 0                         , 125, 0  , 10087, 366, 126), // #1485
+  INST(Vshuff32x4       , VexRvmi_Lx         , E(660F3A,23,_,x,_,0,4,FV ), 0                         , 108, 0  , 10099, 395, 126), // #1486
+  INST(Vshuff64x2       , VexRvmi_Lx         , E(660F3A,23,_,x,_,1,4,FV ), 0                         , 109, 0  , 10110, 396, 126), // #1487
+  INST(Vshufi32x4       , VexRvmi_Lx         , E(660F3A,43,_,x,_,0,4,FV ), 0                         , 108, 0  , 10121, 395, 126), // #1488
+  INST(Vshufi64x2       , VexRvmi_Lx         , E(660F3A,43,_,x,_,1,4,FV ), 0                         , 109, 0  , 10132, 396, 126), // #1489
+  INST(Vshufpd          , VexRvmi_Lx         , V(660F00,C6,_,x,I,1,4,FV ), 0                         , 102, 0  , 10143, 397, 121), // #1490
+  INST(Vshufps          , VexRvmi_Lx         , V(000F00,C6,_,x,I,0,4,FV ), 0                         , 103, 0  , 10151, 398, 121), // #1491
+  INST(Vsqrtpd          , VexRm_Lx           , V(660F00,51,_,x,I,1,4,FV ), 0                         , 102, 0  , 10159, 399, 121), // #1492
+  INST(Vsqrtps          , VexRm_Lx           , V(000F00,51,_,x,I,0,4,FV ), 0                         , 103, 0  , 10167, 222, 121), // #1493
+  INST(Vsqrtsd          , VexRvm             , V(F20F00,51,_,I,I,1,3,T1S), 0                         , 104, 0  , 10175, 190, 122), // #1494
+  INST(Vsqrtss          , VexRvm             , V(F30F00,51,_,I,I,0,2,T1S), 0                         , 105, 0  , 10183, 191, 122), // #1495
+  INST(Vstmxcsr         , VexM               , V(000F00,AE,3,0,I,_,_,_  ), 0                         , 225, 0  , 10191, 291, 123), // #1496
+  INST(Vsubpd           , VexRvm_Lx          , V(660F00,5C,_,x,I,1,4,FV ), 0                         , 102, 0  , 10200, 188, 121), // #1497
+  INST(Vsubps           , VexRvm_Lx          , V(000F00,5C,_,x,I,0,4,FV ), 0                         , 103, 0  , 10207, 189, 121), // #1498
+  INST(Vsubsd           , VexRvm             , V(F20F00,5C,_,I,I,1,3,T1S), 0                         , 104, 0  , 10214, 190, 122), // #1499
+  INST(Vsubss           , VexRvm             , V(F30F00,5C,_,I,I,0,2,T1S), 0                         , 105, 0  , 10221, 191, 122), // #1500
+  INST(Vtestpd          , VexRm_Lx           , V(660F38,0F,_,x,0,_,_,_  ), 0                         , 96 , 0  , 10228, 270, 150), // #1501
+  INST(Vtestps          , VexRm_Lx           , V(660F38,0E,_,x,0,_,_,_  ), 0                         , 96 , 0  , 10236, 270, 150), // #1502
+  INST(Vucomisd         , VexRm              , V(660F00,2E,_,I,I,1,3,T1S), 0                         , 122, 0  , 10244, 218, 132), // #1503
+  INST(Vucomiss         , VexRm              , V(000F00,2E,_,I,I,0,2,T1S), 0                         , 123, 0  , 10253, 219, 132), // #1504
+  INST(Vunpckhpd        , VexRvm_Lx          , V(660F00,15,_,x,I,1,4,FV ), 0                         , 102, 0  , 10262, 198, 121), // #1505
+  INST(Vunpckhps        , VexRvm_Lx          , V(000F00,15,_,x,I,0,4,FV ), 0                         , 103, 0  , 10272, 199, 121), // #1506
+  INST(Vunpcklpd        , VexRvm_Lx          , V(660F00,14,_,x,I,1,4,FV ), 0                         , 102, 0  , 10282, 198, 121), // #1507
+  INST(Vunpcklps        , VexRvm_Lx          , V(000F00,14,_,x,I,0,4,FV ), 0                         , 103, 0  , 10292, 199, 121), // #1508
+  INST(Vxorpd           , VexRvm_Lx          , V(660F00,57,_,x,I,1,4,FV ), 0                         , 102, 0  , 10302, 379, 127), // #1509
+  INST(Vxorps           , VexRvm_Lx          , V(000F00,57,_,x,I,0,4,FV ), 0                         , 103, 0  , 10309, 378, 127), // #1510
+  INST(Vzeroall         , VexOp              , V(000F00,77,_,1,I,_,_,_  ), 0                         , 67 , 0  , 10316, 400, 123), // #1511
+  INST(Vzeroupper       , VexOp              , V(000F00,77,_,0,I,_,_,_  ), 0                         , 71 , 0  , 10325, 400, 123), // #1512
+  INST(Wbinvd           , X86Op              , O(000F00,09,_,_,_,_,_,_  ), 0                         , 4  , 0  , 10336, 30 , 0  ), // #1513
+  INST(Wbnoinvd         , X86Op              , O(F30F00,09,_,_,_,_,_,_  ), 0                         , 6  , 0  , 10343, 30 , 159), // #1514
+  INST(Wrfsbase         , X86M               , O(F30F00,AE,2,_,x,_,_,_  ), 0                         , 226, 0  , 10352, 166, 102), // #1515
+  INST(Wrgsbase         , X86M               , O(F30F00,AE,3,_,x,_,_,_  ), 0                         , 227, 0  , 10361, 166, 102), // #1516
+  INST(Wrmsr            , X86Op              , O(000F00,30,_,_,_,_,_,_  ), 0                         , 4  , 0  , 10370, 167, 103), // #1517
+  INST(Wrssd            , X86Mr              , O(000F38,F6,_,_,_,_,_,_  ), 0                         , 82 , 0  , 10376, 401, 54 ), // #1518
+  INST(Wrssq            , X86Mr              , O(000F38,F6,_,_,1,_,_,_  ), 0                         , 228, 0  , 10382, 402, 54 ), // #1519
+  INST(Wrussd           , X86Mr              , O(660F38,F5,_,_,_,_,_,_  ), 0                         , 2  , 0  , 10388, 401, 54 ), // #1520
+  INST(Wrussq           , X86Mr              , O(660F38,F5,_,_,1,_,_,_  ), 0                         , 229, 0  , 10395, 402, 54 ), // #1521
+  INST(Xabort           , X86Op_Mod11RM_I8   , O(000000,C6,7,_,_,_,_,_  ), 0                         , 26 , 0  , 10402, 77 , 160), // #1522
+  INST(Xadd             , X86Xadd            , O(000F00,C0,_,_,x,_,_,_  ), 0                         , 4  , 0  , 10409, 403, 37 ), // #1523
+  INST(Xbegin           , X86JmpRel          , O(000000,C7,7,_,_,_,_,_  ), 0                         , 26 , 0  , 10414, 404, 160), // #1524
+  INST(Xchg             , X86Xchg            , O(000000,86,_,_,x,_,_,_  ), 0                         , 0  , 0  , 457  , 405, 0  ), // #1525
+  INST(Xend             , X86Op              , O(000F01,D5,_,_,_,_,_,_  ), 0                         , 21 , 0  , 10421, 30 , 160), // #1526
+  INST(Xgetbv           , X86Op              , O(000F01,D0,_,_,_,_,_,_  ), 0                         , 21 , 0  , 10426, 167, 161), // #1527
+  INST(Xlatb            , X86Op              , O(000000,D7,_,_,_,_,_,_  ), 0                         , 0  , 0  , 10433, 30 , 0  ), // #1528
+  INST(Xor              , X86Arith           , O(000000,30,6,_,x,_,_,_  ), 0                         , 31 , 0  , 9521 , 171, 1  ), // #1529
+  INST(Xorpd            , ExtRm              , O(660F00,57,_,_,_,_,_,_  ), 0                         , 3  , 0  , 10303, 144, 4  ), // #1530
+  INST(Xorps            , ExtRm              , O(000F00,57,_,_,_,_,_,_  ), 0                         , 4  , 0  , 10310, 144, 5  ), // #1531
+  INST(Xresldtrk        , X86Op              , O(F20F01,E9,_,_,_,_,_,_  ), 0                         , 92 , 0  , 10439, 30 , 162), // #1532
+  INST(Xrstor           , X86M_Only          , O(000F00,AE,5,_,_,_,_,_  ), 0                         , 75 , 0  , 1159 , 406, 161), // #1533
+  INST(Xrstor64         , X86M_Only          , O(000F00,AE,5,_,1,_,_,_  ), 0                         , 230, 0  , 1167 , 407, 161), // #1534
+  INST(Xrstors          , X86M_Only          , O(000F00,C7,3,_,_,_,_,_  ), 0                         , 76 , 0  , 10449, 406, 163), // #1535
+  INST(Xrstors64        , X86M_Only          , O(000F00,C7,3,_,1,_,_,_  ), 0                         , 231, 0  , 10457, 407, 163), // #1536
+  INST(Xsave            , X86M_Only          , O(000F00,AE,4,_,_,_,_,_  ), 0                         , 97 , 0  , 1177 , 406, 161), // #1537
+  INST(Xsave64          , X86M_Only          , O(000F00,AE,4,_,1,_,_,_  ), 0                         , 232, 0  , 1184 , 407, 161), // #1538
+  INST(Xsavec           , X86M_Only          , O(000F00,C7,4,_,_,_,_,_  ), 0                         , 97 , 0  , 10467, 406, 164), // #1539
+  INST(Xsavec64         , X86M_Only          , O(000F00,C7,4,_,1,_,_,_  ), 0                         , 232, 0  , 10474, 407, 164), // #1540
+  INST(Xsaveopt         , X86M_Only          , O(000F00,AE,6,_,_,_,_,_  ), 0                         , 78 , 0  , 10483, 406, 165), // #1541
+  INST(Xsaveopt64       , X86M_Only          , O(000F00,AE,6,_,1,_,_,_  ), 0                         , 233, 0  , 10492, 407, 165), // #1542
+  INST(Xsaves           , X86M_Only          , O(000F00,C7,5,_,_,_,_,_  ), 0                         , 75 , 0  , 10503, 406, 163), // #1543
+  INST(Xsaves64         , X86M_Only          , O(000F00,C7,5,_,1,_,_,_  ), 0                         , 230, 0  , 10510, 407, 163), // #1544
+  INST(Xsetbv           , X86Op              , O(000F01,D1,_,_,_,_,_,_  ), 0                         , 21 , 0  , 10519, 167, 161), // #1545
+  INST(Xsusldtrk        , X86Op              , O(F20F01,E8,_,_,_,_,_,_  ), 0                         , 92 , 0  , 10526, 30 , 162), // #1546
+  INST(Xtest            , X86Op              , O(000F01,D6,_,_,_,_,_,_  ), 0                         , 21 , 0  , 10536, 30 , 166)  // #1547
+  // ${InstInfo:End}
+};
+#undef NAME_DATA_INDEX
+#undef INST
+
+// ============================================================================
+// [asmjit::x86::InstDB - Opcode Tables]
+// ============================================================================
+
+// ${MainOpcodeTable:Begin}
+// ------------------- Automatically generated, do not edit -------------------
+const uint32_t InstDB::_mainOpcodeTable[] = {
+  O(000000,00,0,0,0,0,0,_  ), // #0 [ref=56x]
+  O(000000,00,2,0,0,0,0,_  ), // #1 [ref=4x]
+  O(660F38,00,0,0,0,0,0,_  ), // #2 [ref=43x]
+  O(660F00,00,0,0,0,0,0,_  ), // #3 [ref=38x]
+  O(000F00,00,0,0,0,0,0,_  ), // #4 [ref=233x]
+  O(F20F00,00,0,0,0,0,0,_  ), // #5 [ref=24x]
+  O(F30F00,00,0,0,0,0,0,_  ), // #6 [ref=29x]
+  O(F30F38,00,0,0,0,0,0,_  ), // #7 [ref=2x]
+  O(660F3A,00,0,0,0,0,0,_  ), // #8 [ref=22x]
+  O(000000,00,4,0,0,0,0,_  ), // #9 [ref=5x]
+  V(000F38,00,0,0,0,0,0,_  ), // #10 [ref=6x]
+  V(XOP_M9,00,1,0,0,0,0,_  ), // #11 [ref=3x]
+  V(XOP_M9,00,6,0,0,0,0,_  ), // #12 [ref=2x]
+  V(XOP_M9,00,5,0,0,0,0,_  ), // #13 [ref=1x]
+  V(XOP_M9,00,3,0,0,0,0,_  ), // #14 [ref=1x]
+  V(XOP_M9,00,2,0,0,0,0,_  ), // #15 [ref=1x]
+  V(000F38,00,3,0,0,0,0,_  ), // #16 [ref=1x]
+  V(000F38,00,2,0,0,0,0,_  ), // #17 [ref=1x]
+  V(000F38,00,1,0,0,0,0,_  ), // #18 [ref=1x]
+  O(660000,00,0,0,0,0,0,_  ), // #19 [ref=7x]
+  O(000000,00,0,0,1,0,0,_  ), // #20 [ref=3x]
+  O(000F01,00,0,0,0,0,0,_  ), // #21 [ref=29x]
+  O(000F00,00,7,0,0,0,0,_  ), // #22 [ref=5x]
+  O(660F00,00,7,0,0,0,0,_  ), // #23 [ref=1x]
+  O(F30F00,00,6,0,0,0,0,_  ), // #24 [ref=3x]
+  O(660F00,00,6,0,0,0,0,_  ), // #25 [ref=3x]
+  O(000000,00,7,0,0,0,0,_  ), // #26 [ref=5x]
+  O(000F00,00,1,0,1,0,0,_  ), // #27 [ref=2x]
+  O(000F00,00,1,0,0,0,0,_  ), // #28 [ref=6x]
+  O(F20F38,00,0,0,0,0,0,_  ), // #29 [ref=2x]
+  O(000000,00,1,0,0,0,0,_  ), // #30 [ref=3x]
+  O(000000,00,6,0,0,0,0,_  ), // #31 [ref=3x]
+  O(F30F00,00,7,0,0,0,0,3  ), // #32 [ref=1x]
+  O(F30F00,00,7,0,0,0,0,2  ), // #33 [ref=1x]
+  O_FPU(00,D900,_)          , // #34 [ref=29x]
+  O_FPU(00,C000,0)          , // #35 [ref=1x]
+  O_FPU(00,DE00,_)          , // #36 [ref=7x]
+  O_FPU(00,0000,4)          , // #37 [ref=4x]
+  O_FPU(00,0000,6)          , // #38 [ref=4x]
+  O_FPU(9B,DB00,_)          , // #39 [ref=2x]
+  O_FPU(00,DA00,_)          , // #40 [ref=5x]
+  O_FPU(00,DB00,_)          , // #41 [ref=8x]
+  O_FPU(00,D000,2)          , // #42 [ref=1x]
+  O_FPU(00,DF00,_)          , // #43 [ref=2x]
+  O_FPU(00,D800,3)          , // #44 [ref=1x]
+  O_FPU(00,F000,6)          , // #45 [ref=1x]
+  O_FPU(00,F800,7)          , // #46 [ref=1x]
+  O_FPU(00,DD00,_)          , // #47 [ref=3x]
+  O_FPU(00,0000,0)          , // #48 [ref=3x]
+  O_FPU(00,0000,2)          , // #49 [ref=3x]
+  O_FPU(00,0000,3)          , // #50 [ref=3x]
+  O_FPU(00,0000,7)          , // #51 [ref=3x]
+  O_FPU(00,0000,1)          , // #52 [ref=2x]
+  O_FPU(00,0000,5)          , // #53 [ref=2x]
+  O_FPU(00,C800,1)          , // #54 [ref=1x]
+  O_FPU(9B,0000,6)          , // #55 [ref=2x]
+  O_FPU(9B,0000,7)          , // #56 [ref=2x]
+  O_FPU(00,E000,4)          , // #57 [ref=1x]
+  O_FPU(00,E800,5)          , // #58 [ref=1x]
+  O_FPU(00,0000,_)          , // #59 [ref=1x]
+  O(000F00,00,0,0,1,0,0,_  ), // #60 [ref=1x]
+  O(000000,00,5,0,0,0,0,_  ), // #61 [ref=3x]
+  O(F30F00,00,5,0,0,0,0,_  ), // #62 [ref=2x]
+  O(F30F00,00,5,0,1,0,0,_  ), // #63 [ref=1x]
+  V(660F00,00,0,1,0,0,0,_  ), // #64 [ref=7x]
+  V(660F00,00,0,1,1,0,0,_  ), // #65 [ref=6x]
+  V(000F00,00,0,1,1,0,0,_  ), // #66 [ref=7x]
+  V(000F00,00,0,1,0,0,0,_  ), // #67 [ref=8x]
+  V(660F00,00,0,0,0,0,0,_  ), // #68 [ref=15x]
+  V(660F00,00,0,0,1,0,0,_  ), // #69 [ref=4x]
+  V(000F00,00,0,0,1,0,0,_  ), // #70 [ref=4x]
+  V(000F00,00,0,0,0,0,0,_  ), // #71 [ref=10x]
+  V(660F3A,00,0,0,0,0,0,_  ), // #72 [ref=45x]
+  V(660F3A,00,0,0,1,0,0,_  ), // #73 [ref=4x]
+  O(000F00,00,2,0,0,0,0,_  ), // #74 [ref=5x]
+  O(000F00,00,5,0,0,0,0,_  ), // #75 [ref=4x]
+  O(000F00,00,3,0,0,0,0,_  ), // #76 [ref=5x]
+  V(XOP_M9,00,0,0,0,0,0,_  ), // #77 [ref=32x]
+  O(000F00,00,6,0,0,0,0,_  ), // #78 [ref=5x]
+  V(XOP_MA,00,0,0,0,0,0,_  ), // #79 [ref=1x]
+  V(XOP_MA,00,1,0,0,0,0,_  ), // #80 [ref=1x]
+  O(F30F01,00,0,0,0,0,0,_  ), // #81 [ref=5x]
+  O(000F38,00,0,0,0,0,0,_  ), // #82 [ref=24x]
+  V(F20F38,00,0,0,0,0,0,_  ), // #83 [ref=6x]
+  O(000000,00,3,0,0,0,0,_  ), // #84 [ref=3x]
+  O(000F3A,00,0,0,0,0,0,_  ), // #85 [ref=4x]
+  O(F30000,00,0,0,0,0,0,_  ), // #86 [ref=1x]
+  O(000F0F,00,0,0,0,0,0,_  ), // #87 [ref=26x]
+  V(F30F38,00,0,0,0,0,0,_  ), // #88 [ref=5x]
+  O(000F3A,00,0,0,1,0,0,_  ), // #89 [ref=1x]
+  O(660F3A,00,0,0,1,0,0,_  ), // #90 [ref=1x]
+  O(F30F00,00,4,0,0,0,0,_  ), // #91 [ref=1x]
+  O(F20F01,00,0,0,0,0,0,_  ), // #92 [ref=4x]
+  O(F30F00,00,1,0,0,0,0,_  ), // #93 [ref=3x]
+  O(F30F00,00,7,0,0,0,0,_  ), // #94 [ref=1x]
+  V(F20F3A,00,0,0,0,0,0,_  ), // #95 [ref=1x]
+  V(660F38,00,0,0,0,0,0,_  ), // #96 [ref=25x]
+  O(000F00,00,4,0,0,0,0,_  ), // #97 [ref=4x]
+  V(XOP_M9,00,7,0,0,0,0,_  ), // #98 [ref=1x]
+  V(XOP_M9,00,4,0,0,0,0,_  ), // #99 [ref=1x]
+  O(F20F00,00,6,0,0,0,0,_  ), // #100 [ref=1x]
+  E(F20F38,00,0,2,0,0,2,T4X), // #101 [ref=6x]
+  V(660F00,00,0,0,0,1,4,FV ), // #102 [ref=22x]
+  V(000F00,00,0,0,0,0,4,FV ), // #103 [ref=16x]
+  V(F20F00,00,0,0,0,1,3,T1S), // #104 [ref=10x]
+  V(F30F00,00,0,0,0,0,2,T1S), // #105 [ref=10x]
+  V(F20F00,00,0,0,0,0,0,_  ), // #106 [ref=4x]
+  V(660F38,00,0,0,0,0,4,FVM), // #107 [ref=14x]
+  E(660F3A,00,0,0,0,0,4,FV ), // #108 [ref=14x]
+  E(660F3A,00,0,0,0,1,4,FV ), // #109 [ref=14x]
+  E(660F38,00,0,0,0,0,4,FVM), // #110 [ref=9x]
+  E(660F38,00,0,0,0,0,4,FV ), // #111 [ref=22x]
+  E(660F38,00,0,0,0,1,4,FV ), // #112 [ref=28x]
+  E(660F38,00,0,0,0,1,4,FVM), // #113 [ref=9x]
+  V(660F38,00,0,1,0,0,0,_  ), // #114 [ref=2x]
+  E(660F38,00,0,0,0,0,3,T2 ), // #115 [ref=2x]
+  E(660F38,00,0,0,0,0,4,T4 ), // #116 [ref=2x]
+  E(660F38,00,0,2,0,0,5,T8 ), // #117 [ref=2x]
+  E(660F38,00,0,0,0,1,4,T2 ), // #118 [ref=2x]
+  E(660F38,00,0,2,0,1,5,T4 ), // #119 [ref=2x]
+  V(660F38,00,0,0,0,1,3,T1S), // #120 [ref=2x]
+  V(660F38,00,0,0,0,0,2,T1S), // #121 [ref=14x]
+  V(660F00,00,0,0,0,1,3,T1S), // #122 [ref=5x]
+  V(000F00,00,0,0,0,0,2,T1S), // #123 [ref=2x]
+  E(660F38,00,0,0,0,1,3,T1S), // #124 [ref=14x]
+  E(660F38,00,0,0,0,0,2,T1S), // #125 [ref=14x]
+  V(F30F00,00,0,0,0,0,3,HV ), // #126 [ref=1x]
+  E(F20F38,00,0,0,0,0,0,_  ), // #127 [ref=1x]
+  E(F30F38,00,0,0,0,0,0,_  ), // #128 [ref=7x]
+  V(F20F00,00,0,0,0,1,4,FV ), // #129 [ref=1x]
+  E(660F00,00,0,0,0,1,4,FV ), // #130 [ref=9x]
+  E(000F00,00,0,0,0,1,4,FV ), // #131 [ref=3x]
+  V(660F38,00,0,0,0,0,3,HVM), // #132 [ref=7x]
+  V(660F00,00,0,0,0,0,4,FV ), // #133 [ref=11x]
+  V(000F00,00,0,0,0,0,4,HV ), // #134 [ref=1x]
+  V(660F3A,00,0,0,0,0,3,HVM), // #135 [ref=1x]
+  E(660F00,00,0,0,0,0,3,HV ), // #136 [ref=4x]
+  E(000F00,00,0,0,0,0,4,FV ), // #137 [ref=2x]
+  E(F30F00,00,0,0,0,1,4,FV ), // #138 [ref=2x]
+  V(F20F00,00,0,0,0,0,3,T1F), // #139 [ref=2x]
+  E(F20F00,00,0,0,0,0,3,T1F), // #140 [ref=2x]
+  V(F20F00,00,0,0,0,0,2,T1W), // #141 [ref=1x]
+  V(F30F00,00,0,0,0,0,2,T1W), // #142 [ref=1x]
+  V(F30F00,00,0,0,0,0,2,T1F), // #143 [ref=2x]
+  E(F30F00,00,0,0,0,0,2,T1F), // #144 [ref=2x]
+  V(F30F00,00,0,0,0,0,4,FV ), // #145 [ref=1x]
+  E(F30F00,00,0,0,0,0,3,HV ), // #146 [ref=1x]
+  E(F20F00,00,0,0,0,0,4,FV ), // #147 [ref=1x]
+  E(F20F00,00,0,0,0,1,4,FV ), // #148 [ref=1x]
+  E(F20F00,00,0,0,0,0,2,T1W), // #149 [ref=1x]
+  E(F30F00,00,0,0,0,0,2,T1W), // #150 [ref=1x]
+  E(660F3A,00,0,0,0,0,4,FVM), // #151 [ref=5x]
+  E(660F38,00,0,2,0,1,4,FV ), // #152 [ref=3x]
+  E(660F38,00,0,2,0,0,4,FV ), // #153 [ref=3x]
+  V(660F3A,00,0,1,0,0,0,_  ), // #154 [ref=6x]
+  E(660F3A,00,0,0,0,0,4,T4 ), // #155 [ref=4x]
+  E(660F3A,00,0,2,0,0,5,T8 ), // #156 [ref=4x]
+  E(660F3A,00,0,0,0,1,4,T2 ), // #157 [ref=4x]
+  E(660F3A,00,0,2,0,1,5,T4 ), // #158 [ref=4x]
+  V(660F3A,00,0,0,0,0,2,T1S), // #159 [ref=4x]
+  E(660F3A,00,0,0,0,1,3,T1S), // #160 [ref=6x]
+  E(660F3A,00,0,0,0,0,2,T1S), // #161 [ref=6x]
+  V(660F38,00,0,0,1,1,4,FV ), // #162 [ref=20x]
+  V(660F38,00,0,0,0,0,4,FV ), // #163 [ref=32x]
+  V(660F38,00,0,0,1,1,3,T1S), // #164 [ref=12x]
+  V(660F38,00,0,0,1,0,0,_  ), // #165 [ref=5x]
+  E(660F38,00,1,2,0,1,3,T1S), // #166 [ref=2x]
+  E(660F38,00,1,2,0,0,2,T1S), // #167 [ref=2x]
+  E(660F38,00,2,2,0,1,3,T1S), // #168 [ref=2x]
+  E(660F38,00,2,2,0,0,2,T1S), // #169 [ref=2x]
+  V(660F3A,00,0,0,1,1,4,FV ), // #170 [ref=2x]
+  V(000F00,00,2,0,0,0,0,_  ), // #171 [ref=1x]
+  V(660F00,00,0,0,0,1,4,FVM), // #172 [ref=3x]
+  V(000F00,00,0,0,0,0,4,FVM), // #173 [ref=3x]
+  V(660F00,00,0,0,0,0,2,T1S), // #174 [ref=1x]
+  V(F20F00,00,0,0,0,1,3,DUP), // #175 [ref=1x]
+  E(660F00,00,0,0,0,0,4,FVM), // #176 [ref=1x]
+  E(660F00,00,0,0,0,1,4,FVM), // #177 [ref=1x]
+  V(F30F00,00,0,0,0,0,0,_  ), // #178 [ref=3x]
+  E(F20F00,00,0,0,0,1,4,FVM), // #179 [ref=1x]
+  E(F30F00,00,0,0,0,0,4,FVM), // #180 [ref=1x]
+  E(F30F00,00,0,0,0,1,4,FVM), // #181 [ref=1x]
+  E(F20F00,00,0,0,0,0,4,FVM), // #182 [ref=1x]
+  V(000F00,00,0,0,0,0,3,T2 ), // #183 [ref=2x]
+  V(660F00,00,0,0,0,0,4,FVM), // #184 [ref=33x]
+  V(F30F00,00,0,0,0,0,4,FVM), // #185 [ref=3x]
+  E(F20F38,00,0,0,0,0,4,FV ), // #186 [ref=1x]
+  E(F20F38,00,0,0,0,1,4,FV ), // #187 [ref=1x]
+  V(660F3A,00,0,0,0,0,4,FVM), // #188 [ref=2x]
+  E(660F00,00,0,0,0,0,4,FV ), // #189 [ref=5x]
+  V(660F38,00,0,0,0,0,0,T1S), // #190 [ref=1x]
+  E(F30F38,00,0,0,0,1,0,_  ), // #191 [ref=5x]
+  V(660F38,00,0,0,0,0,1,T1S), // #192 [ref=1x]
+  V(XOP_M8,00,0,0,0,0,0,_  ), // #193 [ref=22x]
+  V(660F38,00,0,0,0,1,4,FVM), // #194 [ref=2x]
+  E(660F3A,00,0,0,0,1,4,FVM), // #195 [ref=2x]
+  E(660F38,00,0,0,0,0,0,T1S), // #196 [ref=2x]
+  E(660F38,00,0,0,0,1,1,T1S), // #197 [ref=2x]
+  V(660F38,00,0,0,0,1,4,FV ), // #198 [ref=3x]
+  E(660F38,00,0,0,1,1,4,FV ), // #199 [ref=1x]
+  V(660F3A,00,0,0,0,0,0,T1S), // #200 [ref=2x]
+  V(660F3A,00,0,0,1,1,3,T1S), // #201 [ref=2x]
+  V(660F3A,00,0,0,0,0,1,T1S), // #202 [ref=1x]
+  V(660F00,00,0,0,0,0,1,T1S), // #203 [ref=1x]
+  E(F30F38,00,0,0,0,0,2,QVM), // #204 [ref=6x]
+  E(F30F38,00,0,0,0,0,3,HVM), // #205 [ref=9x]
+  E(F30F38,00,0,0,0,0,1,OVM), // #206 [ref=3x]
+  V(660F38,00,0,0,0,0,2,QVM), // #207 [ref=4x]
+  V(660F38,00,0,0,0,0,1,OVM), // #208 [ref=2x]
+  E(660F00,00,1,0,0,0,4,FV ), // #209 [ref=1x]
+  E(660F00,00,1,0,0,1,4,FV ), // #210 [ref=1x]
+  V(F20F00,00,0,0,0,0,4,FVM), // #211 [ref=1x]
+  V(660F00,00,0,0,0,0,4,128), // #212 [ref=5x]
+  V(660F00,00,7,0,0,0,4,FVM), // #213 [ref=1x]
+  V(660F00,00,0,0,0,1,4,128), // #214 [ref=2x]
+  E(660F00,00,0,0,0,1,4,128), // #215 [ref=1x]
+  V(660F00,00,3,0,0,0,4,FVM), // #216 [ref=1x]
+  E(F30F38,00,0,0,0,0,4,FVM), // #217 [ref=1x]
+  E(F30F38,00,0,0,0,0,4,FV ), // #218 [ref=1x]
+  E(F30F38,00,0,0,0,1,4,FV ), // #219 [ref=1x]
+  E(F30F38,00,0,0,0,1,4,FVM), // #220 [ref=1x]
+  E(660F38,00,5,2,0,1,3,T1S), // #221 [ref=2x]
+  E(660F38,00,5,2,0,0,2,T1S), // #222 [ref=2x]
+  E(660F38,00,6,2,0,1,3,T1S), // #223 [ref=2x]
+  E(660F38,00,6,2,0,0,2,T1S), // #224 [ref=2x]
+  V(000F00,00,3,0,0,0,0,_  ), // #225 [ref=1x]
+  O(F30F00,00,2,0,0,0,0,_  ), // #226 [ref=1x]
+  O(F30F00,00,3,0,0,0,0,_  ), // #227 [ref=1x]
+  O(000F38,00,0,0,1,0,0,_  ), // #228 [ref=1x]
+  O(660F38,00,0,0,1,0,0,_  ), // #229 [ref=1x]
+  O(000F00,00,5,0,1,0,0,_  ), // #230 [ref=2x]
+  O(000F00,00,3,0,1,0,0,_  ), // #231 [ref=1x]
+  O(000F00,00,4,0,1,0,0,_  ), // #232 [ref=2x]
+  O(000F00,00,6,0,1,0,0,_  )  // #233 [ref=1x]
+};
+// ----------------------------------------------------------------------------
+// ${MainOpcodeTable:End}
+
+// ${AltOpcodeTable:Begin}
+// ------------------- Automatically generated, do not edit -------------------
+const uint32_t InstDB::_altOpcodeTable[] = {
+  0                         , // #0 [ref=1403x]
+  O(660F00,1B,_,_,_,_,_,_  ), // #1 [ref=1x]
+  O(000F00,BA,4,_,x,_,_,_  ), // #2 [ref=1x]
+  O(000F00,BA,7,_,x,_,_,_  ), // #3 [ref=1x]
+  O(000F00,BA,6,_,x,_,_,_  ), // #4 [ref=1x]
+  O(000F00,BA,5,_,x,_,_,_  ), // #5 [ref=1x]
+  O(000000,48,_,_,x,_,_,_  ), // #6 [ref=1x]
+  O(660F00,78,0,_,_,_,_,_  ), // #7 [ref=1x]
+  O_FPU(00,00DF,5)          , // #8 [ref=1x]
+  O_FPU(00,00DF,7)          , // #9 [ref=1x]
+  O_FPU(00,00DD,1)          , // #10 [ref=1x]
+  O_FPU(00,00DB,5)          , // #11 [ref=1x]
+  O_FPU(00,DFE0,_)          , // #12 [ref=1x]
+  O(000000,DB,7,_,_,_,_,_  ), // #13 [ref=1x]
+  O_FPU(9B,DFE0,_)          , // #14 [ref=1x]
+  O(000000,E4,_,_,_,_,_,_  ), // #15 [ref=1x]
+  O(000000,40,_,_,x,_,_,_  ), // #16 [ref=1x]
+  O(F20F00,78,_,_,_,_,_,_  ), // #17 [ref=1x]
+  O(000000,77,_,_,_,_,_,_  ), // #18 [ref=2x]
+  O(000000,73,_,_,_,_,_,_  ), // #19 [ref=3x]
+  O(000000,72,_,_,_,_,_,_  ), // #20 [ref=3x]
+  O(000000,76,_,_,_,_,_,_  ), // #21 [ref=2x]
+  O(000000,74,_,_,_,_,_,_  ), // #22 [ref=2x]
+  O(000000,E3,_,_,_,_,_,_  ), // #23 [ref=1x]
+  O(000000,7F,_,_,_,_,_,_  ), // #24 [ref=2x]
+  O(000000,7D,_,_,_,_,_,_  ), // #25 [ref=2x]
+  O(000000,7C,_,_,_,_,_,_  ), // #26 [ref=2x]
+  O(000000,7E,_,_,_,_,_,_  ), // #27 [ref=2x]
+  O(000000,EB,_,_,_,_,_,_  ), // #28 [ref=1x]
+  O(000000,75,_,_,_,_,_,_  ), // #29 [ref=2x]
+  O(000000,71,_,_,_,_,_,_  ), // #30 [ref=1x]
+  O(000000,7B,_,_,_,_,_,_  ), // #31 [ref=2x]
+  O(000000,79,_,_,_,_,_,_  ), // #32 [ref=1x]
+  O(000000,70,_,_,_,_,_,_  ), // #33 [ref=1x]
+  O(000000,7A,_,_,_,_,_,_  ), // #34 [ref=2x]
+  O(000000,78,_,_,_,_,_,_  ), // #35 [ref=1x]
+  V(660F00,92,_,0,0,_,_,_  ), // #36 [ref=1x]
+  V(F20F00,92,_,0,0,_,_,_  ), // #37 [ref=1x]
+  V(F20F00,92,_,0,1,_,_,_  ), // #38 [ref=1x]
+  V(000F00,92,_,0,0,_,_,_  ), // #39 [ref=1x]
+  O(000000,E2,_,_,_,_,_,_  ), // #40 [ref=1x]
+  O(000000,E1,_,_,_,_,_,_  ), // #41 [ref=1x]
+  O(000000,E0,_,_,_,_,_,_  ), // #42 [ref=1x]
+  O(660F00,29,_,_,_,_,_,_  ), // #43 [ref=1x]
+  O(000F00,29,_,_,_,_,_,_  ), // #44 [ref=1x]
+  O(000F38,F1,_,_,x,_,_,_  ), // #45 [ref=1x]
+  O(000F00,7E,_,_,_,_,_,_  ), // #46 [ref=1x]
+  O(660F00,7F,_,_,_,_,_,_  ), // #47 [ref=1x]
+  O(F30F00,7F,_,_,_,_,_,_  ), // #48 [ref=1x]
+  O(660F00,17,_,_,_,_,_,_  ), // #49 [ref=1x]
+  O(000F00,17,_,_,_,_,_,_  ), // #50 [ref=1x]
+  O(660F00,13,_,_,_,_,_,_  ), // #51 [ref=1x]
+  O(000F00,13,_,_,_,_,_,_  ), // #52 [ref=1x]
+  O(660F00,E7,_,_,_,_,_,_  ), // #53 [ref=1x]
+  O(660F00,2B,_,_,_,_,_,_  ), // #54 [ref=1x]
+  O(000F00,2B,_,_,_,_,_,_  ), // #55 [ref=1x]
+  O(000F00,E7,_,_,_,_,_,_  ), // #56 [ref=1x]
+  O(F20F00,2B,_,_,_,_,_,_  ), // #57 [ref=1x]
+  O(F30F00,2B,_,_,_,_,_,_  ), // #58 [ref=1x]
+  O(000F00,7E,_,_,x,_,_,_  ), // #59 [ref=1x]
+  O(F20F00,11,_,_,_,_,_,_  ), // #60 [ref=1x]
+  O(F30F00,11,_,_,_,_,_,_  ), // #61 [ref=1x]
+  O(660F00,11,_,_,_,_,_,_  ), // #62 [ref=1x]
+  O(000F00,11,_,_,_,_,_,_  ), // #63 [ref=1x]
+  O(000000,E6,_,_,_,_,_,_  ), // #64 [ref=1x]
+  O(000F3A,15,_,_,_,_,_,_  ), // #65 [ref=1x]
+  O(000000,58,_,_,_,_,_,_  ), // #66 [ref=1x]
+  O(000F00,72,6,_,_,_,_,_  ), // #67 [ref=1x]
+  O(660F00,73,7,_,_,_,_,_  ), // #68 [ref=1x]
+  O(000F00,73,6,_,_,_,_,_  ), // #69 [ref=1x]
+  O(000F00,71,6,_,_,_,_,_  ), // #70 [ref=1x]
+  O(000F00,72,4,_,_,_,_,_  ), // #71 [ref=1x]
+  O(000F00,71,4,_,_,_,_,_  ), // #72 [ref=1x]
+  O(000F00,72,2,_,_,_,_,_  ), // #73 [ref=1x]
+  O(660F00,73,3,_,_,_,_,_  ), // #74 [ref=1x]
+  O(000F00,73,2,_,_,_,_,_  ), // #75 [ref=1x]
+  O(000F00,71,2,_,_,_,_,_  ), // #76 [ref=1x]
+  O(000000,50,_,_,_,_,_,_  ), // #77 [ref=1x]
+  O(000000,F6,_,_,x,_,_,_  ), // #78 [ref=1x]
+  V(660F38,92,_,x,_,1,3,T1S), // #79 [ref=1x]
+  V(660F38,92,_,x,_,0,2,T1S), // #80 [ref=1x]
+  V(660F38,93,_,x,_,1,3,T1S), // #81 [ref=1x]
+  V(660F38,93,_,x,_,0,2,T1S), // #82 [ref=1x]
+  V(660F38,2F,_,x,0,_,_,_  ), // #83 [ref=1x]
+  V(660F38,2E,_,x,0,_,_,_  ), // #84 [ref=1x]
+  V(660F00,29,_,x,I,1,4,FVM), // #85 [ref=1x]
+  V(000F00,29,_,x,I,0,4,FVM), // #86 [ref=1x]
+  V(660F00,7E,_,0,0,0,2,T1S), // #87 [ref=1x]
+  V(660F00,7F,_,x,I,_,_,_  ), // #88 [ref=1x]
+  E(660F00,7F,_,x,_,0,4,FVM), // #89 [ref=1x]
+  E(660F00,7F,_,x,_,1,4,FVM), // #90 [ref=1x]
+  V(F30F00,7F,_,x,I,_,_,_  ), // #91 [ref=1x]
+  E(F20F00,7F,_,x,_,1,4,FVM), // #92 [ref=1x]
+  E(F30F00,7F,_,x,_,0,4,FVM), // #93 [ref=1x]
+  E(F30F00,7F,_,x,_,1,4,FVM), // #94 [ref=1x]
+  E(F20F00,7F,_,x,_,0,4,FVM), // #95 [ref=1x]
+  V(660F00,17,_,0,I,1,3,T1S), // #96 [ref=1x]
+  V(000F00,17,_,0,I,0,3,T2 ), // #97 [ref=1x]
+  V(660F00,13,_,0,I,1,3,T1S), // #98 [ref=1x]
+  V(000F00,13,_,0,I,0,3,T2 ), // #99 [ref=1x]
+  V(660F00,7E,_,0,I,1,3,T1S), // #100 [ref=1x]
+  V(F20F00,11,_,I,I,1,3,T1S), // #101 [ref=1x]
+  V(F30F00,11,_,I,I,0,2,T1S), // #102 [ref=1x]
+  V(660F00,11,_,x,I,1,4,FVM), // #103 [ref=1x]
+  V(000F00,11,_,x,I,0,4,FVM), // #104 [ref=1x]
+  E(660F38,7A,_,x,0,0,0,T1S), // #105 [ref=1x]
+  E(660F38,7C,_,x,0,0,0,T1S), // #106 [ref=1x]
+  E(660F38,7C,_,x,0,1,0,T1S), // #107 [ref=1x]
+  E(660F38,7B,_,x,0,0,0,T1S), // #108 [ref=1x]
+  V(660F3A,05,_,x,0,1,4,FV ), // #109 [ref=1x]
+  V(660F3A,04,_,x,0,0,4,FV ), // #110 [ref=1x]
+  V(660F3A,01,_,x,1,1,4,FV ), // #111 [ref=1x]
+  V(660F3A,00,_,x,1,1,4,FV ), // #112 [ref=1x]
+  V(660F38,90,_,x,_,0,2,T1S), // #113 [ref=1x]
+  V(660F38,90,_,x,_,1,3,T1S), // #114 [ref=1x]
+  V(660F38,91,_,x,_,0,2,T1S), // #115 [ref=1x]
+  V(660F38,91,_,x,_,1,3,T1S), // #116 [ref=1x]
+  V(660F38,8E,_,x,0,_,_,_  ), // #117 [ref=1x]
+  V(660F38,8E,_,x,1,_,_,_  ), // #118 [ref=1x]
+  V(XOP_M8,C0,_,0,x,_,_,_  ), // #119 [ref=1x]
+  V(XOP_M8,C2,_,0,x,_,_,_  ), // #120 [ref=1x]
+  V(XOP_M8,C3,_,0,x,_,_,_  ), // #121 [ref=1x]
+  V(XOP_M8,C1,_,0,x,_,_,_  ), // #122 [ref=1x]
+  V(660F00,72,6,x,I,0,4,FV ), // #123 [ref=1x]
+  V(660F00,73,6,x,I,1,4,FV ), // #124 [ref=1x]
+  V(660F00,71,6,x,I,I,4,FVM), // #125 [ref=1x]
+  V(660F00,72,4,x,I,0,4,FV ), // #126 [ref=1x]
+  E(660F00,72,4,x,_,1,4,FV ), // #127 [ref=1x]
+  V(660F00,71,4,x,I,I,4,FVM), // #128 [ref=1x]
+  V(660F00,72,2,x,I,0,4,FV ), // #129 [ref=1x]
+  V(660F00,73,2,x,I,1,4,FV ), // #130 [ref=1x]
+  V(660F00,71,2,x,I,I,4,FVM)  // #131 [ref=1x]
+};
+// ----------------------------------------------------------------------------
+// ${AltOpcodeTable:End}
+
+#undef O
+#undef V
+#undef E
+#undef O_FPU
+
+// ============================================================================
+// [asmjit::x86::InstDB - CommonInfoTableA]
+// ============================================================================
+
+// ${InstCommonTable:Begin}
+// ------------------- Automatically generated, do not edit -------------------
+#define F(VAL) InstDB::kFlag##VAL
+#define CONTROL(VAL) Inst::kControl##VAL
+#define SINGLE_REG(VAL) InstDB::kSingleReg##VAL
+const InstDB::CommonInfo InstDB::_commonInfoTable[] = {
+  { 0                                                     , 0  , 0 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #0 [ref=1x]
+  { 0                                                     , 347, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #1 [ref=4x]
+  { 0                                                     , 348, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #2 [ref=2x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 16 , 12, CONTROL(None)   , SINGLE_REG(None), 0 }, // #3 [ref=2x]
+  { 0                                                     , 156, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #4 [ref=2x]
+  { F(Vec)                                                , 70 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #5 [ref=54x]
+  { F(Vec)                                                , 97 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #6 [ref=19x]
+  { F(Vec)                                                , 230, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #7 [ref=16x]
+  { F(Vec)                                                , 188, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #8 [ref=20x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 28 , 11, CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #9 [ref=1x]
+  { F(Vex)                                                , 245, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #10 [ref=3x]
+  { F(Vec)                                                , 70 , 1 , CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #11 [ref=12x]
+  { 0                                                     , 349, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #12 [ref=1x]
+  { F(Vex)                                                , 247, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #13 [ref=5x]
+  { F(Vex)                                                , 156, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #14 [ref=12x]
+  { F(Vec)                                                , 350, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #15 [ref=4x]
+  { 0                                                     , 249, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #16 [ref=3x]
+  { F(Mib)                                                , 351, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #17 [ref=1x]
+  { 0                                                     , 352, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #18 [ref=1x]
+  { 0                                                     , 251, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #19 [ref=1x]
+  { F(Mib)                                                , 353, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #20 [ref=1x]
+  { 0                                                     , 253, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #21 [ref=1x]
+  { 0                                                     , 155, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #22 [ref=35x]
+  { 0                                                     , 354, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #23 [ref=3x]
+  { 0                                                     , 119, 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #24 [ref=1x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 119, 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #25 [ref=3x]
+  { F(Rep)|F(RepIgnored)                                  , 255, 2 , CONTROL(Call)   , SINGLE_REG(None), 0 }, // #26 [ref=1x]
+  { 0                                                     , 355, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #27 [ref=1x]
+  { 0                                                     , 356, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #28 [ref=2x]
+  { 0                                                     , 330, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #29 [ref=1x]
+  { 0                                                     , 99 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #30 [ref=83x]
+  { 0                                                     , 357, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #31 [ref=24x]
+  { 0                                                     , 358, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #32 [ref=6x]
+  { 0                                                     , 359, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #33 [ref=1x]
+  { 0                                                     , 16 , 12, CONTROL(None)   , SINGLE_REG(None), 0 }, // #34 [ref=1x]
+  { F(Rep)                                                , 360, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #35 [ref=1x]
+  { F(Vec)                                                , 361, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #36 [ref=2x]
+  { F(Vec)                                                , 362, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #37 [ref=3x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 123, 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #38 [ref=1x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 363, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #39 [ref=1x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 364, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #40 [ref=1x]
+  { 0                                                     , 365, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #41 [ref=1x]
+  { 0                                                     , 366, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #42 [ref=1x]
+  { 0                                                     , 257, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #43 [ref=1x]
+  { F(Mmx)|F(Vec)                                         , 367, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #44 [ref=2x]
+  { F(Mmx)|F(Vec)                                         , 368, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #45 [ref=2x]
+  { F(Mmx)|F(Vec)                                         , 369, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #46 [ref=2x]
+  { F(Vec)                                                , 370, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #47 [ref=2x]
+  { F(Vec)                                                , 371, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #48 [ref=2x]
+  { F(Vec)                                                , 372, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #49 [ref=2x]
+  { 0                                                     , 373, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #50 [ref=1x]
+  { 0                                                     , 374, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #51 [ref=2x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 259, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #52 [ref=2x]
+  { 0                                                     , 39 , 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #53 [ref=3x]
+  { F(Mmx)                                                , 99 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #54 [ref=1x]
+  { 0                                                     , 261, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #55 [ref=2x]
+  { 0                                                     , 375, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #56 [ref=1x]
+  { F(Vec)                                                , 376, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #57 [ref=2x]
+  { F(Vec)                                                , 263, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #58 [ref=1x]
+  { F(FpuM32)|F(FpuM64)                                   , 158, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #59 [ref=6x]
+  { 0                                                     , 265, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #60 [ref=9x]
+  { F(FpuM80)                                             , 377, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #61 [ref=2x]
+  { 0                                                     , 266, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #62 [ref=13x]
+  { F(FpuM32)|F(FpuM64)                                   , 267, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #63 [ref=2x]
+  { F(FpuM16)|F(FpuM32)                                   , 378, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #64 [ref=9x]
+  { F(FpuM16)|F(FpuM32)|F(FpuM64)                         , 379, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #65 [ref=3x]
+  { F(FpuM32)|F(FpuM64)|F(FpuM80)                         , 380, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #66 [ref=2x]
+  { F(FpuM16)                                             , 381, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #67 [ref=3x]
+  { F(FpuM16)                                             , 382, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #68 [ref=2x]
+  { F(FpuM32)|F(FpuM64)                                   , 268, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #69 [ref=1x]
+  { 0                                                     , 383, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #70 [ref=2x]
+  { 0                                                     , 39 , 10, CONTROL(None)   , SINGLE_REG(None), 0 }, // #71 [ref=1x]
+  { 0                                                     , 384, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #72 [ref=1x]
+  { 0                                                     , 385, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #73 [ref=2x]
+  { 0                                                     , 314, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #74 [ref=2x]
+  { F(Rep)                                                , 386, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #75 [ref=1x]
+  { F(Vec)                                                , 269, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #76 [ref=1x]
+  { 0                                                     , 387, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #77 [ref=2x]
+  { 0                                                     , 388, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #78 [ref=8x]
+  { 0                                                     , 271, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #79 [ref=3x]
+  { 0                                                     , 273, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #80 [ref=1x]
+  { 0                                                     , 99 , 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #81 [ref=3x]
+  { 0                                                     , 389, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #82 [ref=1x]
+  { F(Rep)|F(RepIgnored)                                  , 275, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #83 [ref=30x]
+  { F(Rep)|F(RepIgnored)                                  , 277, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #84 [ref=1x]
+  { F(Rep)|F(RepIgnored)                                  , 279, 2 , CONTROL(Jump)   , SINGLE_REG(None), 0 }, // #85 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 390, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #86 [ref=27x]
+  { F(Vec)|F(Vex)                                         , 281, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #87 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 283, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #88 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 285, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #89 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 287, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #90 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 391, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #91 [ref=12x]
+  { F(Vec)|F(Vex)                                         , 392, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #92 [ref=8x]
+  { 0                                                     , 393, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #93 [ref=2x]
+  { 0                                                     , 289, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #94 [ref=1x]
+  { F(Vec)                                                , 197, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #95 [ref=2x]
+  { 0                                                     , 394, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #96 [ref=2x]
+  { 0                                                     , 291, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #97 [ref=2x]
+  { F(Vex)                                                , 395, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #98 [ref=2x]
+  { 0                                                     , 396, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #99 [ref=1x]
+  { 0                                                     , 161, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #100 [ref=3x]
+  { 0                                                     , 397, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #101 [ref=5x]
+  { F(Vex)                                                , 398, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #102 [ref=2x]
+  { F(Rep)                                                , 399, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #103 [ref=1x]
+  { 0                                                     , 277, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #104 [ref=3x]
+  { 0                                                     , 293, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #105 [ref=1x]
+  { F(Vex)                                                , 400, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #106 [ref=2x]
+  { F(Vec)                                                , 401, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #107 [ref=1x]
+  { F(Mmx)                                                , 402, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #108 [ref=1x]
+  { 0                                                     , 403, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #109 [ref=2x]
+  { F(XRelease)                                           , 0  , 16, CONTROL(None)   , SINGLE_REG(None), 0 }, // #110 [ref=1x]
+  { F(Vec)                                                , 70 , 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #111 [ref=6x]
+  { 0                                                     , 64 , 6 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #112 [ref=1x]
+  { F(Mmx)|F(Vec)                                         , 295, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #113 [ref=1x]
+  { 0                                                     , 404, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #114 [ref=1x]
+  { 0                                                     , 68 , 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #115 [ref=2x]
+  { F(Mmx)|F(Vec)                                         , 405, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #116 [ref=1x]
+  { F(Vec)                                                , 264, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #117 [ref=2x]
+  { F(Vec)                                                , 203, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #118 [ref=4x]
+  { F(Vec)                                                , 406, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #119 [ref=2x]
+  { F(Vec)                                                , 71 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #120 [ref=3x]
+  { F(Mmx)                                                , 407, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #121 [ref=1x]
+  { F(Vec)                                                , 98 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #122 [ref=1x]
+  { F(Vec)                                                , 206, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #123 [ref=1x]
+  { F(Mmx)|F(Vec)                                         , 94 , 5 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #124 [ref=1x]
+  { F(Mmx)|F(Vec)                                         , 408, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #125 [ref=1x]
+  { F(Rep)                                                , 409, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #126 [ref=1x]
+  { F(Vec)                                                , 97 , 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #127 [ref=1x]
+  { F(Vec)                                                , 297, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #128 [ref=1x]
+  { 0                                                     , 299, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #129 [ref=2x]
+  { 0                                                     , 301, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #130 [ref=1x]
+  { F(Vex)                                                , 303, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #131 [ref=1x]
+  { 0                                                     , 410, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #132 [ref=1x]
+  { 0                                                     , 411, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #133 [ref=1x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 260, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #134 [ref=2x]
+  { 0                                                     , 99 , 5 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #135 [ref=1x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 16 , 12, CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #136 [ref=1x]
+  { 0                                                     , 412, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #137 [ref=1x]
+  { F(Rep)                                                , 413, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #138 [ref=1x]
+  { F(Mmx)|F(Vec)                                         , 305, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #139 [ref=40x]
+  { F(Mmx)|F(Vec)                                         , 307, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #140 [ref=1x]
+  { F(Mmx)|F(Vec)                                         , 305, 2 , CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #141 [ref=6x]
+  { F(Mmx)|F(Vec)                                         , 305, 2 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #142 [ref=16x]
+  { F(Mmx)                                                , 305, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #143 [ref=26x]
+  { F(Vec)                                                , 70 , 1 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #144 [ref=4x]
+  { F(Vec)                                                , 414, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #145 [ref=1x]
+  { F(Vec)                                                , 415, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #146 [ref=1x]
+  { F(Vec)                                                , 416, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #147 [ref=1x]
+  { F(Vec)                                                , 417, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #148 [ref=1x]
+  { F(Vec)                                                , 418, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #149 [ref=1x]
+  { F(Vec)                                                , 419, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #150 [ref=1x]
+  { F(Mmx)|F(Vec)                                         , 309, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #151 [ref=1x]
+  { F(Vec)                                                , 420, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #152 [ref=1x]
+  { F(Vec)                                                , 421, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #153 [ref=1x]
+  { F(Vec)                                                , 422, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #154 [ref=1x]
+  { F(Mmx)|F(Vec)                                         , 423, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #155 [ref=1x]
+  { F(Mmx)|F(Vec)                                         , 424, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #156 [ref=1x]
+  { F(Vec)                                                , 233, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #157 [ref=2x]
+  { 0                                                     , 127, 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #158 [ref=1x]
+  { 0                                                     , 389, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #159 [ref=9x]
+  { F(Mmx)                                                , 307, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #160 [ref=1x]
+  { F(Mmx)|F(Vec)                                         , 311, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #161 [ref=8x]
+  { F(Vec)                                                , 425, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #162 [ref=2x]
+  { 0                                                     , 426, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #163 [ref=1x]
+  { 0                                                     , 131, 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #164 [ref=1x]
+  { 0                                                     , 427, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #165 [ref=8x]
+  { 0                                                     , 428, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #166 [ref=4x]
+  { 0                                                     , 429, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #167 [ref=8x]
+  { 0                                                     , 313, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #168 [ref=1x]
+  { F(Rep)|F(RepIgnored)                                  , 315, 2 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #169 [ref=1x]
+  { F(Vex)                                                , 317, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #170 [ref=1x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 16 , 12, CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #171 [ref=3x]
+  { F(Rep)                                                , 430, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #172 [ref=1x]
+  { 0                                                     , 431, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #173 [ref=30x]
+  { 0                                                     , 164, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #174 [ref=2x]
+  { 0                                                     , 432, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #175 [ref=3x]
+  { F(Rep)                                                , 433, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #176 [ref=1x]
+  { F(Vex)                                                , 434, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #177 [ref=5x]
+  { 0                                                     , 57 , 7 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #178 [ref=1x]
+  { F(Tsib)|F(Vex)                                        , 435, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #179 [ref=2x]
+  { F(Vex)                                                , 389, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #180 [ref=1x]
+  { F(Tsib)|F(Vex)                                        , 436, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #181 [ref=1x]
+  { F(Vex)                                                , 437, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #182 [ref=1x]
+  { 0                                                     , 438, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #183 [ref=2x]
+  { 0                                                     , 439, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #184 [ref=2x]
+  { 0                                                     , 440, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #185 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ)               , 441, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #186 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ)               , 442, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #187 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64)          , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #188 [ref=22x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32)          , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #189 [ref=22x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE)              , 443, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #190 [ref=18x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE)              , 444, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #191 [ref=17x]
+  { F(Vec)|F(Vex)                                         , 167, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #192 [ref=15x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #193 [ref=5x]
+  { F(Vec)|F(Vex)                                         , 70 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #194 [ref=17x]
+  { F(Vec)|F(Vex)                                         , 188, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #195 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B32)                        , 170, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #196 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B64)                        , 170, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #197 [ref=4x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64)                 , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #198 [ref=10x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32)                 , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #199 [ref=12x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64)                 , 167, 3 , CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #200 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32)                 , 167, 3 , CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #201 [ref=6x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #202 [ref=13x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B32)                        , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #203 [ref=16x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B64)                        , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #204 [ref=19x]
+  { F(Vec)|F(Vex)                                         , 170, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #205 [ref=6x]
+  { F(Vec)|F(Vex)                                         , 319, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #206 [ref=3x]
+  { F(Vec)|F(Vex)                                         , 445, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #207 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 446, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #208 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 447, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #209 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 448, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #210 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 449, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #211 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 446, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #212 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 450, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #213 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64)             , 173, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #214 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32)             , 173, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #215 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE)                 , 451, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #216 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE)                 , 452, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #217 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE)                    , 97 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #218 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE)                    , 230, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #219 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 176, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #220 [ref=6x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32)                 , 179, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #221 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32)          , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #222 [ref=3x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B32)                        , 321, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #223 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64)          , 321, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #224 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64)                 , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #225 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64)                 , 321, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #226 [ref=3x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE)                 , 179, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #227 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32)          , 179, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #228 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE)                 , 185, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #229 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32)                 , 179, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #230 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32)                 , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #231 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE)                 , 370, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #232 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512ER_SAE)                        , 370, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #233 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE)                 , 453, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #234 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE)                 , 444, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #235 [ref=3x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE)                 , 372, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #236 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512ER_SAE)                        , 372, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #237 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64)             , 321, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #238 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64)                    , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #239 [ref=3x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64)                    , 321, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #240 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32)             , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #241 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32)                    , 179, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #242 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32)                    , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #243 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE)                    , 370, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #244 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512SAE)                           , 370, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #245 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE)                    , 372, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #246 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512SAE)                           , 372, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #247 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B32)                        , 179, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #248 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512ER_SAE)                        , 453, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #249 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 170, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #250 [ref=3x]
+  { F(Vec)|F(Vex)                                         , 170, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #251 [ref=9x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64)                    , 74 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #252 [ref=3x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32)                    , 74 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #253 [ref=3x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #254 [ref=9x]
+  { F(Vec)|F(Vex)                                         , 186, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #255 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 454, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #256 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 187, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #257 [ref=4x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 376, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #258 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64)                    , 170, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #259 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32)                    , 170, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #260 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE)                        , 455, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #261 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE)                        , 456, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #262 [ref=4x]
+  { F(Vec)|F(Vex)                                         , 135, 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #263 [ref=13x]
+  { F(Vec)|F(Vex)                                         , 323, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #264 [ref=4x]
+  { F(Vec)|F(Vex)                                         , 325, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #265 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512K_B64)                         , 457, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #266 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512K_B32)                         , 457, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #267 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512K)                             , 458, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #268 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512K)                             , 459, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #269 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 182, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #270 [ref=7x]
+  { F(Vec)|F(Vex)                                         , 97 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #271 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 230, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #272 [ref=1x]
+  { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)              , 104, 5 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #273 [ref=2x]
+  { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)              , 109, 5 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #274 [ref=2x]
+  { F(Vsib)|F(Evex)|F(Avx512K)                            , 460, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #275 [ref=4x]
+  { F(Vsib)|F(Evex)|F(Avx512K)                            , 461, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #276 [ref=4x]
+  { F(Vsib)|F(Evex)|F(Avx512K)                            , 462, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #277 [ref=8x]
+  { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)              , 114, 5 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #278 [ref=2x]
+  { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)              , 139, 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #279 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE)                        , 443, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #280 [ref=3x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE)                        , 444, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #281 [ref=3x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64)                    , 188, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #282 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32)                    , 188, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #283 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 170, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #284 [ref=3x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #285 [ref=22x]
+  { F(Vec)|F(Vex)                                         , 327, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #286 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 327, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #287 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 463, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #288 [ref=4x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 456, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #289 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 197, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #290 [ref=1x]
+  { F(Vex)                                                , 394, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #291 [ref=2x]
+  { F(Vec)|F(Vex)                                         , 401, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #292 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 143, 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #293 [ref=4x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64)             , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #294 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32)             , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #295 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE)                 , 443, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #296 [ref=2x]
+  { 0                                                     , 329, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #297 [ref=3x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 70 , 6 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #298 [ref=4x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 331, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #299 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 191, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #300 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 70 , 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #301 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 70 , 6 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #302 [ref=6x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 205, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #303 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 333, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #304 [ref=4x]
+  { F(Vec)|F(Vex)                                         , 464, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #305 [ref=3x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 194, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #306 [ref=3x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 197, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #307 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 200, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #308 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 203, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #309 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #310 [ref=5x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 206, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #311 [ref=1x]
+  { 0                                                     , 335, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #312 [ref=1x]
+  { 0                                                     , 337, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #313 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512B32)                           , 209, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #314 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512B64)                           , 209, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #315 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 167, 2 , CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #316 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B32)                        , 167, 3 , CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #317 [ref=2x]
+  { F(Vec)|F(Vex)                                         , 167, 2 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #318 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B32)                        , 167, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #319 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B64)                        , 167, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #320 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B64)                        , 167, 3 , CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #321 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 465, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #322 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 466, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #323 [ref=1x]
+  { F(Vec)|F(Evex)                                        , 467, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #324 [ref=6x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 212, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #325 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 468, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #326 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 170, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #327 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512K)                             , 215, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #328 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512K_B32)                         , 215, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #329 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512K)                      , 218, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #330 [ref=4x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B32)                  , 218, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #331 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B64)                  , 218, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #332 [ref=2x]
+  { F(Vec)|F(Vex)                                         , 414, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #333 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 415, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #334 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 416, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #335 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 417, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #336 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512K_B64)                         , 215, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #337 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B32)                        , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #338 [ref=6x]
+  { F(Vec)|F(Vex)                                         , 171, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #339 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32)                 , 168, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #340 [ref=2x]
+  { F(Vec)|F(Vex)                                         , 147, 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #341 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64)                 , 76 , 6 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #342 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64)                 , 151, 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #343 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 418, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #344 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 419, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #345 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 469, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #346 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 470, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #347 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 471, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #348 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 472, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #349 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 473, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #350 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B64)                        , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #351 [ref=4x]
+  { F(Vec)|F(Vex)                                         , 319, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #352 [ref=12x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 167, 3 , CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #353 [ref=8x]
+  { F(Vec)|F(Evex)                                        , 474, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #354 [ref=4x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 221, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #355 [ref=6x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 224, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #356 [ref=9x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 227, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #357 [ref=3x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 230, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #358 [ref=4x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 233, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #359 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 179, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #360 [ref=6x]
+  { F(Vec)|F(Vex)                                         , 135, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #361 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B32)                        , 188, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #362 [ref=3x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B64)                        , 188, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #363 [ref=3x]
+  { F(Vec)|F(Vex)                                         , 339, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #364 [ref=4x]
+  { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K)                     , 236, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #365 [ref=3x]
+  { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K)                     , 341, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #366 [ref=2x]
+  { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K)                     , 239, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #367 [ref=2x]
+  { F(Vec)|F(Vex)                                         , 343, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #368 [ref=8x]
+  { F(Vec)|F(Evex)|F(Avx512K)                             , 242, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #369 [ref=5x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32)                 , 188, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #370 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 188, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #371 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32)                 , 82 , 6 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #372 [ref=3x]
+  { F(Vec)|F(Vex)|F(Evex)                                 , 188, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #373 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64)                 , 82 , 6 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #374 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 82 , 6 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #375 [ref=3x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B64)                        , 88 , 6 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #376 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)                     , 167, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #377 [ref=6x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32)                 , 167, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #378 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64)                 , 167, 3 , CONTROL(None)   , SINGLE_REG(WO)  , 0 }, // #379 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512K_B32)                         , 242, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #380 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512K_B64)                         , 242, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #381 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 443, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #382 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 444, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #383 [ref=2x]
+  { F(Vec)|F(Vex)                                         , 444, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #384 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 455, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #385 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ)                            , 456, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #386 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 188, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #387 [ref=2x]
+  { F(Vec)|F(Vex)                                         , 455, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #388 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 456, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #389 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64)                 , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #390 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32)                 , 167, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #391 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE)                     , 443, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #392 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE)                     , 444, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #393 [ref=1x]
+  { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K)                     , 345, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #394 [ref=1x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B32)                        , 171, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #395 [ref=2x]
+  { F(Vec)|F(Evex)|F(Avx512KZ_B64)                        , 171, 2 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #396 [ref=2x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32)                 , 170, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #397 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64)                 , 170, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #398 [ref=1x]
+  { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64)          , 182, 3 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #399 [ref=1x]
+  { F(Vec)|F(Vex)                                         , 99 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #400 [ref=2x]
+  { 0                                                     , 23 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #401 [ref=2x]
+  { 0                                                     , 52 , 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #402 [ref=2x]
+  { F(Lock)|F(XAcquire)|F(XRelease)                       , 49 , 4 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #403 [ref=1x]
+  { 0                                                     , 475, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #404 [ref=1x]
+  { F(Lock)|F(XAcquire)                                   , 49 , 8 , CONTROL(None)   , SINGLE_REG(RO)  , 0 }, // #405 [ref=1x]
+  { 0                                                     , 476, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }, // #406 [ref=6x]
+  { 0                                                     , 477, 1 , CONTROL(None)   , SINGLE_REG(None), 0 }  // #407 [ref=6x]
+};
+#undef SINGLE_REG
+#undef CONTROL
+#undef F
+// ----------------------------------------------------------------------------
+// ${InstCommonTable:End}
+
+// ============================================================================
+// [asmjit::x86::InstDB - CommonInfoTableB]
+// ============================================================================
+
+// ${InstCommonInfoTableB:Begin}
+// ------------------- Automatically generated, do not edit -------------------
+#define EXT(VAL) uint32_t(Features::k##VAL)
+const InstDB::CommonInfoTableB InstDB::_commonInfoTableB[] = {
+  { { 0 }, 0, 0 }, // #0 [ref=146x]
+  { { 0 }, 1, 0 }, // #1 [ref=32x]
+  { { 0 }, 2, 0 }, // #2 [ref=2x]
+  { { EXT(ADX) }, 3, 0 }, // #3 [ref=1x]
+  { { EXT(SSE2) }, 0, 0 }, // #4 [ref=65x]
+  { { EXT(SSE) }, 0, 0 }, // #5 [ref=44x]
+  { { EXT(SSE3) }, 0, 0 }, // #6 [ref=12x]
+  { { EXT(ADX) }, 4, 0 }, // #7 [ref=1x]
+  { { EXT(AESNI) }, 0, 0 }, // #8 [ref=6x]
+  { { EXT(BMI) }, 1, 0 }, // #9 [ref=6x]
+  { { 0 }, 5, 0 }, // #10 [ref=5x]
+  { { EXT(TBM) }, 0, 0 }, // #11 [ref=9x]
+  { { EXT(SSE4_1) }, 0, 0 }, // #12 [ref=47x]
+  { { EXT(MPX) }, 0, 0 }, // #13 [ref=7x]
+  { { 0 }, 6, 0 }, // #14 [ref=4x]
+  { { EXT(BMI2) }, 1, 0 }, // #15 [ref=1x]
+  { { EXT(SMAP) }, 7, 0 }, // #16 [ref=2x]
+  { { 0 }, 8, 0 }, // #17 [ref=2x]
+  { { 0 }, 9, 0 }, // #18 [ref=2x]
+  { { EXT(CLDEMOTE) }, 0, 0 }, // #19 [ref=1x]
+  { { EXT(CLFLUSH) }, 0, 0 }, // #20 [ref=1x]
+  { { EXT(CLFLUSHOPT) }, 0, 0 }, // #21 [ref=1x]
+  { { EXT(SVM) }, 0, 0 }, // #22 [ref=6x]
+  { { 0 }, 10, 0 }, // #23 [ref=2x]
+  { { EXT(CET_SS) }, 1, 0 }, // #24 [ref=3x]
+  { { EXT(CLWB) }, 0, 0 }, // #25 [ref=1x]
+  { { EXT(CLZERO) }, 0, 0 }, // #26 [ref=1x]
+  { { 0 }, 3, 0 }, // #27 [ref=1x]
+  { { EXT(CMOV) }, 11, 0 }, // #28 [ref=6x]
+  { { EXT(CMOV) }, 12, 0 }, // #29 [ref=8x]
+  { { EXT(CMOV) }, 13, 0 }, // #30 [ref=6x]
+  { { EXT(CMOV) }, 14, 0 }, // #31 [ref=4x]
+  { { EXT(CMOV) }, 15, 0 }, // #32 [ref=4x]
+  { { EXT(CMOV) }, 16, 0 }, // #33 [ref=2x]
+  { { EXT(CMOV) }, 17, 0 }, // #34 [ref=6x]
+  { { EXT(CMOV) }, 18, 0 }, // #35 [ref=2x]
+  { { 0 }, 19, 0 }, // #36 [ref=2x]
+  { { EXT(I486) }, 1, 0 }, // #37 [ref=2x]
+  { { EXT(CMPXCHG16B) }, 5, 0 }, // #38 [ref=1x]
+  { { EXT(CMPXCHG8B) }, 5, 0 }, // #39 [ref=1x]
+  { { EXT(SSE2) }, 1, 0 }, // #40 [ref=2x]
+  { { EXT(SSE) }, 1, 0 }, // #41 [ref=2x]
+  { { EXT(I486) }, 0, 0 }, // #42 [ref=4x]
+  { { EXT(SSE4_2) }, 0, 0 }, // #43 [ref=2x]
+  { { 0 }, 20, 0 }, // #44 [ref=2x]
+  { { EXT(MMX) }, 0, 0 }, // #45 [ref=1x]
+  { { EXT(CET_IBT) }, 0, 0 }, // #46 [ref=2x]
+  { { EXT(ENQCMD) }, 0, 0 }, // #47 [ref=2x]
+  { { EXT(SSE4A) }, 0, 0 }, // #48 [ref=4x]
+  { { 0 }, 21, 0 }, // #49 [ref=4x]
+  { { EXT(3DNOW) }, 0, 0 }, // #50 [ref=21x]
+  { { EXT(FXSR) }, 0, 0 }, // #51 [ref=4x]
+  { { EXT(SMX) }, 0, 0 }, // #52 [ref=1x]
+  { { EXT(GFNI) }, 0, 0 }, // #53 [ref=3x]
+  { { EXT(CET_SS) }, 0, 0 }, // #54 [ref=9x]
+  { { 0 }, 16, 0 }, // #55 [ref=5x]
+  { { EXT(VMX) }, 0, 0 }, // #56 [ref=12x]
+  { { 0 }, 11, 0 }, // #57 [ref=8x]
+  { { 0 }, 12, 0 }, // #58 [ref=12x]
+  { { 0 }, 13, 0 }, // #59 [ref=10x]
+  { { 0 }, 14, 0 }, // #60 [ref=8x]
+  { { 0 }, 15, 0 }, // #61 [ref=8x]
+  { { 0 }, 17, 0 }, // #62 [ref=8x]
+  { { 0 }, 18, 0 }, // #63 [ref=4x]
+  { { EXT(AVX512_DQ) }, 0, 0 }, // #64 [ref=23x]
+  { { EXT(AVX512_BW) }, 0, 0 }, // #65 [ref=22x]
+  { { EXT(AVX512_F) }, 0, 0 }, // #66 [ref=37x]
+  { { EXT(AVX512_DQ) }, 1, 0 }, // #67 [ref=3x]
+  { { EXT(AVX512_BW) }, 1, 0 }, // #68 [ref=4x]
+  { { EXT(AVX512_F) }, 1, 0 }, // #69 [ref=1x]
+  { { EXT(LAHFSAHF) }, 22, 0 }, // #70 [ref=1x]
+  { { EXT(AMX_TILE) }, 0, 0 }, // #71 [ref=7x]
+  { { EXT(LWP) }, 0, 0 }, // #72 [ref=4x]
+  { { 0 }, 23, 0 }, // #73 [ref=3x]
+  { { EXT(LZCNT) }, 1, 0 }, // #74 [ref=1x]
+  { { EXT(MMX2) }, 0, 0 }, // #75 [ref=8x]
+  { { EXT(MCOMMIT) }, 1, 0 }, // #76 [ref=1x]
+  { { EXT(MONITOR) }, 0, 0 }, // #77 [ref=2x]
+  { { EXT(MONITORX) }, 0, 0 }, // #78 [ref=2x]
+  { { EXT(MOVBE) }, 0, 0 }, // #79 [ref=1x]
+  { { EXT(MMX), EXT(SSE2) }, 0, 0 }, // #80 [ref=46x]
+  { { EXT(MOVDIR64B) }, 0, 0 }, // #81 [ref=1x]
+  { { EXT(MOVDIRI) }, 0, 0 }, // #82 [ref=1x]
+  { { EXT(BMI2) }, 0, 0 }, // #83 [ref=7x]
+  { { EXT(SSSE3) }, 0, 0 }, // #84 [ref=15x]
+  { { EXT(MMX2), EXT(SSE2) }, 0, 0 }, // #85 [ref=10x]
+  { { EXT(PCLMULQDQ) }, 0, 0 }, // #86 [ref=1x]
+  { { EXT(SSE4_2) }, 1, 0 }, // #87 [ref=4x]
+  { { EXT(PCONFIG) }, 0, 0 }, // #88 [ref=1x]
+  { { EXT(MMX2), EXT(SSE2), EXT(SSE4_1) }, 0, 0 }, // #89 [ref=1x]
+  { { EXT(3DNOW2) }, 0, 0 }, // #90 [ref=5x]
+  { { EXT(GEODE) }, 0, 0 }, // #91 [ref=2x]
+  { { EXT(POPCNT) }, 1, 0 }, // #92 [ref=1x]
+  { { 0 }, 24, 0 }, // #93 [ref=3x]
+  { { EXT(PREFETCHW) }, 1, 0 }, // #94 [ref=1x]
+  { { EXT(PREFETCHWT1) }, 1, 0 }, // #95 [ref=1x]
+  { { EXT(SNP) }, 20, 0 }, // #96 [ref=3x]
+  { { EXT(SSE4_1) }, 1, 0 }, // #97 [ref=1x]
+  { { EXT(PTWRITE) }, 0, 0 }, // #98 [ref=1x]
+  { { 0 }, 25, 0 }, // #99 [ref=3x]
+  { { EXT(SNP) }, 1, 0 }, // #100 [ref=1x]
+  { { 0 }, 26, 0 }, // #101 [ref=2x]
+  { { EXT(FSGSBASE) }, 0, 0 }, // #102 [ref=4x]
+  { { EXT(MSR) }, 0, 0 }, // #103 [ref=2x]
+  { { EXT(RDPID) }, 0, 0 }, // #104 [ref=1x]
+  { { EXT(OSPKE) }, 0, 0 }, // #105 [ref=1x]
+  { { EXT(RDPRU) }, 0, 0 }, // #106 [ref=1x]
+  { { EXT(RDRAND) }, 1, 0 }, // #107 [ref=1x]
+  { { EXT(RDSEED) }, 1, 0 }, // #108 [ref=1x]
+  { { EXT(RDTSC) }, 0, 0 }, // #109 [ref=1x]
+  { { EXT(RDTSCP) }, 0, 0 }, // #110 [ref=1x]
+  { { 0 }, 27, 0 }, // #111 [ref=2x]
+  { { EXT(LAHFSAHF) }, 28, 0 }, // #112 [ref=1x]
+  { { EXT(SERIALIZE) }, 0, 0 }, // #113 [ref=1x]
+  { { EXT(SHA) }, 0, 0 }, // #114 [ref=7x]
+  { { EXT(SKINIT) }, 0, 0 }, // #115 [ref=2x]
+  { { EXT(AMX_BF16) }, 0, 0 }, // #116 [ref=1x]
+  { { EXT(AMX_INT8) }, 0, 0 }, // #117 [ref=4x]
+  { { EXT(WAITPKG) }, 1, 0 }, // #118 [ref=2x]
+  { { EXT(WAITPKG) }, 0, 0 }, // #119 [ref=1x]
+  { { EXT(AVX512_4FMAPS) }, 0, 0 }, // #120 [ref=4x]
+  { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #121 [ref=46x]
+  { { EXT(AVX), EXT(AVX512_F) }, 0, 0 }, // #122 [ref=32x]
+  { { EXT(AVX) }, 0, 0 }, // #123 [ref=37x]
+  { { EXT(AESNI), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(VAES) }, 0, 0 }, // #124 [ref=4x]
+  { { EXT(AESNI), EXT(AVX) }, 0, 0 }, // #125 [ref=2x]
+  { { EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #126 [ref=112x]
+  { { EXT(AVX), EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #127 [ref=8x]
+  { { EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #128 [ref=26x]
+  { { EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #129 [ref=30x]
+  { { EXT(AVX2) }, 0, 0 }, // #130 [ref=7x]
+  { { EXT(AVX), EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #131 [ref=39x]
+  { { EXT(AVX), EXT(AVX512_F) }, 1, 0 }, // #132 [ref=4x]
+  { { EXT(AVX512_BF16), EXT(AVX512_VL) }, 0, 0 }, // #133 [ref=3x]
+  { { EXT(AVX512_F), EXT(AVX512_VL), EXT(F16C) }, 0, 0 }, // #134 [ref=2x]
+  { { EXT(AVX512_ERI) }, 0, 0 }, // #135 [ref=10x]
+  { { EXT(AVX512_F), EXT(AVX512_VL), EXT(FMA) }, 0, 0 }, // #136 [ref=36x]
+  { { EXT(AVX512_F), EXT(FMA) }, 0, 0 }, // #137 [ref=24x]
+  { { EXT(FMA4) }, 0, 0 }, // #138 [ref=20x]
+  { { EXT(XOP) }, 0, 0 }, // #139 [ref=55x]
+  { { EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #140 [ref=19x]
+  { { EXT(AVX512_PFI) }, 0, 0 }, // #141 [ref=16x]
+  { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(GFNI) }, 0, 0 }, // #142 [ref=3x]
+  { { EXT(AVX), EXT(AVX2) }, 0, 0 }, // #143 [ref=17x]
+  { { EXT(AVX512_VP2INTERSECT) }, 0, 0 }, // #144 [ref=2x]
+  { { EXT(AVX512_4VNNIW) }, 0, 0 }, // #145 [ref=2x]
+  { { EXT(AVX), EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #146 [ref=54x]
+  { { EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #147 [ref=2x]
+  { { EXT(AVX512_CDI), EXT(AVX512_VL) }, 0, 0 }, // #148 [ref=6x]
+  { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(PCLMULQDQ), EXT(VPCLMULQDQ) }, 0, 0 }, // #149 [ref=1x]
+  { { EXT(AVX) }, 1, 0 }, // #150 [ref=7x]
+  { { EXT(AVX512_VBMI2), EXT(AVX512_VL) }, 0, 0 }, // #151 [ref=16x]
+  { { EXT(AVX512_VL), EXT(AVX512_VNNI) }, 0, 0 }, // #152 [ref=4x]
+  { { EXT(AVX512_VBMI), EXT(AVX512_VL) }, 0, 0 }, // #153 [ref=4x]
+  { { EXT(AVX), EXT(AVX512_BW) }, 0, 0 }, // #154 [ref=4x]
+  { { EXT(AVX), EXT(AVX512_DQ) }, 0, 0 }, // #155 [ref=4x]
+  { { EXT(AVX512_IFMA), EXT(AVX512_VL) }, 0, 0 }, // #156 [ref=2x]
+  { { EXT(AVX512_BITALG), EXT(AVX512_VL) }, 0, 0 }, // #157 [ref=3x]
+  { { EXT(AVX512_VL), EXT(AVX512_VPOPCNTDQ) }, 0, 0 }, // #158 [ref=2x]
+  { { EXT(WBNOINVD) }, 0, 0 }, // #159 [ref=1x]
+  { { EXT(RTM) }, 0, 0 }, // #160 [ref=3x]
+  { { EXT(XSAVE) }, 0, 0 }, // #161 [ref=6x]
+  { { EXT(TSXLDTRK) }, 0, 0 }, // #162 [ref=2x]
+  { { EXT(XSAVES) }, 0, 0 }, // #163 [ref=4x]
+  { { EXT(XSAVEC) }, 0, 0 }, // #164 [ref=2x]
+  { { EXT(XSAVEOPT) }, 0, 0 }, // #165 [ref=2x]
+  { { EXT(TSX) }, 1, 0 }  // #166 [ref=1x]
+};
+#undef EXT
+
+#define FLAG(VAL) uint32_t(Status::k##VAL)
+const InstDB::RWFlagsInfoTable InstDB::_rwFlagsInfoTable[] = {
+  { 0, 0 }, // #0 [ref=1315x]
+  { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #1 [ref=83x]
+  { FLAG(CF), FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #2 [ref=2x]
+  { FLAG(CF), FLAG(CF) }, // #3 [ref=2x]
+  { FLAG(OF), FLAG(OF) }, // #4 [ref=1x]
+  { 0, FLAG(ZF) }, // #5 [ref=7x]
+  { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) }, // #6 [ref=4x]
+  { 0, FLAG(AC) }, // #7 [ref=2x]
+  { 0, FLAG(CF) }, // #8 [ref=2x]
+  { 0, FLAG(DF) }, // #9 [ref=2x]
+  { 0, FLAG(IF) }, // #10 [ref=2x]
+  { FLAG(CF) | FLAG(ZF), 0 }, // #11 [ref=14x]
+  { FLAG(CF), 0 }, // #12 [ref=20x]
+  { FLAG(ZF), 0 }, // #13 [ref=16x]
+  { FLAG(OF) | FLAG(SF) | FLAG(ZF), 0 }, // #14 [ref=12x]
+  { FLAG(OF) | FLAG(SF), 0 }, // #15 [ref=12x]
+  { FLAG(OF), 0 }, // #16 [ref=7x]
+  { FLAG(PF), 0 }, // #17 [ref=14x]
+  { FLAG(SF), 0 }, // #18 [ref=6x]
+  { FLAG(DF), FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #19 [ref=2x]
+  { 0, FLAG(AF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #20 [ref=5x]
+  { 0, FLAG(CF) | FLAG(PF) | FLAG(ZF) }, // #21 [ref=4x]
+  { FLAG(AF) | FLAG(CF) | FLAG(PF) | FLAG(SF) | FLAG(ZF), 0 }, // #22 [ref=1x]
+  { FLAG(DF), 0 }, // #23 [ref=3x]
+  { 0, FLAG(AF) | FLAG(CF) | FLAG(DF) | FLAG(IF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #24 [ref=3x]
+  { FLAG(AF) | FLAG(CF) | FLAG(DF) | FLAG(IF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF), 0 }, // #25 [ref=3x]
+  { FLAG(CF) | FLAG(OF), FLAG(CF) | FLAG(OF) }, // #26 [ref=2x]
+  { 0, FLAG(CF) | FLAG(OF) }, // #27 [ref=2x]
+  { 0, FLAG(AF) | FLAG(CF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }  // #28 [ref=1x]
+};
+#undef FLAG
+// ----------------------------------------------------------------------------
+// ${InstCommonInfoTableB:End}
+
+// ============================================================================
+// [asmjit::Inst - NameData]
+// ============================================================================
+
+#ifndef ASMJIT_NO_TEXT
+// ${NameData:Begin}
+// ------------------- Automatically generated, do not edit -------------------
+const char InstDB::_nameData[] =
+  "\0" "aaa\0" "aad\0" "aam\0" "aas\0" "adc\0" "adcx\0" "adox\0" "arpl\0" "bextr\0" "blcfill\0" "blci\0" "blcic\0"
+  "blcmsk\0" "blcs\0" "blsfill\0" "blsi\0" "blsic\0" "blsmsk\0" "blsr\0" "bndcl\0" "bndcn\0" "bndcu\0" "bndldx\0"
+  "bndmk\0" "bndmov\0" "bndstx\0" "bound\0" "bsf\0" "bsr\0" "bswap\0" "bt\0" "btc\0" "btr\0" "bts\0" "bzhi\0" "cbw\0"
+  "cdq\0" "cdqe\0" "clac\0" "clc\0" "cld\0" "cldemote\0" "clflush\0" "clflushopt\0" "clgi\0" "cli\0" "clrssbsy\0"
+  "clts\0" "clwb\0" "clzero\0" "cmc\0" "cmova\0" "cmovae\0" "cmovc\0" "cmovg\0" "cmovge\0" "cmovl\0" "cmovle\0"
+  "cmovna\0" "cmovnae\0" "cmovnc\0" "cmovng\0" "cmovnge\0" "cmovnl\0" "cmovnle\0" "cmovno\0" "cmovnp\0" "cmovns\0"
+  "cmovnz\0" "cmovo\0" "cmovp\0" "cmovpe\0" "cmovpo\0" "cmovs\0" "cmovz\0" "cmp\0" "cmps\0" "cmpxchg\0" "cmpxchg16b\0"
+  "cmpxchg8b\0" "cpuid\0" "cqo\0" "crc32\0" "cvtpd2pi\0" "cvtpi2pd\0" "cvtpi2ps\0" "cvtps2pi\0" "cvttpd2pi\0"
+  "cvttps2pi\0" "cwd\0" "cwde\0" "daa\0" "das\0" "endbr32\0" "endbr64\0" "enqcmd\0" "enqcmds\0" "f2xm1\0" "fabs\0"
+  "faddp\0" "fbld\0" "fbstp\0" "fchs\0" "fclex\0" "fcmovb\0" "fcmovbe\0" "fcmove\0" "fcmovnb\0" "fcmovnbe\0"
+  "fcmovne\0" "fcmovnu\0" "fcmovu\0" "fcom\0" "fcomi\0" "fcomip\0" "fcomp\0" "fcompp\0" "fcos\0" "fdecstp\0" "fdiv\0"
+  "fdivp\0" "fdivr\0" "fdivrp\0" "femms\0" "ffree\0" "fiadd\0" "ficom\0" "ficomp\0" "fidiv\0" "fidivr\0" "fild\0"
+  "fimul\0" "fincstp\0" "finit\0" "fist\0" "fistp\0" "fisttp\0" "fisub\0" "fisubr\0" "fld\0" "fld1\0" "fldcw\0"
+  "fldenv\0" "fldl2e\0" "fldl2t\0" "fldlg2\0" "fldln2\0" "fldpi\0" "fldz\0" "fmulp\0" "fnclex\0" "fninit\0" "fnop\0"
+  "fnsave\0" "fnstcw\0" "fnstenv\0" "fnstsw\0" "fpatan\0" "fprem\0" "fprem1\0" "fptan\0" "frndint\0" "frstor\0"
+  "fsave\0" "fscale\0" "fsin\0" "fsincos\0" "fsqrt\0" "fst\0" "fstcw\0" "fstenv\0" "fstp\0" "fstsw\0" "fsubp\0"
+  "fsubrp\0" "ftst\0" "fucom\0" "fucomi\0" "fucomip\0" "fucomp\0" "fucompp\0" "fwait\0" "fxam\0" "fxch\0" "fxrstor\0"
+  "fxrstor64\0" "fxsave\0" "fxsave64\0" "fxtract\0" "fyl2x\0" "fyl2xp1\0" "getsec\0" "hlt\0" "inc\0" "incsspd\0"
+  "incsspq\0" "insertq\0" "int3\0" "into\0" "invept\0" "invlpg\0" "invlpga\0" "invpcid\0" "invvpid\0" "iret\0"
+  "iretd\0" "iretq\0" "iretw\0" "ja\0" "jae\0" "jb\0" "jbe\0" "jc\0" "je\0" "jecxz\0" "jg\0" "jge\0" "jl\0" "jle\0"
+  "jmp\0" "jna\0" "jnae\0" "jnb\0" "jnbe\0" "jnc\0" "jne\0" "jng\0" "jnge\0" "jnl\0" "jnle\0" "jno\0" "jnp\0" "jns\0"
+  "jnz\0" "jo\0" "jp\0" "jpe\0" "jpo\0" "js\0" "jz\0" "kaddb\0" "kaddd\0" "kaddq\0" "kaddw\0" "kandb\0" "kandd\0"
+  "kandnb\0" "kandnd\0" "kandnq\0" "kandnw\0" "kandq\0" "kandw\0" "kmovb\0" "kmovw\0" "knotb\0" "knotd\0" "knotq\0"
+  "knotw\0" "korb\0" "kord\0" "korq\0" "kortestb\0" "kortestd\0" "kortestq\0" "kortestw\0" "korw\0" "kshiftlb\0"
+  "kshiftld\0" "kshiftlq\0" "kshiftlw\0" "kshiftrb\0" "kshiftrd\0" "kshiftrq\0" "kshiftrw\0" "ktestb\0" "ktestd\0"
+  "ktestq\0" "ktestw\0" "kunpckbw\0" "kunpckdq\0" "kunpckwd\0" "kxnorb\0" "kxnord\0" "kxnorq\0" "kxnorw\0" "kxorb\0"
+  "kxord\0" "kxorq\0" "kxorw\0" "lahf\0" "lar\0" "lds\0" "ldtilecfg\0" "lea\0" "leave\0" "les\0" "lfence\0" "lfs\0"
+  "lgdt\0" "lgs\0" "lidt\0" "lldt\0" "llwpcb\0" "lmsw\0" "lods\0" "loop\0" "loope\0" "loopne\0" "lsl\0" "ltr\0"
+  "lwpins\0" "lwpval\0" "lzcnt\0" "mcommit\0" "mfence\0" "monitorx\0" "movdir64b\0" "movdiri\0" "movdq2q\0" "movnti\0"
+  "movntq\0" "movntsd\0" "movntss\0" "movq2dq\0" "movsx\0" "movsxd\0" "movzx\0" "mulx\0" "mwaitx\0" "neg\0" "not\0"
+  "out\0" "outs\0" "pavgusb\0" "pconfig\0" "pdep\0" "pext\0" "pf2id\0" "pf2iw\0" "pfacc\0" "pfadd\0" "pfcmpeq\0"
+  "pfcmpge\0" "pfcmpgt\0" "pfmax\0" "pfmin\0" "pfmul\0" "pfnacc\0" "pfpnacc\0" "pfrcp\0" "pfrcpit1\0" "pfrcpit2\0"
+  "pfrcpv\0" "pfrsqit1\0" "pfrsqrt\0" "pfrsqrtv\0" "pfsub\0" "pfsubr\0" "pi2fd\0" "pi2fw\0" "pmulhrw\0" "pop\0"
+  "popa\0" "popad\0" "popcnt\0" "popf\0" "popfd\0" "popfq\0" "prefetch\0" "prefetchnta\0" "prefetcht0\0" "prefetcht1\0"
+  "prefetcht2\0" "prefetchw\0" "prefetchwt1\0" "pshufw\0" "psmash\0" "pswapd\0" "ptwrite\0" "push\0" "pusha\0"
+  "pushad\0" "pushf\0" "pushfd\0" "pushfq\0" "pvalidate\0" "rcl\0" "rcr\0" "rdfsbase\0" "rdgsbase\0" "rdmsr\0"
+  "rdpid\0" "rdpkru\0" "rdpmc\0" "rdpru\0" "rdrand\0" "rdseed\0" "rdsspd\0" "rdsspq\0" "rdtsc\0" "rdtscp\0"
+  "rmpadjust\0" "rmpupdate\0" "rol\0" "ror\0" "rorx\0" "rsm\0" "rstorssp\0" "sahf\0" "sal\0" "sar\0" "sarx\0"
+  "saveprevssp\0" "sbb\0" "scas\0" "serialize\0" "seta\0" "setae\0" "setb\0" "setbe\0" "setc\0" "sete\0" "setg\0"
+  "setge\0" "setl\0" "setle\0" "setna\0" "setnae\0" "setnb\0" "setnbe\0" "setnc\0" "setne\0" "setng\0" "setnge\0"
+  "setnl\0" "setnle\0" "setno\0" "setnp\0" "setns\0" "setnz\0" "seto\0" "setp\0" "setpe\0" "setpo\0" "sets\0"
+  "setssbsy\0" "setz\0" "sfence\0" "sgdt\0" "sha1msg1\0" "sha1msg2\0" "sha1nexte\0" "sha1rnds4\0" "sha256msg1\0"
+  "sha256msg2\0" "sha256rnds2\0" "shl\0" "shlx\0" "shr\0" "shrd\0" "shrx\0" "sidt\0" "skinit\0" "sldt\0" "slwpcb\0"
+  "smsw\0" "stac\0" "stc\0" "stgi\0" "sti\0" "stos\0" "str\0" "sttilecfg\0" "swapgs\0" "syscall\0" "sysenter\0"
+  "sysexit\0" "sysexit64\0" "sysret\0" "sysret64\0" "t1mskc\0" "tdpbf16ps\0" "tdpbssd\0" "tdpbsud\0" "tdpbusd\0"
+  "tdpbuud\0" "tileloadd\0" "tileloaddt1\0" "tilerelease\0" "tilestored\0" "tilezero\0" "tpause\0" "tzcnt\0" "tzmsk\0"
+  "ud0\0" "ud1\0" "ud2\0" "umonitor\0" "umwait\0" "v4fmaddps\0" "v4fmaddss\0" "v4fnmaddps\0" "v4fnmaddss\0" "vaddpd\0"
+  "vaddps\0" "vaddsd\0" "vaddss\0" "vaddsubpd\0" "vaddsubps\0" "vaesdec\0" "vaesdeclast\0" "vaesenc\0" "vaesenclast\0"
+  "vaesimc\0" "vaeskeygenassist\0" "valignd\0" "valignq\0" "vandnpd\0" "vandnps\0" "vandpd\0" "vandps\0" "vblendmb\0"
+  "vblendmd\0" "vblendmpd\0" "vblendmps\0" "vblendmq\0" "vblendmw\0" "vblendpd\0" "vblendps\0" "vblendvpd\0"
+  "vblendvps\0" "vbroadcastf128\0" "vbroadcastf32x2\0" "vbroadcastf32x4\0" "vbroadcastf32x8\0" "vbroadcastf64x2\0"
+  "vbroadcastf64x4\0" "vbroadcasti128\0" "vbroadcasti32x2\0" "vbroadcasti32x4\0" "vbroadcasti32x8\0"
+  "vbroadcasti64x2\0" "vbroadcasti64x4\0" "vbroadcastsd\0" "vbroadcastss\0" "vcmppd\0" "vcmpps\0" "vcmpsd\0" "vcmpss\0"
+  "vcomisd\0" "vcomiss\0" "vcompresspd\0" "vcompressps\0" "vcvtdq2pd\0" "vcvtdq2ps\0" "vcvtne2ps2bf16\0"
+  "vcvtneps2bf16\0" "vcvtpd2dq\0" "vcvtpd2ps\0" "vcvtpd2qq\0" "vcvtpd2udq\0" "vcvtpd2uqq\0" "vcvtph2ps\0" "vcvtps2dq\0"
+  "vcvtps2pd\0" "vcvtps2ph\0" "vcvtps2qq\0" "vcvtps2udq\0" "vcvtps2uqq\0" "vcvtqq2pd\0" "vcvtqq2ps\0" "vcvtsd2si\0"
+  "vcvtsd2ss\0" "vcvtsd2usi\0" "vcvtsi2sd\0" "vcvtsi2ss\0" "vcvtss2sd\0" "vcvtss2si\0" "vcvtss2usi\0" "vcvttpd2dq\0"
+  "vcvttpd2qq\0" "vcvttpd2udq\0" "vcvttpd2uqq\0" "vcvttps2dq\0" "vcvttps2qq\0" "vcvttps2udq\0" "vcvttps2uqq\0"
+  "vcvttsd2si\0" "vcvttsd2usi\0" "vcvttss2si\0" "vcvttss2usi\0" "vcvtudq2pd\0" "vcvtudq2ps\0" "vcvtuqq2pd\0"
+  "vcvtuqq2ps\0" "vcvtusi2sd\0" "vcvtusi2ss\0" "vdbpsadbw\0" "vdivpd\0" "vdivps\0" "vdivsd\0" "vdivss\0" "vdpbf16ps\0"
+  "vdppd\0" "vdpps\0" "verr\0" "verw\0" "vexp2pd\0" "vexp2ps\0" "vexpandpd\0" "vexpandps\0" "vextractf128\0"
+  "vextractf32x4\0" "vextractf32x8\0" "vextractf64x2\0" "vextractf64x4\0" "vextracti128\0" "vextracti32x4\0"
+  "vextracti32x8\0" "vextracti64x2\0" "vextracti64x4\0" "vextractps\0" "vfixupimmpd\0" "vfixupimmps\0" "vfixupimmsd\0"
+  "vfixupimmss\0" "vfmadd132pd\0" "vfmadd132ps\0" "vfmadd132sd\0" "vfmadd132ss\0" "vfmadd213pd\0" "vfmadd213ps\0"
+  "vfmadd213sd\0" "vfmadd213ss\0" "vfmadd231pd\0" "vfmadd231ps\0" "vfmadd231sd\0" "vfmadd231ss\0" "vfmaddpd\0"
+  "vfmaddps\0" "vfmaddsd\0" "vfmaddss\0" "vfmaddsub132pd\0" "vfmaddsub132ps\0" "vfmaddsub213pd\0" "vfmaddsub213ps\0"
+  "vfmaddsub231pd\0" "vfmaddsub231ps\0" "vfmaddsubpd\0" "vfmaddsubps\0" "vfmsub132pd\0" "vfmsub132ps\0" "vfmsub132sd\0"
+  "vfmsub132ss\0" "vfmsub213pd\0" "vfmsub213ps\0" "vfmsub213sd\0" "vfmsub213ss\0" "vfmsub231pd\0" "vfmsub231ps\0"
+  "vfmsub231sd\0" "vfmsub231ss\0" "vfmsubadd132pd\0" "vfmsubadd132ps\0" "vfmsubadd213pd\0" "vfmsubadd213ps\0"
+  "vfmsubadd231pd\0" "vfmsubadd231ps\0" "vfmsubaddpd\0" "vfmsubaddps\0" "vfmsubpd\0" "vfmsubps\0" "vfmsubsd\0"
+  "vfmsubss\0" "vfnmadd132pd\0" "vfnmadd132ps\0" "vfnmadd132sd\0" "vfnmadd132ss\0" "vfnmadd213pd\0" "vfnmadd213ps\0"
+  "vfnmadd213sd\0" "vfnmadd213ss\0" "vfnmadd231pd\0" "vfnmadd231ps\0" "vfnmadd231sd\0" "vfnmadd231ss\0" "vfnmaddpd\0"
+  "vfnmaddps\0" "vfnmaddsd\0" "vfnmaddss\0" "vfnmsub132pd\0" "vfnmsub132ps\0" "vfnmsub132sd\0" "vfnmsub132ss\0"
+  "vfnmsub213pd\0" "vfnmsub213ps\0" "vfnmsub213sd\0" "vfnmsub213ss\0" "vfnmsub231pd\0" "vfnmsub231ps\0"
+  "vfnmsub231sd\0" "vfnmsub231ss\0" "vfnmsubpd\0" "vfnmsubps\0" "vfnmsubsd\0" "vfnmsubss\0" "vfpclasspd\0"
+  "vfpclassps\0" "vfpclasssd\0" "vfpclassss\0" "vfrczpd\0" "vfrczps\0" "vfrczsd\0" "vfrczss\0" "vgatherdpd\0"
+  "vgatherdps\0" "vgatherpf0dpd\0" "vgatherpf0dps\0" "vgatherpf0qpd\0" "vgatherpf0qps\0" "vgatherpf1dpd\0"
+  "vgatherpf1dps\0" "vgatherpf1qpd\0" "vgatherpf1qps\0" "vgatherqpd\0" "vgatherqps\0" "vgetexppd\0" "vgetexpps\0"
+  "vgetexpsd\0" "vgetexpss\0" "vgetmantpd\0" "vgetmantps\0" "vgetmantsd\0" "vgetmantss\0" "vgf2p8affineinvqb\0"
+  "vgf2p8affineqb\0" "vgf2p8mulb\0" "vhaddpd\0" "vhaddps\0" "vhsubpd\0" "vhsubps\0" "vinsertf128\0" "vinsertf32x4\0"
+  "vinsertf32x8\0" "vinsertf64x2\0" "vinsertf64x4\0" "vinserti128\0" "vinserti32x4\0" "vinserti32x8\0" "vinserti64x2\0"
+  "vinserti64x4\0" "vinsertps\0" "vlddqu\0" "vldmxcsr\0" "vmaskmovdqu\0" "vmaskmovpd\0" "vmaskmovps\0" "vmaxpd\0"
+  "vmaxps\0" "vmaxsd\0" "vmaxss\0" "vmcall\0" "vmclear\0" "vmfunc\0" "vminpd\0" "vminps\0" "vminsd\0" "vminss\0"
+  "vmlaunch\0" "vmload\0" "vmmcall\0" "vmovapd\0" "vmovaps\0" "vmovd\0" "vmovddup\0" "vmovdqa\0" "vmovdqa32\0"
+  "vmovdqa64\0" "vmovdqu\0" "vmovdqu16\0" "vmovdqu32\0" "vmovdqu64\0" "vmovdqu8\0" "vmovhlps\0" "vmovhpd\0" "vmovhps\0"
+  "vmovlhps\0" "vmovlpd\0" "vmovlps\0" "vmovmskpd\0" "vmovmskps\0" "vmovntdq\0" "vmovntdqa\0" "vmovntpd\0" "vmovntps\0"
+  "vmovq\0" "vmovsd\0" "vmovshdup\0" "vmovsldup\0" "vmovss\0" "vmovupd\0" "vmovups\0" "vmpsadbw\0" "vmptrld\0"
+  "vmptrst\0" "vmread\0" "vmresume\0" "vmrun\0" "vmsave\0" "vmulpd\0" "vmulps\0" "vmulsd\0" "vmulss\0" "vmwrite\0"
+  "vmxon\0" "vorpd\0" "vorps\0" "vp2intersectd\0" "vp2intersectq\0" "vp4dpwssd\0" "vp4dpwssds\0" "vpabsb\0" "vpabsd\0"
+  "vpabsq\0" "vpabsw\0" "vpackssdw\0" "vpacksswb\0" "vpackusdw\0" "vpackuswb\0" "vpaddb\0" "vpaddd\0" "vpaddq\0"
+  "vpaddsb\0" "vpaddsw\0" "vpaddusb\0" "vpaddusw\0" "vpaddw\0" "vpalignr\0" "vpand\0" "vpandd\0" "vpandn\0" "vpandnd\0"
+  "vpandnq\0" "vpandq\0" "vpavgb\0" "vpavgw\0" "vpblendd\0" "vpblendvb\0" "vpblendw\0" "vpbroadcastb\0"
+  "vpbroadcastd\0" "vpbroadcastmb2d\0" "vpbroadcastmb2q\0" "vpbroadcastq\0" "vpbroadcastw\0" "vpclmulqdq\0" "vpcmov\0"
+  "vpcmpb\0" "vpcmpd\0" "vpcmpeqb\0" "vpcmpeqd\0" "vpcmpeqq\0" "vpcmpeqw\0" "vpcmpestri\0" "vpcmpestrm\0" "vpcmpgtb\0"
+  "vpcmpgtd\0" "vpcmpgtq\0" "vpcmpgtw\0" "vpcmpistri\0" "vpcmpistrm\0" "vpcmpq\0" "vpcmpub\0" "vpcmpud\0" "vpcmpuq\0"
+  "vpcmpuw\0" "vpcmpw\0" "vpcomb\0" "vpcomd\0" "vpcompressb\0" "vpcompressd\0" "vpcompressq\0" "vpcompressw\0"
+  "vpcomq\0" "vpcomub\0" "vpcomud\0" "vpcomuq\0" "vpcomuw\0" "vpcomw\0" "vpconflictd\0" "vpconflictq\0" "vpdpbusd\0"
+  "vpdpbusds\0" "vpdpwssd\0" "vpdpwssds\0" "vperm2f128\0" "vperm2i128\0" "vpermb\0" "vpermd\0" "vpermi2b\0"
+  "vpermi2d\0" "vpermi2pd\0" "vpermi2ps\0" "vpermi2q\0" "vpermi2w\0" "vpermil2pd\0" "vpermil2ps\0" "vpermilpd\0"
+  "vpermilps\0" "vpermpd\0" "vpermps\0" "vpermq\0" "vpermt2b\0" "vpermt2d\0" "vpermt2pd\0" "vpermt2ps\0" "vpermt2q\0"
+  "vpermt2w\0" "vpermw\0" "vpexpandb\0" "vpexpandd\0" "vpexpandq\0" "vpexpandw\0" "vpextrb\0" "vpextrd\0" "vpextrq\0"
+  "vpextrw\0" "vpgatherdd\0" "vpgatherdq\0" "vpgatherqd\0" "vpgatherqq\0" "vphaddbd\0" "vphaddbq\0" "vphaddbw\0"
+  "vphaddd\0" "vphadddq\0" "vphaddsw\0" "vphaddubd\0" "vphaddubq\0" "vphaddubw\0" "vphaddudq\0" "vphadduwd\0"
+  "vphadduwq\0" "vphaddw\0" "vphaddwd\0" "vphaddwq\0" "vphminposuw\0" "vphsubbw\0" "vphsubd\0" "vphsubdq\0"
+  "vphsubsw\0" "vphsubw\0" "vphsubwd\0" "vpinsrb\0" "vpinsrd\0" "vpinsrq\0" "vpinsrw\0" "vplzcntd\0" "vplzcntq\0"
+  "vpmacsdd\0" "vpmacsdqh\0" "vpmacsdql\0" "vpmacssdd\0" "vpmacssdqh\0" "vpmacssdql\0" "vpmacsswd\0" "vpmacssww\0"
+  "vpmacswd\0" "vpmacsww\0" "vpmadcsswd\0" "vpmadcswd\0" "vpmadd52huq\0" "vpmadd52luq\0" "vpmaddubsw\0" "vpmaddwd\0"
+  "vpmaskmovd\0" "vpmaskmovq\0" "vpmaxsb\0" "vpmaxsd\0" "vpmaxsq\0" "vpmaxsw\0" "vpmaxub\0" "vpmaxud\0" "vpmaxuq\0"
+  "vpmaxuw\0" "vpminsb\0" "vpminsd\0" "vpminsq\0" "vpminsw\0" "vpminub\0" "vpminud\0" "vpminuq\0" "vpminuw\0"
+  "vpmovb2m\0" "vpmovd2m\0" "vpmovdb\0" "vpmovdw\0" "vpmovm2b\0" "vpmovm2d\0" "vpmovm2q\0" "vpmovm2w\0" "vpmovmskb\0"
+  "vpmovq2m\0" "vpmovqb\0" "vpmovqd\0" "vpmovqw\0" "vpmovsdb\0" "vpmovsdw\0" "vpmovsqb\0" "vpmovsqd\0" "vpmovsqw\0"
+  "vpmovswb\0" "vpmovsxbd\0" "vpmovsxbq\0" "vpmovsxbw\0" "vpmovsxdq\0" "vpmovsxwd\0" "vpmovsxwq\0" "vpmovusdb\0"
+  "vpmovusdw\0" "vpmovusqb\0" "vpmovusqd\0" "vpmovusqw\0" "vpmovuswb\0" "vpmovw2m\0" "vpmovwb\0" "vpmovzxbd\0"
+  "vpmovzxbq\0" "vpmovzxbw\0" "vpmovzxdq\0" "vpmovzxwd\0" "vpmovzxwq\0" "vpmuldq\0" "vpmulhrsw\0" "vpmulhuw\0"
+  "vpmulhw\0" "vpmulld\0" "vpmullq\0" "vpmullw\0" "vpmultishiftqb\0" "vpmuludq\0" "vpopcntb\0" "vpopcntd\0"
+  "vpopcntq\0" "vpopcntw\0" "vpor\0" "vpord\0" "vporq\0" "vpperm\0" "vprold\0" "vprolq\0" "vprolvd\0" "vprolvq\0"
+  "vprord\0" "vprorq\0" "vprorvd\0" "vprorvq\0" "vprotb\0" "vprotd\0" "vprotq\0" "vprotw\0" "vpsadbw\0" "vpscatterdd\0"
+  "vpscatterdq\0" "vpscatterqd\0" "vpscatterqq\0" "vpshab\0" "vpshad\0" "vpshaq\0" "vpshaw\0" "vpshlb\0" "vpshld\0"
+  "vpshldd\0" "vpshldq\0" "vpshldvd\0" "vpshldvq\0" "vpshldvw\0" "vpshldw\0" "vpshlq\0" "vpshlw\0" "vpshrdd\0"
+  "vpshrdq\0" "vpshrdvd\0" "vpshrdvq\0" "vpshrdvw\0" "vpshrdw\0" "vpshufb\0" "vpshufbitqmb\0" "vpshufd\0" "vpshufhw\0"
+  "vpshuflw\0" "vpsignb\0" "vpsignd\0" "vpsignw\0" "vpslld\0" "vpslldq\0" "vpsllq\0" "vpsllvd\0" "vpsllvq\0"
+  "vpsllvw\0" "vpsllw\0" "vpsrad\0" "vpsraq\0" "vpsravd\0" "vpsravq\0" "vpsravw\0" "vpsraw\0" "vpsrld\0" "vpsrldq\0"
+  "vpsrlq\0" "vpsrlvd\0" "vpsrlvq\0" "vpsrlvw\0" "vpsrlw\0" "vpsubb\0" "vpsubd\0" "vpsubq\0" "vpsubsb\0" "vpsubsw\0"
+  "vpsubusb\0" "vpsubusw\0" "vpsubw\0" "vpternlogd\0" "vpternlogq\0" "vptest\0" "vptestmb\0" "vptestmd\0" "vptestmq\0"
+  "vptestmw\0" "vptestnmb\0" "vptestnmd\0" "vptestnmq\0" "vptestnmw\0" "vpunpckhbw\0" "vpunpckhdq\0" "vpunpckhqdq\0"
+  "vpunpckhwd\0" "vpunpcklbw\0" "vpunpckldq\0" "vpunpcklqdq\0" "vpunpcklwd\0" "vpxor\0" "vpxord\0" "vpxorq\0"
+  "vrangepd\0" "vrangeps\0" "vrangesd\0" "vrangess\0" "vrcp14pd\0" "vrcp14ps\0" "vrcp14sd\0" "vrcp14ss\0" "vrcp28pd\0"
+  "vrcp28ps\0" "vrcp28sd\0" "vrcp28ss\0" "vrcpps\0" "vrcpss\0" "vreducepd\0" "vreduceps\0" "vreducesd\0" "vreducess\0"
+  "vrndscalepd\0" "vrndscaleps\0" "vrndscalesd\0" "vrndscaless\0" "vroundpd\0" "vroundps\0" "vroundsd\0" "vroundss\0"
+  "vrsqrt14pd\0" "vrsqrt14ps\0" "vrsqrt14sd\0" "vrsqrt14ss\0" "vrsqrt28pd\0" "vrsqrt28ps\0" "vrsqrt28sd\0"
+  "vrsqrt28ss\0" "vrsqrtps\0" "vrsqrtss\0" "vscalefpd\0" "vscalefps\0" "vscalefsd\0" "vscalefss\0" "vscatterdpd\0"
+  "vscatterdps\0" "vscatterpf0dpd\0" "vscatterpf0dps\0" "vscatterpf0qpd\0" "vscatterpf0qps\0" "vscatterpf1dpd\0"
+  "vscatterpf1dps\0" "vscatterpf1qpd\0" "vscatterpf1qps\0" "vscatterqpd\0" "vscatterqps\0" "vshuff32x4\0"
+  "vshuff64x2\0" "vshufi32x4\0" "vshufi64x2\0" "vshufpd\0" "vshufps\0" "vsqrtpd\0" "vsqrtps\0" "vsqrtsd\0" "vsqrtss\0"
+  "vstmxcsr\0" "vsubpd\0" "vsubps\0" "vsubsd\0" "vsubss\0" "vtestpd\0" "vtestps\0" "vucomisd\0" "vucomiss\0"
+  "vunpckhpd\0" "vunpckhps\0" "vunpcklpd\0" "vunpcklps\0" "vxorpd\0" "vxorps\0" "vzeroall\0" "vzeroupper\0" "wbinvd\0"
+  "wbnoinvd\0" "wrfsbase\0" "wrgsbase\0" "wrmsr\0" "wrssd\0" "wrssq\0" "wrussd\0" "wrussq\0" "xabort\0" "xadd\0"
+  "xbegin\0" "xend\0" "xgetbv\0" "xlatb\0" "xresldtrk\0" "xrstors\0" "xrstors64\0" "xsavec\0" "xsavec64\0" "xsaveopt\0"
+  "xsaveopt64\0" "xsaves\0" "xsaves64\0" "xsetbv\0" "xsusldtrk\0" "xtest";
+
+const InstDB::InstNameIndex InstDB::instNameIndex[26] = {
+  { Inst::kIdAaa          , Inst::kIdArpl          + 1 },
+  { Inst::kIdBextr        , Inst::kIdBzhi          + 1 },
+  { Inst::kIdCall         , Inst::kIdCwde          + 1 },
+  { Inst::kIdDaa          , Inst::kIdDpps          + 1 },
+  { Inst::kIdEmms         , Inst::kIdExtrq         + 1 },
+  { Inst::kIdF2xm1        , Inst::kIdFyl2xp1       + 1 },
+  { Inst::kIdGetsec       , Inst::kIdGf2p8mulb     + 1 },
+  { Inst::kIdHaddpd       , Inst::kIdHsubps        + 1 },
+  { Inst::kIdIdiv         , Inst::kIdIretw         + 1 },
+  { Inst::kIdJa           , Inst::kIdJz            + 1 },
+  { Inst::kIdKaddb        , Inst::kIdKxorw         + 1 },
+  { Inst::kIdLahf         , Inst::kIdLzcnt         + 1 },
+  { Inst::kIdMaskmovdqu   , Inst::kIdMwaitx        + 1 },
+  { Inst::kIdNeg          , Inst::kIdNot           + 1 },
+  { Inst::kIdOr           , Inst::kIdOuts          + 1 },
+  { Inst::kIdPabsb        , Inst::kIdPxor          + 1 },
+  { Inst::kIdNone         , Inst::kIdNone          + 1 },
+  { Inst::kIdRcl          , Inst::kIdRstorssp      + 1 },
+  { Inst::kIdSahf         , Inst::kIdSysret64      + 1 },
+  { Inst::kIdT1mskc       , Inst::kIdTzmsk         + 1 },
+  { Inst::kIdUcomisd      , Inst::kIdUnpcklps      + 1 },
+  { Inst::kIdV4fmaddps    , Inst::kIdVzeroupper    + 1 },
+  { Inst::kIdWbinvd       , Inst::kIdWrussq        + 1 },
+  { Inst::kIdXabort       , Inst::kIdXtest         + 1 },
+  { Inst::kIdNone         , Inst::kIdNone          + 1 },
+  { Inst::kIdNone         , Inst::kIdNone          + 1 }
+};
+// ----------------------------------------------------------------------------
+// ${NameData:End}
+#endif // !ASMJIT_NO_TEXT
+
+// ============================================================================
+// [asmjit::x86::InstDB - InstSignature / OpSignature]
+// ============================================================================
+
+#ifndef ASMJIT_NO_VALIDATION
+// ${InstSignatureTable:Begin}
+// ------------------- Automatically generated, do not edit -------------------
+#define ROW(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5)  \
+  { count, (x86 ? uint8_t(InstDB::kModeX86) : uint8_t(0)) |     \
+           (x64 ? uint8_t(InstDB::kModeX64) : uint8_t(0)) ,     \
+    implicit,                                                   \
+    0,                                                          \
+    { o0, o1, o2, o3, o4, o5 }                                  \
+  }
+const InstDB::InstSignature InstDB::_instSignatureTable[] = {
+  ROW(2, 1, 1, 0, 1  , 2  , 0  , 0  , 0  , 0  ), // #0   {r8lo|r8hi|m8|mem, r8lo|r8hi}
+  ROW(2, 1, 1, 0, 3  , 4  , 0  , 0  , 0  , 0  ), //      {r16|m16|mem|sreg, r16}
+  ROW(2, 1, 1, 0, 5  , 6  , 0  , 0  , 0  , 0  ), //      {r32|m32|mem|sreg, r32}
+  ROW(2, 0, 1, 0, 7  , 8  , 0  , 0  , 0  , 0  ), //      {r64|m64|mem|sreg|creg|dreg, r64}
+  ROW(2, 1, 1, 0, 9  , 10 , 0  , 0  , 0  , 0  ), //      {r8lo|r8hi|m8, i8|u8}
+  ROW(2, 1, 1, 0, 11 , 12 , 0  , 0  , 0  , 0  ), //      {r16|m16, i16|u16}
+  ROW(2, 1, 1, 0, 13 , 14 , 0  , 0  , 0  , 0  ), //      {r32|m32, i32|u32}
+  ROW(2, 0, 1, 0, 15 , 16 , 0  , 0  , 0  , 0  ), //      {r64|m64|mem, i32}
+  ROW(2, 0, 1, 0, 8  , 17 , 0  , 0  , 0  , 0  ), //      {r64, i64|u64|m64|mem|sreg|creg|dreg}
+  ROW(2, 1, 1, 0, 2  , 18 , 0  , 0  , 0  , 0  ), //      {r8lo|r8hi, m8|mem}
+  ROW(2, 1, 1, 0, 4  , 19 , 0  , 0  , 0  , 0  ), //      {r16, m16|mem|sreg}
+  ROW(2, 1, 1, 0, 6  , 20 , 0  , 0  , 0  , 0  ), //      {r32, m32|mem|sreg}
+  ROW(2, 1, 1, 0, 21 , 22 , 0  , 0  , 0  , 0  ), //      {m16|mem, sreg}
+  ROW(2, 1, 1, 0, 22 , 21 , 0  , 0  , 0  , 0  ), //      {sreg, m16|mem}
+  ROW(2, 1, 0, 0, 6  , 23 , 0  , 0  , 0  , 0  ), //      {r32, creg|dreg}
+  ROW(2, 1, 0, 0, 23 , 6  , 0  , 0  , 0  , 0  ), //      {creg|dreg, r32}
+  ROW(2, 1, 1, 0, 9  , 10 , 0  , 0  , 0  , 0  ), // #16  {r8lo|r8hi|m8, i8|u8}
+  ROW(2, 1, 1, 0, 11 , 12 , 0  , 0  , 0  , 0  ), //      {r16|m16, i16|u16}
+  ROW(2, 1, 1, 0, 13 , 14 , 0  , 0  , 0  , 0  ), //      {r32|m32, i32|u32}
+  ROW(2, 0, 1, 0, 15 , 24 , 0  , 0  , 0  , 0  ), //      {r64|m64|mem, i32|r64}
+  ROW(2, 1, 1, 0, 25 , 26 , 0  , 0  , 0  , 0  ), //      {r16|m16|r32|m32|r64|m64|mem, i8}
+  ROW(2, 1, 1, 0, 1  , 2  , 0  , 0  , 0  , 0  ), //      {r8lo|r8hi|m8|mem, r8lo|r8hi}
+  ROW(2, 1, 1, 0, 27 , 4  , 0  , 0  , 0  , 0  ), //      {r16|m16|mem, r16}
+  ROW(2, 1, 1, 0, 28 , 6  , 0  , 0  , 0  , 0  ), // #23  {r32|m32|mem, r32}
+  ROW(2, 1, 1, 0, 2  , 18 , 0  , 0  , 0  , 0  ), //      {r8lo|r8hi, m8|mem}
+  ROW(2, 1, 1, 0, 4  , 21 , 0  , 0  , 0  , 0  ), //      {r16, m16|mem}
+  ROW(2, 1, 1, 0, 6  , 29 , 0  , 0  , 0  , 0  ), //      {r32, m32|mem}
+  ROW(2, 0, 1, 0, 8  , 30 , 0  , 0  , 0  , 0  ), //      {r64, m64|mem}
+  ROW(2, 1, 1, 0, 31 , 10 , 0  , 0  , 0  , 0  ), // #28  {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, i8|u8}
+  ROW(2, 1, 1, 0, 11 , 12 , 0  , 0  , 0  , 0  ), //      {r16|m16, i16|u16}
+  ROW(2, 1, 1, 0, 13 , 14 , 0  , 0  , 0  , 0  ), //      {r32|m32, i32|u32}
+  ROW(2, 0, 1, 0, 8  , 32 , 0  , 0  , 0  , 0  ), //      {r64, u32|i32|r64|m64|mem}
+  ROW(2, 0, 1, 0, 30 , 24 , 0  , 0  , 0  , 0  ), //      {m64|mem, i32|r64}
+  ROW(2, 1, 1, 0, 1  , 2  , 0  , 0  , 0  , 0  ), //      {r8lo|r8hi|m8|mem, r8lo|r8hi}
+  ROW(2, 1, 1, 0, 27 , 4  , 0  , 0  , 0  , 0  ), //      {r16|m16|mem, r16}
+  ROW(2, 1, 1, 0, 28 , 6  , 0  , 0  , 0  , 0  ), //      {r32|m32|mem, r32}
+  ROW(2, 1, 1, 0, 2  , 18 , 0  , 0  , 0  , 0  ), //      {r8lo|r8hi, m8|mem}
+  ROW(2, 1, 1, 0, 4  , 21 , 0  , 0  , 0  , 0  ), //      {r16, m16|mem}
+  ROW(2, 1, 1, 0, 6  , 29 , 0  , 0  , 0  , 0  ), //      {r32, m32|mem}
+  ROW(2, 1, 1, 1, 33 , 1  , 0  , 0  , 0  , 0  ), // #39  {<ax>, r8lo|r8hi|m8|mem}
+  ROW(3, 1, 1, 2, 34 , 33 , 27 , 0  , 0  , 0  ), //      {<dx>, <ax>, r16|m16|mem}
+  ROW(3, 1, 1, 2, 35 , 36 , 28 , 0  , 0  , 0  ), //      {<edx>, <eax>, r32|m32|mem}
+  ROW(3, 0, 1, 2, 37 , 38 , 15 , 0  , 0  , 0  ), //      {<rdx>, <rax>, r64|m64|mem}
+  ROW(2, 1, 1, 0, 4  , 39 , 0  , 0  , 0  , 0  ), //      {r16, r16|m16|mem|i8|i16}
+  ROW(2, 1, 1, 0, 6  , 40 , 0  , 0  , 0  , 0  ), //      {r32, r32|m32|mem|i8|i32}
+  ROW(2, 0, 1, 0, 8  , 41 , 0  , 0  , 0  , 0  ), //      {r64, r64|m64|mem|i8|i32}
+  ROW(3, 1, 1, 0, 4  , 27 , 42 , 0  , 0  , 0  ), //      {r16, r16|m16|mem, i8|i16|u16}
+  ROW(3, 1, 1, 0, 6  , 28 , 43 , 0  , 0  , 0  ), //      {r32, r32|m32|mem, i8|i32|u32}
+  ROW(3, 0, 1, 0, 8  , 15 , 44 , 0  , 0  , 0  ), //      {r64, r64|m64|mem, i8|i32}
+  ROW(2, 1, 1, 0, 1  , 2  , 0  , 0  , 0  , 0  ), // #49  {r8lo|r8hi|m8|mem, r8lo|r8hi}
+  ROW(2, 1, 1, 0, 27 , 4  , 0  , 0  , 0  , 0  ), //      {r16|m16|mem, r16}
+  ROW(2, 1, 1, 0, 28 , 6  , 0  , 0  , 0  , 0  ), //      {r32|m32|mem, r32}
+  ROW(2, 0, 1, 0, 15 , 8  , 0  , 0  , 0  , 0  ), // #52  {r64|m64|mem, r64}
+  ROW(2, 1, 1, 0, 2  , 18 , 0  , 0  , 0  , 0  ), //      {r8lo|r8hi, m8|mem}
+  ROW(2, 1, 1, 0, 4  , 21 , 0  , 0  , 0  , 0  ), //      {r16, m16|mem}
+  ROW(2, 1, 1, 0, 6  , 29 , 0  , 0  , 0  , 0  ), //      {r32, m32|mem}
+  ROW(2, 0, 1, 0, 8  , 30 , 0  , 0  , 0  , 0  ), //      {r64, m64|mem}
+  ROW(2, 1, 1, 0, 9  , 10 , 0  , 0  , 0  , 0  ), // #57  {r8lo|r8hi|m8, i8|u8}
+  ROW(2, 1, 1, 0, 11 , 12 , 0  , 0  , 0  , 0  ), //      {r16|m16, i16|u16}
+  ROW(2, 1, 1, 0, 13 , 14 , 0  , 0  , 0  , 0  ), //      {r32|m32, i32|u32}
+  ROW(2, 0, 1, 0, 15 , 24 , 0  , 0  , 0  , 0  ), //      {r64|m64|mem, i32|r64}
+  ROW(2, 1, 1, 0, 1  , 2  , 0  , 0  , 0  , 0  ), //      {r8lo|r8hi|m8|mem, r8lo|r8hi}
+  ROW(2, 1, 1, 0, 27 , 4  , 0  , 0  , 0  , 0  ), //      {r16|m16|mem, r16}
+  ROW(2, 1, 1, 0, 28 , 6  , 0  , 0  , 0  , 0  ), //      {r32|m32|mem, r32}
+  ROW(2, 1, 1, 0, 4  , 21 , 0  , 0  , 0  , 0  ), // #64  {r16, m16|mem}
+  ROW(2, 1, 1, 0, 6  , 29 , 0  , 0  , 0  , 0  ), //      {r32, m32|mem}
+  ROW(2, 0, 1, 0, 8  , 30 , 0  , 0  , 0  , 0  ), //      {r64, m64|mem}
+  ROW(2, 1, 1, 0, 21 , 4  , 0  , 0  , 0  , 0  ), //      {m16|mem, r16}
+  ROW(2, 1, 1, 0, 29 , 6  , 0  , 0  , 0  , 0  ), // #68  {m32|mem, r32}
+  ROW(2, 0, 1, 0, 30 , 8  , 0  , 0  , 0  , 0  ), //      {m64|mem, r64}
+  ROW(2, 1, 1, 0, 45 , 46 , 0  , 0  , 0  , 0  ), // #70  {xmm, xmm|m128|mem}
+  ROW(2, 1, 1, 0, 47 , 45 , 0  , 0  , 0  , 0  ), // #71  {m128|mem, xmm}
+  ROW(2, 1, 1, 0, 48 , 49 , 0  , 0  , 0  , 0  ), //      {ymm, ymm|m256|mem}
+  ROW(2, 1, 1, 0, 50 , 48 , 0  , 0  , 0  , 0  ), //      {m256|mem, ymm}
+  ROW(2, 1, 1, 0, 51 , 52 , 0  , 0  , 0  , 0  ), // #74  {zmm, zmm|m512|mem}
+  ROW(2, 1, 1, 0, 53 , 51 , 0  , 0  , 0  , 0  ), //      {m512|mem, zmm}
+  ROW(3, 1, 1, 0, 45 , 45 , 54 , 0  , 0  , 0  ), // #76  {xmm, xmm, xmm|m128|mem|i8|u8}
+  ROW(3, 1, 1, 0, 45 , 47 , 10 , 0  , 0  , 0  ), //      {xmm, m128|mem, i8|u8}
+  ROW(3, 1, 1, 0, 48 , 48 , 55 , 0  , 0  , 0  ), //      {ymm, ymm, ymm|m256|mem|i8|u8}
+  ROW(3, 1, 1, 0, 48 , 50 , 10 , 0  , 0  , 0  ), //      {ymm, m256|mem, i8|u8}
+  ROW(3, 1, 1, 0, 51 , 51 , 56 , 0  , 0  , 0  ), //      {zmm, zmm, zmm|m512|mem|i8|u8}
+  ROW(3, 1, 1, 0, 51 , 53 , 10 , 0  , 0  , 0  ), //      {zmm, m512|mem, i8|u8}
+  ROW(3, 1, 1, 0, 45 , 45 , 54 , 0  , 0  , 0  ), // #82  {xmm, xmm, i8|u8|xmm|m128|mem}
+  ROW(3, 1, 1, 0, 48 , 48 , 54 , 0  , 0  , 0  ), //      {ymm, ymm, i8|u8|xmm|m128|mem}
+  ROW(3, 1, 1, 0, 45 , 47 , 10 , 0  , 0  , 0  ), //      {xmm, m128|mem, i8|u8}
+  ROW(3, 1, 1, 0, 48 , 50 , 10 , 0  , 0  , 0  ), //      {ymm, m256|mem, i8|u8}
+  ROW(3, 1, 1, 0, 51 , 51 , 54 , 0  , 0  , 0  ), //      {zmm, zmm, xmm|m128|mem|i8|u8}
+  ROW(3, 1, 1, 0, 51 , 53 , 10 , 0  , 0  , 0  ), //      {zmm, m512|mem, i8|u8}
+  ROW(3, 1, 1, 0, 45 , 45 , 54 , 0  , 0  , 0  ), // #88  {xmm, xmm, xmm|m128|mem|i8|u8}
+  ROW(3, 1, 1, 0, 45 , 47 , 10 , 0  , 0  , 0  ), //      {xmm, m128|mem, i8|u8}
+  ROW(3, 1, 1, 0, 48 , 48 , 54 , 0  , 0  , 0  ), //      {ymm, ymm, xmm|m128|mem|i8|u8}
+  ROW(3, 1, 1, 0, 48 , 50 , 10 , 0  , 0  , 0  ), //      {ymm, m256|mem, i8|u8}
+  ROW(3, 1, 1, 0, 51 , 51 , 54 , 0  , 0  , 0  ), //      {zmm, zmm, xmm|m128|mem|i8|u8}
+  ROW(3, 1, 1, 0, 51 , 53 , 10 , 0  , 0  , 0  ), //      {zmm, m512|mem, i8|u8}
+  ROW(2, 1, 1, 0, 57 , 58 , 0  , 0  , 0  , 0  ), // #94  {mm, mm|m64|mem|r64}
+  ROW(2, 1, 1, 0, 15 , 59 , 0  , 0  , 0  , 0  ), //      {m64|mem|r64, mm|xmm}
+  ROW(2, 0, 1, 0, 45 , 15 , 0  , 0  , 0  , 0  ), //      {xmm, r64|m64|mem}
+  ROW(2, 1, 1, 0, 45 , 60 , 0  , 0  , 0  , 0  ), // #97  {xmm, xmm|m64|mem}
+  ROW(2, 1, 1, 0, 30 , 45 , 0  , 0  , 0  , 0  ), // #98  {m64|mem, xmm}
+  ROW(0, 1, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #99  {}
+  ROW(1, 1, 1, 0, 61 , 0  , 0  , 0  , 0  , 0  ), //      {r16|m16|r32|m32|r64|m64}
+  ROW(2, 1, 1, 0, 27 , 4  , 0  , 0  , 0  , 0  ), //      {r16|m16|mem, r16}
+  ROW(2, 1, 1, 0, 28 , 6  , 0  , 0  , 0  , 0  ), //      {r32|m32|mem, r32}
+  ROW(2, 1, 1, 0, 15 , 8  , 0  , 0  , 0  , 0  ), //      {r64|m64|mem, r64}
+  ROW(3, 1, 1, 0, 45 , 62 , 45 , 0  , 0  , 0  ), // #104 {xmm, vm32x, xmm}
+  ROW(3, 1, 1, 0, 48 , 62 , 48 , 0  , 0  , 0  ), //      {ymm, vm32x, ymm}
+  ROW(2, 1, 1, 0, 45 , 62 , 0  , 0  , 0  , 0  ), //      {xmm, vm32x}
+  ROW(2, 1, 1, 0, 48 , 63 , 0  , 0  , 0  , 0  ), //      {ymm, vm32y}
+  ROW(2, 1, 1, 0, 51 , 64 , 0  , 0  , 0  , 0  ), //      {zmm, vm32z}
+  ROW(3, 1, 1, 0, 45 , 62 , 45 , 0  , 0  , 0  ), // #109 {xmm, vm32x, xmm}
+  ROW(3, 1, 1, 0, 48 , 63 , 48 , 0  , 0  , 0  ), //      {ymm, vm32y, ymm}
+  ROW(2, 1, 1, 0, 45 , 62 , 0  , 0  , 0  , 0  ), //      {xmm, vm32x}
+  ROW(2, 1, 1, 0, 48 , 63 , 0  , 0  , 0  , 0  ), //      {ymm, vm32y}
+  ROW(2, 1, 1, 0, 51 , 64 , 0  , 0  , 0  , 0  ), //      {zmm, vm32z}
+  ROW(3, 1, 1, 0, 45 , 65 , 45 , 0  , 0  , 0  ), // #114 {xmm, vm64x, xmm}
+  ROW(3, 1, 1, 0, 48 , 66 , 48 , 0  , 0  , 0  ), //      {ymm, vm64y, ymm}
+  ROW(2, 1, 1, 0, 45 , 65 , 0  , 0  , 0  , 0  ), //      {xmm, vm64x}
+  ROW(2, 1, 1, 0, 48 , 66 , 0  , 0  , 0  , 0  ), //      {ymm, vm64y}
+  ROW(2, 1, 1, 0, 51 , 67 , 0  , 0  , 0  , 0  ), //      {zmm, vm64z}
+  ROW(2, 1, 1, 0, 25 , 10 , 0  , 0  , 0  , 0  ), // #119 {r16|m16|r32|m32|r64|m64|mem, i8|u8}
+  ROW(2, 1, 1, 0, 27 , 4  , 0  , 0  , 0  , 0  ), //      {r16|m16|mem, r16}
+  ROW(2, 1, 1, 0, 28 , 6  , 0  , 0  , 0  , 0  ), //      {r32|m32|mem, r32}
+  ROW(2, 0, 1, 0, 15 , 8  , 0  , 0  , 0  , 0  ), //      {r64|m64|mem, r64}
+  ROW(3, 1, 1, 1, 1  , 2  , 68 , 0  , 0  , 0  ), // #123 {r8lo|r8hi|m8|mem, r8lo|r8hi, <al>}
+  ROW(3, 1, 1, 1, 27 , 4  , 33 , 0  , 0  , 0  ), //      {r16|m16|mem, r16, <ax>}
+  ROW(3, 1, 1, 1, 28 , 6  , 36 , 0  , 0  , 0  ), //      {r32|m32|mem, r32, <eax>}
+  ROW(3, 0, 1, 1, 15 , 8  , 38 , 0  , 0  , 0  ), //      {r64|m64|mem, r64, <rax>}
+  ROW(1, 1, 1, 0, 69 , 0  , 0  , 0  , 0  , 0  ), // #127 {r16|m16|r64|m64}
+  ROW(1, 1, 0, 0, 13 , 0  , 0  , 0  , 0  , 0  ), //      {r32|m32}
+  ROW(1, 1, 0, 0, 70 , 0  , 0  , 0  , 0  , 0  ), //      {ds|es|ss}
+  ROW(1, 1, 1, 0, 71 , 0  , 0  , 0  , 0  , 0  ), //      {fs|gs}
+  ROW(1, 1, 1, 0, 72 , 0  , 0  , 0  , 0  , 0  ), // #131 {r16|m16|r64|m64|i8|i16|i32}
+  ROW(1, 1, 0, 0, 73 , 0  , 0  , 0  , 0  , 0  ), //      {r32|m32|i32|u32}
+  ROW(1, 1, 0, 0, 74 , 0  , 0  , 0  , 0  , 0  ), //      {cs|ss|ds|es}
+  ROW(1, 1, 1, 0, 71 , 0  , 0  , 0  , 0  , 0  ), //      {fs|gs}
+  ROW(4, 1, 1, 0, 45 , 45 , 45 , 46 , 0  , 0  ), // #135 {xmm, xmm, xmm, xmm|m128|mem}
+  ROW(4, 1, 1, 0, 45 , 45 , 47 , 45 , 0  , 0  ), //      {xmm, xmm, m128|mem, xmm}
+  ROW(4, 1, 1, 0, 48 , 48 , 48 , 49 , 0  , 0  ), //      {ymm, ymm, ymm, ymm|m256|mem}
+  ROW(4, 1, 1, 0, 48 , 48 , 50 , 48 , 0  , 0  ), //      {ymm, ymm, m256|mem, ymm}
+  ROW(3, 1, 1, 0, 45 , 75 , 45 , 0  , 0  , 0  ), // #139 {xmm, vm64x|vm64y, xmm}
+  ROW(2, 1, 1, 0, 45 , 65 , 0  , 0  , 0  , 0  ), //      {xmm, vm64x}
+  ROW(2, 1, 1, 0, 48 , 66 , 0  , 0  , 0  , 0  ), //      {ymm, vm64y}
+  ROW(2, 1, 1, 0, 51 , 67 , 0  , 0  , 0  , 0  ), //      {zmm, vm64z}
+  ROW(3, 1, 1, 0, 47 , 45 , 45 , 0  , 0  , 0  ), // #143 {m128|mem, xmm, xmm}
+  ROW(3, 1, 1, 0, 50 , 48 , 48 , 0  , 0  , 0  ), //      {m256|mem, ymm, ymm}
+  ROW(3, 1, 1, 0, 45 , 45 , 47 , 0  , 0  , 0  ), //      {xmm, xmm, m128|mem}
+  ROW(3, 1, 1, 0, 48 , 48 , 50 , 0  , 0  , 0  ), //      {ymm, ymm, m256|mem}
+  ROW(5, 1, 1, 0, 45 , 45 , 46 , 45 , 76 , 0  ), // #147 {xmm, xmm, xmm|m128|mem, xmm, i4|u4}
+  ROW(5, 1, 1, 0, 45 , 45 , 45 , 47 , 76 , 0  ), //      {xmm, xmm, xmm, m128|mem, i4|u4}
+  ROW(5, 1, 1, 0, 48 , 48 , 49 , 48 , 76 , 0  ), //      {ymm, ymm, ymm|m256|mem, ymm, i4|u4}
+  ROW(5, 1, 1, 0, 48 , 48 , 48 , 50 , 76 , 0  ), //      {ymm, ymm, ymm, m256|mem, i4|u4}
+  ROW(3, 1, 1, 0, 48 , 49 , 10 , 0  , 0  , 0  ), // #151 {ymm, ymm|m256|mem, i8|u8}
+  ROW(3, 1, 1, 0, 48 , 48 , 49 , 0  , 0  , 0  ), //      {ymm, ymm, ymm|m256|mem}
+  ROW(3, 1, 1, 0, 51 , 51 , 56 , 0  , 0  , 0  ), //      {zmm, zmm, zmm|m512|mem|i8|u8}
+  ROW(3, 1, 1, 0, 51 , 53 , 10 , 0  , 0  , 0  ), //      {zmm, m512|mem, i8|u8}
+  ROW(2, 1, 1, 0, 4  , 27 , 0  , 0  , 0  , 0  ), // #155 {r16, r16|m16|mem}
+  ROW(2, 1, 1, 0, 6  , 28 , 0  , 0  , 0  , 0  ), // #156 {r32, r32|m32|mem}
+  ROW(2, 0, 1, 0, 8  , 15 , 0  , 0  , 0  , 0  ), //      {r64, r64|m64|mem}
+  ROW(1, 1, 1, 0, 77 , 0  , 0  , 0  , 0  , 0  ), // #158 {m32|m64}
+  ROW(2, 1, 1, 0, 78 , 79 , 0  , 0  , 0  , 0  ), //      {st0, st}
+  ROW(2, 1, 1, 0, 79 , 78 , 0  , 0  , 0  , 0  ), //      {st, st0}
+  ROW(2, 1, 1, 0, 4  , 29 , 0  , 0  , 0  , 0  ), // #161 {r16, m32|mem}
+  ROW(2, 1, 1, 0, 6  , 80 , 0  , 0  , 0  , 0  ), //      {r32, m48|mem}
+  ROW(2, 0, 1, 0, 8  , 81 , 0  , 0  , 0  , 0  ), //      {r64, m80|mem}
+  ROW(3, 1, 1, 0, 27 , 4  , 82 , 0  , 0  , 0  ), // #164 {r16|m16|mem, r16, cl|i8|u8}
+  ROW(3, 1, 1, 0, 28 , 6  , 82 , 0  , 0  , 0  ), //      {r32|m32|mem, r32, cl|i8|u8}
+  ROW(3, 0, 1, 0, 15 , 8  , 82 , 0  , 0  , 0  ), //      {r64|m64|mem, r64, cl|i8|u8}
+  ROW(3, 1, 1, 0, 45 , 45 , 46 , 0  , 0  , 0  ), // #167 {xmm, xmm, xmm|m128|mem}
+  ROW(3, 1, 1, 0, 48 , 48 , 49 , 0  , 0  , 0  ), // #168 {ymm, ymm, ymm|m256|mem}
+  ROW(3, 1, 1, 0, 51 , 51 , 52 , 0  , 0  , 0  ), //      {zmm, zmm, zmm|m512|mem}
+  ROW(4, 1, 1, 0, 45 , 45 , 46 , 10 , 0  , 0  ), // #170 {xmm, xmm, xmm|m128|mem, i8|u8}
+  ROW(4, 1, 1, 0, 48 , 48 , 49 , 10 , 0  , 0  ), // #171 {ymm, ymm, ymm|m256|mem, i8|u8}
+  ROW(4, 1, 1, 0, 51 , 51 , 52 , 10 , 0  , 0  ), //      {zmm, zmm, zmm|m512|mem, i8|u8}
+  ROW(4, 1, 1, 0, 83 , 45 , 46 , 10 , 0  , 0  ), // #173 {xmm|k, xmm, xmm|m128|mem, i8|u8}
+  ROW(4, 1, 1, 0, 84 , 48 , 49 , 10 , 0  , 0  ), //      {ymm|k, ymm, ymm|m256|mem, i8|u8}
+  ROW(4, 1, 1, 0, 85 , 51 , 52 , 10 , 0  , 0  ), //      {k, zmm, zmm|m512|mem, i8|u8}
+  ROW(2, 1, 1, 0, 46 , 45 , 0  , 0  , 0  , 0  ), // #176 {xmm|m128|mem, xmm}
+  ROW(2, 1, 1, 0, 49 , 48 , 0  , 0  , 0  , 0  ), //      {ymm|m256|mem, ymm}
+  ROW(2, 1, 1, 0, 52 , 51 , 0  , 0  , 0  , 0  ), //      {zmm|m512|mem, zmm}
+  ROW(2, 1, 1, 0, 45 , 60 , 0  , 0  , 0  , 0  ), // #179 {xmm, xmm|m64|mem}
+  ROW(2, 1, 1, 0, 48 , 46 , 0  , 0  , 0  , 0  ), //      {ymm, xmm|m128|mem}
+  ROW(2, 1, 1, 0, 51 , 49 , 0  , 0  , 0  , 0  ), //      {zmm, ymm|m256|mem}
+  ROW(2, 1, 1, 0, 45 , 46 , 0  , 0  , 0  , 0  ), // #182 {xmm, xmm|m128|mem}
+  ROW(2, 1, 1, 0, 48 , 49 , 0  , 0  , 0  , 0  ), //      {ymm, ymm|m256|mem}
+  ROW(2, 1, 1, 0, 51 , 52 , 0  , 0  , 0  , 0  ), //      {zmm, zmm|m512|mem}
+  ROW(3, 1, 1, 0, 60 , 45 , 10 , 0  , 0  , 0  ), // #185 {xmm|m64|mem, xmm, i8|u8}
+  ROW(3, 1, 1, 0, 46 , 48 , 10 , 0  , 0  , 0  ), // #186 {xmm|m128|mem, ymm, i8|u8}
+  ROW(3, 1, 1, 0, 49 , 51 , 10 , 0  , 0  , 0  ), // #187 {ymm|m256|mem, zmm, i8|u8}
+  ROW(3, 1, 1, 0, 45 , 46 , 10 , 0  , 0  , 0  ), // #188 {xmm, xmm|m128|mem, i8|u8}
+  ROW(3, 1, 1, 0, 48 , 49 , 10 , 0  , 0  , 0  ), //      {ymm, ymm|m256|mem, i8|u8}
+  ROW(3, 1, 1, 0, 51 , 52 , 10 , 0  , 0  , 0  ), //      {zmm, zmm|m512|mem, i8|u8}
+  ROW(2, 1, 1, 0, 45 , 60 , 0  , 0  , 0  , 0  ), // #191 {xmm, xmm|m64|mem}
+  ROW(2, 1, 1, 0, 48 , 49 , 0  , 0  , 0  , 0  ), //      {ymm, ymm|m256|mem}
+  ROW(2, 1, 1, 0, 51 , 52 , 0  , 0  , 0  , 0  ), //      {zmm, zmm|m512|mem}
+  ROW(2, 1, 1, 0, 47 , 45 , 0  , 0  , 0  , 0  ), // #194 {m128|mem, xmm}
+  ROW(2, 1, 1, 0, 50 , 48 , 0  , 0  , 0  , 0  ), //      {m256|mem, ymm}
+  ROW(2, 1, 1, 0, 53 , 51 , 0  , 0  , 0  , 0  ), //      {m512|mem, zmm}
+  ROW(2, 1, 1, 0, 45 , 47 , 0  , 0  , 0  , 0  ), // #197 {xmm, m128|mem}
+  ROW(2, 1, 1, 0, 48 , 50 , 0  , 0  , 0  , 0  ), //      {ymm, m256|mem}
+  ROW(2, 1, 1, 0, 51 , 53 , 0  , 0  , 0  , 0  ), //      {zmm, m512|mem}
+  ROW(2, 0, 1, 0, 15 , 45 , 0  , 0  , 0  , 0  ), // #200 {r64|m64|mem, xmm}
+  ROW(2, 1, 1, 0, 45 , 86 , 0  , 0  , 0  , 0  ), //      {xmm, xmm|m64|mem|r64}
+  ROW(2, 1, 1, 0, 30 , 45 , 0  , 0  , 0  , 0  ), //      {m64|mem, xmm}
+  ROW(2, 1, 1, 0, 30 , 45 , 0  , 0  , 0  , 0  ), // #203 {m64|mem, xmm}
+  ROW(2, 1, 1, 0, 45 , 30 , 0  , 0  , 0  , 0  ), //      {xmm, m64|mem}
+  ROW(3, 1, 1, 0, 45 , 45 , 45 , 0  , 0  , 0  ), // #205 {xmm, xmm, xmm}
+  ROW(2, 1, 1, 0, 29 , 45 , 0  , 0  , 0  , 0  ), // #206 {m32|mem, xmm}
+  ROW(2, 1, 1, 0, 45 , 29 , 0  , 0  , 0  , 0  ), //      {xmm, m32|mem}
+  ROW(3, 1, 1, 0, 45 , 45 , 45 , 0  , 0  , 0  ), //      {xmm, xmm, xmm}
+  ROW(4, 1, 1, 0, 85 , 85 , 45 , 46 , 0  , 0  ), // #209 {k, k, xmm, xmm|m128|mem}
+  ROW(4, 1, 1, 0, 85 , 85 , 48 , 49 , 0  , 0  ), //      {k, k, ymm, ymm|m256|mem}
+  ROW(4, 1, 1, 0, 85 , 85 , 51 , 52 , 0  , 0  ), //      {k, k, zmm, zmm|m512|mem}
+  ROW(2, 1, 1, 0, 87 , 86 , 0  , 0  , 0  , 0  ), // #212 {xmm|ymm, xmm|m64|mem|r64}
+  ROW(2, 0, 1, 0, 51 , 8  , 0  , 0  , 0  , 0  ), //      {zmm, r64}
+  ROW(2, 1, 1, 0, 51 , 60 , 0  , 0  , 0  , 0  ), //      {zmm, xmm|m64|mem}
+  ROW(4, 1, 1, 0, 85 , 45 , 46 , 10 , 0  , 0  ), // #215 {k, xmm, xmm|m128|mem, i8|u8}
+  ROW(4, 1, 1, 0, 85 , 48 , 49 , 10 , 0  , 0  ), //      {k, ymm, ymm|m256|mem, i8|u8}
+  ROW(4, 1, 1, 0, 85 , 51 , 52 , 10 , 0  , 0  ), //      {k, zmm, zmm|m512|mem, i8|u8}
+  ROW(3, 1, 1, 0, 83 , 45 , 46 , 0  , 0  , 0  ), // #218 {xmm|k, xmm, xmm|m128|mem}
+  ROW(3, 1, 1, 0, 84 , 48 , 49 , 0  , 0  , 0  ), //      {ymm|k, ymm, ymm|m256|mem}
+  ROW(3, 1, 1, 0, 85 , 51 , 52 , 0  , 0  , 0  ), //      {k, zmm, zmm|m512|mem}
+  ROW(2, 1, 1, 0, 88 , 45 , 0  , 0  , 0  , 0  ), // #221 {xmm|m32|mem, xmm}
+  ROW(2, 1, 1, 0, 60 , 48 , 0  , 0  , 0  , 0  ), //      {xmm|m64|mem, ymm}
+  ROW(2, 1, 1, 0, 46 , 51 , 0  , 0  , 0  , 0  ), //      {xmm|m128|mem, zmm}
+  ROW(2, 1, 1, 0, 60 , 45 , 0  , 0  , 0  , 0  ), // #224 {xmm|m64|mem, xmm}
+  ROW(2, 1, 1, 0, 46 , 48 , 0  , 0  , 0  , 0  ), //      {xmm|m128|mem, ymm}
+  ROW(2, 1, 1, 0, 49 , 51 , 0  , 0  , 0  , 0  ), //      {ymm|m256|mem, zmm}
+  ROW(2, 1, 1, 0, 89 , 45 , 0  , 0  , 0  , 0  ), // #227 {xmm|m16|mem, xmm}
+  ROW(2, 1, 1, 0, 88 , 48 , 0  , 0  , 0  , 0  ), //      {xmm|m32|mem, ymm}
+  ROW(2, 1, 1, 0, 60 , 51 , 0  , 0  , 0  , 0  ), //      {xmm|m64|mem, zmm}
+  ROW(2, 1, 1, 0, 45 , 88 , 0  , 0  , 0  , 0  ), // #230 {xmm, xmm|m32|mem}
+  ROW(2, 1, 1, 0, 48 , 60 , 0  , 0  , 0  , 0  ), //      {ymm, xmm|m64|mem}
+  ROW(2, 1, 1, 0, 51 , 46 , 0  , 0  , 0  , 0  ), //      {zmm, xmm|m128|mem}
+  ROW(2, 1, 1, 0, 45 , 89 , 0  , 0  , 0  , 0  ), // #233 {xmm, xmm|m16|mem}
+  ROW(2, 1, 1, 0, 48 , 88 , 0  , 0  , 0  , 0  ), //      {ymm, xmm|m32|mem}
+  ROW(2, 1, 1, 0, 51 , 60 , 0  , 0  , 0  , 0  ), //      {zmm, xmm|m64|mem}
+  ROW(2, 1, 1, 0, 62 , 45 , 0  , 0  , 0  , 0  ), // #236 {vm32x, xmm}
+  ROW(2, 1, 1, 0, 63 , 48 , 0  , 0  , 0  , 0  ), //      {vm32y, ymm}
+  ROW(2, 1, 1, 0, 64 , 51 , 0  , 0  , 0  , 0  ), //      {vm32z, zmm}
+  ROW(2, 1, 1, 0, 65 , 45 , 0  , 0  , 0  , 0  ), // #239 {vm64x, xmm}
+  ROW(2, 1, 1, 0, 66 , 48 , 0  , 0  , 0  , 0  ), //      {vm64y, ymm}
+  ROW(2, 1, 1, 0, 67 , 51 , 0  , 0  , 0  , 0  ), //      {vm64z, zmm}
+  ROW(3, 1, 1, 0, 85 , 45 , 46 , 0  , 0  , 0  ), // #242 {k, xmm, xmm|m128|mem}
+  ROW(3, 1, 1, 0, 85 , 48 , 49 , 0  , 0  , 0  ), //      {k, ymm, ymm|m256|mem}
+  ROW(3, 1, 1, 0, 85 , 51 , 52 , 0  , 0  , 0  ), //      {k, zmm, zmm|m512|mem}
+  ROW(3, 1, 1, 0, 6  , 6  , 28 , 0  , 0  , 0  ), // #245 {r32, r32, r32|m32|mem}
+  ROW(3, 0, 1, 0, 8  , 8  , 15 , 0  , 0  , 0  ), //      {r64, r64, r64|m64|mem}
+  ROW(3, 1, 1, 0, 6  , 28 , 6  , 0  , 0  , 0  ), // #247 {r32, r32|m32|mem, r32}
+  ROW(3, 0, 1, 0, 8  , 15 , 8  , 0  , 0  , 0  ), //      {r64, r64|m64|mem, r64}
+  ROW(2, 1, 0, 0, 90 , 28 , 0  , 0  , 0  , 0  ), // #249 {bnd, r32|m32|mem}
+  ROW(2, 0, 1, 0, 90 , 15 , 0  , 0  , 0  , 0  ), //      {bnd, r64|m64|mem}
+  ROW(2, 1, 1, 0, 90 , 91 , 0  , 0  , 0  , 0  ), // #251 {bnd, bnd|mem}
+  ROW(2, 1, 1, 0, 92 , 90 , 0  , 0  , 0  , 0  ), //      {mem, bnd}
+  ROW(2, 1, 0, 0, 4  , 29 , 0  , 0  , 0  , 0  ), // #253 {r16, m32|mem}
+  ROW(2, 1, 0, 0, 6  , 30 , 0  , 0  , 0  , 0  ), //      {r32, m64|mem}
+  ROW(1, 1, 0, 0, 93 , 0  , 0  , 0  , 0  , 0  ), // #255 {rel16|r16|m16|r32|m32}
+  ROW(1, 1, 1, 0, 94 , 0  , 0  , 0  , 0  , 0  ), //      {rel32|r64|m64|mem}
+  ROW(2, 1, 1, 0, 6  , 95 , 0  , 0  , 0  , 0  ), // #257 {r32, r8lo|r8hi|m8|r16|m16|r32|m32}
+  ROW(2, 0, 1, 0, 8  , 96 , 0  , 0  , 0  , 0  ), //      {r64, r8lo|r8hi|m8|r64|m64}
+  ROW(1, 1, 0, 0, 97 , 0  , 0  , 0  , 0  , 0  ), // #259 {r16|r32}
+  ROW(1, 1, 1, 0, 31 , 0  , 0  , 0  , 0  , 0  ), // #260 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem}
+  ROW(2, 1, 0, 0, 98 , 53 , 0  , 0  , 0  , 0  ), // #261 {es:[memBase], m512|mem}
+  ROW(2, 0, 1, 0, 98 , 53 , 0  , 0  , 0  , 0  ), //      {es:[memBase], m512|mem}
+  ROW(3, 1, 1, 0, 45 , 10 , 10 , 0  , 0  , 0  ), // #263 {xmm, i8|u8, i8|u8}
+  ROW(2, 1, 1, 0, 45 , 45 , 0  , 0  , 0  , 0  ), // #264 {xmm, xmm}
+  ROW(0, 1, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #265 {}
+  ROW(1, 1, 1, 0, 79 , 0  , 0  , 0  , 0  , 0  ), // #266 {st}
+  ROW(0, 1, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #267 {}
+  ROW(1, 1, 1, 0, 99 , 0  , 0  , 0  , 0  , 0  ), // #268 {m32|m64|st}
+  ROW(2, 1, 1, 0, 45 , 45 , 0  , 0  , 0  , 0  ), // #269 {xmm, xmm}
+  ROW(4, 1, 1, 0, 45 , 45 , 10 , 10 , 0  , 0  ), //      {xmm, xmm, i8|u8, i8|u8}
+  ROW(2, 1, 0, 0, 6  , 47 , 0  , 0  , 0  , 0  ), // #271 {r32, m128|mem}
+  ROW(2, 0, 1, 0, 8  , 47 , 0  , 0  , 0  , 0  ), //      {r64, m128|mem}
+  ROW(2, 1, 0, 2, 36 , 100, 0  , 0  , 0  , 0  ), // #273 {<eax>, <ecx>}
+  ROW(2, 0, 1, 2, 101, 100, 0  , 0  , 0  , 0  ), //      {<eax|rax>, <ecx>}
+  ROW(1, 1, 1, 0, 102, 0  , 0  , 0  , 0  , 0  ), // #275 {rel8|rel32}
+  ROW(1, 1, 0, 0, 103, 0  , 0  , 0  , 0  , 0  ), //      {rel16}
+  ROW(2, 1, 0, 1, 104, 105, 0  , 0  , 0  , 0  ), // #277 {<cx|ecx>, rel8}
+  ROW(2, 0, 1, 1, 106, 105, 0  , 0  , 0  , 0  ), //      {<ecx|rcx>, rel8}
+  ROW(1, 1, 1, 0, 107, 0  , 0  , 0  , 0  , 0  ), // #279 {rel8|rel32|r64|m64|mem}
+  ROW(1, 1, 0, 0, 108, 0  , 0  , 0  , 0  , 0  ), //      {rel16|r32|m32|mem}
+  ROW(2, 1, 1, 0, 85 , 109, 0  , 0  , 0  , 0  ), // #281 {k, k|m8|mem|r32|r8lo|r8hi|r16}
+  ROW(2, 1, 1, 0, 110, 85 , 0  , 0  , 0  , 0  ), //      {m8|mem|r32|r8lo|r8hi|r16, k}
+  ROW(2, 1, 1, 0, 85 , 111, 0  , 0  , 0  , 0  ), // #283 {k, k|m32|mem|r32}
+  ROW(2, 1, 1, 0, 28 , 85 , 0  , 0  , 0  , 0  ), //      {m32|mem|r32, k}
+  ROW(2, 1, 1, 0, 85 , 112, 0  , 0  , 0  , 0  ), // #285 {k, k|m64|mem|r64}
+  ROW(2, 1, 1, 0, 15 , 85 , 0  , 0  , 0  , 0  ), //      {m64|mem|r64, k}
+  ROW(2, 1, 1, 0, 85 , 113, 0  , 0  , 0  , 0  ), // #287 {k, k|m16|mem|r32|r16}
+  ROW(2, 1, 1, 0, 114, 85 , 0  , 0  , 0  , 0  ), //      {m16|mem|r32|r16, k}
+  ROW(2, 1, 1, 0, 4  , 27 , 0  , 0  , 0  , 0  ), // #289 {r16, r16|m16|mem}
+  ROW(2, 1, 1, 0, 6  , 114, 0  , 0  , 0  , 0  ), //      {r32, r32|m16|mem|r16}
+  ROW(2, 1, 0, 0, 4  , 29 , 0  , 0  , 0  , 0  ), // #291 {r16, m32|mem}
+  ROW(2, 1, 0, 0, 6  , 80 , 0  , 0  , 0  , 0  ), //      {r32, m48|mem}
+  ROW(2, 1, 1, 0, 4  , 27 , 0  , 0  , 0  , 0  ), // #293 {r16, r16|m16|mem}
+  ROW(2, 1, 1, 0, 115, 114, 0  , 0  , 0  , 0  ), //      {r32|r64, r32|m16|mem|r16}
+  ROW(2, 1, 1, 0, 59 , 28 , 0  , 0  , 0  , 0  ), // #295 {mm|xmm, r32|m32|mem}
+  ROW(2, 1, 1, 0, 28 , 59 , 0  , 0  , 0  , 0  ), //      {r32|m32|mem, mm|xmm}
+  ROW(2, 1, 1, 0, 45 , 88 , 0  , 0  , 0  , 0  ), // #297 {xmm, xmm|m32|mem}
+  ROW(2, 1, 1, 0, 29 , 45 , 0  , 0  , 0  , 0  ), //      {m32|mem, xmm}
+  ROW(2, 1, 1, 0, 4  , 9  , 0  , 0  , 0  , 0  ), // #299 {r16, r8lo|r8hi|m8}
+  ROW(2, 1, 1, 0, 115, 116, 0  , 0  , 0  , 0  ), //      {r32|r64, r8lo|r8hi|m8|r16|m16}
+  ROW(2, 0, 1, 0, 4  , 27 , 0  , 0  , 0  , 0  ), // #301 {r16, r16|m16|mem}
+  ROW(2, 0, 1, 0, 115, 28 , 0  , 0  , 0  , 0  ), //      {r32|r64, r32|m32|mem}
+  ROW(4, 1, 1, 1, 6  , 6  , 28 , 35 , 0  , 0  ), // #303 {r32, r32, r32|m32|mem, <edx>}
+  ROW(4, 0, 1, 1, 8  , 8  , 15 , 37 , 0  , 0  ), //      {r64, r64, r64|m64|mem, <rdx>}
+  ROW(2, 1, 1, 0, 57 , 117, 0  , 0  , 0  , 0  ), // #305 {mm, mm|m64|mem}
+  ROW(2, 1, 1, 0, 45 , 46 , 0  , 0  , 0  , 0  ), //      {xmm, xmm|m128|mem}
+  ROW(3, 1, 1, 0, 57 , 117, 10 , 0  , 0  , 0  ), // #307 {mm, mm|m64|mem, i8|u8}
+  ROW(3, 1, 1, 0, 45 , 46 , 10 , 0  , 0  , 0  ), //      {xmm, xmm|m128|mem, i8|u8}
+  ROW(3, 1, 1, 0, 6  , 59 , 10 , 0  , 0  , 0  ), // #309 {r32, mm|xmm, i8|u8}
+  ROW(3, 1, 1, 0, 21 , 45 , 10 , 0  , 0  , 0  ), //      {m16|mem, xmm, i8|u8}
+  ROW(2, 1, 1, 0, 57 , 118, 0  , 0  , 0  , 0  ), // #311 {mm, i8|u8|mm|m64|mem}
+  ROW(2, 1, 1, 0, 45 , 54 , 0  , 0  , 0  , 0  ), //      {xmm, i8|u8|xmm|m128|mem}
+  ROW(1, 1, 0, 0, 6  , 0  , 0  , 0  , 0  , 0  ), // #313 {r32}
+  ROW(1, 0, 1, 0, 8  , 0  , 0  , 0  , 0  , 0  ), // #314 {r64}
+  ROW(0, 1, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #315 {}
+  ROW(1, 1, 1, 0, 119, 0  , 0  , 0  , 0  , 0  ), //      {u16}
+  ROW(3, 1, 1, 0, 6  , 28 , 10 , 0  , 0  , 0  ), // #317 {r32, r32|m32|mem, i8|u8}
+  ROW(3, 0, 1, 0, 8  , 15 , 10 , 0  , 0  , 0  ), //      {r64, r64|m64|mem, i8|u8}
+  ROW(4, 1, 1, 0, 45 , 45 , 46 , 45 , 0  , 0  ), // #319 {xmm, xmm, xmm|m128|mem, xmm}
+  ROW(4, 1, 1, 0, 48 , 48 , 49 , 48 , 0  , 0  ), //      {ymm, ymm, ymm|m256|mem, ymm}
+  ROW(2, 1, 1, 0, 45 , 120, 0  , 0  , 0  , 0  ), // #321 {xmm, xmm|m128|ymm|m256}
+  ROW(2, 1, 1, 0, 48 , 52 , 0  , 0  , 0  , 0  ), //      {ymm, zmm|m512|mem}
+  ROW(4, 1, 1, 0, 45 , 45 , 45 , 60 , 0  , 0  ), // #323 {xmm, xmm, xmm, xmm|m64|mem}
+  ROW(4, 1, 1, 0, 45 , 45 , 30 , 45 , 0  , 0  ), //      {xmm, xmm, m64|mem, xmm}
+  ROW(4, 1, 1, 0, 45 , 45 , 45 , 88 , 0  , 0  ), // #325 {xmm, xmm, xmm, xmm|m32|mem}
+  ROW(4, 1, 1, 0, 45 , 45 , 29 , 45 , 0  , 0  ), //      {xmm, xmm, m32|mem, xmm}
+  ROW(4, 1, 1, 0, 48 , 48 , 46 , 10 , 0  , 0  ), // #327 {ymm, ymm, xmm|m128|mem, i8|u8}
+  ROW(4, 1, 1, 0, 51 , 51 , 46 , 10 , 0  , 0  ), //      {zmm, zmm, xmm|m128|mem, i8|u8}
+  ROW(1, 1, 0, 1, 36 , 0  , 0  , 0  , 0  , 0  ), // #329 {<eax>}
+  ROW(1, 0, 1, 1, 38 , 0  , 0  , 0  , 0  , 0  ), // #330 {<rax>}
+  ROW(2, 1, 1, 0, 28 , 45 , 0  , 0  , 0  , 0  ), // #331 {r32|m32|mem, xmm}
+  ROW(2, 1, 1, 0, 45 , 28 , 0  , 0  , 0  , 0  ), //      {xmm, r32|m32|mem}
+  ROW(2, 1, 1, 0, 30 , 45 , 0  , 0  , 0  , 0  ), // #333 {m64|mem, xmm}
+  ROW(3, 1, 1, 0, 45 , 45 , 30 , 0  , 0  , 0  ), //      {xmm, xmm, m64|mem}
+  ROW(2, 1, 0, 0, 28 , 6  , 0  , 0  , 0  , 0  ), // #335 {r32|m32|mem, r32}
+  ROW(2, 0, 1, 0, 15 , 8  , 0  , 0  , 0  , 0  ), //      {r64|m64|mem, r64}
+  ROW(2, 1, 0, 0, 6  , 28 , 0  , 0  , 0  , 0  ), // #337 {r32, r32|m32|mem}
+  ROW(2, 0, 1, 0, 8  , 15 , 0  , 0  , 0  , 0  ), //      {r64, r64|m64|mem}
+  ROW(3, 1, 1, 0, 45 , 45 , 54 , 0  , 0  , 0  ), // #339 {xmm, xmm, xmm|m128|mem|i8|u8}
+  ROW(3, 1, 1, 0, 45 , 47 , 121, 0  , 0  , 0  ), //      {xmm, m128|mem, i8|u8|xmm}
+  ROW(2, 1, 1, 0, 75 , 45 , 0  , 0  , 0  , 0  ), // #341 {vm64x|vm64y, xmm}
+  ROW(2, 1, 1, 0, 67 , 48 , 0  , 0  , 0  , 0  ), //      {vm64z, ymm}
+  ROW(3, 1, 1, 0, 45 , 45 , 46 , 0  , 0  , 0  ), // #343 {xmm, xmm, xmm|m128|mem}
+  ROW(3, 1, 1, 0, 45 , 47 , 45 , 0  , 0  , 0  ), //      {xmm, m128|mem, xmm}
+  ROW(2, 1, 1, 0, 62 , 87 , 0  , 0  , 0  , 0  ), // #345 {vm32x, xmm|ymm}
+  ROW(2, 1, 1, 0, 63 , 51 , 0  , 0  , 0  , 0  ), //      {vm32y, zmm}
+  ROW(1, 1, 0, 1, 33 , 0  , 0  , 0  , 0  , 0  ), // #347 {<ax>}
+  ROW(2, 1, 0, 1, 33 , 10 , 0  , 0  , 0  , 0  ), // #348 {<ax>, i8|u8}
+  ROW(2, 1, 0, 0, 27 , 4  , 0  , 0  , 0  , 0  ), // #349 {r16|m16|mem, r16}
+  ROW(3, 1, 1, 1, 45 , 46 , 122, 0  , 0  , 0  ), // #350 {xmm, xmm|m128|mem, <xmm0>}
+  ROW(2, 1, 1, 0, 90 , 123, 0  , 0  , 0  , 0  ), // #351 {bnd, mib}
+  ROW(2, 1, 1, 0, 90 , 92 , 0  , 0  , 0  , 0  ), // #352 {bnd, mem}
+  ROW(2, 1, 1, 0, 123, 90 , 0  , 0  , 0  , 0  ), // #353 {mib, bnd}
+  ROW(1, 1, 1, 0, 124, 0  , 0  , 0  , 0  , 0  ), // #354 {r16|r32|r64}
+  ROW(1, 1, 1, 1, 33 , 0  , 0  , 0  , 0  , 0  ), // #355 {<ax>}
+  ROW(2, 1, 1, 2, 35 , 36 , 0  , 0  , 0  , 0  ), // #356 {<edx>, <eax>}
+  ROW(1, 1, 1, 0, 92 , 0  , 0  , 0  , 0  , 0  ), // #357 {mem}
+  ROW(1, 1, 1, 0, 30 , 0  , 0  , 0  , 0  , 0  ), // #358 {m64|mem}
+  ROW(1, 1, 1, 1, 125, 0  , 0  , 0  , 0  , 0  ), // #359 {<ds:[memBase|zax]>}
+  ROW(2, 1, 1, 2, 126, 127, 0  , 0  , 0  , 0  ), // #360 {<ds:[memBase|zsi]>, <es:[memBase|zdi]>}
+  ROW(3, 1, 1, 0, 45 , 60 , 10 , 0  , 0  , 0  ), // #361 {xmm, xmm|m64|mem, i8|u8}
+  ROW(3, 1, 1, 0, 45 , 88 , 10 , 0  , 0  , 0  ), // #362 {xmm, xmm|m32|mem, i8|u8}
+  ROW(5, 0, 1, 4, 47 , 37 , 38 , 128, 129, 0  ), // #363 {m128|mem, <rdx>, <rax>, <rcx>, <rbx>}
+  ROW(5, 1, 1, 4, 30 , 35 , 36 , 100, 130, 0  ), // #364 {m64|mem, <edx>, <eax>, <ecx>, <ebx>}
+  ROW(4, 1, 1, 4, 36 , 130, 100, 35 , 0  , 0  ), // #365 {<eax>, <ebx>, <ecx>, <edx>}
+  ROW(2, 0, 1, 2, 37 , 38 , 0  , 0  , 0  , 0  ), // #366 {<rdx>, <rax>}
+  ROW(2, 1, 1, 0, 57 , 46 , 0  , 0  , 0  , 0  ), // #367 {mm, xmm|m128|mem}
+  ROW(2, 1, 1, 0, 45 , 117, 0  , 0  , 0  , 0  ), // #368 {xmm, mm|m64|mem}
+  ROW(2, 1, 1, 0, 57 , 60 , 0  , 0  , 0  , 0  ), // #369 {mm, xmm|m64|mem}
+  ROW(2, 1, 1, 0, 115, 60 , 0  , 0  , 0  , 0  ), // #370 {r32|r64, xmm|m64|mem}
+  ROW(2, 1, 1, 0, 45 , 131, 0  , 0  , 0  , 0  ), // #371 {xmm, r32|m32|mem|r64|m64}
+  ROW(2, 1, 1, 0, 115, 88 , 0  , 0  , 0  , 0  ), // #372 {r32|r64, xmm|m32|mem}
+  ROW(2, 1, 1, 2, 34 , 33 , 0  , 0  , 0  , 0  ), // #373 {<dx>, <ax>}
+  ROW(1, 1, 1, 1, 36 , 0  , 0  , 0  , 0  , 0  ), // #374 {<eax>}
+  ROW(2, 1, 1, 0, 12 , 10 , 0  , 0  , 0  , 0  ), // #375 {i16|u16, i8|u8}
+  ROW(3, 1, 1, 0, 28 , 45 , 10 , 0  , 0  , 0  ), // #376 {r32|m32|mem, xmm, i8|u8}
+  ROW(1, 1, 1, 0, 81 , 0  , 0  , 0  , 0  , 0  ), // #377 {m80|mem}
+  ROW(1, 1, 1, 0, 132, 0  , 0  , 0  , 0  , 0  ), // #378 {m16|m32}
+  ROW(1, 1, 1, 0, 133, 0  , 0  , 0  , 0  , 0  ), // #379 {m16|m32|m64}
+  ROW(1, 1, 1, 0, 134, 0  , 0  , 0  , 0  , 0  ), // #380 {m32|m64|m80|st}
+  ROW(1, 1, 1, 0, 21 , 0  , 0  , 0  , 0  , 0  ), // #381 {m16|mem}
+  ROW(1, 1, 1, 0, 135, 0  , 0  , 0  , 0  , 0  ), // #382 {ax|m16|mem}
+  ROW(1, 0, 1, 0, 92 , 0  , 0  , 0  , 0  , 0  ), // #383 {mem}
+  ROW(2, 1, 1, 0, 136, 137, 0  , 0  , 0  , 0  ), // #384 {al|ax|eax, i8|u8|dx}
+  ROW(1, 1, 1, 0, 6  , 0  , 0  , 0  , 0  , 0  ), // #385 {r32}
+  ROW(2, 1, 1, 0, 138, 139, 0  , 0  , 0  , 0  ), // #386 {es:[memBase|zdi], dx}
+  ROW(1, 1, 1, 0, 10 , 0  , 0  , 0  , 0  , 0  ), // #387 {i8|u8}
+  ROW(0, 1, 0, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #388 {}
+  ROW(0, 0, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #389 {}
+  ROW(3, 1, 1, 0, 85 , 85 , 85 , 0  , 0  , 0  ), // #390 {k, k, k}
+  ROW(2, 1, 1, 0, 85 , 85 , 0  , 0  , 0  , 0  ), // #391 {k, k}
+  ROW(3, 1, 1, 0, 85 , 85 , 10 , 0  , 0  , 0  ), // #392 {k, k, i8|u8}
+  ROW(1, 1, 1, 1, 140, 0  , 0  , 0  , 0  , 0  ), // #393 {<ah>}
+  ROW(1, 1, 1, 0, 29 , 0  , 0  , 0  , 0  , 0  ), // #394 {m32|mem}
+  ROW(1, 0, 1, 0, 53 , 0  , 0  , 0  , 0  , 0  ), // #395 {m512|mem}
+  ROW(2, 1, 1, 0, 124, 141, 0  , 0  , 0  , 0  ), // #396 {r16|r32|r64, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024}
+  ROW(1, 1, 1, 0, 27 , 0  , 0  , 0  , 0  , 0  ), // #397 {r16|m16|mem}
+  ROW(1, 1, 1, 0, 115, 0  , 0  , 0  , 0  , 0  ), // #398 {r32|r64}
+  ROW(2, 1, 1, 2, 142, 126, 0  , 0  , 0  , 0  ), // #399 {<al|ax|eax|rax>, <ds:[memBase|zsi]>}
+  ROW(3, 1, 1, 0, 115, 28 , 14 , 0  , 0  , 0  ), // #400 {r32|r64, r32|m32|mem, i32|u32}
+  ROW(3, 1, 1, 1, 45 , 45 , 143, 0  , 0  , 0  ), // #401 {xmm, xmm, <ds:[memBase|zdi]>}
+  ROW(3, 1, 1, 1, 57 , 57 , 143, 0  , 0  , 0  ), // #402 {mm, mm, <ds:[memBase|zdi]>}
+  ROW(3, 1, 1, 3, 125, 100, 35 , 0  , 0  , 0  ), // #403 {<ds:[memBase|zax]>, <ecx>, <edx>}
+  ROW(2, 1, 1, 0, 98 , 53 , 0  , 0  , 0  , 0  ), // #404 {es:[memBase], m512|mem}
+  ROW(2, 1, 1, 0, 57 , 45 , 0  , 0  , 0  , 0  ), // #405 {mm, xmm}
+  ROW(2, 1, 1, 0, 6  , 45 , 0  , 0  , 0  , 0  ), // #406 {r32, xmm}
+  ROW(2, 1, 1, 0, 30 , 57 , 0  , 0  , 0  , 0  ), // #407 {m64|mem, mm}
+  ROW(2, 1, 1, 0, 45 , 57 , 0  , 0  , 0  , 0  ), // #408 {xmm, mm}
+  ROW(2, 1, 1, 2, 127, 126, 0  , 0  , 0  , 0  ), // #409 {<es:[memBase|zdi]>, <ds:[memBase|zsi]>}
+  ROW(2, 1, 1, 2, 36 , 100, 0  , 0  , 0  , 0  ), // #410 {<eax>, <ecx>}
+  ROW(3, 1, 1, 3, 36 , 100, 130, 0  , 0  , 0  ), // #411 {<eax>, <ecx>, <ebx>}
+  ROW(2, 1, 1, 0, 144, 136, 0  , 0  , 0  , 0  ), // #412 {u8|dx, al|ax|eax}
+  ROW(2, 1, 1, 0, 139, 145, 0  , 0  , 0  , 0  ), // #413 {dx, ds:[memBase|zsi]}
+  ROW(6, 1, 1, 3, 45 , 46 , 10 , 100, 36 , 35 ), // #414 {xmm, xmm|m128|mem, i8|u8, <ecx>, <eax>, <edx>}
+  ROW(6, 1, 1, 3, 45 , 46 , 10 , 122, 36 , 35 ), // #415 {xmm, xmm|m128|mem, i8|u8, <xmm0>, <eax>, <edx>}
+  ROW(4, 1, 1, 1, 45 , 46 , 10 , 100, 0  , 0  ), // #416 {xmm, xmm|m128|mem, i8|u8, <ecx>}
+  ROW(4, 1, 1, 1, 45 , 46 , 10 , 122, 0  , 0  ), // #417 {xmm, xmm|m128|mem, i8|u8, <xmm0>}
+  ROW(3, 1, 1, 0, 110, 45 , 10 , 0  , 0  , 0  ), // #418 {r32|m8|mem|r8lo|r8hi|r16, xmm, i8|u8}
+  ROW(3, 0, 1, 0, 15 , 45 , 10 , 0  , 0  , 0  ), // #419 {r64|m64|mem, xmm, i8|u8}
+  ROW(3, 1, 1, 0, 45 , 110, 10 , 0  , 0  , 0  ), // #420 {xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8}
+  ROW(3, 1, 1, 0, 45 , 28 , 10 , 0  , 0  , 0  ), // #421 {xmm, r32|m32|mem, i8|u8}
+  ROW(3, 0, 1, 0, 45 , 15 , 10 , 0  , 0  , 0  ), // #422 {xmm, r64|m64|mem, i8|u8}
+  ROW(3, 1, 1, 0, 59 , 114, 10 , 0  , 0  , 0  ), // #423 {mm|xmm, r32|m16|mem|r16, i8|u8}
+  ROW(2, 1, 1, 0, 6  , 59 , 0  , 0  , 0  , 0  ), // #424 {r32, mm|xmm}
+  ROW(2, 1, 1, 0, 45 , 10 , 0  , 0  , 0  , 0  ), // #425 {xmm, i8|u8}
+  ROW(1, 1, 1, 0, 131, 0  , 0  , 0  , 0  , 0  ), // #426 {r32|m32|mem|r64|m64}
+  ROW(2, 1, 1, 0, 31 , 82 , 0  , 0  , 0  , 0  ), // #427 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, cl|i8|u8}
+  ROW(1, 0, 1, 0, 115, 0  , 0  , 0  , 0  , 0  ), // #428 {r32|r64}
+  ROW(3, 1, 1, 3, 35 , 36 , 100, 0  , 0  , 0  ), // #429 {<edx>, <eax>, <ecx>}
+  ROW(2, 1, 1, 2, 142, 127, 0  , 0  , 0  , 0  ), // #430 {<al|ax|eax|rax>, <es:[memBase|zdi]>}
+  ROW(1, 1, 1, 0, 1  , 0  , 0  , 0  , 0  , 0  ), // #431 {r8lo|r8hi|m8|mem}
+  ROW(1, 1, 1, 0, 146, 0  , 0  , 0  , 0  , 0  ), // #432 {r16|m16|mem|r32|r64}
+  ROW(2, 1, 1, 2, 127, 142, 0  , 0  , 0  , 0  ), // #433 {<es:[memBase|zdi]>, <al|ax|eax|rax>}
+  ROW(3, 0, 1, 0, 147, 147, 147, 0  , 0  , 0  ), // #434 {tmm, tmm, tmm}
+  ROW(2, 0, 1, 0, 147, 92 , 0  , 0  , 0  , 0  ), // #435 {tmm, tmem}
+  ROW(2, 0, 1, 0, 92 , 147, 0  , 0  , 0  , 0  ), // #436 {tmem, tmm}
+  ROW(1, 0, 1, 0, 147, 0  , 0  , 0  , 0  , 0  ), // #437 {tmm}
+  ROW(3, 1, 1, 2, 6  , 35 , 36 , 0  , 0  , 0  ), // #438 {r32, <edx>, <eax>}
+  ROW(1, 1, 1, 0, 28 , 0  , 0  , 0  , 0  , 0  ), // #439 {r32|m32|mem}
+  ROW(1, 1, 1, 0, 148, 0  , 0  , 0  , 0  , 0  ), // #440 {ds:[memBase]}
+  ROW(6, 1, 1, 0, 51 , 51 , 51 , 51 , 51 , 47 ), // #441 {zmm, zmm, zmm, zmm, zmm, m128|mem}
+  ROW(6, 1, 1, 0, 45 , 45 , 45 , 45 , 45 , 47 ), // #442 {xmm, xmm, xmm, xmm, xmm, m128|mem}
+  ROW(3, 1, 1, 0, 45 , 45 , 60 , 0  , 0  , 0  ), // #443 {xmm, xmm, xmm|m64|mem}
+  ROW(3, 1, 1, 0, 45 , 45 , 88 , 0  , 0  , 0  ), // #444 {xmm, xmm, xmm|m32|mem}
+  ROW(2, 1, 1, 0, 48 , 47 , 0  , 0  , 0  , 0  ), // #445 {ymm, m128|mem}
+  ROW(2, 1, 1, 0, 149, 60 , 0  , 0  , 0  , 0  ), // #446 {ymm|zmm, xmm|m64|mem}
+  ROW(2, 1, 1, 0, 149, 47 , 0  , 0  , 0  , 0  ), // #447 {ymm|zmm, m128|mem}
+  ROW(2, 1, 1, 0, 51 , 50 , 0  , 0  , 0  , 0  ), // #448 {zmm, m256|mem}
+  ROW(2, 1, 1, 0, 150, 60 , 0  , 0  , 0  , 0  ), // #449 {xmm|ymm|zmm, xmm|m64|mem}
+  ROW(2, 1, 1, 0, 150, 88 , 0  , 0  , 0  , 0  ), // #450 {xmm|ymm|zmm, m32|mem|xmm}
+  ROW(4, 1, 1, 0, 83 , 45 , 60 , 10 , 0  , 0  ), // #451 {xmm|k, xmm, xmm|m64|mem, i8|u8}
+  ROW(4, 1, 1, 0, 83 , 45 , 88 , 10 , 0  , 0  ), // #452 {xmm|k, xmm, xmm|m32|mem, i8|u8}
+  ROW(3, 1, 1, 0, 45 , 45 , 131, 0  , 0  , 0  ), // #453 {xmm, xmm, r32|m32|mem|r64|m64}
+  ROW(3, 1, 1, 0, 46 , 149, 10 , 0  , 0  , 0  ), // #454 {xmm|m128|mem, ymm|zmm, i8|u8}
+  ROW(4, 1, 1, 0, 45 , 45 , 60 , 10 , 0  , 0  ), // #455 {xmm, xmm, xmm|m64|mem, i8|u8}
+  ROW(4, 1, 1, 0, 45 , 45 , 88 , 10 , 0  , 0  ), // #456 {xmm, xmm, xmm|m32|mem, i8|u8}
+  ROW(3, 1, 1, 0, 85 , 151, 10 , 0  , 0  , 0  ), // #457 {k, xmm|m128|ymm|m256|zmm|m512, i8|u8}
+  ROW(3, 1, 1, 0, 85 , 60 , 10 , 0  , 0  , 0  ), // #458 {k, xmm|m64|mem, i8|u8}
+  ROW(3, 1, 1, 0, 85 , 88 , 10 , 0  , 0  , 0  ), // #459 {k, xmm|m32|mem, i8|u8}
+  ROW(1, 1, 1, 0, 63 , 0  , 0  , 0  , 0  , 0  ), // #460 {vm32y}
+  ROW(1, 1, 1, 0, 64 , 0  , 0  , 0  , 0  , 0  ), // #461 {vm32z}
+  ROW(1, 1, 1, 0, 67 , 0  , 0  , 0  , 0  , 0  ), // #462 {vm64z}
+  ROW(4, 1, 1, 0, 51 , 51 , 49 , 10 , 0  , 0  ), // #463 {zmm, zmm, ymm|m256|mem, i8|u8}
+  ROW(2, 1, 1, 0, 6  , 87 , 0  , 0  , 0  , 0  ), // #464 {r32, xmm|ymm}
+  ROW(2, 1, 1, 0, 150, 152, 0  , 0  , 0  , 0  ), // #465 {xmm|ymm|zmm, xmm|m8|mem|r32|r8lo|r8hi|r16}
+  ROW(2, 1, 1, 0, 150, 153, 0  , 0  , 0  , 0  ), // #466 {xmm|ymm|zmm, xmm|m32|mem|r32}
+  ROW(2, 1, 1, 0, 150, 85 , 0  , 0  , 0  , 0  ), // #467 {xmm|ymm|zmm, k}
+  ROW(2, 1, 1, 0, 150, 154, 0  , 0  , 0  , 0  ), // #468 {xmm|ymm|zmm, xmm|m16|mem|r32|r16}
+  ROW(3, 1, 1, 0, 114, 45 , 10 , 0  , 0  , 0  ), // #469 {r32|m16|mem|r16, xmm, i8|u8}
+  ROW(4, 1, 1, 0, 45 , 45 , 110, 10 , 0  , 0  ), // #470 {xmm, xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8}
+  ROW(4, 1, 1, 0, 45 , 45 , 28 , 10 , 0  , 0  ), // #471 {xmm, xmm, r32|m32|mem, i8|u8}
+  ROW(4, 0, 1, 0, 45 , 45 , 15 , 10 , 0  , 0  ), // #472 {xmm, xmm, r64|m64|mem, i8|u8}
+  ROW(4, 1, 1, 0, 45 , 45 , 114, 10 , 0  , 0  ), // #473 {xmm, xmm, r32|m16|mem|r16, i8|u8}
+  ROW(2, 1, 1, 0, 85 , 150, 0  , 0  , 0  , 0  ), // #474 {k, xmm|ymm|zmm}
+  ROW(1, 1, 1, 0, 103, 0  , 0  , 0  , 0  , 0  ), // #475 {rel16|rel32}
+  ROW(3, 1, 1, 2, 92 , 35 , 36 , 0  , 0  , 0  ), // #476 {mem, <edx>, <eax>}
+  ROW(3, 0, 1, 2, 92 , 35 , 36 , 0  , 0  , 0  )  // #477 {mem, <edx>, <eax>}
+};
+#undef ROW
+
+#define ROW(flags, mFlags, extFlags, regId) { uint32_t(flags), uint16_t(mFlags), uint8_t(extFlags), uint8_t(regId) }
+#define F(VAL) InstDB::kOp##VAL
+#define M(VAL) InstDB::kMemOp##VAL
+const InstDB::OpSignature InstDB::_opSignatureTable[] = {
+  ROW(0, 0, 0, 0xFF),
+  ROW(F(GpbLo) | F(GpbHi) | F(Mem), M(M8) | M(Any), 0, 0x00),
+  ROW(F(GpbLo) | F(GpbHi), 0, 0, 0x00),
+  ROW(F(Gpw) | F(SReg) | F(Mem), M(M16) | M(Any), 0, 0x00),
+  ROW(F(Gpw), 0, 0, 0x00),
+  ROW(F(Gpd) | F(SReg) | F(Mem), M(M32) | M(Any), 0, 0x00),
+  ROW(F(Gpd), 0, 0, 0x00),
+  ROW(F(Gpq) | F(SReg) | F(CReg) | F(DReg) | F(Mem), M(M64) | M(Any), 0, 0x00),
+  ROW(F(Gpq), 0, 0, 0x00),
+  ROW(F(GpbLo) | F(GpbHi) | F(Mem), M(M8), 0, 0x00),
+  ROW(F(I8) | F(U8), 0, 0, 0x00),
+  ROW(F(Gpw) | F(Mem), M(M16), 0, 0x00),
+  ROW(F(I16) | F(U16), 0, 0, 0x00),
+  ROW(F(Gpd) | F(Mem), M(M32), 0, 0x00),
+  ROW(F(I32) | F(U32), 0, 0, 0x00),
+  ROW(F(Gpq) | F(Mem), M(M64) | M(Any), 0, 0x00),
+  ROW(F(I32), 0, 0, 0x00),
+  ROW(F(SReg) | F(CReg) | F(DReg) | F(Mem) | F(I64) | F(U64), M(M64) | M(Any), 0, 0x00),
+  ROW(F(Mem), M(M8) | M(Any), 0, 0x00),
+  ROW(F(SReg) | F(Mem), M(M16) | M(Any), 0, 0x00),
+  ROW(F(SReg) | F(Mem), M(M32) | M(Any), 0, 0x00),
+  ROW(F(Mem), M(M16) | M(Any), 0, 0x00),
+  ROW(F(SReg), 0, 0, 0x00),
+  ROW(F(CReg) | F(DReg), 0, 0, 0x00),
+  ROW(F(Gpq) | F(I32), 0, 0, 0x00),
+  ROW(F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M16) | M(M32) | M(M64) | M(Any), 0, 0x00),
+  ROW(F(I8), 0, 0, 0x00),
+  ROW(F(Gpw) | F(Mem), M(M16) | M(Any), 0, 0x00),
+  ROW(F(Gpd) | F(Mem), M(M32) | M(Any), 0, 0x00),
+  ROW(F(Mem), M(M32) | M(Any), 0, 0x00),
+  ROW(F(Mem), M(M64) | M(Any), 0, 0x00),
+  ROW(F(GpbLo) | F(GpbHi) | F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M8) | M(M16) | M(M32) | M(M64) | M(Any), 0, 0x00),
+  ROW(F(Gpq) | F(Mem) | F(I32) | F(U32), M(M64) | M(Any), 0, 0x00),
+  ROW(F(Gpw) | F(Implicit), 0, 0, 0x01),
+  ROW(F(Gpw) | F(Implicit), 0, 0, 0x04),
+  ROW(F(Gpd) | F(Implicit), 0, 0, 0x04),
+  ROW(F(Gpd) | F(Implicit), 0, 0, 0x01),
+  ROW(F(Gpq) | F(Implicit), 0, 0, 0x04),
+  ROW(F(Gpq) | F(Implicit), 0, 0, 0x01),
+  ROW(F(Gpw) | F(Mem) | F(I8) | F(I16), M(M16) | M(Any), 0, 0x00),
+  ROW(F(Gpd) | F(Mem) | F(I8) | F(I32), M(M32) | M(Any), 0, 0x00),
+  ROW(F(Gpq) | F(Mem) | F(I8) | F(I32), M(M64) | M(Any), 0, 0x00),
+  ROW(F(I8) | F(I16) | F(U16), 0, 0, 0x00),
+  ROW(F(I8) | F(I32) | F(U32), 0, 0, 0x00),
+  ROW(F(I8) | F(I32), 0, 0, 0x00),
+  ROW(F(Xmm), 0, 0, 0x00),
+  ROW(F(Xmm) | F(Mem), M(M128) | M(Any), 0, 0x00),
+  ROW(F(Mem), M(M128) | M(Any), 0, 0x00),
+  ROW(F(Ymm), 0, 0, 0x00),
+  ROW(F(Ymm) | F(Mem), M(M256) | M(Any), 0, 0x00),
+  ROW(F(Mem), M(M256) | M(Any), 0, 0x00),
+  ROW(F(Zmm), 0, 0, 0x00),
+  ROW(F(Zmm) | F(Mem), M(M512) | M(Any), 0, 0x00),
+  ROW(F(Mem), M(M512) | M(Any), 0, 0x00),
+  ROW(F(Xmm) | F(Mem) | F(I8) | F(U8), M(M128) | M(Any), 0, 0x00),
+  ROW(F(Ymm) | F(Mem) | F(I8) | F(U8), M(M256) | M(Any), 0, 0x00),
+  ROW(F(Zmm) | F(Mem) | F(I8) | F(U8), M(M512) | M(Any), 0, 0x00),
+  ROW(F(Mm), 0, 0, 0x00),
+  ROW(F(Gpq) | F(Mm) | F(Mem), M(M64) | M(Any), 0, 0x00),
+  ROW(F(Xmm) | F(Mm), 0, 0, 0x00),
+  ROW(F(Xmm) | F(Mem), M(M64) | M(Any), 0, 0x00),
+  ROW(F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M16) | M(M32) | M(M64), 0, 0x00),
+  ROW(F(Vm), M(Vm32x), 0, 0x00),
+  ROW(F(Vm), M(Vm32y), 0, 0x00),
+  ROW(F(Vm), M(Vm32z), 0, 0x00),
+  ROW(F(Vm), M(Vm64x), 0, 0x00),
+  ROW(F(Vm), M(Vm64y), 0, 0x00),
+  ROW(F(Vm), M(Vm64z), 0, 0x00),
+  ROW(F(GpbLo) | F(Implicit), 0, 0, 0x01),
+  ROW(F(Gpw) | F(Gpq) | F(Mem), M(M16) | M(M64), 0, 0x00),
+  ROW(F(SReg), 0, 0, 0x1A),
+  ROW(F(SReg), 0, 0, 0x60),
+  ROW(F(Gpw) | F(Gpq) | F(Mem) | F(I8) | F(I16) | F(I32), M(M16) | M(M64), 0, 0x00),
+  ROW(F(Gpd) | F(Mem) | F(I32) | F(U32), M(M32), 0, 0x00),
+  ROW(F(SReg), 0, 0, 0x1E),
+  ROW(F(Vm), M(Vm64x) | M(Vm64y), 0, 0x00),
+  ROW(F(I4) | F(U4), 0, 0, 0x00),
+  ROW(F(Mem), M(M32) | M(M64), 0, 0x00),
+  ROW(F(St), 0, 0, 0x01),
+  ROW(F(St), 0, 0, 0x00),
+  ROW(F(Mem), M(M48) | M(Any), 0, 0x00),
+  ROW(F(Mem), M(M80) | M(Any), 0, 0x00),
+  ROW(F(GpbLo) | F(I8) | F(U8), 0, 0, 0x02),
+  ROW(F(Xmm) | F(KReg), 0, 0, 0x00),
+  ROW(F(Ymm) | F(KReg), 0, 0, 0x00),
+  ROW(F(KReg), 0, 0, 0x00),
+  ROW(F(Gpq) | F(Xmm) | F(Mem), M(M64) | M(Any), 0, 0x00),
+  ROW(F(Xmm) | F(Ymm), 0, 0, 0x00),
+  ROW(F(Xmm) | F(Mem), M(M32) | M(Any), 0, 0x00),
+  ROW(F(Xmm) | F(Mem), M(M16) | M(Any), 0, 0x00),
+  ROW(F(Bnd), 0, 0, 0x00),
+  ROW(F(Bnd) | F(Mem), M(Any), 0, 0x00),
+  ROW(F(Mem), M(Any), 0, 0x00),
+  ROW(F(Gpw) | F(Gpd) | F(Mem) | F(I32) | F(I64) | F(Rel32), M(M16) | M(M32), 0, 0x00),
+  ROW(F(Gpq) | F(Mem) | F(I32) | F(I64) | F(Rel32), M(M64) | M(Any), 0, 0x00),
+  ROW(F(GpbLo) | F(GpbHi) | F(Gpw) | F(Gpd) | F(Mem), M(M8) | M(M16) | M(M32), 0, 0x00),
+  ROW(F(GpbLo) | F(GpbHi) | F(Gpq) | F(Mem), M(M8) | M(M64), 0, 0x00),
+  ROW(F(Gpw) | F(Gpd), 0, 0, 0x00),
+  ROW(F(Mem), M(BaseOnly) | M(Es), 0, 0x00),
+  ROW(F(St) | F(Mem), M(M32) | M(M64), 0, 0x00),
+  ROW(F(Gpd) | F(Implicit), 0, 0, 0x02),
+  ROW(F(Gpd) | F(Gpq) | F(Implicit), 0, 0, 0x01),
+  ROW(F(I32) | F(I64) | F(Rel8) | F(Rel32), 0, 0, 0x00),
+  ROW(F(I32) | F(I64) | F(Rel32), 0, 0, 0x00),
+  ROW(F(Gpw) | F(Gpd) | F(Implicit), 0, 0, 0x02),
+  ROW(F(I32) | F(I64) | F(Rel8), 0, 0, 0x00),
+  ROW(F(Gpd) | F(Gpq) | F(Implicit), 0, 0, 0x02),
+  ROW(F(Gpq) | F(Mem) | F(I32) | F(I64) | F(Rel8) | F(Rel32), M(M64) | M(Any), 0, 0x00),
+  ROW(F(Gpd) | F(Mem) | F(I32) | F(I64) | F(Rel32), M(M32) | M(Any), 0, 0x00),
+  ROW(F(GpbLo) | F(GpbHi) | F(Gpw) | F(Gpd) | F(KReg) | F(Mem), M(M8) | M(Any), 0, 0x00),
+  ROW(F(GpbLo) | F(GpbHi) | F(Gpw) | F(Gpd) | F(Mem), M(M8) | M(Any), 0, 0x00),
+  ROW(F(Gpd) | F(KReg) | F(Mem), M(M32) | M(Any), 0, 0x00),
+  ROW(F(Gpq) | F(KReg) | F(Mem), M(M64) | M(Any), 0, 0x00),
+  ROW(F(Gpw) | F(Gpd) | F(KReg) | F(Mem), M(M16) | M(Any), 0, 0x00),
+  ROW(F(Gpw) | F(Gpd) | F(Mem), M(M16) | M(Any), 0, 0x00),
+  ROW(F(Gpd) | F(Gpq), 0, 0, 0x00),
+  ROW(F(GpbLo) | F(GpbHi) | F(Gpw) | F(Mem), M(M8) | M(M16), 0, 0x00),
+  ROW(F(Mm) | F(Mem), M(M64) | M(Any), 0, 0x00),
+  ROW(F(Mm) | F(Mem) | F(I8) | F(U8), M(M64) | M(Any), 0, 0x00),
+  ROW(F(U16), 0, 0, 0x00),
+  ROW(F(Xmm) | F(Ymm) | F(Mem), M(M128) | M(M256), 0, 0x00),
+  ROW(F(Xmm) | F(I8) | F(U8), 0, 0, 0x00),
+  ROW(F(Xmm) | F(Implicit), 0, 0, 0x01),
+  ROW(F(Mem), M(Mib), 0, 0x00),
+  ROW(F(Gpw) | F(Gpd) | F(Gpq), 0, 0, 0x00),
+  ROW(F(Mem) | F(Implicit), M(BaseOnly) | M(Ds), 0, 0x01),
+  ROW(F(Mem) | F(Implicit), M(BaseOnly) | M(Ds), 0, 0x40),
+  ROW(F(Mem) | F(Implicit), M(BaseOnly) | M(Es), 0, 0x80),
+  ROW(F(Gpq) | F(Implicit), 0, 0, 0x02),
+  ROW(F(Gpq) | F(Implicit), 0, 0, 0x08),
+  ROW(F(Gpd) | F(Implicit), 0, 0, 0x08),
+  ROW(F(Gpd) | F(Gpq) | F(Mem), M(M32) | M(M64) | M(Any), 0, 0x00),
+  ROW(F(Mem), M(M16) | M(M32), 0, 0x00),
+  ROW(F(Mem), M(M16) | M(M32) | M(M64), 0, 0x00),
+  ROW(F(St) | F(Mem), M(M32) | M(M64) | M(M80), 0, 0x00),
+  ROW(F(Gpw) | F(Mem), M(M16) | M(Any), 0, 0x01),
+  ROW(F(GpbLo) | F(Gpw) | F(Gpd), 0, 0, 0x01),
+  ROW(F(Gpw) | F(I8) | F(U8), 0, 0, 0x04),
+  ROW(F(Mem), M(BaseOnly) | M(Es), 0, 0x80),
+  ROW(F(Gpw), 0, 0, 0x04),
+  ROW(F(GpbHi) | F(Implicit), 0, 0, 0x01),
+  ROW(F(Mem), M(M8) | M(M16) | M(M32) | M(M48) | M(M64) | M(M80) | M(M128) | M(M256) | M(M512) | M(M1024) | M(Any), 0, 0x00),
+  ROW(F(GpbLo) | F(Gpw) | F(Gpd) | F(Gpq) | F(Implicit), 0, 0, 0x01),
+  ROW(F(Mem) | F(Implicit), M(BaseOnly) | M(Ds), 0, 0x80),
+  ROW(F(Gpw) | F(U8), 0, 0, 0x04),
+  ROW(F(Mem), M(BaseOnly) | M(Ds), 0, 0x40),
+  ROW(F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M16) | M(Any), 0, 0x00),
+  ROW(F(Tmm), 0, 0, 0x00),
+  ROW(F(Mem), M(BaseOnly) | M(Ds), 0, 0x00),
+  ROW(F(Ymm) | F(Zmm), 0, 0, 0x00),
+  ROW(F(Xmm) | F(Ymm) | F(Zmm), 0, 0, 0x00),
+  ROW(F(Xmm) | F(Ymm) | F(Zmm) | F(Mem), M(M128) | M(M256) | M(M512), 0, 0x00),
+  ROW(F(GpbLo) | F(GpbHi) | F(Gpw) | F(Gpd) | F(Xmm) | F(Mem), M(M8) | M(Any), 0, 0x00),
+  ROW(F(Gpd) | F(Xmm) | F(Mem), M(M32) | M(Any), 0, 0x00),
+  ROW(F(Gpw) | F(Gpd) | F(Xmm) | F(Mem), M(M16) | M(Any), 0, 0x00)
+};
+#undef M
+#undef F
+#undef ROW
+// ----------------------------------------------------------------------------
+// ${InstSignatureTable:End}
+#endif // !ASMJIT_NO_VALIDATION
+
+// ============================================================================
+// [asmjit::x86::InstInternal - QueryRWInfo]
+// ============================================================================
+
+// ${InstRWInfoTable:Begin}
+// ------------------- Automatically generated, do not edit -------------------
+const uint8_t InstDB::rwInfoIndexA[Inst::_kIdCount] = {
+  0, 0, 1, 1, 0, 2, 3, 2, 4, 4, 5, 6, 4, 4, 3, 4, 4, 4, 4, 7, 0, 2, 0, 4, 4, 4,
+  4, 8, 0, 9, 9, 9, 9, 9, 0, 0, 0, 0, 9, 9, 9, 9, 9, 10, 10, 10, 11, 11, 12, 13,
+  14, 9, 9, 0, 15, 16, 16, 16, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+  3, 3, 3, 3, 3, 3, 18, 0, 0, 19, 0, 0, 0, 0, 0, 20, 21, 0, 22, 23, 24, 7, 25,
+  25, 25, 24, 26, 7, 24, 27, 28, 29, 30, 31, 32, 33, 25, 25, 7, 27, 28, 33, 34,
+  0, 0, 0, 0, 35, 4, 4, 5, 6, 0, 0, 0, 0, 0, 36, 36, 0, 0, 37, 0, 0, 38, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 38, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 38, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 4, 0, 4, 4, 35,
+  39, 40, 0, 0, 0, 41, 0, 37, 0, 0, 0, 0, 42, 0, 43, 42, 42, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 45, 46, 47, 48, 49, 50, 51,
+  52, 0, 0, 0, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 54, 55, 56, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 57, 58, 0, 59, 0, 60, 0, 59, 0, 59, 0, 59, 0, 0,
+  0, 0, 61, 62, 62, 62, 57, 59, 0, 0, 0, 9, 0, 0, 4, 4, 5, 6, 0, 0, 4, 4, 5, 6,
+  0, 0, 63, 64, 64, 65, 46, 24, 36, 65, 51, 64, 64, 66, 67, 67, 68, 69, 69, 70,
+  70, 58, 58, 65, 58, 58, 69, 69, 71, 47, 51, 72, 47, 7, 7, 46, 73, 9, 64, 64,
+  73, 0, 35, 4, 4, 5, 6, 0, 74, 0, 0, 75, 0, 2, 4, 4, 76, 77, 9, 9, 9, 3, 3, 4,
+  3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 3, 3, 0, 3, 78, 3, 0, 0, 0, 3, 3, 4, 3, 0, 0, 3,
+  3, 4, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 27, 78, 78, 78, 78, 78, 78, 78, 78, 78,
+  78, 27, 78, 78, 78, 27, 27, 78, 78, 78, 3, 3, 3, 79, 3, 3, 3, 27, 27, 0, 0,
+  0, 0, 3, 3, 4, 4, 3, 3, 4, 4, 4, 4, 3, 3, 4, 4, 80, 81, 82, 24, 24, 24, 81, 81,
+  82, 24, 24, 24, 81, 4, 3, 78, 3, 3, 4, 3, 3, 0, 0, 0, 9, 0, 0, 0, 3, 0, 0,
+  0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 83, 3, 3, 0, 3, 3, 3, 83, 3, 3, 3,
+  3, 3, 3, 3, 3, 3, 3, 27, 84, 0, 3, 3, 4, 3, 3, 3, 4, 3, 0, 0, 0, 0, 0, 0, 0,
+  3, 85, 7, 86, 85, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 87, 0, 0, 0, 0, 85, 85, 0,
+  0, 0, 0, 0, 0, 7, 86, 0, 0, 85, 85, 0, 0, 2, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4,
+  4, 0, 4, 4, 0, 85, 0, 0, 85, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 7, 26, 86, 0, 0,
+  0, 0, 0, 0, 89, 0, 0, 2, 4, 4, 5, 6, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 15,
+  90, 90, 0, 91, 0, 0, 9, 9, 20, 21, 0, 0, 0, 0, 0, 4, 4, 4, 4, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 92, 28, 93, 94, 93, 94, 92, 28, 93, 94, 93, 94, 95, 96, 0, 0, 0, 0, 20, 21,
+  97, 97, 98, 9, 0, 73, 99, 99, 9, 99, 9, 98, 9, 98, 0, 98, 9, 98, 9, 99, 28,
+  0, 28, 0, 0, 0, 33, 33, 99, 9, 99, 9, 9, 98, 9, 98, 28, 28, 33, 33, 98, 9, 9,
+  99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 100, 100, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 27, 101, 59, 59, 0, 0, 0, 0, 0,
+  0, 0, 0, 59, 59, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 102,
+  102, 46, 103, 102, 102, 102, 102, 102, 102, 102, 102, 0, 104, 104, 0, 69, 69,
+  105, 106, 65, 65, 65, 65, 107, 69, 9, 9, 71, 102, 102, 0, 0, 0, 97, 0, 0, 0,
+  0, 0, 0, 0, 108, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 109, 33, 110, 110, 28, 111, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 97, 97, 97,
+  97, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 59, 59, 59, 59, 7,
+  7, 7, 0, 7, 0, 7, 7, 7, 7, 7, 7, 0, 7, 7, 79, 7, 0, 7, 0, 0, 7, 0, 0, 0, 0, 9,
+  9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 112, 112, 113, 114, 110, 110, 110, 110, 80, 112,
+  115, 114, 113, 113, 114, 115, 114, 113, 114, 116, 117, 98, 98, 98, 116, 113, 114,
+  115, 114, 113, 114, 112, 114, 116, 117, 98, 98, 98, 116, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 65,
+  118, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 100, 100, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 100, 100, 0, 0, 9, 0, 0, 0, 0, 0, 65, 65, 0, 0,
+  0, 0, 0, 0, 0, 0, 65, 118, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 108, 108,
+  20, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 119, 120, 119, 120, 0, 121,
+  0, 122, 0, 0, 0, 2, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = {
+  0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 3, 0, 0, 0,
+  0, 0, 4, 0, 0, 0, 0, 0, 5, 5, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 7, 0, 0, 0, 0, 4, 8, 1, 0, 9, 0, 0, 0, 10, 10, 10, 0, 0, 11, 0, 10, 12, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 5, 5, 0, 13, 14, 15, 16, 17, 0, 0, 18, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 1, 1, 20, 21, 0, 0, 0,
+  0, 5, 5, 0, 0, 0, 0, 0, 0, 22, 23, 0, 0, 24, 25, 26, 27, 0, 0, 25, 25, 25, 25,
+  25, 25, 25, 25, 28, 29, 29, 28, 0, 0, 0, 24, 25, 24, 25, 0, 25, 24, 24, 24, 24,
+  24, 24, 24, 0, 0, 30, 30, 30, 24, 24, 28, 0, 31, 10, 0, 0, 0, 0, 0, 0, 24,
+  25, 0, 0, 0, 32, 33, 32, 34, 0, 0, 0, 0, 0, 10, 32, 0, 0, 0, 0, 35, 33, 32, 35,
+  34, 24, 25, 24, 25, 0, 29, 29, 29, 29, 0, 0, 0, 25, 10, 10, 32, 32, 0, 0, 0,
+  0, 5, 5, 0, 0, 0, 0, 0, 0, 21, 36, 0, 20, 37, 38, 0, 39, 40, 0, 0, 0, 0, 0, 10,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 44, 41, 42, 41, 42, 43,
+  44, 43, 44, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 0, 0, 0, 0, 44, 45, 46, 47, 48,
+  45, 46, 47, 48, 0, 0, 0, 0, 49, 50, 51, 41, 42, 43, 44, 41, 42, 43, 44, 52,
+  0, 0, 53, 0, 54, 0, 0, 0, 0, 0, 10, 0, 10, 55, 56, 55, 0, 0, 0, 0, 0, 0, 55, 57,
+  57, 0, 58, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 60, 60, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 5, 61, 0, 0, 0, 0, 62, 0, 63, 20, 64, 20, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 6, 5, 5, 0, 0,
+  0, 0, 66, 67, 0, 0, 0, 0, 68, 69, 0, 3, 3, 70, 22, 71, 72, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 39,
+  74, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 0, 0, 0, 0, 0, 0, 0, 10, 10, 10, 10, 10,
+  10, 10, 0, 0, 2, 2, 2, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 78, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 79, 79, 80, 79, 80, 80, 80, 79, 79, 81, 82, 0, 83, 0, 0, 0, 0, 0, 84,
+  2, 2, 85, 86, 0, 0, 0, 11, 87, 0, 0, 4, 0, 0, 0, 0, 88, 88, 88, 88, 88, 88,
+  88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88,
+  88, 88, 88, 0, 88, 0, 32, 0, 0, 0, 5, 0, 0, 6, 0, 89, 4, 0, 89, 4, 5, 5, 32,
+  19, 90, 79, 90, 0, 0, 0, 0, 0, 0, 0, 0, 0, 91, 0, 90, 92, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 93, 93, 93, 93, 93, 0, 0, 0, 0, 0, 94, 95, 0, 0, 0, 0, 96,
+  96, 0, 56, 95, 0, 0, 0, 0, 97, 98, 97, 98, 3, 3, 99, 100, 3, 3, 3, 3, 3, 3,
+  0, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 101, 101, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 3, 3, 102, 103, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 104, 0, 0, 0, 0, 0, 0, 105, 0, 106, 107, 108, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 107, 3, 3, 3, 99, 100, 3, 109, 3, 55, 55, 0,
+  0, 0, 0, 110, 111, 112, 111, 112, 110, 111, 112, 111, 112, 22, 113, 113, 114,
+  115, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 116, 117, 118, 118, 119,
+  120, 113, 113, 113, 113, 113, 113, 118, 118, 113, 113, 116, 117, 113, 113,
+  116, 117, 113, 113, 116, 117, 113, 113, 113, 113, 113, 113, 118, 118, 118, 118,
+  119, 120, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 116, 117, 118,
+  118, 119, 120, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 121, 122, 118,
+  118, 119, 120, 123, 123, 77, 124, 0, 0, 0, 0, 125, 126, 10, 10, 10, 10, 10,
+  10, 10, 10, 126, 127, 0, 0, 128, 129, 84, 84, 128, 129, 3, 3, 3, 3, 3, 3, 3, 130,
+  131, 132, 131, 132, 130, 131, 132, 131, 132, 100, 0, 53, 58, 133, 133, 3,
+  3, 99, 100, 0, 134, 0, 3, 3, 99, 100, 0, 135, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 136, 137, 137, 138, 139, 139, 0, 0, 0, 0, 0, 0, 0, 140, 0, 0, 141, 0, 0,
+  3, 11, 134, 0, 0, 142, 135, 3, 3, 99, 100, 0, 11, 3, 3, 143, 143, 144, 144,
+  0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+  101, 3, 0, 0, 0, 0, 0, 0, 3, 118, 145, 145, 3, 3, 3, 3, 66, 67, 3, 3, 3, 3, 68,
+  69, 145, 145, 145, 145, 145, 145, 109, 109, 0, 0, 0, 0, 109, 109, 109, 109,
+  109, 109, 0, 0, 113, 113, 113, 113, 146, 146, 3, 3, 3, 113, 3, 3, 113, 113, 118,
+  118, 147, 147, 147, 3, 147, 3, 113, 113, 113, 113, 113, 3, 0, 0, 0, 0, 70,
+  22, 71, 148, 126, 125, 127, 126, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 0, 3, 0, 0,
+  0, 0, 3, 0, 3, 3, 0, 149, 100, 99, 150, 0, 0, 151, 151, 151, 151, 151, 151, 151,
+  151, 151, 151, 151, 151, 113, 113, 3, 3, 133, 133, 3, 3, 3, 3, 3, 3, 3, 3,
+  3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3,
+  3, 3, 3, 3, 0, 0, 0, 0, 3, 3, 3, 152, 84, 84, 3, 3, 84, 84, 3, 3, 153, 153, 153,
+  153, 3, 0, 0, 0, 0, 153, 153, 153, 153, 153, 153, 3, 3, 113, 113, 113, 3, 153,
+  153, 3, 3, 113, 113, 113, 3, 3, 145, 84, 84, 84, 3, 3, 3, 154, 155, 154, 3,
+  3, 3, 154, 154, 154, 3, 3, 3, 154, 154, 155, 154, 3, 3, 3, 154, 3, 3, 3, 3,
+  3, 3, 3, 3, 113, 113, 0, 145, 145, 145, 145, 145, 145, 145, 145, 3, 3, 3, 3, 3,
+  3, 3, 3, 3, 3, 3, 3, 3, 128, 129, 0, 0, 128, 129, 0, 0, 128, 129, 0, 129, 84,
+  84, 128, 129, 84, 84, 128, 129, 84, 84, 128, 129, 0, 0, 128, 129, 0, 0, 128,
+  129, 0, 129, 3, 3, 99, 100, 0, 0, 10, 10, 10, 10, 10, 10, 10, 10, 0, 0, 3, 3,
+  3, 3, 3, 3, 0, 0, 128, 129, 91, 3, 3, 99, 100, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3,
+  0, 0, 0, 0, 56, 56, 156, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80, 0, 0, 0, 0, 0, 157, 157,
+  157, 157, 158, 158, 158, 158, 158, 158, 158, 158, 156, 0, 0
+};
+
+const InstDB::RWInfo InstDB::rwInfoA[] = {
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 0 , 0 , 0 , 0 , 0 , 0  } }, // #0 [ref=931x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 1 , 0 , 0 , 0 , 0 , 0  } }, // #1 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 1 , { 2 , 3 , 0 , 0 , 0 , 0  } }, // #2 [ref=7x]
+  { InstDB::RWInfo::kCategoryGeneric   , 2 , { 2 , 3 , 0 , 0 , 0 , 0  } }, // #3 [ref=99x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 4 , 5 , 0 , 0 , 0 , 0  } }, // #4 [ref=55x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 6 , 7 , 0 , 0 , 0 , 0  } }, // #5 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 8 , 9 , 0 , 0 , 0 , 0  } }, // #6 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 10, 5 , 0 , 0 , 0 , 0  } }, // #7 [ref=26x]
+  { InstDB::RWInfo::kCategoryGeneric   , 7 , { 12, 13, 0 , 0 , 0 , 0  } }, // #8 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 2 , { 11, 3 , 0 , 0 , 0 , 0  } }, // #9 [ref=65x]
+  { InstDB::RWInfo::kCategoryGeneric   , 2 , { 5 , 3 , 0 , 0 , 0 , 0  } }, // #10 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 8 , { 10, 3 , 0 , 0 , 0 , 0  } }, // #11 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 9 , { 10, 5 , 0 , 0 , 0 , 0  } }, // #12 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 8 , { 15, 5 , 0 , 0 , 0 , 0  } }, // #13 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 3 , 3 , 0 , 0 , 0 , 0  } }, // #14 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 10, { 3 , 3 , 0 , 0 , 0 , 0  } }, // #15 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 10, { 2 , 3 , 0 , 0 , 0 , 0  } }, // #16 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 16, 17, 0 , 0 , 0 , 0  } }, // #17 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 1 , { 3 , 3 , 0 , 0 , 0 , 0  } }, // #18 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 20, 21, 0 , 0 , 0 , 0  } }, // #19 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 7 , 7 , 0 , 0 , 0 , 0  } }, // #20 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 9 , 9 , 0 , 0 , 0 , 0  } }, // #21 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 33, 34, 0 , 0 , 0 , 0  } }, // #22 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 14, { 2 , 3 , 0 , 0 , 0 , 0  } }, // #23 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 10, 7 , 0 , 0 , 0 , 0  } }, // #24 [ref=10x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 35, 5 , 0 , 0 , 0 , 0  } }, // #25 [ref=5x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 36, 7 , 0 , 0 , 0 , 0  } }, // #26 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 35, 7 , 0 , 0 , 0 , 0  } }, // #27 [ref=11x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 11, 7 , 0 , 0 , 0 , 0  } }, // #28 [ref=9x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 37, 7 , 0 , 0 , 0 , 0  } }, // #29 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 14, { 36, 3 , 0 , 0 , 0 , 0  } }, // #30 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 14, { 37, 3 , 0 , 0 , 0 , 0  } }, // #31 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 36, 9 , 0 , 0 , 0 , 0  } }, // #32 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 11, 9 , 0 , 0 , 0 , 0  } }, // #33 [ref=7x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 38, 39, 0 , 0 , 0 , 0  } }, // #34 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 15, { 1 , 40, 0 , 0 , 0 , 0  } }, // #35 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 16, { 11, 43, 0 , 0 , 0 , 0  } }, // #36 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 4 , 5 , 0 , 0 , 0 , 0  } }, // #37 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 45, 46, 0 , 0 , 0 , 0  } }, // #38 [ref=6x]
+  { InstDB::RWInfo::kCategoryImul      , 2 , { 0 , 0 , 0 , 0 , 0 , 0  } }, // #39 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 50, 51, 0 , 0 , 0 , 0  } }, // #40 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 53, 51, 0 , 0 , 0 , 0  } }, // #41 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 13, { 3 , 5 , 0 , 0 , 0 , 0  } }, // #42 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 22, 29, 0 , 0 , 0 , 0  } }, // #43 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 54, 0 , 0 , 0 , 0 , 0  } }, // #44 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 23, { 55, 40, 0 , 0 , 0 , 0  } }, // #45 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 24, { 44, 9 , 0 , 0 , 0 , 0  } }, // #46 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 25, { 35, 7 , 0 , 0 , 0 , 0  } }, // #47 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 26, { 48, 13, 0 , 0 , 0 , 0  } }, // #48 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 55, 40, 0 , 0 , 0 , 0  } }, // #49 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 44, 9 , 0 , 0 , 0 , 0  } }, // #50 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 35, 7 , 0 , 0 , 0 , 0  } }, // #51 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 48, 13, 0 , 0 , 0 , 0  } }, // #52 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 40, 40, 0 , 0 , 0 , 0  } }, // #53 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 9 , 9 , 0 , 0 , 0 , 0  } }, // #54 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 7 , 7 , 0 , 0 , 0 , 0  } }, // #55 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 13, 13, 0 , 0 , 0 , 0  } }, // #56 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 27, { 11, 3 , 0 , 0 , 0 , 0  } }, // #57 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 13, { 10, 5 , 0 , 0 , 0 , 0  } }, // #58 [ref=5x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 2 , 3 , 0 , 0 , 0 , 0  } }, // #59 [ref=13x]
+  { InstDB::RWInfo::kCategoryGeneric   , 8 , { 11, 3 , 0 , 0 , 0 , 0  } }, // #60 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 50, 20, 0 , 0 , 0 , 0  } }, // #61 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 57, 0 , 0 , 0 , 0 , 0  } }, // #62 [ref=3x]
+  { InstDB::RWInfo::kCategoryMov       , 29, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #63 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 30, { 10, 5 , 0 , 0 , 0 , 0  } }, // #64 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 11, 3 , 0 , 0 , 0 , 0  } }, // #65 [ref=14x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 36, 60, 0 , 0 , 0 , 0  } }, // #66 [ref=1x]
+  { InstDB::RWInfo::kCategoryMovh64    , 12, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #67 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 61, 7 , 0 , 0 , 0 , 0  } }, // #68 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 12, { 35, 7 , 0 , 0 , 0 , 0  } }, // #69 [ref=7x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 55, 5 , 0 , 0 , 0 , 0  } }, // #70 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 28, { 44, 9 , 0 , 0 , 0 , 0  } }, // #71 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 62, 20, 0 , 0 , 0 , 0  } }, // #72 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 14, { 11, 3 , 0 , 0 , 0 , 0  } }, // #73 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 17, 29, 0 , 0 , 0 , 0  } }, // #74 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 11, { 3 , 3 , 0 , 0 , 0 , 0  } }, // #75 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 51, 22, 0 , 0 , 0 , 0  } }, // #76 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 51, 65, 0 , 0 , 0 , 0  } }, // #77 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 26, 7 , 0 , 0 , 0 , 0  } }, // #78 [ref=18x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 68, 5 , 0 , 0 , 0 , 0  } }, // #79 [ref=2x]
+  { InstDB::RWInfo::kCategoryVmov1_8   , 0 , { 0 , 0 , 0 , 0 , 0 , 0  } }, // #80 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 10, 9 , 0 , 0 , 0 , 0  } }, // #81 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 27, { 10, 13, 0 , 0 , 0 , 0  } }, // #82 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 4 , 0 , 0 , 0 , 0 , 0  } }, // #83 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 5 , 5 , 0 , 0 , 0 , 0  } }, // #84 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 10, { 2 , 70, 0 , 0 , 0 , 0  } }, // #85 [ref=8x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 37, 9 , 0 , 0 , 0 , 0  } }, // #86 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 16, 71, 0 , 0 , 0 , 0  } }, // #87 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 22, 21, 0 , 0 , 0 , 0  } }, // #88 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 62, 22, 0 , 0 , 0 , 0  } }, // #89 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 8 , { 74, 3 , 0 , 0 , 0 , 0  } }, // #90 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 8 , { 11, 43, 0 , 0 , 0 , 0  } }, // #91 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 13, { 76, 5 , 0 , 0 , 0 , 0  } }, // #92 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 13, { 11, 5 , 0 , 0 , 0 , 0  } }, // #93 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 37, { 74, 77, 0 , 0 , 0 , 0  } }, // #94 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 38, { 11, 7 , 0 , 0 , 0 , 0  } }, // #95 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 39, { 11, 9 , 0 , 0 , 0 , 0  } }, // #96 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 11, { 11, 3 , 0 , 0 , 0 , 0  } }, // #97 [ref=7x]
+  { InstDB::RWInfo::kCategoryVmov2_1   , 40, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #98 [ref=14x]
+  { InstDB::RWInfo::kCategoryVmov1_2   , 14, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #99 [ref=7x]
+  { InstDB::RWInfo::kCategoryGeneric   , 44, { 74, 43, 0 , 0 , 0 , 0  } }, // #100 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 44, 9 , 0 , 0 , 0 , 0  } }, // #101 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 51, { 11, 3 , 0 , 0 , 0 , 0  } }, // #102 [ref=12x]
+  { InstDB::RWInfo::kCategoryVmovddup  , 52, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #103 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 12, { 35, 60, 0 , 0 , 0 , 0  } }, // #104 [ref=2x]
+  { InstDB::RWInfo::kCategoryVmovmskpd , 0 , { 0 , 0 , 0 , 0 , 0 , 0  } }, // #105 [ref=1x]
+  { InstDB::RWInfo::kCategoryVmovmskps , 0 , { 0 , 0 , 0 , 0 , 0 , 0  } }, // #106 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 53, { 35, 7 , 0 , 0 , 0 , 0  } }, // #107 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 2 , { 3 , 3 , 0 , 0 , 0 , 0  } }, // #108 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 15, { 11, 40, 0 , 0 , 0 , 0  } }, // #109 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 11, 7 , 0 , 0 , 0 , 0  } }, // #110 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 27, { 11, 13, 0 , 0 , 0 , 0  } }, // #111 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 35, 3 , 0 , 0 , 0 , 0  } }, // #112 [ref=4x]
+  { InstDB::RWInfo::kCategoryVmov1_4   , 57, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #113 [ref=6x]
+  { InstDB::RWInfo::kCategoryVmov1_2   , 41, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #114 [ref=9x]
+  { InstDB::RWInfo::kCategoryVmov1_8   , 58, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #115 [ref=3x]
+  { InstDB::RWInfo::kCategoryVmov4_1   , 59, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #116 [ref=4x]
+  { InstDB::RWInfo::kCategoryVmov8_1   , 60, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #117 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 18, { 11, 3 , 0 , 0 , 0 , 0  } }, // #118 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 17, { 44, 9 , 0 , 0 , 0 , 0  } }, // #119 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 32, { 35, 7 , 0 , 0 , 0 , 0  } }, // #120 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 11, { 2 , 2 , 0 , 0 , 0 , 0  } }, // #121 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 51, { 2 , 2 , 0 , 0 , 0 , 0  } }  // #122 [ref=1x]
+};
+
+const InstDB::RWInfo InstDB::rwInfoB[] = {
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 0 , 0 , 0 , 0 , 0 , 0  } }, // #0 [ref=734x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 1 , 0 , 0 , 0 , 0 , 0  } }, // #1 [ref=5x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 10, 5 , 0 , 0 , 0 , 0  } }, // #2 [ref=7x]
+  { InstDB::RWInfo::kCategoryGeneric   , 6 , { 11, 3 , 3 , 0 , 0 , 0  } }, // #3 [ref=186x]
+  { InstDB::RWInfo::kCategoryGeneric   , 2 , { 11, 3 , 3 , 0 , 0 , 0  } }, // #4 [ref=5x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 4 , 5 , 0 , 0 , 0 , 0  } }, // #5 [ref=14x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 4 , 5 , 14, 0 , 0 , 0  } }, // #6 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 2 , 0 , 0 , 0 , 0 , 0  } }, // #7 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 11, { 3 , 0 , 0 , 0 , 0 , 0  } }, // #8 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 18, 0 , 0 , 0 , 0 , 0  } }, // #9 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 8 , { 3 , 0 , 0 , 0 , 0 , 0  } }, // #10 [ref=34x]
+  { InstDB::RWInfo::kCategoryGeneric   , 12, { 7 , 0 , 0 , 0 , 0 , 0  } }, // #11 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 19, 0 , 0 , 0 , 0 , 0  } }, // #12 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 6 , 7 , 0 , 0 , 0 , 0  } }, // #13 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 8 , 9 , 0 , 0 , 0 , 0  } }, // #14 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 11, { 2 , 3 , 22, 0 , 0 , 0  } }, // #15 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 13, { 4 , 23, 18, 24, 25, 0  } }, // #16 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 12, { 26, 27, 28, 29, 30, 0  } }, // #17 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 28, 31, 32, 16, 0 , 0  } }, // #18 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 28, 0 , 0 , 0 , 0 , 0  } }, // #19 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 10, { 2 , 0 , 0 , 0 , 0 , 0  } }, // #20 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 6 , { 41, 42, 3 , 0 , 0 , 0  } }, // #21 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 17, { 44, 5 , 0 , 0 , 0 , 0  } }, // #22 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 4 , 0 , 0 , 0 , 0 , 0  } }, // #23 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 18, { 3 , 0 , 0 , 0 , 0 , 0  } }, // #24 [ref=15x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 45, 0 , 0 , 0 , 0 , 0  } }, // #25 [ref=16x]
+  { InstDB::RWInfo::kCategoryGeneric   , 19, { 46, 0 , 0 , 0 , 0 , 0  } }, // #26 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 19, { 47, 0 , 0 , 0 , 0 , 0  } }, // #27 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 20, { 3 , 0 , 0 , 0 , 0 , 0  } }, // #28 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 46, 0 , 0 , 0 , 0 , 0  } }, // #29 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 18, { 11, 0 , 0 , 0 , 0 , 0  } }, // #30 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 21, { 13, 0 , 0 , 0 , 0 , 0  } }, // #31 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 8 , { 11, 0 , 0 , 0 , 0 , 0  } }, // #32 [ref=8x]
+  { InstDB::RWInfo::kCategoryGeneric   , 21, { 48, 0 , 0 , 0 , 0 , 0  } }, // #33 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 7 , { 49, 0 , 0 , 0 , 0 , 0  } }, // #34 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 20, { 11, 0 , 0 , 0 , 0 , 0  } }, // #35 [ref=2x]
+  { InstDB::RWInfo::kCategoryImul      , 22, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #36 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 52, 0 , 0 , 0 , 0 , 0  } }, // #37 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 26, 0 , 0 , 0 , 0 , 0  } }, // #38 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 4 , 9 , 0 , 0 , 0 , 0  } }, // #39 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 4 , 5 , 0 , 0 , 0 , 0  } }, // #40 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 55, 40, 40, 0 , 0 , 0  } }, // #41 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 44, 9 , 9 , 0 , 0 , 0  } }, // #42 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 35, 7 , 7 , 0 , 0 , 0  } }, // #43 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 48, 13, 13, 0 , 0 , 0  } }, // #44 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 55, 40, 0 , 0 , 0 , 0  } }, // #45 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 44, 9 , 0 , 0 , 0 , 0  } }, // #46 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 35, 7 , 0 , 0 , 0 , 0  } }, // #47 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 48, 13, 0 , 0 , 0 , 0  } }, // #48 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 48, 40, 40, 0 , 0 , 0  } }, // #49 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 35, 9 , 9 , 0 , 0 , 0  } }, // #50 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 44, 13, 13, 0 , 0 , 0  } }, // #51 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 56, 0 , 0 , 0 , 0 , 0  } }, // #52 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 28, { 9 , 0 , 0 , 0 , 0 , 0  } }, // #53 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 16, { 43, 0 , 0 , 0 , 0 , 0  } }, // #54 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 7 , { 13, 0 , 0 , 0 , 0 , 0  } }, // #55 [ref=5x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 3 , 0 , 0 , 0 , 0 , 0  } }, // #56 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 3 , 9 , 0 , 0 , 0 , 0  } }, // #57 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 5 , 5 , 58, 0 , 0 , 0  } }, // #58 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 7 , 7 , 58, 0 , 0 , 0  } }, // #59 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 19, 29, 59, 0 , 0 , 0  } }, // #60 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 6 , { 63, 42, 3 , 0 , 0 , 0  } }, // #61 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 6 , { 11, 11, 3 , 64, 0 , 0  } }, // #62 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 17, 29, 30, 0 , 0 , 0  } }, // #63 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 10, { 3 , 0 , 0 , 0 , 0 , 0  } }, // #64 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 2 , { 2 , 3 , 0 , 0 , 0 , 0  } }, // #65 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 5 , 5 , 0 , 66, 17, 59 } }, // #66 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 5 , 5 , 0 , 67, 17, 59 } }, // #67 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 5 , 5 , 0 , 66, 0 , 0  } }, // #68 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 3 , { 5 , 5 , 0 , 67, 0 , 0  } }, // #69 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 31, { 55, 5 , 0 , 0 , 0 , 0  } }, // #70 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 32, { 35, 5 , 0 , 0 , 0 , 0  } }, // #71 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 33, { 48, 3 , 0 , 0 , 0 , 0  } }, // #72 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 15, { 4 , 40, 0 , 0 , 0 , 0  } }, // #73 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 4 , 7 , 0 , 0 , 0 , 0  } }, // #74 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 27, { 2 , 13, 0 , 0 , 0 , 0  } }, // #75 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 10, { 69, 0 , 0 , 0 , 0 , 0  } }, // #76 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 35, 7 , 0 , 0 , 0 , 0  } }, // #77 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 10, { 64, 0 , 0 , 0 , 0 , 0  } }, // #78 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 11, 0 , 0 , 0 , 0 , 0  } }, // #79 [ref=6x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 16, 71, 29, 0 , 0 , 0  } }, // #80 [ref=5x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 44, 0 , 0 , 0 , 0 , 0  } }, // #81 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 35, 0 , 0 , 0 , 0 , 0  } }, // #82 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 16, 71, 66, 0 , 0 , 0  } }, // #83 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 2 , { 11, 3 , 0 , 0 , 0 , 0  } }, // #84 [ref=16x]
+  { InstDB::RWInfo::kCategoryGeneric   , 4 , { 36, 7 , 0 , 0 , 0 , 0  } }, // #85 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 37, 9 , 0 , 0 , 0 , 0  } }, // #86 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 72, 0 , 0 , 0 , 0 , 0  } }, // #87 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 31, { 73, 0 , 0 , 0 , 0 , 0  } }, // #88 [ref=30x]
+  { InstDB::RWInfo::kCategoryGeneric   , 11, { 2 , 3 , 70, 0 , 0 , 0  } }, // #89 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 34, { 11, 0 , 0 , 0 , 0 , 0  } }, // #90 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 28, { 44, 0 , 0 , 0 , 0 , 0  } }, // #91 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 16, { 74, 0 , 0 , 0 , 0 , 0  } }, // #92 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 75, 43, 43, 0 , 0 , 0  } }, // #93 [ref=5x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 74, 0 , 0 , 0 , 0 , 0  } }, // #94 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 9 , 59, 17, 0 , 0 , 0  } }, // #95 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 17, { 52, 0 , 0 , 0 , 0 , 0  } }, // #96 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 13, { 75, 43, 43, 43, 43, 5  } }, // #97 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 13, { 4 , 5 , 5 , 5 , 5 , 5  } }, // #98 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 35, { 10, 5 , 7 , 0 , 0 , 0  } }, // #99 [ref=8x]
+  { InstDB::RWInfo::kCategoryGeneric   , 36, { 10, 5 , 9 , 0 , 0 , 0  } }, // #100 [ref=9x]
+  { InstDB::RWInfo::kCategoryGeneric   , 6 , { 11, 3 , 3 , 3 , 0 , 0  } }, // #101 [ref=3x]
+  { InstDB::RWInfo::kCategoryGeneric   , 35, { 11, 5 , 7 , 0 , 0 , 0  } }, // #102 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 36, { 11, 5 , 9 , 0 , 0 , 0  } }, // #103 [ref=1x]
+  { InstDB::RWInfo::kCategoryVmov1_2   , 41, { 0 , 0 , 0 , 0 , 0 , 0  } }, // #104 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 35, { 10, 78, 7 , 0 , 0 , 0  } }, // #105 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 42, { 10, 60, 3 , 0 , 0 , 0  } }, // #106 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 42, { 10, 78, 3 , 0 , 0 , 0  } }, // #107 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 36, { 10, 60, 9 , 0 , 0 , 0  } }, // #108 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 43, { 10, 5 , 5 , 0 , 0 , 0  } }, // #109 [ref=9x]
+  { InstDB::RWInfo::kCategoryGeneric   , 45, { 10, 77, 0 , 0 , 0 , 0  } }, // #110 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 45, { 10, 3 , 0 , 0 , 0 , 0  } }, // #111 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 46, { 76, 43, 0 , 0 , 0 , 0  } }, // #112 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 6 , { 2 , 3 , 3 , 0 , 0 , 0  } }, // #113 [ref=60x]
+  { InstDB::RWInfo::kCategoryGeneric   , 35, { 4 , 60, 7 , 0 , 0 , 0  } }, // #114 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 36, { 4 , 78, 9 , 0 , 0 , 0  } }, // #115 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 35, { 6 , 7 , 7 , 0 , 0 , 0  } }, // #116 [ref=11x]
+  { InstDB::RWInfo::kCategoryGeneric   , 36, { 8 , 9 , 9 , 0 , 0 , 0  } }, // #117 [ref=11x]
+  { InstDB::RWInfo::kCategoryGeneric   , 47, { 11, 3 , 3 , 3 , 0 , 0  } }, // #118 [ref=15x]
+  { InstDB::RWInfo::kCategoryGeneric   , 48, { 35, 7 , 7 , 7 , 0 , 0  } }, // #119 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 49, { 44, 9 , 9 , 9 , 0 , 0  } }, // #120 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 35, { 26, 7 , 7 , 0 , 0 , 0  } }, // #121 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 36, { 52, 9 , 9 , 0 , 0 , 0  } }, // #122 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 14, { 35, 3 , 0 , 0 , 0 , 0  } }, // #123 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 5 , { 35, 9 , 0 , 0 , 0 , 0  } }, // #124 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 8 , { 2 , 3 , 2 , 0 , 0 , 0  } }, // #125 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 2 , 3 , 2 , 0 , 0 , 0  } }, // #126 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 18, { 4 , 3 , 4 , 0 , 0 , 0  } }, // #127 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 35, { 10, 60, 7 , 0 , 0 , 0  } }, // #128 [ref=11x]
+  { InstDB::RWInfo::kCategoryGeneric   , 36, { 10, 78, 9 , 0 , 0 , 0  } }, // #129 [ref=13x]
+  { InstDB::RWInfo::kCategoryGeneric   , 43, { 76, 77, 5 , 0 , 0 , 0  } }, // #130 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 43, { 11, 3 , 5 , 0 , 0 , 0  } }, // #131 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 50, { 74, 43, 77, 0 , 0 , 0  } }, // #132 [ref=4x]
+  { InstDB::RWInfo::kCategoryVmaskmov  , 0 , { 0 , 0 , 0 , 0 , 0 , 0  } }, // #133 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 12, { 35, 0 , 0 , 0 , 0 , 0  } }, // #134 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 22, 0 , 0 , 0 , 0 , 0  } }, // #135 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 10, 60, 60, 0 , 0 , 0  } }, // #136 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 12, { 10, 7 , 7 , 0 , 0 , 0  } }, // #137 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 10, 7 , 7 , 0 , 0 , 0  } }, // #138 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 12, { 10, 60, 7 , 0 , 0 , 0  } }, // #139 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 10, 60, 7 , 0 , 0 , 0  } }, // #140 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 10, 78, 9 , 0 , 0 , 0  } }, // #141 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 79, 0 , 0 , 0 , 0 , 0  } }, // #142 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 54, { 35, 11, 3 , 3 , 0 , 0  } }, // #143 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 13, { 74, 43, 43, 43, 43, 5  } }, // #144 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 6 , { 35, 3 , 3 , 0 , 0 , 0  } }, // #145 [ref=17x]
+  { InstDB::RWInfo::kCategoryGeneric   , 50, { 76, 77, 77, 0 , 0 , 0  } }, // #146 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 22, { 11, 3 , 3 , 0 , 0 , 0  } }, // #147 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 7 , { 48, 5 , 0 , 0 , 0 , 0  } }, // #148 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 55, { 10, 5 , 40, 0 , 0 , 0  } }, // #149 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 56, { 10, 5 , 13, 0 , 0 , 0  } }, // #150 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 43, { 10, 5 , 5 , 5 , 0 , 0  } }, // #151 [ref=12x]
+  { InstDB::RWInfo::kCategoryGeneric   , 61, { 10, 5 , 5 , 5 , 0 , 0  } }, // #152 [ref=1x]
+  { InstDB::RWInfo::kCategoryGeneric   , 62, { 10, 5 , 5 , 0 , 0 , 0  } }, // #153 [ref=12x]
+  { InstDB::RWInfo::kCategoryGeneric   , 22, { 11, 3 , 5 , 0 , 0 , 0  } }, // #154 [ref=9x]
+  { InstDB::RWInfo::kCategoryGeneric   , 63, { 11, 3 , 0 , 0 , 0 , 0  } }, // #155 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 0 , { 59, 17, 29, 0 , 0 , 0  } }, // #156 [ref=2x]
+  { InstDB::RWInfo::kCategoryGeneric   , 8 , { 3 , 59, 17, 0 , 0 , 0  } }, // #157 [ref=4x]
+  { InstDB::RWInfo::kCategoryGeneric   , 8 , { 11, 59, 17, 0 , 0 , 0  } }  // #158 [ref=8x]
+};
+
+const InstDB::RWInfoOp InstDB::rwInfoOp[] = {
+  { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, 0 }, // #0 [ref=15421x]
+  { 0x0000000000000003u, 0x0000000000000003u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId }, // #1 [ref=10x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #2 [ref=217x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #3 [ref=989x]
+  { 0x000000000000FFFFu, 0x000000000000FFFFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #4 [ref=92x]
+  { 0x000000000000FFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #5 [ref=305x]
+  { 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kRW }, // #6 [ref=18x]
+  { 0x00000000000000FFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #7 [ref=185x]
+  { 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kRW }, // #8 [ref=18x]
+  { 0x000000000000000Fu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #9 [ref=133x]
+  { 0x0000000000000000u, 0x000000000000FFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #10 [ref=160x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #11 [ref=420x]
+  { 0x0000000000000003u, 0x0000000000000003u, 0xFF, { 0 }, OpRWInfo::kRW }, // #12 [ref=1x]
+  { 0x0000000000000003u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #13 [ref=34x]
+  { 0x000000000000FFFFu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #14 [ref=4x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kMemBaseWrite | OpRWInfo::kMemIndexWrite }, // #15 [ref=1x]
+  { 0x0000000000000000u, 0x000000000000000Fu, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #16 [ref=9x]
+  { 0x000000000000000Fu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #17 [ref=23x]
+  { 0x00000000000000FFu, 0x00000000000000FFu, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #18 [ref=2x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemPhysId }, // #19 [ref=3x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x06, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemBaseRW | OpRWInfo::kMemBasePostModify | OpRWInfo::kMemPhysId }, // #20 [ref=3x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x07, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemBaseRW | OpRWInfo::kMemBasePostModify | OpRWInfo::kMemPhysId }, // #21 [ref=2x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #22 [ref=7x]
+  { 0x00000000000000FFu, 0x00000000000000FFu, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #23 [ref=1x]
+  { 0x00000000000000FFu, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #24 [ref=1x]
+  { 0x00000000000000FFu, 0x0000000000000000u, 0x03, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #25 [ref=1x]
+  { 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #26 [ref=21x]
+  { 0x000000000000000Fu, 0x000000000000000Fu, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #27 [ref=1x]
+  { 0x000000000000000Fu, 0x000000000000000Fu, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #28 [ref=4x]
+  { 0x000000000000000Fu, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #29 [ref=13x]
+  { 0x000000000000000Fu, 0x0000000000000000u, 0x03, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #30 [ref=2x]
+  { 0x0000000000000000u, 0x000000000000000Fu, 0x03, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #31 [ref=1x]
+  { 0x000000000000000Fu, 0x000000000000000Fu, 0x01, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #32 [ref=1x]
+  { 0x0000000000000000u, 0x00000000000000FFu, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #33 [ref=1x]
+  { 0x00000000000000FFu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #34 [ref=1x]
+  { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #35 [ref=80x]
+  { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kWrite }, // #36 [ref=6x]
+  { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kWrite }, // #37 [ref=6x]
+  { 0x0000000000000000u, 0x0000000000000003u, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId }, // #38 [ref=1x]
+  { 0x0000000000000003u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #39 [ref=1x]
+  { 0x0000000000000001u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #40 [ref=28x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #41 [ref=2x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #42 [ref=3x]
+  { 0xFFFFFFFFFFFFFFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #43 [ref=45x]
+  { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #44 [ref=30x]
+  { 0x00000000000003FFu, 0x00000000000003FFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #45 [ref=22x]
+  { 0x00000000000003FFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #46 [ref=13x]
+  { 0x0000000000000000u, 0x00000000000003FFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #47 [ref=1x]
+  { 0x0000000000000000u, 0x0000000000000003u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #48 [ref=15x]
+  { 0x0000000000000000u, 0x0000000000000003u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #49 [ref=2x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #50 [ref=2x]
+  { 0x0000000000000003u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #51 [ref=4x]
+  { 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #52 [ref=4x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x07, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kMemPhysId }, // #53 [ref=1x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #54 [ref=1x]
+  { 0x0000000000000000u, 0x0000000000000001u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #55 [ref=14x]
+  { 0x0000000000000000u, 0x0000000000000001u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId }, // #56 [ref=1x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #57 [ref=3x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x07, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kMemPhysId }, // #58 [ref=3x]
+  { 0x000000000000000Fu, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #59 [ref=22x]
+  { 0x000000000000FF00u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #60 [ref=23x]
+  { 0x0000000000000000u, 0x000000000000FF00u, 0xFF, { 0 }, OpRWInfo::kWrite }, // #61 [ref=1x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x07, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kMemBaseRW | OpRWInfo::kMemBasePostModify | OpRWInfo::kMemPhysId }, // #62 [ref=2x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #63 [ref=1x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #64 [ref=2x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x06, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemPhysId }, // #65 [ref=1x]
+  { 0x0000000000000000u, 0x000000000000000Fu, 0x01, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #66 [ref=5x]
+  { 0x0000000000000000u, 0x000000000000FFFFu, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #67 [ref=4x]
+  { 0x0000000000000000u, 0x0000000000000007u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #68 [ref=2x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x04, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #69 [ref=1x]
+  { 0x0000000000000001u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #70 [ref=10x]
+  { 0x0000000000000000u, 0x000000000000000Fu, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #71 [ref=7x]
+  { 0x0000000000000001u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #72 [ref=1x]
+  { 0x0000000000000000u, 0x0000000000000001u, 0xFF, { 0 }, OpRWInfo::kWrite }, // #73 [ref=30x]
+  { 0x0000000000000000u, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #74 [ref=20x]
+  { 0xFFFFFFFFFFFFFFFFu, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #75 [ref=7x]
+  { 0x0000000000000000u, 0x00000000FFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #76 [ref=10x]
+  { 0x00000000FFFFFFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #77 [ref=16x]
+  { 0x000000000000FFF0u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #78 [ref=18x]
+  { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }  // #79 [ref=1x]
+};
+
+const InstDB::RWInfoRm InstDB::rwInfoRm[] = {
+  { InstDB::RWInfoRm::kCategoryNone      , 0x00, 0 , 0, 0 }, // #0 [ref=1880x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #1 [ref=8x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, 0 }, // #2 [ref=194x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x02, 16, 0, 0 }, // #3 [ref=122x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x02, 8 , 0, 0 }, // #4 [ref=66x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x02, 4 , 0, 0 }, // #5 [ref=33x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x04, 0 , 0, 0 }, // #6 [ref=270x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x01, 2 , 0, 0 }, // #7 [ref=9x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x00, 0 , 0, 0 }, // #8 [ref=63x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x03, 0 , 0, 0 }, // #9 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #10 [ref=21x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , 0, 0 }, // #11 [ref=14x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x00, 8 , 0, 0 }, // #12 [ref=22x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x00, 16, 0, 0 }, // #13 [ref=21x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #14 [ref=15x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x02, 1 , 0, 0 }, // #15 [ref=5x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x00, 64, 0, 0 }, // #16 [ref=5x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x01, 4 , 0, 0 }, // #17 [ref=8x]
+  { InstDB::RWInfoRm::kCategoryNone      , 0x00, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #18 [ref=22x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x00, 10, 0, 0 }, // #19 [ref=2x]
+  { InstDB::RWInfoRm::kCategoryNone      , 0x01, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #20 [ref=5x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x00, 2 , 0, 0 }, // #21 [ref=3x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x06, 0 , 0, 0 }, // #22 [ref=14x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x03, 1 , 0, 0 }, // #23 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x03, 4 , 0, 0 }, // #24 [ref=4x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x03, 8 , 0, 0 }, // #25 [ref=3x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x03, 2 , 0, 0 }, // #26 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x02, 2 , 0, 0 }, // #27 [ref=6x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x00, 4 , 0, 0 }, // #28 [ref=6x]
+  { InstDB::RWInfoRm::kCategoryNone      , 0x03, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #29 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x03, 16, 0, 0 }, // #30 [ref=6x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x01, 1 , 0, 0 }, // #31 [ref=32x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x01, 8 , 0, 0 }, // #32 [ref=4x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x01, 2 , 0, Features::kSSE4_1 }, // #33 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x01, 2 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #34 [ref=3x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x04, 8 , 0, 0 }, // #35 [ref=34x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x04, 4 , 0, 0 }, // #36 [ref=37x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x00, 32, 0, 0 }, // #37 [ref=4x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x02, 8 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #38 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x02, 4 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #39 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryHalf      , 0x02, 0 , 0, 0 }, // #40 [ref=14x]
+  { InstDB::RWInfoRm::kCategoryHalf      , 0x01, 0 , 0, 0 }, // #41 [ref=10x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x04, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #42 [ref=4x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x04, 16, 0, 0 }, // #43 [ref=27x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x02, 64, 0, 0 }, // #44 [ref=6x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x01, 16, 0, 0 }, // #45 [ref=6x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x01, 32, 0, 0 }, // #46 [ref=4x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x0C, 0 , 0, 0 }, // #47 [ref=15x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x0C, 8 , 0, 0 }, // #48 [ref=4x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x0C, 4 , 0, 0 }, // #49 [ref=4x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x04, 32, 0, 0 }, // #50 [ref=6x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , 0, 0 }, // #51 [ref=13x]
+  { InstDB::RWInfoRm::kCategoryNone      , 0x02, 0 , 0, 0 }, // #52 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x03, 8 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #53 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x08, 0 , 0, 0 }, // #54 [ref=2x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x04, 1 , 0, 0 }, // #55 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x04, 2 , 0, 0 }, // #56 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryQuarter   , 0x01, 0 , 0, 0 }, // #57 [ref=6x]
+  { InstDB::RWInfoRm::kCategoryEighth    , 0x01, 0 , 0, 0 }, // #58 [ref=3x]
+  { InstDB::RWInfoRm::kCategoryQuarter   , 0x02, 0 , 0, 0 }, // #59 [ref=4x]
+  { InstDB::RWInfoRm::kCategoryEighth    , 0x02, 0 , 0, 0 }, // #60 [ref=2x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x0C, 16, 0, 0 }, // #61 [ref=1x]
+  { InstDB::RWInfoRm::kCategoryFixed     , 0x06, 16, 0, 0 }, // #62 [ref=12x]
+  { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, Features::kAVX512_BW }  // #63 [ref=2x]
+};
+// ----------------------------------------------------------------------------
+// ${InstRWInfoTable:End}
+
+// ============================================================================
+// [asmjit::x86::InstDB - Unit]
+// ============================================================================
+
+#if defined(ASMJIT_TEST)
+UNIT(x86_inst_db) {
+  INFO("Checking validity of Inst enums");
+
+  // Cross-validate prefixes.
+  EXPECT(Inst::kOptionRex  == 0x40000000u, "REX prefix must be at 0x40000000");
+  EXPECT(Inst::kOptionVex3 == 0x00000400u, "VEX3 prefix must be at 0x00000400");
+  EXPECT(Inst::kOptionEvex == 0x00001000u, "EVEX prefix must be at 0x00001000");
+
+  // These could be combined together to form a valid REX prefix, they must match.
+  EXPECT(uint32_t(Inst::kOptionOpCodeB) == uint32_t(Opcode::kB), "Opcode::kB must match Inst::kOptionOpCodeB");
+  EXPECT(uint32_t(Inst::kOptionOpCodeX) == uint32_t(Opcode::kX), "Opcode::kX must match Inst::kOptionOpCodeX");
+  EXPECT(uint32_t(Inst::kOptionOpCodeR) == uint32_t(Opcode::kR), "Opcode::kR must match Inst::kOptionOpCodeR");
+  EXPECT(uint32_t(Inst::kOptionOpCodeW) == uint32_t(Opcode::kW), "Opcode::kW must match Inst::kOptionOpCodeW");
+
+  uint32_t rex_rb = (Opcode::kR >> Opcode::kREX_Shift) | (Opcode::kB >> Opcode::kREX_Shift) | 0x40;
+  uint32_t rex_rw = (Opcode::kR >> Opcode::kREX_Shift) | (Opcode::kW >> Opcode::kREX_Shift) | 0x40;
+
+  EXPECT(rex_rb == 0x45, "Opcode::kR|B must form a valid REX prefix (0x45) if combined with 0x40");
+  EXPECT(rex_rw == 0x4C, "Opcode::kR|W must form a valid REX prefix (0x4C) if combined with 0x40");
+}
+#endif
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86
diff --git a/client/asmjit/x86/x86instdb.h b/client/asmjit/x86/x86instdb.h
new file mode 100644
index 0000000..f02c3e8
--- /dev/null
+++ b/client/asmjit/x86/x86instdb.h
@@ -0,0 +1,470 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86INSTDB_H_INCLUDED
+#define ASMJIT_X86_X86INSTDB_H_INCLUDED
+
+#include "../x86/x86globals.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \addtogroup asmjit_x86
+//! \{
+
+//! Instruction database (X86).
+namespace InstDB {
+
+// ============================================================================
+// [asmjit::x86::InstDB::Mode]
+// ============================================================================
+
+//! Describes which mode is supported by an instruction or instruction signature.
+enum Mode : uint32_t {
+  kModeNone               = 0x00u,       //!< Invalid.
+  kModeX86                = 0x01u,       //!< X86 mode supported.
+  kModeX64                = 0x02u,       //!< X64 mode supported.
+  kModeAny                = 0x03u        //!< Both X86 and X64 modes supported.
+};
+
+static constexpr uint32_t modeFromArch(uint32_t arch) noexcept {
+  return arch == Environment::kArchX86 ? kModeX86 :
+         arch == Environment::kArchX64 ? kModeX64 : kModeNone;
+}
+
+// ============================================================================
+// [asmjit::x86::InstDB::OpFlags]
+// ============================================================================
+
+//! Operand flags (X86).
+enum OpFlags : uint32_t {
+  kOpNone                 = 0x00000000u, //!< No flags.
+
+  kOpGpbLo                = 0x00000001u, //!< Operand can be low 8-bit GPB register.
+  kOpGpbHi                = 0x00000002u, //!< Operand can be high 8-bit GPB register.
+  kOpGpw                  = 0x00000004u, //!< Operand can be 16-bit GPW register.
+  kOpGpd                  = 0x00000008u, //!< Operand can be 32-bit GPD register.
+  kOpGpq                  = 0x00000010u, //!< Operand can be 64-bit GPQ register.
+  kOpXmm                  = 0x00000020u, //!< Operand can be 128-bit XMM register.
+  kOpYmm                  = 0x00000040u, //!< Operand can be 256-bit YMM register.
+  kOpZmm                  = 0x00000080u, //!< Operand can be 512-bit ZMM register.
+  kOpMm                   = 0x00000100u, //!< Operand can be 64-bit MM register.
+  kOpKReg                 = 0x00000200u, //!< Operand can be 64-bit K register.
+  kOpSReg                 = 0x00000400u, //!< Operand can be SReg (segment register).
+  kOpCReg                 = 0x00000800u, //!< Operand can be CReg (control register).
+  kOpDReg                 = 0x00001000u, //!< Operand can be DReg (debug register).
+  kOpSt                   = 0x00002000u, //!< Operand can be 80-bit ST register (X87).
+  kOpBnd                  = 0x00004000u, //!< Operand can be 128-bit BND register.
+  kOpTmm                  = 0x00008000u, //!< Operand can be 0..8192-bit TMM register.
+  kOpAllRegs              = 0x0000FFFFu, //!< Combination of all possible registers.
+
+  kOpI4                   = 0x00010000u, //!< Operand can be unsigned 4-bit immediate.
+  kOpU4                   = 0x00020000u, //!< Operand can be unsigned 4-bit immediate.
+  kOpI8                   = 0x00040000u, //!< Operand can be signed 8-bit immediate.
+  kOpU8                   = 0x00080000u, //!< Operand can be unsigned 8-bit immediate.
+  kOpI16                  = 0x00100000u, //!< Operand can be signed 16-bit immediate.
+  kOpU16                  = 0x00200000u, //!< Operand can be unsigned 16-bit immediate.
+  kOpI32                  = 0x00400000u, //!< Operand can be signed 32-bit immediate.
+  kOpU32                  = 0x00800000u, //!< Operand can be unsigned 32-bit immediate.
+  kOpI64                  = 0x01000000u, //!< Operand can be signed 64-bit immediate.
+  kOpU64                  = 0x02000000u, //!< Operand can be unsigned 64-bit immediate.
+  kOpAllImm               = 0x03FF0000u, //!< Operand can be any immediate.
+
+  kOpMem                  = 0x04000000u, //!< Operand can be a scalar memory pointer.
+  kOpVm                   = 0x08000000u, //!< Operand can be a vector memory pointer.
+
+  kOpRel8                 = 0x10000000u, //!< Operand can be relative 8-bit  displacement.
+  kOpRel32                = 0x20000000u, //!< Operand can be relative 32-bit displacement.
+
+  kOpImplicit             = 0x80000000u  //!< Operand is implicit.
+};
+
+// ============================================================================
+// [asmjit::x86::InstDB::MemFlags]
+// ============================================================================
+
+//! Memory operand flags (X86).
+enum MemFlags : uint32_t {
+  // NOTE: Instruction uses either scalar or vector memory operands, they never
+  // collide. This allows us to share bits between "M" and "Vm" enums.
+
+  kMemOpAny               = 0x0001u,     //!< Operand can be any scalar memory pointer.
+  kMemOpM8                = 0x0002u,     //!< Operand can be an 8-bit memory pointer.
+  kMemOpM16               = 0x0004u,     //!< Operand can be a 16-bit memory pointer.
+  kMemOpM32               = 0x0008u,     //!< Operand can be a 32-bit memory pointer.
+  kMemOpM48               = 0x0010u,     //!< Operand can be a 48-bit memory pointer (FAR pointers only).
+  kMemOpM64               = 0x0020u,     //!< Operand can be a 64-bit memory pointer.
+  kMemOpM80               = 0x0040u,     //!< Operand can be an 80-bit memory pointer.
+  kMemOpM128              = 0x0080u,     //!< Operand can be a 128-bit memory pointer.
+  kMemOpM256              = 0x0100u,     //!< Operand can be a 256-bit memory pointer.
+  kMemOpM512              = 0x0200u,     //!< Operand can be a 512-bit memory pointer.
+  kMemOpM1024             = 0x0400u,     //!< Operand can be a 1024-bit memory pointer.
+
+  kMemOpVm32x             = 0x0002u,     //!< Operand can be a vm32x (vector) pointer.
+  kMemOpVm32y             = 0x0004u,     //!< Operand can be a vm32y (vector) pointer.
+  kMemOpVm32z             = 0x0008u,     //!< Operand can be a vm32z (vector) pointer.
+  kMemOpVm64x             = 0x0020u,     //!< Operand can be a vm64x (vector) pointer.
+  kMemOpVm64y             = 0x0040u,     //!< Operand can be a vm64y (vector) pointer.
+  kMemOpVm64z             = 0x0080u,     //!< Operand can be a vm64z (vector) pointer.
+
+  kMemOpBaseOnly          = 0x0800u,     //!< Only memory base is allowed (no index, no offset).
+  kMemOpDs                = 0x1000u,     //!< Implicit memory operand's DS segment.
+  kMemOpEs                = 0x2000u,     //!< Implicit memory operand's ES segment.
+
+  kMemOpMib               = 0x4000u,     //!< Operand must be MIB (base+index) pointer.
+  kMemOpTMem              = 0x8000u      //!< Operand is a sib_mem (ADX memory operand).
+};
+
+// ============================================================================
+// [asmjit::x86::InstDB::Flags]
+// ============================================================================
+
+//! Instruction flags (X86).
+//!
+//! Details about instruction encoding, operation, features, and some limitations.
+enum Flags : uint32_t {
+  kFlagNone               = 0x00000000u, //!< No flags.
+
+  // Instruction Family
+  // ------------------
+  //
+  // Instruction family information.
+
+  kFlagFpu                = 0x00000100u, //!< Instruction that accesses FPU registers.
+  kFlagMmx                = 0x00000200u, //!< Instruction that accesses MMX registers (including 3DNOW and GEODE) and EMMS.
+  kFlagVec                = 0x00000400u, //!< Instruction that accesses XMM registers (SSE, AVX, AVX512).
+
+  // Prefixes and Encoding Flags
+  // ---------------------------
+  //
+  // These describe optional X86 prefixes that can be used to change the instruction's operation.
+
+  kFlagTsib               = 0x00000800u, //!< Instruction uses TSIB (or SIB_MEM) encoding (MODRM followed by SIB).
+  kFlagRep                = 0x00001000u, //!< Instruction can be prefixed with using the REP(REPE) or REPNE prefix.
+  kFlagRepIgnored         = 0x00002000u, //!< Instruction ignores REP|REPNE prefixes, but they are accepted.
+  kFlagLock               = 0x00004000u, //!< Instruction can be prefixed with using the LOCK prefix.
+  kFlagXAcquire           = 0x00008000u, //!< Instruction can be prefixed with using the XACQUIRE prefix.
+  kFlagXRelease           = 0x00010000u, //!< Instruction can be prefixed with using the XRELEASE prefix.
+  kFlagMib                = 0x00020000u, //!< Instruction uses MIB (BNDLDX|BNDSTX) to encode two registers.
+  kFlagVsib               = 0x00040000u, //!< Instruction uses VSIB instead of legacy SIB.
+  kFlagVex                = 0x00080000u, //!< Instruction can be encoded by VEX|XOP (AVX|AVX2|BMI|XOP|...).
+  kFlagEvex               = 0x00100000u, //!< Instruction can be encoded by EVEX (AVX512).
+
+  // FPU Flags
+  // ---------
+  //
+  // Used to tell the encoder which memory operand sizes are encodable.
+
+  kFlagFpuM16             = 0x00200000u, //!< FPU instruction can address `word_ptr` (shared with M80).
+  kFlagFpuM32             = 0x00400000u, //!< FPU instruction can address `dword_ptr`.
+  kFlagFpuM64             = 0x00800000u, //!< FPU instruction can address `qword_ptr`.
+  kFlagFpuM80             = 0x00200000u, //!< FPU instruction can address `tword_ptr` (shared with M16).
+
+  // AVX and AVX515 Flags
+  // --------------------
+  //
+  // If both `kFlagPrefixVex` and `kFlagPrefixEvex` flags are specified it
+  // means that the instructions can be encoded by either VEX or EVEX prefix.
+  // In that case AsmJit checks global options and also instruction options
+  // to decide whether to emit VEX or EVEX prefix.
+
+  kFlagAvx512_            = 0x00000000u, //!< Internally used in tables, has no meaning.
+  kFlagAvx512K            = 0x01000000u, //!< Supports masking {k1..k7}.
+  kFlagAvx512Z            = 0x02000000u, //!< Supports zeroing {z}, must be used together with `kAvx512k`.
+  kFlagAvx512ER           = 0x04000000u, //!< Supports 'embedded-rounding' {er} with implicit {sae},
+  kFlagAvx512SAE          = 0x08000000u, //!< Supports 'suppress-all-exceptions' {sae}.
+  kFlagAvx512B32          = 0x10000000u, //!< Supports 32-bit broadcast 'b32'.
+  kFlagAvx512B64          = 0x20000000u, //!< Supports 64-bit broadcast 'b64'.
+  kFlagAvx512T4X          = 0x80000000u, //!< Operates on a vector of consecutive registers (AVX512_4FMAPS and AVX512_4VNNIW).
+
+  // Combinations used by instruction tables to make AVX512 definitions more compact.
+  kFlagAvx512KZ            = kFlagAvx512K         | kFlagAvx512Z,
+  kFlagAvx512ER_SAE        = kFlagAvx512ER        | kFlagAvx512SAE,
+  kFlagAvx512KZ_SAE        = kFlagAvx512KZ        | kFlagAvx512SAE,
+  kFlagAvx512KZ_SAE_B32    = kFlagAvx512KZ_SAE    | kFlagAvx512B32,
+  kFlagAvx512KZ_SAE_B64    = kFlagAvx512KZ_SAE    | kFlagAvx512B64,
+
+  kFlagAvx512KZ_ER_SAE     = kFlagAvx512KZ        | kFlagAvx512ER_SAE,
+  kFlagAvx512KZ_ER_SAE_B32 = kFlagAvx512KZ_ER_SAE | kFlagAvx512B32,
+  kFlagAvx512KZ_ER_SAE_B64 = kFlagAvx512KZ_ER_SAE | kFlagAvx512B64,
+
+  kFlagAvx512K_B32         = kFlagAvx512K         | kFlagAvx512B32,
+  kFlagAvx512K_B64         = kFlagAvx512K         | kFlagAvx512B64,
+  kFlagAvx512KZ_B32        = kFlagAvx512KZ        | kFlagAvx512B32,
+  kFlagAvx512KZ_B64        = kFlagAvx512KZ        | kFlagAvx512B64
+};
+
+// ============================================================================
+// [asmjit::x86::InstDB::SingleRegCase]
+// ============================================================================
+
+enum SingleRegCase : uint32_t {
+  //! No special handling.
+  kSingleRegNone = 0,
+  //! Operands become read-only  - `REG & REG` and similar.
+  kSingleRegRO = 1,
+  //! Operands become write-only - `REG ^ REG` and similar.
+  kSingleRegWO = 2
+};
+
+// ============================================================================
+// [asmjit::x86::InstDB::InstSignature / OpSignature]
+// ============================================================================
+
+//! Operand signature (X86).
+//!
+//! Contains all possible operand combinations, memory size information, and
+//! a fixed register id (or `BaseReg::kIdBad` if fixed id isn't required).
+struct OpSignature {
+  //! Operand flags.
+  uint32_t opFlags;
+  //! Memory flags.
+  uint16_t memFlags;
+  //! Extra flags.
+  uint8_t extFlags;
+  //! Mask of possible register IDs.
+  uint8_t regMask;
+};
+
+ASMJIT_VARAPI const OpSignature _opSignatureTable[];
+
+//! Instruction signature (X86).
+//!
+//! Contains a sequence of operands' combinations and other metadata that defines
+//! a single instruction. This data is used by instruction validator.
+struct InstSignature {
+  //! Count of operands in `opIndex` (0..6).
+  uint8_t opCount : 3;
+  //! Architecture modes supported (X86 / X64).
+  uint8_t modes : 2;
+  //! Number of implicit operands.
+  uint8_t implicit : 3;
+  //! Reserved for future use.
+  uint8_t reserved;
+  //! Indexes to `OpSignature` table.
+  uint8_t operands[Globals::kMaxOpCount];
+};
+
+ASMJIT_VARAPI const InstSignature _instSignatureTable[];
+
+// ============================================================================
+// [asmjit::x86::InstDB::CommonInfo]
+// ============================================================================
+
+//! Instruction common information (X86)
+//!
+//! Aggregated information shared across one or more instruction.
+struct CommonInfo {
+  //! Instruction flags.
+  uint32_t _flags;
+  //! First `InstSignature` entry in the database.
+  uint32_t _iSignatureIndex : 11;
+  //! Number of relevant `ISignature` entries.
+  uint32_t _iSignatureCount : 5;
+  //! Control type, see `ControlType`.
+  uint32_t _controlType : 3;
+  //! Specifies what happens if all source operands share the same register.
+  uint32_t _singleRegCase : 2;
+  //! Reserved for future use.
+  uint32_t _reserved : 11;
+
+  // --------------------------------------------------------------------------
+  // [Accessors]
+  // --------------------------------------------------------------------------
+
+  //! Returns instruction flags, see `InstInfo::Flags`.
+  inline uint32_t flags() const noexcept { return _flags; }
+  //! Tests whether the instruction has a `flag`, see `InstInfo::Flags`.
+  inline bool hasFlag(uint32_t flag) const noexcept { return (_flags & flag) != 0; }
+
+  //! Tests whether the instruction is FPU instruction.
+  inline bool isFpu() const noexcept { return hasFlag(kFlagFpu); }
+  //! Tests whether the instruction is MMX/3DNOW instruction that accesses MMX registers (includes EMMS and FEMMS).
+  inline bool isMmx() const noexcept { return hasFlag(kFlagMmx); }
+  //! Tests whether the instruction is SSE|AVX|AVX512 instruction that accesses XMM|YMM|ZMM registers.
+  inline bool isVec() const noexcept { return hasFlag(kFlagVec); }
+  //! Tests whether the instruction is SSE+ (SSE4.2, AES, SHA included) instruction that accesses XMM registers.
+  inline bool isSse() const noexcept { return (flags() & (kFlagVec | kFlagVex | kFlagEvex)) == kFlagVec; }
+  //! Tests whether the instruction is AVX+ (FMA included) instruction that accesses XMM|YMM|ZMM registers.
+  inline bool isAvx() const noexcept { return isVec() && isVexOrEvex(); }
+
+  //! Tests whether the instruction can be prefixed with LOCK prefix.
+  inline bool hasLockPrefix() const noexcept { return hasFlag(kFlagLock); }
+  //! Tests whether the instruction can be prefixed with REP (REPE|REPZ) prefix.
+  inline bool hasRepPrefix() const noexcept { return hasFlag(kFlagRep); }
+  //! Tests whether the instruction can be prefixed with XACQUIRE prefix.
+  inline bool hasXAcquirePrefix() const noexcept { return hasFlag(kFlagXAcquire); }
+  //! Tests whether the instruction can be prefixed with XRELEASE prefix.
+  inline bool hasXReleasePrefix() const noexcept { return hasFlag(kFlagXRelease); }
+
+  //! Tests whether the rep prefix is supported by the instruction, but ignored (has no effect).
+  inline bool isRepIgnored() const noexcept { return hasFlag(kFlagRepIgnored); }
+  //! Tests whether the instruction uses MIB.
+  inline bool isMibOp() const noexcept { return hasFlag(kFlagMib); }
+  //! Tests whether the instruction uses VSIB.
+  inline bool isVsibOp() const noexcept { return hasFlag(kFlagVsib); }
+  //! Tests whether the instruction uses TSIB (AMX, instruction requires MOD+SIB).
+  inline bool isTsibOp() const noexcept { return hasFlag(kFlagTsib); }
+  //! Tests whether the instruction uses VEX (can be set together with EVEX if both are encodable).
+  inline bool isVex() const noexcept { return hasFlag(kFlagVex); }
+  //! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
+  inline bool isEvex() const noexcept { return hasFlag(kFlagEvex); }
+  //! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
+  inline bool isVexOrEvex() const noexcept { return hasFlag(kFlagVex | kFlagEvex); }
+
+  //! Tests whether the instruction supports AVX512 masking {k}.
+  inline bool hasAvx512K() const noexcept { return hasFlag(kFlagAvx512K); }
+  //! Tests whether the instruction supports AVX512 zeroing {k}{z}.
+  inline bool hasAvx512Z() const noexcept { return hasFlag(kFlagAvx512Z); }
+  //! Tests whether the instruction supports AVX512 embedded-rounding {er}.
+  inline bool hasAvx512ER() const noexcept { return hasFlag(kFlagAvx512ER); }
+  //! Tests whether the instruction supports AVX512 suppress-all-exceptions {sae}.
+  inline bool hasAvx512SAE() const noexcept { return hasFlag(kFlagAvx512SAE); }
+  //! Tests whether the instruction supports AVX512 broadcast (either 32-bit or 64-bit).
+  inline bool hasAvx512B() const noexcept { return hasFlag(kFlagAvx512B32 | kFlagAvx512B64); }
+  //! Tests whether the instruction supports AVX512 broadcast (32-bit).
+  inline bool hasAvx512B32() const noexcept { return hasFlag(kFlagAvx512B32); }
+  //! Tests whether the instruction supports AVX512 broadcast (64-bit).
+  inline bool hasAvx512B64() const noexcept { return hasFlag(kFlagAvx512B64); }
+
+  inline uint32_t signatureIndex() const noexcept { return _iSignatureIndex; }
+  inline uint32_t signatureCount() const noexcept { return _iSignatureCount; }
+
+  inline const InstSignature* signatureData() const noexcept { return _instSignatureTable + _iSignatureIndex; }
+  inline const InstSignature* signatureEnd() const noexcept { return _instSignatureTable + _iSignatureIndex + _iSignatureCount; }
+
+  //! Returns the control-flow type of the instruction.
+  inline uint32_t controlType() const noexcept { return _controlType; }
+
+  inline uint32_t singleRegCase() const noexcept { return _singleRegCase; }
+};
+
+ASMJIT_VARAPI const CommonInfo _commonInfoTable[];
+
+// ============================================================================
+// [asmjit::x86::InstDB::InstInfo]
+// ============================================================================
+
+//! Instruction information (X86).
+struct InstInfo {
+  //! Index to `_nameData`.
+  uint32_t _nameDataIndex : 14;
+  //! Index to `_commonInfoTable`.
+  uint32_t _commonInfoIndex : 10;
+  //! Index to `InstDB::_commonInfoTableB`.
+  uint32_t _commonInfoIndexB : 8;
+
+  //! Instruction encoding, see `InstDB::EncodingId`.
+  uint8_t _encoding;
+  //! Main opcode value (0.255).
+  uint8_t _mainOpcodeValue;
+  //! Index to `InstDB::_mainOpcodeTable` that is combined with `_mainOpcodeValue`
+  //! to form the final opcode.
+  uint8_t _mainOpcodeIndex;
+  //! Index to `InstDB::_altOpcodeTable` that contains a full alternative opcode.
+  uint8_t _altOpcodeIndex;
+
+  // --------------------------------------------------------------------------
+  // [Accessors]
+  // --------------------------------------------------------------------------
+
+  //! Returns common information, see `CommonInfo`.
+  inline const CommonInfo& commonInfo() const noexcept { return _commonInfoTable[_commonInfoIndex]; }
+
+  //! Tests whether the instruction has flag `flag`, see `Flags`.
+  inline bool hasFlag(uint32_t flag) const noexcept { return commonInfo().hasFlag(flag); }
+  //! Returns instruction flags, see `Flags`.
+  inline uint32_t flags() const noexcept { return commonInfo().flags(); }
+
+  //! Tests whether the instruction is FPU instruction.
+  inline bool isFpu() const noexcept { return commonInfo().isFpu(); }
+  //! Tests whether the instruction is MMX/3DNOW instruction that accesses MMX registers (includes EMMS and FEMMS).
+  inline bool isMmx() const noexcept { return commonInfo().isMmx(); }
+  //! Tests whether the instruction is SSE|AVX|AVX512 instruction that accesses XMM|YMM|ZMM registers.
+  inline bool isVec() const noexcept { return commonInfo().isVec(); }
+  //! Tests whether the instruction is SSE+ (SSE4.2, AES, SHA included) instruction that accesses XMM registers.
+  inline bool isSse() const noexcept { return commonInfo().isSse(); }
+  //! Tests whether the instruction is AVX+ (FMA included) instruction that accesses XMM|YMM|ZMM registers.
+  inline bool isAvx() const noexcept { return commonInfo().isAvx(); }
+
+  //! Tests whether the instruction can be prefixed with LOCK prefix.
+  inline bool hasLockPrefix() const noexcept { return commonInfo().hasLockPrefix(); }
+  //! Tests whether the instruction can be prefixed with REP (REPE|REPZ) prefix.
+  inline bool hasRepPrefix() const noexcept { return commonInfo().hasRepPrefix(); }
+  //! Tests whether the instruction can be prefixed with XACQUIRE prefix.
+  inline bool hasXAcquirePrefix() const noexcept { return commonInfo().hasXAcquirePrefix(); }
+  //! Tests whether the instruction can be prefixed with XRELEASE prefix.
+  inline bool hasXReleasePrefix() const noexcept { return commonInfo().hasXReleasePrefix(); }
+
+  //! Tests whether the rep prefix is supported by the instruction, but ignored (has no effect).
+  inline bool isRepIgnored() const noexcept { return commonInfo().isRepIgnored(); }
+  //! Tests whether the instruction uses MIB.
+  inline bool isMibOp() const noexcept { return hasFlag(kFlagMib); }
+  //! Tests whether the instruction uses VSIB.
+  inline bool isVsibOp() const noexcept { return hasFlag(kFlagVsib); }
+  //! Tests whether the instruction uses VEX (can be set together with EVEX if both are encodable).
+  inline bool isVex() const noexcept { return hasFlag(kFlagVex); }
+  //! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
+  inline bool isEvex() const noexcept { return hasFlag(kFlagEvex); }
+  //! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
+  inline bool isVexOrEvex() const noexcept { return hasFlag(kFlagVex | kFlagEvex); }
+
+  //! Tests whether the instruction supports AVX512 masking {k}.
+  inline bool hasAvx512K() const noexcept { return hasFlag(kFlagAvx512K); }
+  //! Tests whether the instruction supports AVX512 zeroing {k}{z}.
+  inline bool hasAvx512Z() const noexcept { return hasFlag(kFlagAvx512Z); }
+  //! Tests whether the instruction supports AVX512 embedded-rounding {er}.
+  inline bool hasAvx512ER() const noexcept { return hasFlag(kFlagAvx512ER); }
+  //! Tests whether the instruction supports AVX512 suppress-all-exceptions {sae}.
+  inline bool hasAvx512SAE() const noexcept { return hasFlag(kFlagAvx512SAE); }
+  //! Tests whether the instruction supports AVX512 broadcast (either 32-bit or 64-bit).
+  inline bool hasAvx512B() const noexcept { return hasFlag(kFlagAvx512B32 | kFlagAvx512B64); }
+  //! Tests whether the instruction supports AVX512 broadcast (32-bit).
+  inline bool hasAvx512B32() const noexcept { return hasFlag(kFlagAvx512B32); }
+  //! Tests whether the instruction supports AVX512 broadcast (64-bit).
+  inline bool hasAvx512B64() const noexcept { return hasFlag(kFlagAvx512B64); }
+
+  //! Gets the control-flow type of the instruction.
+  inline uint32_t controlType() const noexcept { return commonInfo().controlType(); }
+  inline uint32_t singleRegCase() const noexcept { return commonInfo().singleRegCase(); }
+
+  inline uint32_t signatureIndex() const noexcept { return commonInfo().signatureIndex(); }
+  inline uint32_t signatureCount() const noexcept { return commonInfo().signatureCount(); }
+
+  inline const InstSignature* signatureData() const noexcept { return commonInfo().signatureData(); }
+  inline const InstSignature* signatureEnd() const noexcept { return commonInfo().signatureEnd(); }
+};
+
+ASMJIT_VARAPI const InstInfo _instInfoTable[];
+
+inline const InstInfo& infoById(uint32_t instId) noexcept {
+  ASMJIT_ASSERT(Inst::isDefinedId(instId));
+  return _instInfoTable[instId];
+}
+
+} // {InstDB}
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86INSTDB_H_INCLUDED
diff --git a/client/asmjit/x86/x86instdb_p.h b/client/asmjit/x86/x86instdb_p.h
new file mode 100644
index 0000000..9c48bed
--- /dev/null
+++ b/client/asmjit/x86/x86instdb_p.h
@@ -0,0 +1,329 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86INSTDB_P_H_INCLUDED
+#define ASMJIT_X86_X86INSTDB_P_H_INCLUDED
+
+#include "../x86/x86instdb.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_x86
+//! \{
+
+namespace InstDB {
+
+// ============================================================================
+// [asmjit::x86::InstDB::Encoding]
+// ============================================================================
+
+//! Instruction encoding (X86).
+//!
+//! This is a specific identifier that is used by AsmJit to describe the way
+//! each instruction is encoded. Some encodings are special only for a single
+//! instruction as X86 instruction set contains a lot of legacy encodings, and
+//! some encodings describe a group of instructions that share some commons,
+//! like MMX, SSE, AVX, AVX512 instructions, etc...
+enum EncodingId : uint32_t {
+  kEncodingNone = 0,                     //!< Never used.
+  kEncodingX86Op,                        //!< X86 [OP].
+  kEncodingX86Op_Mod11RM,                //!< X86 [OP] (opcode with ModRM byte where MOD must be 11b).
+  kEncodingX86Op_Mod11RM_I8,             //!< X86 [OP] (opcode with ModRM byte + 8-bit immediate).
+  kEncodingX86Op_xAddr,                  //!< X86 [OP] (implicit address in the first register operand).
+  kEncodingX86Op_xAX,                    //!< X86 [OP] (implicit or explicit '?AX' form).
+  kEncodingX86Op_xDX_xAX,                //!< X86 [OP] (implicit or explicit '?DX, ?AX' form).
+  kEncodingX86Op_MemZAX,                 //!< X86 [OP] (implicit or explicit '[EAX|RAX]' form).
+  kEncodingX86I_xAX,                     //!< X86 [I] (implicit or explicit '?AX' form).
+  kEncodingX86M,                         //!< X86 [M] (handles 2|4|8-bytes size).
+  kEncodingX86M_NoSize,                  //!< X86 [M] (doesn't handle any size).
+  kEncodingX86M_GPB,                     //!< X86 [M] (handles single-byte size).
+  kEncodingX86M_GPB_MulDiv,              //!< X86 [M] (like GPB, handles implicit|explicit MUL|DIV|IDIV).
+  kEncodingX86M_Only,                    //!< X86 [M] (restricted to memory operand of any size).
+  kEncodingX86M_Nop,                     //!< X86 [M] (special case of NOP instruction).
+  kEncodingX86R_Native,                  //!< X86 [R] (register must be either 32-bit or 64-bit depending on arch).
+  kEncodingX86R_FromM,                   //!< X86 [R] - which specifies memory address.
+  kEncodingX86R32_EDX_EAX,               //!< X86 [R32] followed by implicit EDX and EAX.
+  kEncodingX86Rm,                        //!< X86 [RM] (doesn't handle single-byte size).
+  kEncodingX86Rm_Raw66H,                 //!< X86 [RM] (used by LZCNT, POPCNT, and TZCNT).
+  kEncodingX86Rm_NoSize,                 //!< X86 [RM] (doesn't add REX.W prefix if 64-bit reg is used).
+  kEncodingX86Mr,                        //!< X86 [MR] (doesn't handle single-byte size).
+  kEncodingX86Mr_NoSize,                 //!< X86 [MR] (doesn't handle any size).
+  kEncodingX86Arith,                     //!< X86 adc, add, and, cmp, or, sbb, sub, xor.
+  kEncodingX86Bswap,                     //!< X86 bswap.
+  kEncodingX86Bt,                        //!< X86 bt, btc, btr, bts.
+  kEncodingX86Call,                      //!< X86 call.
+  kEncodingX86Cmpxchg,                   //!< X86 [MR] cmpxchg.
+  kEncodingX86Cmpxchg8b_16b,             //!< X86 [MR] cmpxchg8b, cmpxchg16b.
+  kEncodingX86Crc,                       //!< X86 crc32.
+  kEncodingX86Enter,                     //!< X86 enter.
+  kEncodingX86Imul,                      //!< X86 imul.
+  kEncodingX86In,                        //!< X86 in.
+  kEncodingX86Ins,                       //!< X86 ins[b|q|d].
+  kEncodingX86IncDec,                    //!< X86 inc, dec.
+  kEncodingX86Int,                       //!< X86 int (interrupt).
+  kEncodingX86Jcc,                       //!< X86 jcc.
+  kEncodingX86JecxzLoop,                 //!< X86 jcxz, jecxz, jrcxz, loop, loope, loopne.
+  kEncodingX86Jmp,                       //!< X86 jmp.
+  kEncodingX86JmpRel,                    //!< X86 xbegin.
+  kEncodingX86Lea,                       //!< X86 lea.
+  kEncodingX86Mov,                       //!< X86 mov (all possible cases).
+  kEncodingX86MovsxMovzx,                //!< X86 movsx, movzx.
+  kEncodingX86MovntiMovdiri,             //!< X86 movnti/movdiri.
+  kEncodingX86EnqcmdMovdir64b,           //!< X86 enqcmd/enqcmds/movdir64b.
+  kEncodingX86Out,                       //!< X86 out.
+  kEncodingX86Outs,                      //!< X86 out[b|w|d].
+  kEncodingX86Push,                      //!< X86 push.
+  kEncodingX86Pop,                       //!< X86 pop.
+  kEncodingX86Ret,                       //!< X86 ret.
+  kEncodingX86Rot,                       //!< X86 rcl, rcr, rol, ror, sal, sar, shl, shr.
+  kEncodingX86Set,                       //!< X86 setcc.
+  kEncodingX86ShldShrd,                  //!< X86 shld, shrd.
+  kEncodingX86StrRm,                     //!< X86 lods.
+  kEncodingX86StrMr,                     //!< X86 scas, stos.
+  kEncodingX86StrMm,                     //!< X86 cmps, movs.
+  kEncodingX86Test,                      //!< X86 test.
+  kEncodingX86Xadd,                      //!< X86 xadd.
+  kEncodingX86Xchg,                      //!< X86 xchg.
+  kEncodingX86Fence,                     //!< X86 lfence, mfence, sfence.
+  kEncodingX86Bndmov,                    //!< X86 [RM|MR] (used by BNDMOV).
+  kEncodingFpuOp,                        //!< FPU [OP].
+  kEncodingFpuArith,                     //!< FPU fadd, fdiv, fdivr, fmul, fsub, fsubr.
+  kEncodingFpuCom,                       //!< FPU fcom, fcomp.
+  kEncodingFpuFldFst,                    //!< FPU fld, fst, fstp.
+  kEncodingFpuM,                         //!< FPU fiadd, ficom, ficomp, fidiv, fidivr, fild, fimul, fist, fistp, fisttp, fisub, fisubr.
+  kEncodingFpuR,                         //!< FPU fcmov, fcomi, fcomip, ffree, fucom, fucomi, fucomip, fucomp, fxch.
+  kEncodingFpuRDef,                      //!< FPU faddp, fdivp, fdivrp, fmulp, fsubp, fsubrp.
+  kEncodingFpuStsw,                      //!< FPU fnstsw, Fstsw.
+  kEncodingExtRm,                        //!< EXT [RM].
+  kEncodingExtRm_XMM0,                   //!< EXT [RM<XMM0>].
+  kEncodingExtRm_ZDI,                    //!< EXT [RM<ZDI>].
+  kEncodingExtRm_P,                      //!< EXT [RM] (propagates 66H if the instruction uses XMM register).
+  kEncodingExtRm_Wx,                     //!< EXT [RM] (propagates REX.W if GPQ is used).
+  kEncodingExtRmRi,                      //!< EXT [RM|RI].
+  kEncodingExtRmRi_P,                    //!< EXT [RM|RI] (propagates 66H if the instruction uses XMM register).
+  kEncodingExtRmi,                       //!< EXT [RMI].
+  kEncodingExtRmi_P,                     //!< EXT [RMI] (propagates 66H if the instruction uses XMM register).
+  kEncodingExtPextrw,                    //!< EXT pextrw.
+  kEncodingExtExtract,                   //!< EXT pextrb, pextrd, pextrq, extractps.
+  kEncodingExtMov,                       //!< EXT mov?? - #1:[MM|XMM, MM|XMM|Mem] #2:[MM|XMM|Mem, MM|XMM].
+  kEncodingExtMovbe,                     //!< EXT movbe.
+  kEncodingExtMovd,                      //!< EXT movd.
+  kEncodingExtMovq,                      //!< EXT movq.
+  kEncodingExtExtrq,                     //!< EXT extrq (SSE4A).
+  kEncodingExtInsertq,                   //!< EXT insrq (SSE4A).
+  kEncodingExt3dNow,                     //!< EXT [RMI] (3DNOW specific).
+  kEncodingVexOp,                        //!< VEX [OP].
+  kEncodingVexOpMod,                     //!< VEX [OP] with MODR/M.
+  kEncodingVexKmov,                      //!< VEX [RM|MR] (used by kmov[b|w|d|q]).
+  kEncodingVexR_Wx,                      //!< VEX|EVEX [R] (propagatex VEX.W if GPQ used).
+  kEncodingVexM,                         //!< VEX|EVEX [M].
+  kEncodingVexM_VM,                      //!< VEX|EVEX [M] (propagates VEX|EVEX.L, VSIB support).
+  kEncodingVexMr_Lx,                     //!< VEX|EVEX [MR] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexMr_VM,                     //!< VEX|EVEX [MR] (propagates VEX|EVEX.L, VSIB support).
+  kEncodingVexMri,                       //!< VEX|EVEX [MRI].
+  kEncodingVexMri_Lx,                    //!< VEX|EVEX [MRI] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexRm,                        //!< VEX|EVEX [RM].
+  kEncodingVexRm_ZDI,                    //!< VEX|EVEX [RM<ZDI>].
+  kEncodingVexRm_Wx,                     //!< VEX|EVEX [RM] (propagates VEX|EVEX.W if GPQ used).
+  kEncodingVexRm_Lx,                     //!< VEX|EVEX [RM] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexRm_Lx_Bcst,                //!< VEX|EVEX [RM] (can handle broadcast r32/r64).
+  kEncodingVexRm_VM,                     //!< VEX|EVEX [RM] (propagates VEX|EVEX.L, VSIB support).
+  kEncodingVexRm_T1_4X,                  //!<     EVEX [RM] (used by NN instructions that use RM-T1_4X encoding).
+  kEncodingVexRmi,                       //!< VEX|EVEX [RMI].
+  kEncodingVexRmi_Wx,                    //!< VEX|EVEX [RMI] (propagates VEX|EVEX.W if GPQ used).
+  kEncodingVexRmi_Lx,                    //!< VEX|EVEX [RMI] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexRvm,                       //!< VEX|EVEX [RVM].
+  kEncodingVexRvm_Wx,                    //!< VEX|EVEX [RVM] (propagates VEX|EVEX.W if GPQ used).
+  kEncodingVexRvm_ZDX_Wx,                //!< VEX|EVEX [RVM<ZDX>] (propagates VEX|EVEX.W if GPQ used).
+  kEncodingVexRvm_Lx,                    //!< VEX|EVEX [RVM] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexRvm_Lx_2xK,                //!< VEX|EVEX [RVM] (vp2intersectd/vp2intersectq).
+  kEncodingVexRvmr,                      //!< VEX|EVEX [RVMR].
+  kEncodingVexRvmr_Lx,                   //!< VEX|EVEX [RVMR] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexRvmi,                      //!< VEX|EVEX [RVMI].
+  kEncodingVexRvmi_Lx,                   //!< VEX|EVEX [RVMI] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexRmv,                       //!< VEX|EVEX [RMV].
+  kEncodingVexRmv_Wx,                    //!< VEX|EVEX [RMV] (propagates VEX|EVEX.W if GPQ used).
+  kEncodingVexRmv_VM,                    //!< VEX|EVEX [RMV] (propagates VEX|EVEX.L, VSIB support).
+  kEncodingVexRmvRm_VM,                  //!< VEX|EVEX [RMV|RM] (propagates VEX|EVEX.L, VSIB support).
+  kEncodingVexRmvi,                      //!< VEX|EVEX [RMVI].
+  kEncodingVexRmMr,                      //!< VEX|EVEX [RM|MR].
+  kEncodingVexRmMr_Lx,                   //!< VEX|EVEX [RM|MR] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexRvmRmv,                    //!< VEX|EVEX [RVM|RMV].
+  kEncodingVexRvmRmi,                    //!< VEX|EVEX [RVM|RMI].
+  kEncodingVexRvmRmi_Lx,                 //!< VEX|EVEX [RVM|RMI] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexRvmRmvRmi,                 //!< VEX|EVEX [RVM|RMV|RMI].
+  kEncodingVexRvmMr,                     //!< VEX|EVEX [RVM|MR].
+  kEncodingVexRvmMvr,                    //!< VEX|EVEX [RVM|MVR].
+  kEncodingVexRvmMvr_Lx,                 //!< VEX|EVEX [RVM|MVR] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexRvmVmi,                    //!< VEX|EVEX [RVM|VMI].
+  kEncodingVexRvmVmi_Lx,                 //!< VEX|EVEX [RVM|VMI] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexVm,                        //!< VEX|EVEX [VM].
+  kEncodingVexVm_Wx,                     //!< VEX|EVEX [VM] (propagates VEX|EVEX.W if GPQ used).
+  kEncodingVexVmi,                       //!< VEX|EVEX [VMI].
+  kEncodingVexVmi_Lx,                    //!< VEX|EVEX [VMI] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexVmi4_Wx,                   //!< VEX|EVEX [VMI] (propagates VEX|EVEX.W if GPQ used, DWORD Immediate).
+  kEncodingVexEvexVmi_Lx,                //!< VEX|EVEX [VMI] (special, used by vpsrldq and vpslldq)
+  kEncodingVexRvrmRvmr,                  //!< VEX|EVEX [RVRM|RVMR].
+  kEncodingVexRvrmRvmr_Lx,               //!< VEX|EVEX [RVRM|RVMR] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexRvrmiRvmri_Lx,             //!< VEX|EVEX [RVRMI|RVMRI] (propagates VEX|EVEX.L if YMM used).
+  kEncodingVexMovdMovq,                  //!< VEX|EVEX vmovd, vmovq.
+  kEncodingVexMovssMovsd,                //!< VEX|EVEX vmovss, vmovsd.
+  kEncodingFma4,                         //!< FMA4 [R, R, R/M, R/M].
+  kEncodingFma4_Lx,                      //!< FMA4 [R, R, R/M, R/M] (propagates AVX.L if YMM used).
+  kEncodingAmxCfg,                       //!< AMX ldtilecfg/sttilecfg.
+  kEncodingAmxR,                         //!< AMX [R] - tilezero.
+  kEncodingAmxRm,                        //!< AMX tileloadd/tileloaddt1.
+  kEncodingAmxMr,                        //!< AMX tilestored.
+  kEncodingAmxRmv,                       //!< AMX instructions that use TMM registers.
+  kEncodingCount                         //!< Count of instruction encodings.
+};
+
+// ============================================================================
+// [asmjit::x86::InstDB - CommonInfoTableB]
+// ============================================================================
+
+//! CPU extensions required to execute instruction.
+struct CommonInfoTableB {
+  //! Features vector.
+  uint8_t _features[6];
+  //! Index to `_rwFlagsTable`.
+  uint8_t _rwFlagsIndex;
+  //! Reserved for future use.
+  uint8_t _reserved;
+
+  inline const uint8_t* featuresBegin() const noexcept { return _features; }
+  inline const uint8_t* featuresEnd() const noexcept { return _features + ASMJIT_ARRAY_SIZE(_features); }
+};
+
+// ============================================================================
+// [asmjit::x86::InstDB - InstNameIndex]
+// ============================================================================
+
+// ${NameLimits:Begin}
+// ------------------- Automatically generated, do not edit -------------------
+enum : uint32_t { kMaxNameSize = 17 };
+// ----------------------------------------------------------------------------
+// ${NameLimits:End}
+
+struct InstNameIndex {
+  uint16_t start;
+  uint16_t end;
+};
+
+// ============================================================================
+// [asmjit::x86::InstDB - RWInfo]
+// ============================================================================
+
+struct RWInfo {
+  enum Category : uint8_t {
+    kCategoryGeneric,
+    kCategoryMov,
+    kCategoryImul,
+    kCategoryMovh64,
+    kCategoryVmaskmov,
+    kCategoryVmovddup,
+    kCategoryVmovmskpd,
+    kCategoryVmovmskps,
+    kCategoryVmov1_2,
+    kCategoryVmov1_4,
+    kCategoryVmov1_8,
+    kCategoryVmov2_1,
+    kCategoryVmov4_1,
+    kCategoryVmov8_1
+  };
+
+  uint8_t category;
+  uint8_t rmInfo;
+  uint8_t opInfoIndex[6];
+};
+
+struct RWInfoOp {
+  uint64_t rByteMask;
+  uint64_t wByteMask;
+  uint8_t physId;
+  uint8_t reserved[3];
+  uint32_t flags;
+};
+
+//! R/M information.
+//!
+//! This data is used to replace register operand by a memory operand reliably.
+struct RWInfoRm {
+  enum Category : uint8_t {
+    kCategoryNone = 0,
+    kCategoryFixed,
+    kCategoryConsistent,
+    kCategoryHalf,
+    kCategoryQuarter,
+    kCategoryEighth
+  };
+
+  enum Flags : uint8_t {
+    kFlagAmbiguous = 0x01
+  };
+
+  uint8_t category;
+  uint8_t rmOpsMask;
+  uint8_t fixedSize;
+  uint8_t flags;
+  uint8_t rmFeature;
+};
+
+struct RWFlagsInfoTable {
+  //! CPU/FPU flags read.
+  uint32_t readFlags;
+  //! CPU/FPU flags written or undefined.
+  uint32_t writeFlags;
+};
+
+extern const uint8_t rwInfoIndexA[Inst::_kIdCount];
+extern const uint8_t rwInfoIndexB[Inst::_kIdCount];
+extern const RWInfo rwInfoA[];
+extern const RWInfo rwInfoB[];
+extern const RWInfoOp rwInfoOp[];
+extern const RWInfoRm rwInfoRm[];
+extern const RWFlagsInfoTable _rwFlagsInfoTable[];
+
+// ============================================================================
+// [asmjit::x86::InstDB::Tables]
+// ============================================================================
+
+extern const uint32_t _mainOpcodeTable[];
+extern const uint32_t _altOpcodeTable[];
+
+#ifndef ASMJIT_NO_TEXT
+extern const char _nameData[];
+extern const InstNameIndex instNameIndex[26];
+#endif // !ASMJIT_NO_TEXT
+
+extern const CommonInfoTableB _commonInfoTableB[];
+
+} // {InstDB}
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86INSTDB_P_H_INCLUDED
diff --git a/client/asmjit/x86/x86internal.cpp b/client/asmjit/x86/x86internal.cpp
new file mode 100644
index 0000000..062525f
--- /dev/null
+++ b/client/asmjit/x86/x86internal.cpp
@@ -0,0 +1,1733 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#include "../core/api-build_p.h"
+#ifdef ASMJIT_BUILD_X86
+
+#include "../core/formatter.h"
+#include "../core/string.h"
+#include "../core/support.h"
+#include "../core/type.h"
+#include "../x86/x86internal_p.h"
+
+// Can be used for debugging...
+// #define ASMJIT_DUMP_ARGS_ASSIGNMENT
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::X86Internal - Helpers]
+// ============================================================================
+
+static ASMJIT_INLINE uint32_t x86GetXmmMovInst(const FuncFrame& frame) {
+  bool avx = frame.isAvxEnabled();
+  bool aligned = frame.hasAlignedVecSR();
+
+  return aligned ? (avx ? Inst::kIdVmovaps : Inst::kIdMovaps)
+                 : (avx ? Inst::kIdVmovups : Inst::kIdMovups);
+}
+
+static ASMJIT_INLINE uint32_t x86VecTypeIdToRegType(uint32_t typeId) noexcept {
+  return typeId <= Type::_kIdVec128End ? Reg::kTypeXmm :
+         typeId <= Type::_kIdVec256End ? Reg::kTypeYmm : Reg::kTypeZmm;
+}
+
+//! Converts `size` to a 'kmov?' instructio.
+static inline uint32_t x86KmovFromSize(uint32_t size) noexcept {
+  switch (size) {
+    case  1: return Inst::kIdKmovb;
+    case  2: return Inst::kIdKmovw;
+    case  4: return Inst::kIdKmovd;
+    case  8: return Inst::kIdKmovq;
+    default: return Inst::kIdNone;
+  }
+}
+
+// ============================================================================
+// [asmjit::X86Internal - FuncDetail]
+// ============================================================================
+
+ASMJIT_FAVOR_SIZE Error X86Internal::initFuncDetail(FuncDetail& func, const FuncSignature& signature, uint32_t registerSize) noexcept {
+  const CallConv& cc = func.callConv();
+  uint32_t arch = cc.arch();
+  uint32_t stackOffset = cc._spillZoneSize;
+
+  uint32_t i;
+  uint32_t argCount = func.argCount();
+
+  if (func.retCount() != 0) {
+    uint32_t typeId = func._rets[0].typeId();
+    switch (typeId) {
+      case Type::kIdI64:
+      case Type::kIdU64: {
+        if (Environment::is32Bit(arch)) {
+          // Convert a 64-bit return value to two 32-bit return values.
+          func._retCount = 2;
+          typeId -= 2;
+
+          // 64-bit value is returned in EDX:EAX on X86.
+          func._rets[0].initReg(Reg::kTypeGpd, Gp::kIdAx, typeId);
+          func._rets[1].initReg(Reg::kTypeGpd, Gp::kIdDx, typeId);
+          break;
+        }
+        else {
+          func._rets[0].initReg(Reg::kTypeGpq, Gp::kIdAx, typeId);
+        }
+        break;
+      }
+
+      case Type::kIdI8:
+      case Type::kIdI16:
+      case Type::kIdI32: {
+        func._rets[0].initReg(Reg::kTypeGpd, Gp::kIdAx, Type::kIdI32);
+        break;
+      }
+
+      case Type::kIdU8:
+      case Type::kIdU16:
+      case Type::kIdU32: {
+        func._rets[0].initReg(Reg::kTypeGpd, Gp::kIdAx, Type::kIdU32);
+        break;
+      }
+
+      case Type::kIdF32:
+      case Type::kIdF64: {
+        uint32_t regType = Environment::is32Bit(arch) ? Reg::kTypeSt : Reg::kTypeXmm;
+        func._rets[0].initReg(regType, 0, typeId);
+        break;
+      }
+
+      case Type::kIdF80: {
+        // 80-bit floats are always returned by FP0.
+        func._rets[0].initReg(Reg::kTypeSt, 0, typeId);
+        break;
+      }
+
+      case Type::kIdMmx32:
+      case Type::kIdMmx64: {
+        // MM registers are returned through XMM (SystemV) or GPQ (Win64).
+        uint32_t regType = Reg::kTypeMm;
+        if (Environment::is64Bit(arch))
+          regType = cc.strategy() == CallConv::kStrategyDefault ? Reg::kTypeXmm : Reg::kTypeGpq;
+
+        func._rets[0].initReg(regType, 0, typeId);
+        break;
+      }
+
+      default: {
+        func._rets[0].initReg(x86VecTypeIdToRegType(typeId), 0, typeId);
+        break;
+      }
+    }
+  }
+
+  switch (cc.strategy()) {
+    case CallConv::kStrategyDefault: {
+      uint32_t gpzPos = 0;
+      uint32_t vecPos = 0;
+
+      for (i = 0; i < argCount; i++) {
+        FuncValue& arg = func._args[i];
+        uint32_t typeId = arg.typeId();
+
+        if (Type::isInt(typeId)) {
+          uint32_t regId = BaseReg::kIdBad;
+
+          if (gpzPos < CallConv::kMaxRegArgsPerGroup)
+            regId = cc._passedOrder[Reg::kGroupGp].id[gpzPos];
+
+          if (regId != BaseReg::kIdBad) {
+            uint32_t regType = (typeId <= Type::kIdU32) ? Reg::kTypeGpd : Reg::kTypeGpq;
+            arg.assignRegData(regType, regId);
+            func.addUsedRegs(Reg::kGroupGp, Support::bitMask(regId));
+            gpzPos++;
+          }
+          else {
+            uint32_t size = Support::max<uint32_t>(Type::sizeOf(typeId), registerSize);
+            arg.assignStackOffset(int32_t(stackOffset));
+            stackOffset += size;
+          }
+          continue;
+        }
+
+        if (Type::isFloat(typeId) || Type::isVec(typeId)) {
+          uint32_t regId = BaseReg::kIdBad;
+
+          if (vecPos < CallConv::kMaxRegArgsPerGroup)
+            regId = cc._passedOrder[Reg::kGroupVec].id[vecPos];
+
+          if (Type::isFloat(typeId)) {
+            // If this is a float, but `kFlagPassFloatsByVec` is false, we have
+            // to use stack instead. This should be only used by 32-bit calling
+            // conventions.
+            if (!cc.hasFlag(CallConv::kFlagPassFloatsByVec))
+              regId = BaseReg::kIdBad;
+          }
+          else {
+            // Pass vector registers via stack if this is a variable arguments
+            // function. This should be only used by 32-bit calling conventions.
+            if (signature.hasVarArgs() && cc.hasFlag(CallConv::kFlagPassVecByStackIfVA))
+              regId = BaseReg::kIdBad;
+          }
+
+          if (regId != BaseReg::kIdBad) {
+            arg.initTypeId(typeId);
+            arg.assignRegData(x86VecTypeIdToRegType(typeId), regId);
+            func.addUsedRegs(Reg::kGroupVec, Support::bitMask(regId));
+            vecPos++;
+          }
+          else {
+            uint32_t size = Type::sizeOf(typeId);
+            arg.assignStackOffset(int32_t(stackOffset));
+            stackOffset += size;
+          }
+          continue;
+        }
+      }
+      break;
+    }
+
+    case CallConv::kStrategyX64Windows:
+    case CallConv::kStrategyX64VectorCall: {
+      // Both X64 and VectorCall behave similarly - arguments are indexed
+      // from left to right. The position of the argument determines in
+      // which register the argument is allocated, so it's either GP or
+      // one of XMM/YMM/ZMM registers.
+      //
+      //       [       X64       ] [VecCall]
+      // Index: #0   #1   #2   #3   #4   #5
+      //
+      // GP   : RCX  RDX  R8   R9
+      // VEC  : XMM0 XMM1 XMM2 XMM3 XMM4 XMM5
+      //
+      // For example function `f(int a, double b, int c, double d)` will be:
+      //
+      //        (a)  (b)  (c)  (d)
+      //        RCX  XMM1 R8   XMM3
+      //
+      // Unused vector registers are used by HVA.
+
+      bool isVectorCall = (cc.strategy() == CallConv::kStrategyX64VectorCall);
+
+      for (i = 0; i < argCount; i++) {
+        FuncValue& arg = func._args[i];
+
+        uint32_t typeId = arg.typeId();
+        uint32_t size = Type::sizeOf(typeId);
+
+        if (Type::isInt(typeId) || Type::isMmx(typeId)) {
+          uint32_t regId = BaseReg::kIdBad;
+
+          if (i < CallConv::kMaxRegArgsPerGroup)
+            regId = cc._passedOrder[Reg::kGroupGp].id[i];
+
+          if (regId != BaseReg::kIdBad) {
+            uint32_t regType = (size <= 4 && !Type::isMmx(typeId)) ? Reg::kTypeGpd : Reg::kTypeGpq;
+            arg.assignRegData(regType, regId);
+            func.addUsedRegs(Reg::kGroupGp, Support::bitMask(regId));
+          }
+          else {
+            arg.assignStackOffset(int32_t(stackOffset));
+            stackOffset += 8;
+          }
+          continue;
+        }
+
+        if (Type::isFloat(typeId) || Type::isVec(typeId)) {
+          uint32_t regId = BaseReg::kIdBad;
+
+          if (i < CallConv::kMaxRegArgsPerGroup)
+            regId = cc._passedOrder[Reg::kGroupVec].id[i];
+
+          if (regId != BaseReg::kIdBad) {
+            // X64-ABI doesn't allow vector types (XMM|YMM|ZMM) to be passed
+            // via registers, however, VectorCall was designed for that purpose.
+            if (Type::isFloat(typeId) || isVectorCall) {
+              uint32_t regType = x86VecTypeIdToRegType(typeId);
+              arg.assignRegData(regType, regId);
+              func.addUsedRegs(Reg::kGroupVec, Support::bitMask(regId));
+              continue;
+            }
+          }
+
+          // Passed via stack if the argument is float/double or indirectly.
+          // The trap is - if the argument is passed indirectly, the address
+          // can be passed via register, if the argument's index has GP one.
+          if (Type::isFloat(typeId)) {
+            arg.assignStackOffset(int32_t(stackOffset));
+          }
+          else {
+            uint32_t gpRegId = cc._passedOrder[Reg::kGroupGp].id[i];
+            if (gpRegId != BaseReg::kIdBad)
+              arg.assignRegData(Reg::kTypeGpq, gpRegId);
+            else
+              arg.assignStackOffset(int32_t(stackOffset));
+            arg.addFlags(FuncValue::kFlagIsIndirect);
+          }
+
+          // Always 8 bytes (float/double/pointer).
+          stackOffset += 8;
+          continue;
+        }
+      }
+      break;
+    }
+  }
+
+  func._argStackSize = stackOffset;
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::X86FuncArgsContext]
+// ============================================================================
+
+static RegInfo x86GetRegForMemToMemMove(uint32_t arch, uint32_t dstTypeId, uint32_t srcTypeId) noexcept {
+  uint32_t dstSize = Type::sizeOf(dstTypeId);
+  uint32_t srcSize = Type::sizeOf(srcTypeId);
+  uint32_t maxSize = Support::max<uint32_t>(dstSize, srcSize);
+  uint32_t regSize = Environment::registerSizeFromArch(arch);
+
+  uint32_t signature = 0;
+  if (maxSize <= regSize || (Type::isInt(dstTypeId) && Type::isInt(srcTypeId)))
+    signature = maxSize <= 4 ? Gpd::kSignature : Gpq::kSignature;
+  else if (maxSize <= 16)
+    signature = Xmm::kSignature;
+  else if (maxSize <= 32)
+    signature = Ymm::kSignature;
+  else if (maxSize <= 64)
+    signature = Zmm::kSignature;
+
+  return RegInfo { signature };
+}
+
+// Used by both `argsToFuncFrame()` and `emitArgsAssignment()`.
+class X86FuncArgsContext {
+public:
+  enum VarId : uint32_t {
+    kVarIdNone = 0xFF
+  };
+
+  //! Contains information about a single argument or SA register that may need shuffling.
+  struct Var {
+    inline void init(const FuncValue& cur_, const FuncValue& out_) noexcept {
+      cur = cur_;
+      out = out_;
+    }
+
+    //! Reset the value to its unassigned state.
+    inline void reset() noexcept {
+      cur.reset();
+      out.reset();
+    }
+
+    inline bool isDone() const noexcept { return cur.isDone(); }
+    inline void markDone() noexcept { cur.addFlags(FuncValue::kFlagIsDone); }
+
+    FuncValue cur;
+    FuncValue out;
+  };
+
+  struct WorkData {
+    inline void reset() noexcept {
+      _archRegs = 0;
+      _workRegs = 0;
+      _usedRegs = 0;
+      _assignedRegs = 0;
+      _dstRegs = 0;
+      _dstShuf = 0;
+      _numSwaps = 0;
+      _numStackArgs = 0;
+      memset(_reserved, 0, sizeof(_reserved));
+      memset(_physToVarId, kVarIdNone, 32);
+    }
+
+    inline bool isAssigned(uint32_t regId) const noexcept {
+      ASMJIT_ASSERT(regId < 32);
+      return Support::bitTest(_assignedRegs, regId);
+    }
+
+    inline void assign(uint32_t varId, uint32_t regId) noexcept {
+      ASMJIT_ASSERT(!isAssigned(regId));
+      ASMJIT_ASSERT(_physToVarId[regId] == kVarIdNone);
+
+      _physToVarId[regId] = uint8_t(varId);
+      _assignedRegs ^= Support::bitMask(regId);
+    }
+
+    inline void reassign(uint32_t varId, uint32_t newId, uint32_t oldId) noexcept {
+      ASMJIT_ASSERT( isAssigned(oldId));
+      ASMJIT_ASSERT(!isAssigned(newId));
+      ASMJIT_ASSERT(_physToVarId[oldId] == varId);
+      ASMJIT_ASSERT(_physToVarId[newId] == kVarIdNone);
+
+      _physToVarId[oldId] = uint8_t(kVarIdNone);
+      _physToVarId[newId] = uint8_t(varId);
+      _assignedRegs ^= Support::bitMask(newId) ^ Support::bitMask(oldId);
+    }
+
+    inline void swap(uint32_t aVarId, uint32_t aRegId, uint32_t bVarId, uint32_t bRegId) noexcept {
+      ASMJIT_ASSERT(isAssigned(aRegId));
+      ASMJIT_ASSERT(isAssigned(bRegId));
+      ASMJIT_ASSERT(_physToVarId[aRegId] == aVarId);
+      ASMJIT_ASSERT(_physToVarId[bRegId] == bVarId);
+
+      _physToVarId[aRegId] = uint8_t(bVarId);
+      _physToVarId[bRegId] = uint8_t(aVarId);
+    }
+
+    inline void unassign(uint32_t varId, uint32_t regId) noexcept {
+      ASMJIT_ASSERT(isAssigned(regId));
+      ASMJIT_ASSERT(_physToVarId[regId] == varId);
+
+      DebugUtils::unused(varId);
+      _physToVarId[regId] = uint8_t(kVarIdNone);
+      _assignedRegs ^= Support::bitMask(regId);
+    }
+
+    inline uint32_t archRegs() const noexcept { return _archRegs; }
+    inline uint32_t workRegs() const noexcept { return _workRegs; }
+    inline uint32_t usedRegs() const noexcept { return _usedRegs; }
+    inline uint32_t assignedRegs() const noexcept { return _assignedRegs; }
+    inline uint32_t dstRegs() const noexcept { return _dstRegs; }
+    inline uint32_t availableRegs() const noexcept { return _workRegs & ~_assignedRegs; }
+
+    uint32_t _archRegs;                  //!< All allocable registers provided by the architecture.
+    uint32_t _workRegs;                  //!< All registers that can be used by the shuffler.
+    uint32_t _usedRegs;                  //!< Registers used by the shuffler (all).
+    uint32_t _assignedRegs;              //!< Assigned registers.
+    uint32_t _dstRegs;                   //!< Destination registers assigned to arguments or SA.
+    uint32_t _dstShuf;                   //!< Destination registers that require shuffling.
+    uint8_t _numSwaps;                   //!< Number of register swaps.
+    uint8_t _numStackArgs;               //!< Number of stack loads.
+    uint8_t _reserved[6];                //!< Reserved (only used as padding).
+    uint8_t _physToVarId[32];            //!< Physical ID to variable ID mapping.
+  };
+
+  uint8_t _arch;
+  bool _hasStackSrc;                     //!< Has arguments passed via stack (SRC).
+  bool _hasPreservedFP;                  //!< Has preserved frame-pointer (FP).
+  uint8_t _stackDstMask;                 //!< Has arguments assigned to stack (DST).
+  uint8_t _regSwapsMask;                 //!< Register swap groups (bit-mask).
+  uint8_t _saVarId;
+  uint32_t _varCount;
+  WorkData _workData[BaseReg::kGroupVirt];
+  Var _vars[kFuncArgCountLoHi + 1];
+
+  X86FuncArgsContext() noexcept;
+
+  inline uint32_t arch() const noexcept { return _arch; }
+  inline uint32_t varCount() const noexcept { return _varCount; }
+
+  inline Var& var(size_t varId) noexcept { return _vars[varId]; }
+  inline const Var& var(size_t varId) const noexcept { return _vars[varId]; }
+  inline size_t indexOf(const Var* var) const noexcept { return (size_t)(var - _vars); }
+
+  Error initWorkData(const FuncFrame& frame, const FuncArgsAssignment& args) noexcept;
+  Error markScratchRegs(FuncFrame& frame) noexcept;
+  Error markDstRegsDirty(FuncFrame& frame) noexcept;
+  Error markStackArgsReg(FuncFrame& frame) noexcept;
+};
+
+X86FuncArgsContext::X86FuncArgsContext() noexcept {
+  _arch = Environment::kArchUnknown;
+  _varCount = 0;
+  _hasStackSrc = false;
+  _hasPreservedFP = false;
+  _stackDstMask = 0;
+  _regSwapsMask = 0;
+  _saVarId = kVarIdNone;
+
+  for (uint32_t group = 0; group < BaseReg::kGroupVirt; group++)
+    _workData[group].reset();
+}
+
+ASMJIT_FAVOR_SIZE Error X86FuncArgsContext::initWorkData(const FuncFrame& frame, const FuncArgsAssignment& args) noexcept {
+  // The code has to be updated if this changes.
+  ASMJIT_ASSERT(BaseReg::kGroupVirt == 4);
+
+  uint32_t i;
+  const FuncDetail& func = *args.funcDetail();
+
+  // Initialize Architecture.
+  uint32_t arch = func.callConv().arch();
+  uint32_t archRegCount = Environment::is32Bit(arch) ? 8 : 16;
+
+  _arch = uint8_t(arch);
+
+  // Initialize `_archRegs`.
+  _workData[Reg::kGroupGp  ]._archRegs = Support::lsbMask<uint32_t>(archRegCount) & ~Support::bitMask(Gp::kIdSp);
+  _workData[Reg::kGroupVec ]._archRegs = Support::lsbMask<uint32_t>(archRegCount);
+  _workData[Reg::kGroupMm  ]._archRegs = Support::lsbMask<uint32_t>(8);
+  _workData[Reg::kGroupKReg]._archRegs = Support::lsbMask<uint32_t>(8);
+
+  if (frame.hasPreservedFP())
+    _workData[Reg::kGroupGp]._archRegs &= ~Support::bitMask(Gp::kIdBp);
+
+  // Extract information from all function arguments/assignments and build Var[] array.
+  uint32_t varId = 0;
+  for (i = 0; i < kFuncArgCountLoHi; i++) {
+    const FuncValue& dst_ = args.arg(i);
+    if (!dst_.isAssigned())
+      continue;
+
+    const FuncValue& src_ = func.arg(i);
+    if (ASMJIT_UNLIKELY(!src_.isAssigned()))
+      return DebugUtils::errored(kErrorInvalidState);
+
+    Var& var = _vars[varId];
+    var.init(src_, dst_);
+
+    FuncValue& src = var.cur;
+    FuncValue& dst = var.out;
+
+    uint32_t dstGroup = 0xFFFFFFFFu;
+    uint32_t dstId = BaseReg::kIdBad;
+    WorkData* dstWd = nullptr;
+
+    // Not supported.
+    if (src.isIndirect())
+      return DebugUtils::errored(kErrorInvalidAssignment);
+
+    if (dst.isReg()) {
+      uint32_t dstType = dst.regType();
+      if (ASMJIT_UNLIKELY(dstType >= Reg::kTypeCount))
+        return DebugUtils::errored(kErrorInvalidRegType);
+
+      // Copy TypeId from source if the destination doesn't have it. The RA
+      // used by BaseCompiler would never leave TypeId undefined, but users
+      // of FuncAPI can just assign phys regs without specifying the type.
+      if (!dst.hasTypeId())
+        dst.setTypeId(Reg::typeIdOf(dst.regType()));
+
+      dstGroup = Reg::groupOf(dstType);
+      if (ASMJIT_UNLIKELY(dstGroup >= BaseReg::kGroupVirt))
+        return DebugUtils::errored(kErrorInvalidRegGroup);
+
+      dstWd = &_workData[dstGroup];
+      dstId = dst.regId();
+      if (ASMJIT_UNLIKELY(dstId >= 32 || !Support::bitTest(dstWd->archRegs(), dstId)))
+        return DebugUtils::errored(kErrorInvalidPhysId);
+
+      if (ASMJIT_UNLIKELY(Support::bitTest(dstWd->dstRegs(), dstId)))
+        return DebugUtils::errored(kErrorOverlappedRegs);
+
+      dstWd->_dstRegs  |= Support::bitMask(dstId);
+      dstWd->_dstShuf  |= Support::bitMask(dstId);
+      dstWd->_usedRegs |= Support::bitMask(dstId);
+    }
+    else {
+      if (!dst.hasTypeId())
+        dst.setTypeId(src.typeId());
+
+      RegInfo regInfo = x86GetRegForMemToMemMove(arch, dst.typeId(), src.typeId());
+      if (ASMJIT_UNLIKELY(!regInfo.isValid()))
+        return DebugUtils::errored(kErrorInvalidState);
+      _stackDstMask = uint8_t(_stackDstMask | Support::bitMask(regInfo.group()));
+    }
+
+    if (src.isReg()) {
+      uint32_t srcId = src.regId();
+      uint32_t srcGroup = Reg::groupOf(src.regType());
+
+      if (dstGroup == srcGroup) {
+        dstWd->assign(varId, srcId);
+
+        // The best case, register is allocated where it is expected to be.
+        if (dstId == srcId)
+          var.markDone();
+      }
+      else {
+        if (ASMJIT_UNLIKELY(srcGroup >= BaseReg::kGroupVirt))
+          return DebugUtils::errored(kErrorInvalidState);
+
+        WorkData& srcData = _workData[srcGroup];
+        srcData.assign(varId, srcId);
+      }
+    }
+    else {
+      if (dstWd)
+        dstWd->_numStackArgs++;
+      _hasStackSrc = true;
+    }
+
+    varId++;
+  }
+
+  // Initialize WorkData::workRegs.
+  for (i = 0; i < BaseReg::kGroupVirt; i++)
+    _workData[i]._workRegs = (_workData[i].archRegs() & (frame.dirtyRegs(i) | ~frame.preservedRegs(i))) | _workData[i].dstRegs() | _workData[i].assignedRegs();
+
+  // Create a variable that represents `SARegId` if necessary.
+  bool saRegRequired = _hasStackSrc && frame.hasDynamicAlignment() && !frame.hasPreservedFP();
+
+  WorkData& gpRegs = _workData[BaseReg::kGroupGp];
+  uint32_t saCurRegId = frame.saRegId();
+  uint32_t saOutRegId = args.saRegId();
+
+  if (saCurRegId != BaseReg::kIdBad) {
+    // Check if the provided `SARegId` doesn't collide with input registers.
+    if (ASMJIT_UNLIKELY(gpRegs.isAssigned(saCurRegId)))
+      return DebugUtils::errored(kErrorOverlappedRegs);
+  }
+
+  if (saOutRegId != BaseReg::kIdBad) {
+    // Check if the provided `SARegId` doesn't collide with argument assignments.
+    if (ASMJIT_UNLIKELY(Support::bitTest(gpRegs.dstRegs(), saOutRegId)))
+      return DebugUtils::errored(kErrorOverlappedRegs);
+    saRegRequired = true;
+  }
+
+  if (saRegRequired) {
+    uint32_t ptrTypeId = Environment::is32Bit(arch) ? Type::kIdU32 : Type::kIdU64;
+    uint32_t ptrRegType = Environment::is32Bit(arch) ? BaseReg::kTypeGp32 : BaseReg::kTypeGp64;
+
+    _saVarId = uint8_t(varId);
+    _hasPreservedFP = frame.hasPreservedFP();
+
+    Var& var = _vars[varId];
+    var.reset();
+
+    if (saCurRegId == BaseReg::kIdBad) {
+      if (saOutRegId != BaseReg::kIdBad && !gpRegs.isAssigned(saOutRegId)) {
+        saCurRegId = saOutRegId;
+      }
+      else {
+        uint32_t availableRegs = gpRegs.availableRegs();
+        if (!availableRegs)
+          availableRegs = gpRegs.archRegs() & ~gpRegs.workRegs();
+
+        if (ASMJIT_UNLIKELY(!availableRegs))
+          return DebugUtils::errored(kErrorNoMorePhysRegs);
+
+        saCurRegId = Support::ctz(availableRegs);
+      }
+    }
+
+    var.cur.initReg(ptrRegType, saCurRegId, ptrTypeId);
+    gpRegs.assign(varId, saCurRegId);
+    gpRegs._workRegs |= Support::bitMask(saCurRegId);
+
+    if (saOutRegId != BaseReg::kIdBad) {
+      var.out.initReg(ptrRegType, saOutRegId, ptrTypeId);
+      gpRegs._dstRegs  |= Support::bitMask(saOutRegId);
+      gpRegs._workRegs |= Support::bitMask(saOutRegId);
+    }
+    else {
+      var.markDone();
+    }
+
+    varId++;
+  }
+
+  _varCount = varId;
+
+  // Detect register swaps.
+  for (varId = 0; varId < _varCount; varId++) {
+    Var& var = _vars[varId];
+    if (var.cur.isReg() && var.out.isReg()) {
+      uint32_t srcId = var.cur.regId();
+      uint32_t dstId = var.out.regId();
+
+      uint32_t group = Reg::groupOf(var.cur.regType());
+      if (group != Reg::groupOf(var.out.regType()))
+        continue;
+
+      WorkData& wd = _workData[group];
+      if (wd.isAssigned(dstId)) {
+        Var& other = _vars[wd._physToVarId[dstId]];
+        if (Reg::groupOf(other.out.regType()) == group && other.out.regId() == srcId) {
+          wd._numSwaps++;
+          _regSwapsMask = uint8_t(_regSwapsMask | Support::bitMask(group));
+        }
+      }
+    }
+  }
+
+  return kErrorOk;
+}
+
+ASMJIT_FAVOR_SIZE Error X86FuncArgsContext::markDstRegsDirty(FuncFrame& frame) noexcept {
+  for (uint32_t i = 0; i < BaseReg::kGroupVirt; i++) {
+    WorkData& wd = _workData[i];
+    uint32_t regs = wd.usedRegs() | wd._dstShuf;
+
+    wd._workRegs |= regs;
+    frame.addDirtyRegs(i, regs);
+  }
+
+  return kErrorOk;
+}
+
+ASMJIT_FAVOR_SIZE Error X86FuncArgsContext::markScratchRegs(FuncFrame& frame) noexcept {
+  uint32_t groupMask = 0;
+
+  // Handle stack to stack moves.
+  groupMask |= _stackDstMask;
+
+  // Handle register swaps.
+  groupMask |= _regSwapsMask & ~Support::bitMask(BaseReg::kGroupGp);
+
+  if (!groupMask)
+    return kErrorOk;
+
+  // Selects one dirty register per affected group that can be used as a scratch register.
+  for (uint32_t group = 0; group < BaseReg::kGroupVirt; group++) {
+    if (Support::bitTest(groupMask, group)) {
+      WorkData& wd = _workData[group];
+
+      // Initially, pick some clobbered or dirty register.
+      uint32_t workRegs = wd.workRegs();
+      uint32_t regs = workRegs & ~(wd.usedRegs() | wd._dstShuf);
+
+      // If that didn't work out pick some register which is not in 'used'.
+      if (!regs)
+        regs = workRegs & ~wd.usedRegs();
+
+      // If that didn't work out pick any other register that is allocable.
+      // This last resort case will, however, result in marking one more
+      // register dirty.
+      if (!regs)
+        regs = wd.archRegs() & ~workRegs;
+
+      // If that didn't work out we will have to use XORs instead of MOVs.
+      if (!regs)
+        continue;
+
+      uint32_t regMask = Support::blsi(regs);
+      wd._workRegs |= regMask;
+      frame.addDirtyRegs(group, regMask);
+    }
+  }
+
+  return kErrorOk;
+}
+
+ASMJIT_FAVOR_SIZE Error X86FuncArgsContext::markStackArgsReg(FuncFrame& frame) noexcept {
+  if (_saVarId != kVarIdNone) {
+    const Var& var = _vars[_saVarId];
+    frame.setSARegId(var.cur.regId());
+  }
+  else if (frame.hasPreservedFP()) {
+    // Always EBP|RBP if the frame-pointer isn't omitted.
+    frame.setSARegId(Gp::kIdBp);
+  }
+
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::X86Internal - FrameLayout]
+// ============================================================================
+
+ASMJIT_FAVOR_SIZE Error X86Internal::initFuncFrame(FuncFrame& frame, const FuncDetail& func) noexcept {
+  uint32_t arch = func.callConv().arch();
+
+  // Initializing FuncFrame means making a copy of some properties of `func`.
+  // Properties like `_localStackSize` will be set by the user before the frame
+  // is finalized.
+  frame.reset();
+
+  frame._arch = uint8_t(arch);
+  frame._spRegId = Gp::kIdSp;
+  frame._saRegId = Gp::kIdBad;
+
+  uint32_t naturalStackAlignment = func.callConv().naturalStackAlignment();
+  uint32_t minDynamicAlignment = Support::max<uint32_t>(naturalStackAlignment, 16);
+
+  if (minDynamicAlignment == naturalStackAlignment)
+    minDynamicAlignment <<= 1;
+
+  frame._naturalStackAlignment = uint8_t(naturalStackAlignment);
+  frame._minDynamicAlignment = uint8_t(minDynamicAlignment);
+  frame._redZoneSize = uint8_t(func.redZoneSize());
+  frame._spillZoneSize = uint8_t(func.spillZoneSize());
+  frame._finalStackAlignment = uint8_t(frame._naturalStackAlignment);
+
+  if (func.hasFlag(CallConv::kFlagCalleePopsStack)) {
+    frame._calleeStackCleanup = uint16_t(func.argStackSize());
+  }
+
+  // Initial masks of dirty and preserved registers.
+  for (uint32_t group = 0; group < BaseReg::kGroupVirt; group++) {
+    frame._dirtyRegs[group] = func.usedRegs(group);
+    frame._preservedRegs[group] = func.preservedRegs(group);
+  }
+
+  // Exclude ESP/RSP - this register is never included in saved GP regs.
+  frame._preservedRegs[BaseReg::kGroupGp] &= ~Support::bitMask(Gp::kIdSp);
+
+  return kErrorOk;
+}
+
+ASMJIT_FAVOR_SIZE Error X86Internal::finalizeFuncFrame(FuncFrame& frame) noexcept {
+  uint32_t registerSize = Environment::registerSizeFromArch(frame.arch());
+
+  // The final stack alignment must be updated accordingly to call and local stack alignments.
+  uint32_t stackAlignment = frame._finalStackAlignment;
+  ASMJIT_ASSERT(stackAlignment == Support::max(frame._naturalStackAlignment,
+                                               frame._callStackAlignment,
+                                               frame._localStackAlignment));
+
+  // TODO: Must be configurable.
+  uint32_t vecSize = 16;
+
+  bool hasFP = frame.hasPreservedFP();
+  bool hasDA = frame.hasDynamicAlignment();
+
+  // Include EBP|RBP if the function preserves the frame-pointer.
+  if (hasFP)
+    frame._dirtyRegs[Reg::kGroupGp] |= Support::bitMask(Gp::kIdBp);
+
+  // These two are identical if the function doesn't align its stack dynamically.
+  uint32_t saRegId = frame.saRegId();
+  if (saRegId == BaseReg::kIdBad)
+    saRegId = Gp::kIdSp;
+
+  // Fix stack arguments base-register from ESP|RSP to EBP|RBP in case it was
+  // not picked before and the function performs dynamic stack alignment.
+  if (hasDA && saRegId == Gp::kIdSp)
+    saRegId = Gp::kIdBp;
+
+  // Mark as dirty any register but ESP|RSP if used as SA pointer.
+  if (saRegId != Gp::kIdSp)
+    frame._dirtyRegs[Reg::kGroupGp] |= Support::bitMask(saRegId);
+
+  frame._spRegId = uint8_t(Gp::kIdSp);
+  frame._saRegId = uint8_t(saRegId);
+
+  // Setup stack size used to save preserved registers.
+  frame._gpSaveSize    = uint16_t(Support::popcnt(frame.savedRegs(Reg::kGroupGp  )) * registerSize);
+  frame._nonGpSaveSize = uint16_t(Support::popcnt(frame.savedRegs(Reg::kGroupVec )) * vecSize +
+                                  Support::popcnt(frame.savedRegs(Reg::kGroupMm  )) * 8 +
+                                  Support::popcnt(frame.savedRegs(Reg::kGroupKReg)) * 8);
+
+  uint32_t v = 0;                             // The beginning of the stack frame relative to SP after prolog.
+  v += frame.callStackSize();                 // Count 'callStackSize'    <- This is used to call functions.
+  v  = Support::alignUp(v, stackAlignment);   // Align to function's stack alignment.
+
+  frame._localStackOffset = v;                // Store 'localStackOffset' <- Function's local stack starts here.
+  v += frame.localStackSize();                // Count 'localStackSize'   <- Function's local stack ends here.
+
+  // If the function's stack must be aligned, calculate the alignment necessary
+  // to store vector registers, and set `FuncFrame::kAttrAlignedVecSR` to inform
+  // PEI that it can use instructions that perform aligned stores/loads.
+  if (stackAlignment >= vecSize && frame._nonGpSaveSize) {
+    frame.addAttributes(FuncFrame::kAttrAlignedVecSR);
+    v = Support::alignUp(v, vecSize);         // Align '_nonGpSaveOffset'.
+  }
+
+  frame._nonGpSaveOffset = v;                 // Store '_nonGpSaveOffset' <- Non-GP Save/Restore starts here.
+  v += frame._nonGpSaveSize;                  // Count '_nonGpSaveSize'   <- Non-GP Save/Restore ends here.
+
+  // Calculate if dynamic alignment (DA) slot (stored as offset relative to SP) is required and its offset.
+  if (hasDA && !hasFP) {
+    frame._daOffset = v;                      // Store 'daOffset'         <- DA pointer would be stored here.
+    v += registerSize;                        // Count 'daOffset'.
+  }
+  else {
+    frame._daOffset = FuncFrame::kTagInvalidOffset;
+  }
+
+  // The return address should be stored after GP save/restore regs. It has
+  // the same size as `registerSize` (basically the native register/pointer
+  // size). We don't adjust it now as `v` now contains the exact size that the
+  // function requires to adjust (call frame + stack frame, vec stack size).
+  // The stack (if we consider this size) is misaligned now, as it's always
+  // aligned before the function call - when `call()` is executed it pushes
+  // the current EIP|RIP onto the stack, and misaligns it by 12 or 8 bytes
+  // (depending on the architecture). So count number of bytes needed to align
+  // it up to the function's CallFrame (the beginning).
+  if (v || frame.hasFuncCalls())
+    v += Support::alignUpDiff(v + frame.gpSaveSize() + registerSize, stackAlignment);
+
+  frame._gpSaveOffset = v;                    // Store 'gpSaveOffset'     <- Function's GP Save/Restore starts here.
+  frame._stackAdjustment = v;                 // Store 'stackAdjustment'  <- SA used by 'add zsp, SA' and 'sub zsp, SA'.
+
+  v += frame._gpSaveSize;                     // Count 'gpSaveSize'       <- Function's GP Save/Restore ends here.
+  v += registerSize;                          // Count 'ReturnAddress'    <- As CALL pushes onto stack.
+
+  // If the function performs dynamic stack alignment then the stack-adjustment must be aligned.
+  if (hasDA)
+    frame._stackAdjustment = Support::alignUp(frame._stackAdjustment, stackAlignment);
+
+  uint32_t saInvOff = FuncFrame::kTagInvalidOffset;
+  uint32_t saTmpOff = registerSize + frame._gpSaveSize;
+
+  // Calculate where the function arguments start relative to SP.
+  frame._saOffsetFromSP = hasDA ? saInvOff : v;
+
+  // Calculate where the function arguments start relative to FP or user-provided register.
+  frame._saOffsetFromSA = hasFP ? registerSize * 2  // Return address + frame pointer.
+                                : saTmpOff;         // Return address + all saved GP regs.
+
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::X86Internal - ArgsToFrameInfo]
+// ============================================================================
+
+ASMJIT_FAVOR_SIZE Error X86Internal::argsToFuncFrame(const FuncArgsAssignment& args, FuncFrame& frame) noexcept {
+  X86FuncArgsContext ctx;
+  ASMJIT_PROPAGATE(ctx.initWorkData(frame, args));
+  ASMJIT_PROPAGATE(ctx.markDstRegsDirty(frame));
+  ASMJIT_PROPAGATE(ctx.markScratchRegs(frame));
+  ASMJIT_PROPAGATE(ctx.markStackArgsReg(frame));
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::X86Internal - Emit Helpers]
+// ============================================================================
+
+ASMJIT_FAVOR_SIZE Error X86Internal::emitRegMove(Emitter* emitter,
+  const Operand_& dst_,
+  const Operand_& src_, uint32_t typeId, bool avxEnabled, const char* comment) {
+
+  // Invalid or abstract TypeIds are not allowed.
+  ASMJIT_ASSERT(Type::isValid(typeId) && !Type::isAbstract(typeId));
+
+  Operand dst(dst_);
+  Operand src(src_);
+
+  uint32_t instId = Inst::kIdNone;
+  uint32_t memFlags = 0;
+  uint32_t overrideMemSize = 0;
+
+  enum MemFlags : uint32_t {
+    kDstMem = 0x1,
+    kSrcMem = 0x2
+  };
+
+  // Detect memory operands and patch them to have the same size as the register.
+  // BaseCompiler always sets memory size of allocs and spills, so it shouldn't
+  // be really necessary, however, after this function was separated from Compiler
+  // it's better to make sure that the size is always specified, as we can use
+  // 'movzx' and 'movsx' that rely on it.
+  if (dst.isMem()) { memFlags |= kDstMem; dst.as<Mem>().setSize(src.size()); }
+  if (src.isMem()) { memFlags |= kSrcMem; src.as<Mem>().setSize(dst.size()); }
+
+  switch (typeId) {
+    case Type::kIdI8:
+    case Type::kIdU8:
+    case Type::kIdI16:
+    case Type::kIdU16:
+      // Special case - 'movzx' load.
+      if (memFlags & kSrcMem) {
+        instId = Inst::kIdMovzx;
+        dst.setSignature(Reg::signatureOfT<Reg::kTypeGpd>());
+      }
+      else if (!memFlags) {
+        // Change both destination and source registers to GPD (safer, no dependencies).
+        dst.setSignature(Reg::signatureOfT<Reg::kTypeGpd>());
+        src.setSignature(Reg::signatureOfT<Reg::kTypeGpd>());
+      }
+      ASMJIT_FALLTHROUGH;
+
+    case Type::kIdI32:
+    case Type::kIdU32:
+    case Type::kIdI64:
+    case Type::kIdU64:
+      instId = Inst::kIdMov;
+      break;
+
+    case Type::kIdMmx32:
+      instId = Inst::kIdMovd;
+      if (memFlags) break;
+      ASMJIT_FALLTHROUGH;
+
+    case Type::kIdMmx64 : instId = Inst::kIdMovq ; break;
+    case Type::kIdMask8 : instId = Inst::kIdKmovb; break;
+    case Type::kIdMask16: instId = Inst::kIdKmovw; break;
+    case Type::kIdMask32: instId = Inst::kIdKmovd; break;
+    case Type::kIdMask64: instId = Inst::kIdKmovq; break;
+
+    default: {
+      uint32_t elementTypeId = Type::baseOf(typeId);
+      if (Type::isVec32(typeId) && memFlags) {
+        overrideMemSize = 4;
+        if (elementTypeId == Type::kIdF32)
+          instId = avxEnabled ? Inst::kIdVmovss : Inst::kIdMovss;
+        else
+          instId = avxEnabled ? Inst::kIdVmovd : Inst::kIdMovd;
+        break;
+      }
+
+      if (Type::isVec64(typeId) && memFlags) {
+        overrideMemSize = 8;
+        if (elementTypeId == Type::kIdF64)
+          instId = avxEnabled ? Inst::kIdVmovsd : Inst::kIdMovsd;
+        else
+          instId = avxEnabled ? Inst::kIdVmovq : Inst::kIdMovq;
+        break;
+      }
+
+      if (elementTypeId == Type::kIdF32)
+        instId = avxEnabled ? Inst::kIdVmovaps : Inst::kIdMovaps;
+      else if (elementTypeId == Type::kIdF64)
+        instId = avxEnabled ? Inst::kIdVmovapd : Inst::kIdMovapd;
+      else if (typeId <= Type::_kIdVec256End)
+        instId = avxEnabled ? Inst::kIdVmovdqa : Inst::kIdMovdqa;
+      else if (elementTypeId <= Type::kIdU32)
+        instId = Inst::kIdVmovdqa32;
+      else
+        instId = Inst::kIdVmovdqa64;
+      break;
+    }
+  }
+
+  if (!instId)
+    return DebugUtils::errored(kErrorInvalidState);
+
+  if (overrideMemSize) {
+    if (dst.isMem()) dst.as<Mem>().setSize(overrideMemSize);
+    if (src.isMem()) src.as<Mem>().setSize(overrideMemSize);
+  }
+
+  emitter->setInlineComment(comment);
+  return emitter->emit(instId, dst, src);
+}
+
+ASMJIT_FAVOR_SIZE Error X86Internal::emitArgMove(Emitter* emitter,
+  const Reg& dst_, uint32_t dstTypeId,
+  const Operand_& src_, uint32_t srcTypeId, bool avxEnabled, const char* comment) {
+
+  // Deduce optional `dstTypeId`, which may be `Type::kIdVoid` in some cases.
+  if (!dstTypeId)
+    dstTypeId = opData.archRegs.regTypeToTypeId[dst_.type()];
+
+  // Invalid or abstract TypeIds are not allowed.
+  ASMJIT_ASSERT(Type::isValid(dstTypeId) && !Type::isAbstract(dstTypeId));
+  ASMJIT_ASSERT(Type::isValid(srcTypeId) && !Type::isAbstract(srcTypeId));
+
+  Reg dst(dst_);
+  Operand src(src_);
+
+  uint32_t dstSize = Type::sizeOf(dstTypeId);
+  uint32_t srcSize = Type::sizeOf(srcTypeId);
+
+  uint32_t instId = Inst::kIdNone;
+
+  // Not a real loop, just 'break' is nicer than 'goto'.
+  for (;;) {
+    if (Type::isInt(dstTypeId)) {
+      if (Type::isInt(srcTypeId)) {
+        instId = Inst::kIdMovsx;
+        uint32_t typeOp = (dstTypeId << 8) | srcTypeId;
+
+        // Sign extend by using 'movsx'.
+        if (typeOp == ((Type::kIdI16 << 8) | Type::kIdI8 ) ||
+            typeOp == ((Type::kIdI32 << 8) | Type::kIdI8 ) ||
+            typeOp == ((Type::kIdI32 << 8) | Type::kIdI16) ||
+            typeOp == ((Type::kIdI64 << 8) | Type::kIdI8 ) ||
+            typeOp == ((Type::kIdI64 << 8) | Type::kIdI16))
+          break;
+
+        // Sign extend by using 'movsxd'.
+        instId = Inst::kIdMovsxd;
+        if (typeOp == ((Type::kIdI64 << 8) | Type::kIdI32))
+          break;
+      }
+
+      if (Type::isInt(srcTypeId) || src_.isMem()) {
+        // Zero extend by using 'movzx' or 'mov'.
+        if (dstSize <= 4 && srcSize < 4) {
+          instId = Inst::kIdMovzx;
+          dst.setSignature(Reg::signatureOfT<Reg::kTypeGpd>());
+        }
+        else {
+          // We should have caught all possibilities where `srcSize` is less
+          // than 4, so we don't have to worry about 'movzx' anymore. Minimum
+          // size is enough to determine if we want 32-bit or 64-bit move.
+          instId = Inst::kIdMov;
+          srcSize = Support::min(srcSize, dstSize);
+
+          dst.setSignature(srcSize == 4 ? Reg::signatureOfT<Reg::kTypeGpd>()
+                                        : Reg::signatureOfT<Reg::kTypeGpq>());
+          if (src.isReg())
+            src.setSignature(dst.signature());
+        }
+        break;
+      }
+
+      // NOTE: The previous branch caught all memory sources, from here it's
+      // always register to register conversion, so catch the remaining cases.
+      srcSize = Support::min(srcSize, dstSize);
+
+      if (Type::isMmx(srcTypeId)) {
+        // 64-bit move.
+        instId = Inst::kIdMovq;
+        if (srcSize == 8)
+          break;
+
+        // 32-bit move.
+        instId = Inst::kIdMovd;
+        dst.setSignature(Reg::signatureOfT<Reg::kTypeGpd>());
+        break;
+      }
+
+      if (Type::isMask(srcTypeId)) {
+        instId = x86KmovFromSize(srcSize);
+        dst.setSignature(srcSize <= 4 ? Reg::signatureOfT<Reg::kTypeGpd>()
+                                      : Reg::signatureOfT<Reg::kTypeGpq>());
+        break;
+      }
+
+      if (Type::isVec(srcTypeId)) {
+        // 64-bit move.
+        instId = avxEnabled ? Inst::kIdVmovq : Inst::kIdMovq;
+        if (srcSize == 8)
+          break;
+
+        // 32-bit move.
+        instId = avxEnabled ? Inst::kIdVmovd : Inst::kIdMovd;
+        dst.setSignature(Reg::signatureOfT<Reg::kTypeGpd>());
+        break;
+      }
+    }
+
+    if (Type::isMmx(dstTypeId)) {
+      instId = Inst::kIdMovq;
+      srcSize = Support::min(srcSize, dstSize);
+
+      if (Type::isInt(srcTypeId) || src.isMem()) {
+        // 64-bit move.
+        if (srcSize == 8)
+          break;
+
+        // 32-bit move.
+        instId = Inst::kIdMovd;
+        if (src.isReg())
+          src.setSignature(Reg::signatureOfT<Reg::kTypeGpd>());
+        break;
+      }
+
+      if (Type::isMmx(srcTypeId))
+        break;
+
+      // This will hurt if `avxEnabled`.
+      instId = Inst::kIdMovdq2q;
+      if (Type::isVec(srcTypeId))
+break;
+    }
+
+    if (Type::isMask(dstTypeId)) {
+      srcSize = Support::min(srcSize, dstSize);
+
+      if (Type::isInt(srcTypeId) || Type::isMask(srcTypeId) || src.isMem()) {
+        instId = x86KmovFromSize(srcSize);
+        if (Reg::isGp(src) && srcSize <= 4)
+          src.setSignature(Reg::signatureOfT<Reg::kTypeGpd>());
+        break;
+      }
+    }
+
+    if (Type::isVec(dstTypeId)) {
+      // By default set destination to XMM, will be set to YMM|ZMM if needed.
+      dst.setSignature(Reg::signatureOfT<Reg::kTypeXmm>());
+
+      // This will hurt if `avxEnabled`.
+      if (Reg::isMm(src)) {
+        // 64-bit move.
+        instId = Inst::kIdMovq2dq;
+        break;
+      }
+
+      // Argument conversion.
+      uint32_t dstElement = Type::baseOf(dstTypeId);
+      uint32_t srcElement = Type::baseOf(srcTypeId);
+
+      if (dstElement == Type::kIdF32 && srcElement == Type::kIdF64) {
+        srcSize = Support::min(dstSize * 2, srcSize);
+        dstSize = srcSize / 2;
+
+        if (srcSize <= 8)
+          instId = avxEnabled ? Inst::kIdVcvtss2sd : Inst::kIdCvtss2sd;
+        else
+          instId = avxEnabled ? Inst::kIdVcvtps2pd : Inst::kIdCvtps2pd;
+
+        if (dstSize == 32)
+          dst.setSignature(Reg::signatureOfT<Reg::kTypeYmm>());
+        if (src.isReg())
+          src.setSignature(Reg::signatureOfVecBySize(srcSize));
+        break;
+      }
+
+      if (dstElement == Type::kIdF64 && srcElement == Type::kIdF32) {
+        srcSize = Support::min(dstSize, srcSize * 2) / 2;
+        dstSize = srcSize * 2;
+
+        if (srcSize <= 4)
+          instId = avxEnabled ? Inst::kIdVcvtsd2ss : Inst::kIdCvtsd2ss;
+        else
+          instId = avxEnabled ? Inst::kIdVcvtpd2ps : Inst::kIdCvtpd2ps;
+
+        dst.setSignature(Reg::signatureOfVecBySize(dstSize));
+        if (src.isReg() && srcSize >= 32)
+          src.setSignature(Reg::signatureOfT<Reg::kTypeYmm>());
+        break;
+      }
+
+      srcSize = Support::min(srcSize, dstSize);
+      if (Reg::isGp(src) || src.isMem()) {
+        // 32-bit move.
+        if (srcSize <= 4) {
+          instId = avxEnabled ? Inst::kIdVmovd : Inst::kIdMovd;
+          if (src.isReg())
+            src.setSignature(Reg::signatureOfT<Reg::kTypeGpd>());
+          break;
+        }
+
+        // 64-bit move.
+        if (srcSize == 8) {
+          instId = avxEnabled ? Inst::kIdVmovq : Inst::kIdMovq;
+          break;
+        }
+      }
+
+      if (Reg::isVec(src) || src.isMem()) {
+        instId = avxEnabled ? Inst::kIdVmovaps : Inst::kIdMovaps;
+
+        if (src.isMem() && srcSize < emitter->environment().stackAlignment())
+          instId = avxEnabled ? Inst::kIdVmovups : Inst::kIdMovups;
+
+        uint32_t signature = Reg::signatureOfVecBySize(srcSize);
+        dst.setSignature(signature);
+        if (src.isReg())
+          src.setSignature(signature);
+        break;
+      }
+    }
+
+    return DebugUtils::errored(kErrorInvalidState);
+  }
+
+  if (src.isMem())
+    src.as<Mem>().setSize(srcSize);
+
+  emitter->setInlineComment(comment);
+  return emitter->emit(instId, dst, src);
+}
+
+// ============================================================================
+// [asmjit::X86Internal - Emit Prolog & Epilog]
+// ============================================================================
+
+static ASMJIT_INLINE void X86Internal_setupSaveRestoreInfo(uint32_t group, const FuncFrame& frame, Reg& xReg, uint32_t& xInst, uint32_t& xSize) noexcept {
+  switch (group) {
+    case Reg::kGroupVec:
+      xReg = xmm(0);
+      xInst = x86GetXmmMovInst(frame);
+      xSize = xReg.size();
+      break;
+    case Reg::kGroupMm:
+      xReg = mm(0);
+      xInst = Inst::kIdMovq;
+      xSize = xReg.size();
+      break;
+    case Reg::kGroupKReg:
+      xReg = k(0);
+      xInst = Inst::kIdKmovq;
+      xSize = xReg.size();
+      break;
+  }
+}
+
+ASMJIT_FAVOR_SIZE Error X86Internal::emitProlog(Emitter* emitter, const FuncFrame& frame) {
+  uint32_t gpSaved = frame.savedRegs(Reg::kGroupGp);
+
+  Gp zsp = emitter->zsp();   // ESP|RSP register.
+  Gp zbp = emitter->zbp();   // EBP|RBP register.
+  Gp gpReg = zsp;            // General purpose register (temporary).
+  Gp saReg = zsp;            // Stack-arguments base pointer.
+
+  // Emit: 'push zbp'
+  //       'mov  zbp, zsp'.
+  if (frame.hasPreservedFP()) {
+    gpSaved &= ~Support::bitMask(Gp::kIdBp);
+    ASMJIT_PROPAGATE(emitter->push(zbp));
+    ASMJIT_PROPAGATE(emitter->mov(zbp, zsp));
+  }
+
+  // Emit: 'push gp' sequence.
+  {
+    Support::BitWordIterator<uint32_t> it(gpSaved);
+    while (it.hasNext()) {
+      gpReg.setId(it.next());
+      ASMJIT_PROPAGATE(emitter->push(gpReg));
+    }
+  }
+
+  // Emit: 'mov saReg, zsp'.
+  uint32_t saRegId = frame.saRegId();
+  if (saRegId != BaseReg::kIdBad && saRegId != Gp::kIdSp) {
+    saReg.setId(saRegId);
+    if (frame.hasPreservedFP()) {
+      if (saRegId != Gp::kIdBp)
+        ASMJIT_PROPAGATE(emitter->mov(saReg, zbp));
+    }
+    else {
+      ASMJIT_PROPAGATE(emitter->mov(saReg, zsp));
+    }
+  }
+
+  // Emit: 'and zsp, StackAlignment'.
+  if (frame.hasDynamicAlignment()) {
+    ASMJIT_PROPAGATE(emitter->and_(zsp, -int32_t(frame.finalStackAlignment())));
+  }
+
+  // Emit: 'sub zsp, StackAdjustment'.
+  if (frame.hasStackAdjustment()) {
+    ASMJIT_PROPAGATE(emitter->sub(zsp, frame.stackAdjustment()));
+  }
+
+  // Emit: 'mov [zsp + DAOffset], saReg'.
+  if (frame.hasDynamicAlignment() && frame.hasDAOffset()) {
+    Mem saMem = ptr(zsp, int32_t(frame.daOffset()));
+    ASMJIT_PROPAGATE(emitter->mov(saMem, saReg));
+  }
+
+  // Emit 'movxxx [zsp + X], {[x|y|z]mm, k}'.
+  {
+    Reg xReg;
+    Mem xBase = ptr(zsp, int32_t(frame.nonGpSaveOffset()));
+
+    uint32_t xInst;
+    uint32_t xSize;
+
+    for (uint32_t group = 1; group < BaseReg::kGroupVirt; group++) {
+      Support::BitWordIterator<uint32_t> it(frame.savedRegs(group));
+      if (it.hasNext()) {
+        X86Internal_setupSaveRestoreInfo(group, frame, xReg, xInst, xSize);
+        do {
+          xReg.setId(it.next());
+          ASMJIT_PROPAGATE(emitter->emit(xInst, xBase, xReg));
+          xBase.addOffsetLo32(int32_t(xSize));
+        } while (it.hasNext());
+      }
+    }
+  }
+
+  return kErrorOk;
+}
+
+ASMJIT_FAVOR_SIZE Error X86Internal::emitEpilog(Emitter* emitter, const FuncFrame& frame) {
+  uint32_t i;
+  uint32_t regId;
+
+  uint32_t registerSize = emitter->registerSize();
+  uint32_t gpSaved = frame.savedRegs(Reg::kGroupGp);
+
+  Gp zsp = emitter->zsp();   // ESP|RSP register.
+  Gp zbp = emitter->zbp();   // EBP|RBP register.
+  Gp gpReg = emitter->zsp(); // General purpose register (temporary).
+
+  // Don't emit 'pop zbp' in the pop sequence, this case is handled separately.
+  if (frame.hasPreservedFP())
+    gpSaved &= ~Support::bitMask(Gp::kIdBp);
+
+  // Emit 'movxxx {[x|y|z]mm, k}, [zsp + X]'.
+  {
+    Reg xReg;
+    Mem xBase = ptr(zsp, int32_t(frame.nonGpSaveOffset()));
+
+    uint32_t xInst;
+    uint32_t xSize;
+
+    for (uint32_t group = 1; group < BaseReg::kGroupVirt; group++) {
+      Support::BitWordIterator<uint32_t> it(frame.savedRegs(group));
+      if (it.hasNext()) {
+        X86Internal_setupSaveRestoreInfo(group, frame, xReg, xInst, xSize);
+        do {
+          xReg.setId(it.next());
+          ASMJIT_PROPAGATE(emitter->emit(xInst, xReg, xBase));
+          xBase.addOffsetLo32(int32_t(xSize));
+        } while (it.hasNext());
+      }
+    }
+  }
+
+  // Emit 'emms' and/or 'vzeroupper'.
+  if (frame.hasMmxCleanup()) ASMJIT_PROPAGATE(emitter->emms());
+  if (frame.hasAvxCleanup()) ASMJIT_PROPAGATE(emitter->vzeroupper());
+
+  if (frame.hasPreservedFP()) {
+    // Emit 'mov zsp, zbp' or 'lea zsp, [zbp - x]'
+    int32_t count = int32_t(frame.gpSaveSize() - registerSize);
+    if (!count)
+      ASMJIT_PROPAGATE(emitter->mov(zsp, zbp));
+    else
+      ASMJIT_PROPAGATE(emitter->lea(zsp, ptr(zbp, -count)));
+  }
+  else {
+    if (frame.hasDynamicAlignment() && frame.hasDAOffset()) {
+      // Emit 'mov zsp, [zsp + DsaSlot]'.
+      Mem saMem = ptr(zsp, int32_t(frame.daOffset()));
+      ASMJIT_PROPAGATE(emitter->mov(zsp, saMem));
+    }
+    else if (frame.hasStackAdjustment()) {
+      // Emit 'add zsp, StackAdjustment'.
+      ASMJIT_PROPAGATE(emitter->add(zsp, int32_t(frame.stackAdjustment())));
+    }
+  }
+
+  // Emit 'pop gp' sequence.
+  if (gpSaved) {
+    i = gpSaved;
+    regId = 16;
+
+    do {
+      regId--;
+      if (i & 0x8000) {
+        gpReg.setId(regId);
+        ASMJIT_PROPAGATE(emitter->pop(gpReg));
+      }
+      i <<= 1;
+    } while (regId != 0);
+  }
+
+  // Emit 'pop zbp'.
+  if (frame.hasPreservedFP())
+    ASMJIT_PROPAGATE(emitter->pop(zbp));
+
+  // Emit 'ret' or 'ret x'.
+  if (frame.hasCalleeStackCleanup())
+    ASMJIT_PROPAGATE(emitter->emit(Inst::kIdRet, int(frame.calleeStackCleanup())));
+  else
+    ASMJIT_PROPAGATE(emitter->emit(Inst::kIdRet));
+
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::X86Internal - Emit Arguments Assignment]
+// ============================================================================
+
+#ifdef ASMJIT_DUMP_ARGS_ASSIGNMENT
+static void dumpFuncValue(String& sb, uint32_t arch, const FuncValue& value) noexcept {
+  Formatter::formatTypeId(sb, value.typeId());
+  sb.append('@');
+
+  if (value.isIndirect())
+    sb.append('[');
+
+  if (value.isReg())
+    Formatter::formatRegister(sb, 0, nullptr, arch, value.regType(), value.regId());
+  else if (value.isStack())
+    sb.appendFormat("[%d]", value.stackOffset());
+  else
+    sb.append("<none>");
+
+  if (value.isIndirect())
+    sb.append(']');
+}
+
+static void dumpAssignment(String& sb, const X86FuncArgsContext& ctx) noexcept {
+  typedef X86FuncArgsContext::Var Var;
+
+  uint32_t arch = ctx.arch();
+  uint32_t varCount = ctx.varCount();
+
+  for (uint32_t i = 0; i < varCount; i++) {
+    const Var& var = ctx.var(i);
+    const FuncValue& dst = var.out;
+    const FuncValue& cur = var.cur;
+
+    sb.appendFormat("Var%u: ", i);
+    dumpFuncValue(sb, arch, dst);
+    sb.append(" <- ");
+    dumpFuncValue(sb, arch, cur);
+
+    if (var.isDone())
+      sb.append(" {Done}");
+
+    sb.append('\n');
+  }
+}
+#endif
+
+ASMJIT_FAVOR_SIZE Error X86Internal::emitArgsAssignment(Emitter* emitter, const FuncFrame& frame, const FuncArgsAssignment& args) {
+  typedef X86FuncArgsContext::Var Var;
+  typedef X86FuncArgsContext::WorkData WorkData;
+
+  enum WorkFlags : uint32_t {
+    kWorkNone      = 0x00,
+    kWorkDidSome   = 0x01,
+    kWorkPending   = 0x02,
+    kWorkPostponed = 0x04
+  };
+
+  X86FuncArgsContext ctx;
+  ASMJIT_PROPAGATE(ctx.initWorkData(frame, args));
+
+#ifdef ASMJIT_DUMP_ARGS_ASSIGNMENT
+  {
+    String sb;
+    dumpAssignment(sb, ctx);
+    printf("%s\n", sb.data());
+  }
+#endif
+
+  uint32_t arch = ctx.arch();
+  uint32_t varCount = ctx._varCount;
+  WorkData* workData = ctx._workData;
+
+  // Use AVX if it's enabled.
+  bool avxEnabled = frame.isAvxEnabled();
+
+  uint32_t saVarId = ctx._saVarId;
+  uint32_t saRegId = Gp::kIdSp;
+
+  if (frame.hasDynamicAlignment()) {
+    if (frame.hasPreservedFP())
+      saRegId = Gp::kIdBp;
+    else
+      saRegId = saVarId < varCount ? ctx._vars[saVarId].cur.regId() : frame.saRegId();
+  }
+
+  RegInfo gpRegInfo = emitter->_gpRegInfo;
+
+  // --------------------------------------------------------------------------
+  // Register to stack and stack to stack moves must be first as now we have
+  // the biggest chance of having as many as possible unassigned registers.
+  // --------------------------------------------------------------------------
+
+  if (ctx._stackDstMask) {
+    // Base address of all arguments passed by stack.
+    Mem baseArgPtr = ptr(emitter->gpz(saRegId), int32_t(frame.saOffset(saRegId)));
+    Mem baseStackPtr = ptr(emitter->gpz(Gp::kIdSp), int32_t(0));
+
+    for (uint32_t varId = 0; varId < varCount; varId++) {
+      Var& var = ctx._vars[varId];
+
+      if (!var.out.isStack())
+        continue;
+
+      FuncValue& cur = var.cur;
+      FuncValue& out = var.out;
+
+      ASMJIT_ASSERT(cur.isReg() || cur.isStack());
+      Reg reg;
+
+      Mem dstStackPtr = baseStackPtr.cloneAdjusted(out.stackOffset());
+      Mem srcStackPtr = baseArgPtr.cloneAdjusted(cur.stackOffset());
+
+      if (cur.isIndirect()) {
+        if (cur.isStack()) {
+          // TODO: Indirect stack.
+          return DebugUtils::errored(kErrorInvalidAssignment);
+        }
+        else {
+          srcStackPtr = ptr(Gp(gpRegInfo.signature(), cur.regId()));
+        }
+      }
+
+      if (cur.isReg() && !cur.isIndirect()) {
+        WorkData& wd = workData[Reg::groupOf(cur.regType())];
+        uint32_t rId = cur.regId();
+
+        reg.setSignatureAndId(Reg::signatureOf(cur.regType()), rId);
+        wd.unassign(varId, rId);
+      }
+      else {
+        // Stack to reg move - tricky since we move stack to stack we can decide which
+        // register to use. In general we follow the rule that IntToInt moves will use
+        // GP regs with possibility to signature or zero extend, and all other moves will
+        // either use GP or VEC regs depending on the size of the move.
+        RegInfo rInfo = x86GetRegForMemToMemMove(arch, out.typeId(), cur.typeId());
+        if (ASMJIT_UNLIKELY(!rInfo.isValid()))
+          return DebugUtils::errored(kErrorInvalidState);
+
+        WorkData& wd = workData[rInfo.group()];
+        uint32_t availableRegs = wd.availableRegs();
+        if (ASMJIT_UNLIKELY(!availableRegs))
+          return DebugUtils::errored(kErrorInvalidState);
+
+        uint32_t rId = Support::ctz(availableRegs);
+        reg.setSignatureAndId(rInfo.signature(), rId);
+
+        ASMJIT_PROPAGATE(emitArgMove(emitter, reg, out.typeId(), srcStackPtr, cur.typeId(), avxEnabled));
+      }
+
+      if (cur.isIndirect() && cur.isReg())
+        workData[BaseReg::kGroupGp].unassign(varId, cur.regId());
+
+      // Register to stack move.
+      ASMJIT_PROPAGATE(emitRegMove(emitter, dstStackPtr, reg, cur.typeId(), avxEnabled));
+      var.markDone();
+    }
+  }
+
+  // --------------------------------------------------------------------------
+  // Shuffle all registers that are currently assigned accordingly to target
+  // assignment.
+  // --------------------------------------------------------------------------
+
+  uint32_t workFlags = kWorkNone;
+  for (;;) {
+    for (uint32_t varId = 0; varId < varCount; varId++) {
+      Var& var = ctx._vars[varId];
+      if (var.isDone() || !var.cur.isReg())
+        continue;
+
+      FuncValue& cur = var.cur;
+      FuncValue& out = var.out;
+
+      uint32_t curGroup = Reg::groupOf(cur.regType());
+      uint32_t outGroup = Reg::groupOf(out.regType());
+
+      uint32_t curId = cur.regId();
+      uint32_t outId = out.regId();
+
+      if (curGroup != outGroup) {
+        // TODO: Conversion is not supported.
+        return DebugUtils::errored(kErrorInvalidAssignment);
+      }
+      else {
+        WorkData& wd = workData[outGroup];
+        if (!wd.isAssigned(outId)) {
+EmitMove:
+          ASMJIT_PROPAGATE(
+            emitArgMove(emitter,
+              Reg::fromTypeAndId(out.regType(), outId), out.typeId(),
+              Reg::fromTypeAndId(cur.regType(), curId), cur.typeId(), avxEnabled));
+
+          wd.reassign(varId, outId, curId);
+          cur.initReg(out.regType(), outId, out.typeId());
+
+          if (outId == out.regId())
+            var.markDone();
+          workFlags |= kWorkDidSome | kWorkPending;
+        }
+        else {
+          uint32_t altId = wd._physToVarId[outId];
+          Var& altVar = ctx._vars[altId];
+
+          if (!altVar.out.isInitialized() || (altVar.out.isReg() && altVar.out.regId() == curId)) {
+            // Swap operation is possible only between two GP registers.
+            if (curGroup == Reg::kGroupGp) {
+              uint32_t highestType = Support::max(cur.regType(), altVar.cur.regType());
+              uint32_t signature = highestType == Reg::kTypeGpq ? Reg::signatureOfT<Reg::kTypeGpq>()
+                                                                : Reg::signatureOfT<Reg::kTypeGpd>();
+
+              ASMJIT_PROPAGATE(emitter->emit(Inst::kIdXchg, Reg(signature, outId), Reg(signature, curId)));
+              wd.swap(varId, curId, altId, outId);
+              cur.setRegId(outId);
+              var.markDone();
+              altVar.cur.setRegId(curId);
+
+              if (altVar.out.isInitialized())
+                altVar.markDone();
+              workFlags |= kWorkDidSome;
+            }
+            else {
+              // If there is a scratch register it can be used to perform the swap.
+              uint32_t availableRegs = wd.availableRegs();
+              if (availableRegs) {
+                uint32_t inOutRegs = wd.dstRegs();
+                if (availableRegs & ~inOutRegs)
+                  availableRegs &= ~inOutRegs;
+                outId = Support::ctz(availableRegs);
+                goto EmitMove;
+              }
+              else {
+                workFlags |= kWorkPending;
+              }
+            }
+          }
+          else {
+            workFlags |= kWorkPending;
+          }
+        }
+      }
+    }
+
+    if (!(workFlags & kWorkPending))
+      break;
+
+    // If we did nothing twice it means that something is really broken.
+    if ((workFlags & (kWorkDidSome | kWorkPostponed)) == kWorkPostponed)
+      return DebugUtils::errored(kErrorInvalidState);
+
+    workFlags = (workFlags & kWorkDidSome) ? kWorkNone : kWorkPostponed;
+  }
+
+  // --------------------------------------------------------------------------
+  // Load arguments passed by stack into registers. This is pretty simple and
+  // it never requires multiple iterations like the previous phase.
+  // --------------------------------------------------------------------------
+
+  if (ctx._hasStackSrc) {
+    uint32_t iterCount = 1;
+    if (frame.hasDynamicAlignment() && !frame.hasPreservedFP())
+      saRegId = saVarId < varCount ? ctx._vars[saVarId].cur.regId() : frame.saRegId();
+
+    // Base address of all arguments passed by stack.
+    Mem baseArgPtr = ptr(emitter->gpz(saRegId), int32_t(frame.saOffset(saRegId)));
+
+    for (uint32_t iter = 0; iter < iterCount; iter++) {
+      for (uint32_t varId = 0; varId < varCount; varId++) {
+        Var& var = ctx._vars[varId];
+        if (var.isDone())
+          continue;
+
+        if (var.cur.isStack()) {
+          ASMJIT_ASSERT(var.out.isReg());
+
+          uint32_t outId = var.out.regId();
+          uint32_t outType = var.out.regType();
+
+          uint32_t group = Reg::groupOf(outType);
+          WorkData& wd = ctx._workData[group];
+
+          if (outId == saRegId && group == BaseReg::kGroupGp) {
+            // This register will be processed last as we still need `saRegId`.
+            if (iterCount == 1) {
+              iterCount++;
+              continue;
+            }
+            wd.unassign(wd._physToVarId[outId], outId);
+          }
+
+          Reg dstReg = Reg::fromTypeAndId(outType, outId);
+          Mem srcMem = baseArgPtr.cloneAdjusted(var.cur.stackOffset());
+
+          ASMJIT_PROPAGATE(
+            emitArgMove(emitter,
+              dstReg, var.out.typeId(),
+              srcMem, var.cur.typeId(), avxEnabled));
+
+          wd.assign(varId, outId);
+          var.cur.initReg(outType, outId, var.cur.typeId(), FuncValue::kFlagIsDone);
+        }
+      }
+    }
+  }
+
+  return kErrorOk;
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86
diff --git a/client/asmjit/x86/x86internal_p.h b/client/asmjit/x86/x86internal_p.h
new file mode 100644
index 0000000..d4ea8e1
--- /dev/null
+++ b/client/asmjit/x86/x86internal_p.h
@@ -0,0 +1,87 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86INTERNAL_P_H_INCLUDED
+#define ASMJIT_X86_X86INTERNAL_P_H_INCLUDED
+
+#include "../core/api-config.h"
+
+#include "../core/func.h"
+#include "../x86/x86emitter.h"
+#include "../x86/x86operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::X86Internal]
+// ============================================================================
+
+//! X86 utilities used at multiple places, not part of public API, not exported.
+struct X86Internal {
+  //! Initialize `FuncDetail` (X86 specific).
+  static Error initFuncDetail(FuncDetail& func, const FuncSignature& signature, uint32_t registerSize) noexcept;
+
+  //! Initialize `FuncFrame` (X86 specific).
+  static Error initFuncFrame(FuncFrame& frame, const FuncDetail& signature) noexcept;
+
+  //! Finalize `FuncFrame` (X86 specific).
+  static Error finalizeFuncFrame(FuncFrame& frame) noexcept;
+
+  static Error argsToFuncFrame(const FuncArgsAssignment& args, FuncFrame& frame) noexcept;
+
+  //! Emit function prolog.
+  static Error emitProlog(Emitter* emitter, const FuncFrame& frame);
+
+  //! Emit function epilog.
+  static Error emitEpilog(Emitter* emitter, const FuncFrame& frame);
+
+  //! Emit a pure move operation between two registers or the same type or
+  //! between a register and its home slot. This function does not handle
+  //! register conversion.
+  static Error emitRegMove(Emitter* emitter,
+    const Operand_& dst_,
+    const Operand_& src_, uint32_t typeId, bool avxEnabled, const char* comment = nullptr);
+
+  //! Emit move from a function argument (either register or stack) to a register.
+  //!
+  //! This function can handle the necessary conversion from one argument to
+  //! another, and from one register type to another, if it's possible. Any
+  //! attempt of conversion that requires third register of a different group
+  //! (for example conversion from K to MMX) will fail.
+  static Error emitArgMove(Emitter* emitter,
+    const Reg& dst_, uint32_t dstTypeId,
+    const Operand_& src_, uint32_t srcTypeId, bool avxEnabled, const char* comment = nullptr);
+
+  static Error emitArgsAssignment(Emitter* emitter, const FuncFrame& frame, const FuncArgsAssignment& args);
+};
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86INTERNAL_P_H_INCLUDED
diff --git a/client/asmjit/x86/x86opcode_p.h b/client/asmjit/x86/x86opcode_p.h
new file mode 100644
index 0000000..5f936bf
--- /dev/null
+++ b/client/asmjit/x86/x86opcode_p.h
@@ -0,0 +1,478 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86OPCODE_P_H_INCLUDED
+#define ASMJIT_X86_X86OPCODE_P_H_INCLUDED
+
+#include "../x86/x86globals.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \cond INTERNAL
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [asmjit::x86::Opcode]
+// ============================================================================
+
+//! Helper class to store and manipulate X86 opcodes.
+//!
+//! The first 8 least significant bits describe the opcode byte as defined in
+//! ISA manuals, all other bits describe other properties like prefixes, see
+//! `Opcode::Bits` for more information.
+struct Opcode {
+  uint32_t v;
+
+  //! Describes a meaning of all bits of AsmJit's 32-bit opcode value.
+  //!
+  //! This schema is AsmJit specific and has been designed to allow encoding of
+  //! all X86 instructions available. X86, MMX, and SSE+ instructions always use
+  //! `MM` and `PP` fields, which are encoded to corresponding prefixes needed
+  //! by X86 or SIMD instructions. AVX+ instructions embed `MMMMM` and `PP` fields
+  //! in a VEX prefix, and AVX-512 instructions embed `MM` and `PP` in EVEX prefix.
+  //!
+  //! The instruction opcode definition uses 1 or 2 bytes as an opcode value. 1
+  //! byte is needed by most of the instructions, 2 bytes are only used by legacy
+  //! X87-FPU instructions. This means that a second byte is free to by used by
+  //! instructions encoded by using VEX and/or EVEX prefix.
+  //!
+  //! The fields description:
+  //!
+  //! - `MM` field is used to encode prefixes needed by the instruction or as
+  //!   a part of VEX/EVEX prefix. Described as `mm` and `mmmmm` in instruction
+  //!   manuals.
+  //!
+  //!   NOTE: Since `MM` field is defined as `mmmmm` (5 bits), but only 2 least
+  //!   significant bits are used by VEX and EVEX prefixes, and additional 4th
+  //!   bit is used by XOP prefix, AsmJit uses the 3rd and 5th bit for it's own
+  //!   purposes. These bits will probably never be used in future encodings as
+  //!   AVX512 uses only `000mm` from `mmmmm`.
+  //!
+  //! - `PP` field is used to encode prefixes needed by the instruction or as a
+  //!   part of VEX/EVEX prefix. Described as `pp` in instruction manuals.
+  //!
+  //! - `LL` field is used exclusively by AVX+ and AVX512+ instruction sets. It
+  //!   describes vector size, which is `L.128` for XMM register, `L.256` for
+  //!   for YMM register, and `L.512` for ZMM register. The `LL` field is omitted
+  //!   in case that instruction supports multiple vector lengths, however, if the
+  //!   instruction requires specific `L` value it must be specified as a part of
+  //!   the opcode.
+  //!
+  //!   NOTE: `LL` having value `11` is not defined yet.
+  //!
+  //! - `W` field is the most complicated. It was added by 64-bit architecture
+  //!   to promote default operation width (instructions that perform 32-bit
+  //!   operation by default require to override the width to 64-bit explicitly).
+  //!   There is nothing wrong on this, however, some instructions introduced
+  //!   implicit `W` override, for example a `cdqe` instruction is basically a
+  //!   `cwde` instruction with overridden `W` (set to 1). There are some others
+  //!   in the base X86 instruction set. More recent instruction sets started
+  //!   using `W` field more often:
+  //!
+  //!   - AVX instructions started using `W` field as an extended opcode for FMA,
+  //!     GATHER, PERM, and other instructions. It also uses `W` field to override
+  //!     the default operation width in instructions like `vmovq`.
+  //!
+  //!   - AVX-512 instructions started using `W` field as an extended opcode for
+  //!     all new instructions. This wouldn't have been an issue if the `W` field
+  //!     of AVX-512 have matched AVX, but this is not always the case.
+  //!
+  //! - `O` field is an extended opcode field (3 bits) embedded in ModR/M BYTE.
+  //!
+  //! - `CDSHL` and `CDTT` fields describe 'compressed-displacement'. `CDSHL` is
+  //!   defined for each instruction that is AVX-512 encodable (EVEX) and contains
+  //!   a base N shift (base shift to perform the calculation). The `CDTT` field
+  //!   is derived from instruction specification and describes additional shift
+  //!   to calculate the final `CDSHL` that will be used in SIB byte.
+  //!
+  //! \note Don't reorder any fields here, the shifts and masks were defined
+  //! carefully to make encoding of X86 instructions fast, especially to construct
+  //! REX, VEX, and EVEX prefixes in the most efficient way. Changing values defined
+  //! by these enums many cause AsmJit to emit invalid binary representations of
+  //! instructions passed to `x86::Assembler::_emit`.
+  enum Bits : uint32_t {
+    // MM & VEX & EVEX & XOP
+    // ---------------------
+    //
+    // Two meanings:
+    //  * Part of a legacy opcode (prefixes emitted before the main opcode byte).
+    //  * `MMMMM` field in VEX|EVEX|XOP instruction.
+    //
+    // AVX reserves 5 bits for `MMMMM` field, however AVX instructions only use
+    // 2 bits and XOP 3 bits. AVX-512 shrinks `MMMMM` field into `MM` so it's
+    // safe to assume that bits [4:2] of `MM` field won't be used in future
+    // extensions, which will most probably use EVEX encoding. AsmJit divides
+    // MM field into this layout:
+    //
+    // [1:0] - Used to describe 0F, 0F38 and 0F3A legacy prefix bytes and
+    //         2 bits of MM field.
+    // [2]   - Used to force 3-BYTE VEX prefix, but then cleared to zero before
+    //         the prefix is emitted. This bit is not used by any instruction
+    //         so it can be used for any purpose by AsmJit. Also, this bit is
+    //         used as an extension to `MM` field describing 0F|0F38|0F3A to also
+    //         describe 0F01 as used by some legacy instructions (instructions
+    //         not using VEX/EVEX prefix).
+    // [3]   - Required by XOP instructions, so we use this bit also to indicate
+    //         that this is a XOP opcode.
+    kMM_Shift      = 8,
+    kMM_Mask       = 0x1Fu << kMM_Shift,
+    kMM_00         = 0x00u << kMM_Shift,
+    kMM_0F         = 0x01u << kMM_Shift,
+    kMM_0F38       = 0x02u << kMM_Shift,
+    kMM_0F3A       = 0x03u << kMM_Shift,   // Described also as XOP.M3 in AMD manuals.
+    kMM_0F01       = 0x04u << kMM_Shift,   // AsmJit way to describe 0F01 (never VEX/EVEX).
+
+    // `XOP` field is only used to force XOP prefix instead of VEX3 prefix. We
+    // know that only XOP encoding uses bit 0b1000 of MM field and that no VEX
+    // and EVEX instruction uses such bit, so we can use this bit to force XOP
+    // prefix to be emitted instead of VEX3 prefix. See `x86VEXPrefix` defined
+    // in `x86assembler.cpp`.
+    kMM_XOP08      = 0x08u << kMM_Shift,   // XOP.M8.
+    kMM_XOP09      = 0x09u << kMM_Shift,   // XOP.M9.
+    kMM_XOP0A      = 0x0Au << kMM_Shift,   // XOP.MA.
+
+    kMM_IsXOP_Shift= kMM_Shift + 3,
+    kMM_IsXOP      = kMM_XOP08,
+
+    // NOTE: Force VEX3 allows to force to emit VEX3 instead of VEX2 in some
+    // cases (similar to forcing REX prefix). Force EVEX will force emitting
+    // EVEX prefix instead of VEX2|VEX3. EVEX-only instructions will have
+    // ForceEvex always set, however. instructions that can be encoded by
+    // either VEX or EVEX prefix should not have ForceEvex set.
+
+    kMM_ForceVex3  = 0x04u << kMM_Shift,   // Force 3-BYTE VEX prefix.
+    kMM_ForceEvex  = 0x10u << kMM_Shift,   // Force 4-BYTE EVEX prefix.
+
+    // FPU_2B - Second-Byte of the Opcode used by FPU
+    // ----------------------------------------------
+    //
+    // Second byte opcode. This BYTE is ONLY used by FPU instructions and
+    // collides with 3 bits from `MM` and 5 bits from 'CDSHL' and 'CDTT'.
+    // It's fine as FPU and AVX512 flags are never used at the same time.
+    kFPU_2B_Shift  = 10,
+    kFPU_2B_Mask   = 0xFF << kFPU_2B_Shift,
+
+    // CDSHL & CDTT
+    // ------------
+    //
+    // Compressed displacement bits.
+    //
+    // Each opcode defines the base size (N) shift:
+    //   [0]: BYTE  (1 byte).
+    //   [1]: WORD  (2 bytes).
+    //   [2]: DWORD (4 bytes - float/int32).
+    //   [3]: QWORD (8 bytes - double/int64).
+    //   [4]: OWORD (16 bytes - used by FV|FVM|M128).
+    //
+    // Which is then scaled by the instruction's TT (TupleType) into possible:
+    //   [5]: YWORD (32 bytes)
+    //   [6]: ZWORD (64 bytes)
+    //
+    // These bits are then adjusted before calling EmitModSib or EmitModVSib.
+    kCDSHL_Shift   = 13,
+    kCDSHL_Mask    = 0x7u << kCDSHL_Shift,
+
+    kCDSHL__       = 0x0u << kCDSHL_Shift, // Base element size not used.
+    kCDSHL_0       = 0x0u << kCDSHL_Shift, // N << 0.
+    kCDSHL_1       = 0x1u << kCDSHL_Shift, // N << 1.
+    kCDSHL_2       = 0x2u << kCDSHL_Shift, // N << 2.
+    kCDSHL_3       = 0x3u << kCDSHL_Shift, // N << 3.
+    kCDSHL_4       = 0x4u << kCDSHL_Shift, // N << 4.
+    kCDSHL_5       = 0x5u << kCDSHL_Shift, // N << 5.
+
+    // Compressed displacement tuple-type (specific to AsmJit).
+    //
+    // Since we store the base offset independently of CDTT we can simplify the
+    // number of 'TUPLE_TYPE' groups significantly and just handle special cases.
+    kCDTT_Shift    = 16,
+    kCDTT_Mask     = 0x3u << kCDTT_Shift,
+    kCDTT_None     = 0x0u << kCDTT_Shift,  // Does nothing.
+    kCDTT_ByLL     = 0x1u << kCDTT_Shift,  // Scales by LL (1x 2x 4x).
+    kCDTT_T1W      = 0x2u << kCDTT_Shift,  // Used to add 'W' to the shift.
+    kCDTT_DUP      = 0x3u << kCDTT_Shift,  // Special 'VMOVDDUP' case.
+
+    // Aliases that match names used in instruction manuals.
+    kCDTT__        = kCDTT_None,
+    kCDTT_FV       = kCDTT_ByLL,
+    kCDTT_HV       = kCDTT_ByLL,
+    kCDTT_FVM      = kCDTT_ByLL,
+    kCDTT_T1S      = kCDTT_None,
+    kCDTT_T1F      = kCDTT_None,
+    kCDTT_T1_4X    = kCDTT_None,
+    kCDTT_T2       = kCDTT_None,
+    kCDTT_T4       = kCDTT_None,
+    kCDTT_T8       = kCDTT_None,
+    kCDTT_HVM      = kCDTT_ByLL,
+    kCDTT_QVM      = kCDTT_ByLL,
+    kCDTT_OVM      = kCDTT_ByLL,
+    kCDTT_128      = kCDTT_None,
+
+    kCDTT_T4X      = kCDTT_T1_4X,          // Alias to have only 3 letters.
+
+    // `O` Field in ModR/M (??:xxx:???)
+    // --------------------------------
+
+    kModO_Shift    = 18,
+    kModO_Mask     = 0x7u << kModO_Shift,
+
+    kModO__        = 0x0u,
+    kModO_0        = 0x0u << kModO_Shift,
+    kModO_1        = 0x1u << kModO_Shift,
+    kModO_2        = 0x2u << kModO_Shift,
+    kModO_3        = 0x3u << kModO_Shift,
+    kModO_4        = 0x4u << kModO_Shift,
+    kModO_5        = 0x5u << kModO_Shift,
+    kModO_6        = 0x6u << kModO_Shift,
+    kModO_7        = 0x7u << kModO_Shift,
+
+    // `RM` Field in ModR/M (??:???:xxx)
+    // ---------------------------------
+    //
+    // Second data field used by ModR/M byte. This is only used by few
+    // instructions that use OPCODE+MOD/RM where both values in Mod/RM
+    // are part of the opcode.
+
+    kModRM_Shift    = 10,
+    kModRM_Mask     = 0x7u << kModRM_Shift,
+
+    kModRM__        = 0x0u,
+    kModRM_0        = 0x0u << kModRM_Shift,
+    kModRM_1        = 0x1u << kModRM_Shift,
+    kModRM_2        = 0x2u << kModRM_Shift,
+    kModRM_3        = 0x3u << kModRM_Shift,
+    kModRM_4        = 0x4u << kModRM_Shift,
+    kModRM_5        = 0x5u << kModRM_Shift,
+    kModRM_6        = 0x6u << kModRM_Shift,
+    kModRM_7        = 0x7u << kModRM_Shift,
+
+    // `PP` Field
+    // ----------
+    //
+    // These fields are stored deliberately right after each other as it makes
+    // it easier to construct VEX prefix from the opcode value stored in the
+    // instruction database.
+    //
+    // Two meanings:
+    //   * "PP" field in AVX/XOP/AVX-512 instruction.
+    //   * Mandatory Prefix in legacy encoding.
+    //
+    // AVX reserves 2 bits for `PP` field, but AsmJit extends the storage by 1
+    // more bit that is used to emit 9B prefix for some X87-FPU instructions.
+
+    kPP_Shift      = 21,
+    kPP_VEXMask    = 0x03u << kPP_Shift,   // PP field mask used by VEX/EVEX.
+    kPP_FPUMask    = 0x07u << kPP_Shift,   // Mask used by EMIT_PP, also includes '0x9B'.
+    kPP_00         = 0x00u << kPP_Shift,
+    kPP_66         = 0x01u << kPP_Shift,
+    kPP_F3         = 0x02u << kPP_Shift,
+    kPP_F2         = 0x03u << kPP_Shift,
+
+    kPP_9B         = 0x07u << kPP_Shift,   // AsmJit specific to emit FPU's '9B' byte.
+
+    // REX|VEX|EVEX B|X|R|W Bits
+    // -------------------------
+    //
+    // NOTE: REX.[B|X|R] are never stored within the opcode itself, they are
+    // reserved by AsmJit are are added dynamically to the opcode to represent
+    // [REX|VEX|EVEX].[B|X|R] bits. REX.W can be stored in DB as it's sometimes
+    // part of the opcode itself.
+
+    // These must be binary compatible with instruction options.
+    kREX_Shift     = 24,
+    kREX_Mask      = 0x0Fu << kREX_Shift,
+    kB             = 0x01u << kREX_Shift,  // Never stored in DB, used by encoder.
+    kX             = 0x02u << kREX_Shift,  // Never stored in DB, used by encoder.
+    kR             = 0x04u << kREX_Shift,  // Never stored in DB, used by encoder.
+    kW             = 0x08u << kREX_Shift,
+    kW_Shift       = kREX_Shift + 3,
+
+    kW__           = 0u << kW_Shift,       // REX.W/VEX.W is unspecified.
+    kW_x           = 0u << kW_Shift,       // REX.W/VEX.W is based on instruction operands.
+    kW_I           = 0u << kW_Shift,       // REX.W/VEX.W is ignored (WIG).
+    kW_0           = 0u << kW_Shift,       // REX.W/VEX.W is 0 (W0).
+    kW_1           = 1u << kW_Shift,       // REX.W/VEX.W is 1 (W1).
+
+    // EVEX.W Field
+    // ------------
+    //
+    // `W` field used by EVEX instruction encoding.
+
+    kEvex_W_Shift  = 28,
+    kEvex_W_Mask   = 1u << kEvex_W_Shift,
+
+    kEvex_W__      = 0u << kEvex_W_Shift,  // EVEX.W is unspecified (not EVEX instruction).
+    kEvex_W_x      = 0u << kEvex_W_Shift,  // EVEX.W is based on instruction operands.
+    kEvex_W_I      = 0u << kEvex_W_Shift,  // EVEX.W is ignored (WIG).
+    kEvex_W_0      = 0u << kEvex_W_Shift,  // EVEX.W is 0 (W0).
+    kEvex_W_1      = 1u << kEvex_W_Shift,  // EVEX.W is 1 (W1).
+
+    // `L` or `LL` field in AVX/XOP/AVX-512
+    // ------------------------------------
+    //
+    // VEX/XOP prefix can only use the first bit `L.128` or `L.256`. EVEX prefix
+    // prefix makes it possible to use also `L.512`.
+    //
+    // If the instruction set manual describes an instruction by `LIG` it means
+    // that the `L` field is ignored and AsmJit defaults to `0` in such case.
+    kLL_Shift      = 29,
+    kLL_Mask       = 0x3u << kLL_Shift,
+
+    kLL__          = 0x0u << kLL_Shift,    // LL is unspecified.
+    kLL_x          = 0x0u << kLL_Shift,    // LL is based on instruction operands.
+    kLL_I          = 0x0u << kLL_Shift,    // LL is ignored (LIG).
+    kLL_0          = 0x0u << kLL_Shift,    // LL is 0 (L.128).
+    kLL_1          = 0x1u << kLL_Shift,    // LL is 1 (L.256).
+    kLL_2          = 0x2u << kLL_Shift,    // LL is 2 (L.512).
+
+    // Opcode Combinations
+    // -------------------
+
+    k0      = 0,                           // '__' (no prefix, used internally).
+    k000000 = kPP_00 | kMM_00,             // '__' (no prefix, to be the same width as others).
+    k000F00 = kPP_00 | kMM_0F,             // '0F'
+    k000F01 = kPP_00 | kMM_0F01,           // '0F01'
+    k000F0F = kPP_00 | kMM_0F,             // '0F0F' - 3DNOW, equal to 0x0F, must have special encoding to take effect.
+    k000F38 = kPP_00 | kMM_0F38,           // '0F38'
+    k000F3A = kPP_00 | kMM_0F3A,           // '0F3A'
+    k660000 = kPP_66 | kMM_00,             // '66'
+    k660F00 = kPP_66 | kMM_0F,             // '660F'
+    k660F01 = kPP_66 | kMM_0F01,           // '660F01'
+    k660F38 = kPP_66 | kMM_0F38,           // '660F38'
+    k660F3A = kPP_66 | kMM_0F3A,           // '660F3A'
+    kF20000 = kPP_F2 | kMM_00,             // 'F2'
+    kF20F00 = kPP_F2 | kMM_0F,             // 'F20F'
+    kF20F01 = kPP_F2 | kMM_0F01,           // 'F20F01'
+    kF20F38 = kPP_F2 | kMM_0F38,           // 'F20F38'
+    kF20F3A = kPP_F2 | kMM_0F3A,           // 'F20F3A'
+    kF30000 = kPP_F3 | kMM_00,             // 'F3'
+    kF30F00 = kPP_F3 | kMM_0F,             // 'F30F'
+    kF30F01 = kPP_F3 | kMM_0F01,           // 'F30F01'
+    kF30F38 = kPP_F3 | kMM_0F38,           // 'F30F38'
+    kF30F3A = kPP_F3 | kMM_0F3A,           // 'F30F3A'
+    kFPU_00 = kPP_00 | kMM_00,             // '__' (FPU)
+    kFPU_9B = kPP_9B | kMM_00,             // '9B' (FPU)
+    kXOP_M8 = kPP_00 | kMM_XOP08,          // 'M8' (XOP)
+    kXOP_M9 = kPP_00 | kMM_XOP09,          // 'M9' (XOP)
+    kXOP_MA = kPP_00 | kMM_XOP0A           // 'MA' (XOP)
+  };
+
+  // --------------------------------------------------------------------------
+  // [Opcode Builder]
+  // --------------------------------------------------------------------------
+
+  ASMJIT_INLINE uint32_t get() const noexcept { return v; }
+
+  ASMJIT_INLINE bool hasW() const noexcept { return (v & kW) != 0; }
+  ASMJIT_INLINE bool has66h() const noexcept { return (v & kPP_66) != 0; }
+
+  ASMJIT_INLINE Opcode& add(uint32_t x) noexcept { return operator+=(x); }
+
+  ASMJIT_INLINE Opcode& add66h() noexcept { return operator|=(kPP_66); }
+  template<typename T>
+  ASMJIT_INLINE Opcode& add66hIf(T exp) noexcept { return operator|=(uint32_t(exp) << kPP_Shift); }
+  template<typename T>
+  ASMJIT_INLINE Opcode& add66hBySize(T size) noexcept { return add66hIf(size == 2); }
+
+  ASMJIT_INLINE Opcode& addW() noexcept { return operator|=(kW); }
+  template<typename T>
+  ASMJIT_INLINE Opcode& addWIf(T exp) noexcept { return operator|=(uint32_t(exp) << kW_Shift); }
+  template<typename T>
+  ASMJIT_INLINE Opcode& addWBySize(T size) noexcept { return addWIf(size == 8); }
+
+  template<typename T>
+  ASMJIT_INLINE Opcode& addPrefixBySize(T size) noexcept {
+    static const uint32_t mask[16] = {
+      0,          // #0
+      0,          // #1 -> nothing (already handled or not possible)
+      kPP_66,     // #2 -> 66H
+      0,          // #3
+      0,          // #4 -> nothing
+      0,          // #5
+      0,          // #6
+      0,          // #7
+      kW          // #8 -> REX.W
+    };
+    return operator|=(mask[size & 0xF]);
+  }
+
+  template<typename T>
+  ASMJIT_INLINE Opcode& addArithBySize(T size) noexcept {
+    static const uint32_t mask[16] = {
+      0,          // #0
+      0,          // #1 -> nothing
+      1 | kPP_66, // #2 -> NOT_BYTE_OP(1) and 66H
+      0,          // #3
+      1,          // #4 -> NOT_BYTE_OP(1)
+      0,          // #5
+      0,          // #6
+      0,          // #7
+      1 | kW      // #8 -> NOT_BYTE_OP(1) and REX.W
+    };
+    return operator|=(mask[size & 0xF]);
+  }
+
+  //! Extract `O` field (R) from the opcode (specified as /0..7 in instruction manuals).
+  ASMJIT_INLINE uint32_t extractModO() const noexcept {
+    return (v >> kModO_Shift) & 0x07;
+  }
+
+  //! Extract `RM` field (RM) from the opcode (usually specified as another opcode value).
+  ASMJIT_INLINE uint32_t extractModRM() const noexcept {
+    return (v >> kModRM_Shift) & 0x07;
+  }
+
+  //! Extract `REX` prefix from opcode combined with `options`.
+  ASMJIT_INLINE uint32_t extractRex(uint32_t options) const noexcept {
+    // kREX was designed in a way that when shifted there will be no bytes
+    // set except REX.[B|X|R|W]. The returned value forms a real REX prefix byte.
+    // This case should be unit-tested as well.
+    return (v | options) >> kREX_Shift;
+  }
+
+  ASMJIT_INLINE uint32_t extractLLMM(uint32_t options) const noexcept {
+    uint32_t x = v       & (kLL_Mask | kMM_Mask);
+    uint32_t y = options & (Inst::kOptionVex3 | Inst::kOptionEvex);
+    return (x | y) >> kMM_Shift;
+  }
+
+  ASMJIT_INLINE Opcode& operator=(uint32_t x) noexcept { v = x; return *this; }
+  ASMJIT_INLINE Opcode& operator+=(uint32_t x) noexcept { v += x; return *this; }
+  ASMJIT_INLINE Opcode& operator-=(uint32_t x) noexcept { v -= x; return *this; }
+  ASMJIT_INLINE Opcode& operator&=(uint32_t x) noexcept { v &= x; return *this; }
+  ASMJIT_INLINE Opcode& operator|=(uint32_t x) noexcept { v |= x; return *this; }
+  ASMJIT_INLINE Opcode& operator^=(uint32_t x) noexcept { v ^= x; return *this; }
+
+  ASMJIT_INLINE uint32_t operator&(uint32_t x) const noexcept { return v & x; }
+  ASMJIT_INLINE uint32_t operator|(uint32_t x) const noexcept { return v | x; }
+  ASMJIT_INLINE uint32_t operator^(uint32_t x) const noexcept { return v ^ x; }
+  ASMJIT_INLINE uint32_t operator<<(uint32_t x) const noexcept { return v << x; }
+  ASMJIT_INLINE uint32_t operator>>(uint32_t x) const noexcept { return v >> x; }
+};
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_X86_X86OPCODE_P_H_INCLUDED
diff --git a/client/asmjit/x86/x86operand.cpp b/client/asmjit/x86/x86operand.cpp
new file mode 100644
index 0000000..ca7ce5a
--- /dev/null
+++ b/client/asmjit/x86/x86operand.cpp
@@ -0,0 +1,271 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#include "../core/api-build_p.h"
+#ifdef ASMJIT_BUILD_X86
+
+#include "../core/misc_p.h"
+#include "../x86/x86operand.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::x86::OpData]
+// ============================================================================
+
+const OpData opData = {
+  {
+    // RegInfo[]
+    #define VALUE(X) { RegTraits<X>::kSignature }
+    { ASMJIT_LOOKUP_TABLE_32(VALUE, 0) },
+    #undef VALUE
+
+    // RegCount[]
+    #define VALUE(X) RegTraits<X>::kCount
+    { ASMJIT_LOOKUP_TABLE_32(VALUE, 0) },
+    #undef VALUE
+
+    // RegTypeToTypeId[]
+    #define VALUE(X) RegTraits<X>::kTypeId
+    { ASMJIT_LOOKUP_TABLE_32(VALUE, 0) }
+    #undef VALUE
+  }
+};
+
+// ============================================================================
+// [asmjit::x86::Operand - Unit]
+// ============================================================================
+
+#if defined(ASMJIT_TEST)
+UNIT(x86_operand) {
+  Label L(1000); // Label with some ID.
+
+  INFO("Checking basic properties of built-in X86 registers");
+  EXPECT(gpb(Gp::kIdAx) == al);
+  EXPECT(gpb(Gp::kIdBx) == bl);
+  EXPECT(gpb(Gp::kIdCx) == cl);
+  EXPECT(gpb(Gp::kIdDx) == dl);
+
+  EXPECT(gpb_lo(Gp::kIdAx) == al);
+  EXPECT(gpb_lo(Gp::kIdBx) == bl);
+  EXPECT(gpb_lo(Gp::kIdCx) == cl);
+  EXPECT(gpb_lo(Gp::kIdDx) == dl);
+
+  EXPECT(gpb_hi(Gp::kIdAx) == ah);
+  EXPECT(gpb_hi(Gp::kIdBx) == bh);
+  EXPECT(gpb_hi(Gp::kIdCx) == ch);
+  EXPECT(gpb_hi(Gp::kIdDx) == dh);
+
+  EXPECT(gpw(Gp::kIdAx) == ax);
+  EXPECT(gpw(Gp::kIdBx) == bx);
+  EXPECT(gpw(Gp::kIdCx) == cx);
+  EXPECT(gpw(Gp::kIdDx) == dx);
+
+  EXPECT(gpd(Gp::kIdAx) == eax);
+  EXPECT(gpd(Gp::kIdBx) == ebx);
+  EXPECT(gpd(Gp::kIdCx) == ecx);
+  EXPECT(gpd(Gp::kIdDx) == edx);
+
+  EXPECT(gpq(Gp::kIdAx) == rax);
+  EXPECT(gpq(Gp::kIdBx) == rbx);
+  EXPECT(gpq(Gp::kIdCx) == rcx);
+  EXPECT(gpq(Gp::kIdDx) == rdx);
+
+  EXPECT(gpb(Gp::kIdAx) != dl);
+  EXPECT(gpw(Gp::kIdBx) != cx);
+  EXPECT(gpd(Gp::kIdCx) != ebx);
+  EXPECT(gpq(Gp::kIdDx) != rax);
+
+  INFO("Checking if x86::reg(...) matches built-in IDs");
+  EXPECT(gpb(5) == bpl);
+  EXPECT(gpw(5) == bp);
+  EXPECT(gpd(5) == ebp);
+  EXPECT(gpq(5) == rbp);
+  EXPECT(st(5)  == st5);
+  EXPECT(mm(5)  == mm5);
+  EXPECT(k(5)   == k5);
+  EXPECT(cr(5)  == cr5);
+  EXPECT(dr(5)  == dr5);
+  EXPECT(xmm(5) == xmm5);
+  EXPECT(ymm(5) == ymm5);
+  EXPECT(zmm(5) == zmm5);
+
+  INFO("Checking x86::Gp register properties");
+  EXPECT(Gp().isReg() == true);
+  EXPECT(eax.isReg() == true);
+  EXPECT(eax.id() == 0);
+  EXPECT(eax.size() == 4);
+  EXPECT(eax.type() == Reg::kTypeGpd);
+  EXPECT(eax.group() == Reg::kGroupGp);
+
+  INFO("Checking x86::Xmm register properties");
+  EXPECT(Xmm().isReg() == true);
+  EXPECT(xmm4.isReg() == true);
+  EXPECT(xmm4.id() == 4);
+  EXPECT(xmm4.size() == 16);
+  EXPECT(xmm4.type() == Reg::kTypeXmm);
+  EXPECT(xmm4.group() == Reg::kGroupVec);
+  EXPECT(xmm4.isVec());
+
+  INFO("Checking x86::Ymm register properties");
+  EXPECT(Ymm().isReg() == true);
+  EXPECT(ymm5.isReg() == true);
+  EXPECT(ymm5.id() == 5);
+  EXPECT(ymm5.size() == 32);
+  EXPECT(ymm5.type() == Reg::kTypeYmm);
+  EXPECT(ymm5.group() == Reg::kGroupVec);
+  EXPECT(ymm5.isVec());
+
+  INFO("Checking x86::Zmm register properties");
+  EXPECT(Zmm().isReg() == true);
+  EXPECT(zmm6.isReg() == true);
+  EXPECT(zmm6.id() == 6);
+  EXPECT(zmm6.size() == 64);
+  EXPECT(zmm6.type() == Reg::kTypeZmm);
+  EXPECT(zmm6.group() == Reg::kGroupVec);
+  EXPECT(zmm6.isVec());
+
+  INFO("Checking x86::Vec register properties");
+  EXPECT(Vec().isReg() == true);
+  // Converts a VEC register to a type of the passed register, but keeps the ID.
+  EXPECT(xmm4.cloneAs(ymm10) == ymm4);
+  EXPECT(xmm4.cloneAs(zmm11) == zmm4);
+  EXPECT(ymm5.cloneAs(xmm12) == xmm5);
+  EXPECT(ymm5.cloneAs(zmm13) == zmm5);
+  EXPECT(zmm6.cloneAs(xmm14) == xmm6);
+  EXPECT(zmm6.cloneAs(ymm15) == ymm6);
+
+  EXPECT(xmm7.xmm() == xmm7);
+  EXPECT(xmm7.ymm() == ymm7);
+  EXPECT(xmm7.zmm() == zmm7);
+
+  EXPECT(ymm7.xmm() == xmm7);
+  EXPECT(ymm7.ymm() == ymm7);
+  EXPECT(ymm7.zmm() == zmm7);
+
+  EXPECT(zmm7.xmm() == xmm7);
+  EXPECT(zmm7.ymm() == ymm7);
+  EXPECT(zmm7.zmm() == zmm7);
+
+  INFO("Checking x86::FpMm register properties");
+  EXPECT(Mm().isReg() == true);
+  EXPECT(mm2.isReg() == true);
+  EXPECT(mm2.id() == 2);
+  EXPECT(mm2.size() == 8);
+  EXPECT(mm2.type() == Reg::kTypeMm);
+  EXPECT(mm2.group() == Reg::kGroupMm);
+
+  INFO("Checking x86::KReg register properties");
+  EXPECT(KReg().isReg() == true);
+  EXPECT(k3.isReg() == true);
+  EXPECT(k3.id() == 3);
+  EXPECT(k3.size() == 0);
+  EXPECT(k3.type() == Reg::kTypeKReg);
+  EXPECT(k3.group() == Reg::kGroupKReg);
+
+  INFO("Checking x86::St register properties");
+  EXPECT(St().isReg() == true);
+  EXPECT(st1.isReg() == true);
+  EXPECT(st1.id() == 1);
+  EXPECT(st1.size() == 10);
+  EXPECT(st1.type() == Reg::kTypeSt);
+  EXPECT(st1.group() == Reg::kGroupSt);
+
+  INFO("Checking if default constructed regs behave as expected");
+  EXPECT(Reg().isValid() == false);
+  EXPECT(Gp().isValid() == false);
+  EXPECT(Xmm().isValid() == false);
+  EXPECT(Ymm().isValid() == false);
+  EXPECT(Zmm().isValid() == false);
+  EXPECT(Mm().isValid() == false);
+  EXPECT(KReg().isValid() == false);
+  EXPECT(SReg().isValid() == false);
+  EXPECT(CReg().isValid() == false);
+  EXPECT(DReg().isValid() == false);
+  EXPECT(St().isValid() == false);
+  EXPECT(Bnd().isValid() == false);
+
+  INFO("Checking x86::Mem operand");
+  Mem m;
+  EXPECT(m == Mem(), "Two default constructed x86::Mem operands must be equal");
+
+  m = ptr(L);
+  EXPECT(m.hasBase() == true);
+  EXPECT(m.hasBaseReg() == false);
+  EXPECT(m.hasBaseLabel() == true);
+  EXPECT(m.hasOffset() == false);
+  EXPECT(m.isOffset64Bit() == false);
+  EXPECT(m.offset() == 0);
+  EXPECT(m.offsetLo32() == 0);
+
+  m = ptr(0x0123456789ABCDEFu);
+  EXPECT(m.hasBase() == false);
+  EXPECT(m.hasBaseReg() == false);
+  EXPECT(m.hasIndex() == false);
+  EXPECT(m.hasIndexReg() == false);
+  EXPECT(m.hasOffset() == true);
+  EXPECT(m.isOffset64Bit() == true);
+  EXPECT(m.offset() == int64_t(0x0123456789ABCDEFu));
+  EXPECT(m.offsetLo32() == int32_t(0x89ABCDEFu));
+  m.addOffset(1);
+  EXPECT(m.offset() == int64_t(0x0123456789ABCDF0u));
+
+  m = ptr(0x0123456789ABCDEFu, rdi, 4);
+  EXPECT(m.hasBase() == false);
+  EXPECT(m.hasBaseReg() == false);
+  EXPECT(m.hasIndex() == true);
+  EXPECT(m.hasIndexReg() == true);
+  EXPECT(m.indexType() == rdi.type());
+  EXPECT(m.indexId() == rdi.id());
+  EXPECT(m.hasOffset() == true);
+  EXPECT(m.isOffset64Bit() == true);
+  EXPECT(m.offset() == int64_t(0x0123456789ABCDEFu));
+  EXPECT(m.offsetLo32() == int32_t(0x89ABCDEFu));
+  m.resetIndex();
+  EXPECT(m.hasIndex() == false);
+  EXPECT(m.hasIndexReg() == false);
+
+  m = ptr(rax);
+  EXPECT(m.hasBase() == true);
+  EXPECT(m.hasBaseReg() == true);
+  EXPECT(m.baseType() == rax.type());
+  EXPECT(m.baseId() == rax.id());
+  EXPECT(m.hasIndex() == false);
+  EXPECT(m.hasIndexReg() == false);
+  EXPECT(m.indexType() == 0);
+  EXPECT(m.indexId() == 0);
+  EXPECT(m.hasOffset() == false);
+  EXPECT(m.isOffset64Bit() == false);
+  EXPECT(m.offset() == 0);
+  EXPECT(m.offsetLo32() == 0);
+  m.setIndex(rsi);
+  EXPECT(m.hasIndex() == true);
+  EXPECT(m.hasIndexReg() == true);
+  EXPECT(m.indexType() == rsi.type());
+  EXPECT(m.indexId() == rsi.id());
+}
+#endif
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86
diff --git a/client/asmjit/x86/x86operand.h b/client/asmjit/x86/x86operand.h
new file mode 100644
index 0000000..da988ce
--- /dev/null
+++ b/client/asmjit/x86/x86operand.h
@@ -0,0 +1,1105 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86OPERAND_H_INCLUDED
+#define ASMJIT_X86_X86OPERAND_H_INCLUDED
+
+#include "../core/arch.h"
+#include "../core/operand.h"
+#include "../core/type.h"
+#include "../x86/x86globals.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+#define ASMJIT_MEM_PTR(FUNC, SIZE)                                                    \
+  static constexpr Mem FUNC(const Gp& base, int32_t offset = 0) noexcept {            \
+    return Mem(base, offset, SIZE);                                                   \
+  }                                                                                   \
+  static constexpr Mem FUNC(const Gp& base, const Gp& index, uint32_t shift = 0, int32_t offset = 0) noexcept { \
+    return Mem(base, index, shift, offset, SIZE);                                     \
+  }                                                                                   \
+  static constexpr Mem FUNC(const Gp& base, const Vec& index, uint32_t shift = 0, int32_t offset = 0) noexcept { \
+    return Mem(base, index, shift, offset, SIZE);                                     \
+  }                                                                                   \
+  static constexpr Mem FUNC(const Label& base, int32_t offset = 0) noexcept {         \
+    return Mem(base, offset, SIZE);                                                   \
+  }                                                                                   \
+  static constexpr Mem FUNC(const Label& base, const Gp& index, uint32_t shift = 0, int32_t offset = 0) noexcept { \
+    return Mem(base, index, shift, offset, SIZE);                                     \
+  }                                                                                   \
+  static constexpr Mem FUNC(const Rip& rip_, int32_t offset = 0) noexcept {           \
+    return Mem(rip_, offset, SIZE);                                                   \
+  }                                                                                   \
+  static constexpr Mem FUNC(uint64_t base) noexcept {                                 \
+    return Mem(base, SIZE);                                                           \
+  }                                                                                   \
+  static constexpr Mem FUNC(uint64_t base, const Gp& index, uint32_t shift = 0) noexcept { \
+    return Mem(base, index, shift, SIZE);                                             \
+  }                                                                                   \
+  static constexpr Mem FUNC(uint64_t base, const Vec& index, uint32_t shift = 0) noexcept { \
+    return Mem(base, index, shift, SIZE);                                             \
+  }                                                                                   \
+                                                                                      \
+  static constexpr Mem FUNC##_abs(uint64_t base) noexcept {                           \
+    return Mem(base, SIZE, BaseMem::kSignatureMemAbs);                                \
+  }                                                                                   \
+  static constexpr Mem FUNC##_abs(uint64_t base, const Gp& index, uint32_t shift = 0) noexcept { \
+    return Mem(base, index, shift, SIZE, BaseMem::kSignatureMemAbs);                  \
+  }                                                                                   \
+  static constexpr Mem FUNC##_abs(uint64_t base, const Vec& index, uint32_t shift = 0) noexcept { \
+    return Mem(base, index, shift, SIZE, BaseMem::kSignatureMemAbs);                  \
+  }                                                                                   \
+                                                                                      \
+  static constexpr Mem FUNC##_rel(uint64_t base) noexcept {                           \
+    return Mem(base, SIZE, BaseMem::kSignatureMemRel);                                \
+  }                                                                                   \
+  static constexpr Mem FUNC##_rel(uint64_t base, const Gp& index, uint32_t shift = 0) noexcept { \
+    return Mem(base, index, shift, SIZE, BaseMem::kSignatureMemRel);                  \
+  }                                                                                   \
+  static constexpr Mem FUNC##_rel(uint64_t base, const Vec& index, uint32_t shift = 0) noexcept { \
+    return Mem(base, index, shift, SIZE, BaseMem::kSignatureMemRel);                  \
+  }
+
+//! \addtogroup asmjit_x86
+//! \{
+
+// ============================================================================
+// [Forward Declarations]
+// ============================================================================
+
+class Reg;
+class Mem;
+
+class Gp;
+class Gpb;
+class GpbLo;
+class GpbHi;
+class Gpw;
+class Gpd;
+class Gpq;
+class Vec;
+class Xmm;
+class Ymm;
+class Zmm;
+class Mm;
+class KReg;
+class SReg;
+class CReg;
+class DReg;
+class St;
+class Bnd;
+class Tmm;
+class Rip;
+
+// ============================================================================
+// [asmjit::x86::Reg]
+// ============================================================================
+
+//! Register traits (X86).
+//!
+//! Register traits contains information about a particular register type. It's
+//! used by asmjit to setup register information on-the-fly and to populate
+//! tables that contain register information (this way it's possible to change
+//! register types and groups without having to reorder these tables).
+template<uint32_t REG_TYPE>
+struct RegTraits : public BaseRegTraits {};
+
+//! \cond
+// <--------------------+-----+-------------------------+------------------------+---+---+----------------+
+//                      | Reg |        Reg-Type         |        Reg-Group       |Sz |Cnt|     TypeId     |
+// <--------------------+-----+-------------------------+------------------------+---+---+----------------+
+ASMJIT_DEFINE_REG_TRAITS(GpbLo, BaseReg::kTypeGp8Lo     , BaseReg::kGroupGp      , 1 , 16, Type::kIdI8    );
+ASMJIT_DEFINE_REG_TRAITS(GpbHi, BaseReg::kTypeGp8Hi     , BaseReg::kGroupGp      , 1 , 4 , Type::kIdI8    );
+ASMJIT_DEFINE_REG_TRAITS(Gpw  , BaseReg::kTypeGp16      , BaseReg::kGroupGp      , 2 , 16, Type::kIdI16   );
+ASMJIT_DEFINE_REG_TRAITS(Gpd  , BaseReg::kTypeGp32      , BaseReg::kGroupGp      , 4 , 16, Type::kIdI32   );
+ASMJIT_DEFINE_REG_TRAITS(Gpq  , BaseReg::kTypeGp64      , BaseReg::kGroupGp      , 8 , 16, Type::kIdI64   );
+ASMJIT_DEFINE_REG_TRAITS(Xmm  , BaseReg::kTypeVec128    , BaseReg::kGroupVec     , 16, 32, Type::kIdI32x4 );
+ASMJIT_DEFINE_REG_TRAITS(Ymm  , BaseReg::kTypeVec256    , BaseReg::kGroupVec     , 32, 32, Type::kIdI32x8 );
+ASMJIT_DEFINE_REG_TRAITS(Zmm  , BaseReg::kTypeVec512    , BaseReg::kGroupVec     , 64, 32, Type::kIdI32x16);
+ASMJIT_DEFINE_REG_TRAITS(Mm   , BaseReg::kTypeOther0    , BaseReg::kGroupOther0  , 8 , 8 , Type::kIdMmx64 );
+ASMJIT_DEFINE_REG_TRAITS(KReg , BaseReg::kTypeOther1    , BaseReg::kGroupOther1  , 0 , 8 , Type::kIdVoid  );
+ASMJIT_DEFINE_REG_TRAITS(SReg , BaseReg::kTypeCustom + 0, BaseReg::kGroupVirt + 0, 2 , 7 , Type::kIdVoid  );
+ASMJIT_DEFINE_REG_TRAITS(CReg , BaseReg::kTypeCustom + 1, BaseReg::kGroupVirt + 1, 0 , 16, Type::kIdVoid  );
+ASMJIT_DEFINE_REG_TRAITS(DReg , BaseReg::kTypeCustom + 2, BaseReg::kGroupVirt + 2, 0 , 16, Type::kIdVoid  );
+ASMJIT_DEFINE_REG_TRAITS(St   , BaseReg::kTypeCustom + 3, BaseReg::kGroupVirt + 3, 10, 8 , Type::kIdF80   );
+ASMJIT_DEFINE_REG_TRAITS(Bnd  , BaseReg::kTypeCustom + 4, BaseReg::kGroupVirt + 4, 16, 4 , Type::kIdVoid  );
+ASMJIT_DEFINE_REG_TRAITS(Tmm  , BaseReg::kTypeCustom + 5, BaseReg::kGroupVirt + 5, 0 , 8 , Type::kIdVoid  );
+ASMJIT_DEFINE_REG_TRAITS(Rip  , BaseReg::kTypeIP        , BaseReg::kGroupVirt + 6, 0 , 1 , Type::kIdVoid  );
+//! \endcond
+
+//! Register (X86).
+class Reg : public BaseReg {
+public:
+  ASMJIT_DEFINE_ABSTRACT_REG(Reg, BaseReg)
+
+  //! Register type.
+  enum RegType : uint32_t {
+    //! No register type or invalid register.
+    kTypeNone = BaseReg::kTypeNone,
+
+    //! Low GPB register (AL, BL, CL, DL, ...).
+    kTypeGpbLo = BaseReg::kTypeGp8Lo,
+    //! High GPB register (AH, BH, CH, DH only).
+    kTypeGpbHi = BaseReg::kTypeGp8Hi,
+    //! GPW register.
+    kTypeGpw = BaseReg::kTypeGp16,
+    //! GPD register.
+    kTypeGpd = BaseReg::kTypeGp32,
+    //! GPQ register (64-bit).
+    kTypeGpq = BaseReg::kTypeGp64,
+    //! XMM register (SSE+).
+    kTypeXmm = BaseReg::kTypeVec128,
+    //! YMM register (AVX+).
+    kTypeYmm = BaseReg::kTypeVec256,
+    //! ZMM register (AVX512+).
+    kTypeZmm = BaseReg::kTypeVec512,
+    //! MMX register.
+    kTypeMm = BaseReg::kTypeOther0,
+    //! K register (AVX512+).
+    kTypeKReg = BaseReg::kTypeOther1,
+    //! Instruction pointer (EIP, RIP).
+    kTypeRip = BaseReg::kTypeIP,
+    //! Segment register (None, ES, CS, SS, DS, FS, GS).
+    kTypeSReg = BaseReg::kTypeCustom + 0,
+    //! Control register (CR).
+    kTypeCReg = BaseReg::kTypeCustom + 1,
+    //! Debug register (DR).
+    kTypeDReg = BaseReg::kTypeCustom + 2,
+    //! FPU (x87) register.
+    kTypeSt = BaseReg::kTypeCustom + 3,
+    //! Bound register (BND).
+    kTypeBnd = BaseReg::kTypeCustom + 4,
+    //! TMM register (AMX_TILE)
+    kTypeTmm = BaseReg::kTypeCustom + 5,
+
+    //! Count of register types.
+    kTypeCount = BaseReg::kTypeCustom + 6
+  };
+
+  //! Register group.
+  enum RegGroup : uint32_t {
+    //! GP register group or none (universal).
+    kGroupGp   = BaseReg::kGroupGp,
+    //! XMM|YMM|ZMM register group (universal).
+    kGroupVec  = BaseReg::kGroupVec,
+    //! MMX register group (legacy).
+    kGroupMm   = BaseReg::kGroupOther0,
+    //! K register group.
+    kGroupKReg = BaseReg::kGroupOther1,
+
+    // These are not managed by Compiler nor used by Func-API:
+
+    //! Segment register group.
+    kGroupSReg = BaseReg::kGroupVirt+0,
+    //! Control register group.
+    kGroupCReg = BaseReg::kGroupVirt+1,
+    //! Debug register group.
+    kGroupDReg = BaseReg::kGroupVirt+2,
+    //! FPU register group.
+    kGroupSt   = BaseReg::kGroupVirt+3,
+    //! Bound register group.
+    kGroupBnd  = BaseReg::kGroupVirt+4,
+    //! TMM register group.
+    kGroupTmm  = BaseReg::kGroupVirt+5,
+    //! Instrucion pointer (IP).
+    kGroupRip  = BaseReg::kGroupVirt+6,
+
+    //! Count of all register groups.
+    kGroupCount
+  };
+
+  //! Tests whether the register is a GPB register (8-bit).
+  constexpr bool isGpb() const noexcept { return size() == 1; }
+  //! Tests whether the register is a low GPB register (8-bit).
+  constexpr bool isGpbLo() const noexcept { return hasSignature(RegTraits<kTypeGpbLo>::kSignature); }
+  //! Tests whether the register is a high GPB register (8-bit).
+  constexpr bool isGpbHi() const noexcept { return hasSignature(RegTraits<kTypeGpbHi>::kSignature); }
+  //! Tests whether the register is a GPW register (16-bit).
+  constexpr bool isGpw() const noexcept { return hasSignature(RegTraits<kTypeGpw>::kSignature); }
+  //! Tests whether the register is a GPD register (32-bit).
+  constexpr bool isGpd() const noexcept { return hasSignature(RegTraits<kTypeGpd>::kSignature); }
+  //! Tests whether the register is a GPQ register (64-bit).
+  constexpr bool isGpq() const noexcept { return hasSignature(RegTraits<kTypeGpq>::kSignature); }
+  //! Tests whether the register is an XMM register (128-bit).
+  constexpr bool isXmm() const noexcept { return hasSignature(RegTraits<kTypeXmm>::kSignature); }
+  //! Tests whether the register is a YMM register (256-bit).
+  constexpr bool isYmm() const noexcept { return hasSignature(RegTraits<kTypeYmm>::kSignature); }
+  //! Tests whether the register is a ZMM register (512-bit).
+  constexpr bool isZmm() const noexcept { return hasSignature(RegTraits<kTypeZmm>::kSignature); }
+  //! Tests whether the register is an MMX register (64-bit).
+  constexpr bool isMm() const noexcept { return hasSignature(RegTraits<kTypeMm>::kSignature); }
+  //! Tests whether the register is a K register (64-bit).
+  constexpr bool isKReg() const noexcept { return hasSignature(RegTraits<kTypeKReg>::kSignature); }
+  //! Tests whether the register is a segment register.
+  constexpr bool isSReg() const noexcept { return hasSignature(RegTraits<kTypeSReg>::kSignature); }
+  //! Tests whether the register is a control register.
+  constexpr bool isCReg() const noexcept { return hasSignature(RegTraits<kTypeCReg>::kSignature); }
+  //! Tests whether the register is a debug register.
+  constexpr bool isDReg() const noexcept { return hasSignature(RegTraits<kTypeDReg>::kSignature); }
+  //! Tests whether the register is an FPU register (80-bit).
+  constexpr bool isSt() const noexcept { return hasSignature(RegTraits<kTypeSt>::kSignature); }
+  //! Tests whether the register is a bound register.
+  constexpr bool isBnd() const noexcept { return hasSignature(RegTraits<kTypeBnd>::kSignature); }
+  //! Tests whether the register is a TMM register.
+  constexpr bool isTmm() const noexcept { return hasSignature(RegTraits<kTypeTmm>::kSignature); }
+  //! Tests whether the register is RIP.
+  constexpr bool isRip() const noexcept { return hasSignature(RegTraits<kTypeRip>::kSignature); }
+
+  template<uint32_t REG_TYPE>
+  inline void setRegT(uint32_t rId) noexcept {
+    setSignature(RegTraits<REG_TYPE>::kSignature);
+    setId(rId);
+  }
+
+  inline void setTypeAndId(uint32_t rType, uint32_t rId) noexcept {
+    ASMJIT_ASSERT(rType < kTypeCount);
+    setSignature(signatureOf(rType));
+    setId(rId);
+  }
+
+  static inline uint32_t groupOf(uint32_t rType) noexcept;
+  template<uint32_t REG_TYPE>
+  static inline uint32_t groupOfT() noexcept { return RegTraits<REG_TYPE>::kGroup; }
+
+  static inline uint32_t typeIdOf(uint32_t rType) noexcept;
+  template<uint32_t REG_TYPE>
+  static inline uint32_t typeIdOfT() noexcept { return RegTraits<REG_TYPE>::kTypeId; }
+
+  static inline uint32_t signatureOf(uint32_t rType) noexcept;
+  template<uint32_t REG_TYPE>
+  static inline uint32_t signatureOfT() noexcept { return RegTraits<REG_TYPE>::kSignature; }
+
+  static inline uint32_t signatureOfVecByType(uint32_t typeId) noexcept {
+    return typeId <= Type::_kIdVec128End ? RegTraits<kTypeXmm>::kSignature :
+           typeId <= Type::_kIdVec256End ? RegTraits<kTypeYmm>::kSignature : RegTraits<kTypeZmm>::kSignature;
+  }
+
+  static inline uint32_t signatureOfVecBySize(uint32_t size) noexcept {
+    return size <= 16 ? RegTraits<kTypeXmm>::kSignature :
+           size <= 32 ? RegTraits<kTypeYmm>::kSignature : RegTraits<kTypeZmm>::kSignature;
+  }
+
+  //! Tests whether the `op` operand is either a low or high 8-bit GPB register.
+  static inline bool isGpb(const Operand_& op) noexcept {
+    // Check operand type, register group, and size. Not interested in register type.
+    const uint32_t kSgn = (Operand::kOpReg << kSignatureOpShift  ) |
+                          (1               << kSignatureSizeShift) ;
+    return (op.signature() & (kSignatureOpMask | kSignatureSizeMask)) == kSgn;
+  }
+
+  static inline bool isGpbLo(const Operand_& op) noexcept { return op.as<Reg>().isGpbLo(); }
+  static inline bool isGpbHi(const Operand_& op) noexcept { return op.as<Reg>().isGpbHi(); }
+  static inline bool isGpw(const Operand_& op) noexcept { return op.as<Reg>().isGpw(); }
+  static inline bool isGpd(const Operand_& op) noexcept { return op.as<Reg>().isGpd(); }
+  static inline bool isGpq(const Operand_& op) noexcept { return op.as<Reg>().isGpq(); }
+  static inline bool isXmm(const Operand_& op) noexcept { return op.as<Reg>().isXmm(); }
+  static inline bool isYmm(const Operand_& op) noexcept { return op.as<Reg>().isYmm(); }
+  static inline bool isZmm(const Operand_& op) noexcept { return op.as<Reg>().isZmm(); }
+  static inline bool isMm(const Operand_& op) noexcept { return op.as<Reg>().isMm(); }
+  static inline bool isKReg(const Operand_& op) noexcept { return op.as<Reg>().isKReg(); }
+  static inline bool isSReg(const Operand_& op) noexcept { return op.as<Reg>().isSReg(); }
+  static inline bool isCReg(const Operand_& op) noexcept { return op.as<Reg>().isCReg(); }
+  static inline bool isDReg(const Operand_& op) noexcept { return op.as<Reg>().isDReg(); }
+  static inline bool isSt(const Operand_& op) noexcept { return op.as<Reg>().isSt(); }
+  static inline bool isBnd(const Operand_& op) noexcept { return op.as<Reg>().isBnd(); }
+  static inline bool isTmm(const Operand_& op) noexcept { return op.as<Reg>().isTmm(); }
+  static inline bool isRip(const Operand_& op) noexcept { return op.as<Reg>().isRip(); }
+
+  static inline bool isGpb(const Operand_& op, uint32_t rId) noexcept { return isGpb(op) & (op.id() == rId); }
+  static inline bool isGpbLo(const Operand_& op, uint32_t rId) noexcept { return isGpbLo(op) & (op.id() == rId); }
+  static inline bool isGpbHi(const Operand_& op, uint32_t rId) noexcept { return isGpbHi(op) & (op.id() == rId); }
+  static inline bool isGpw(const Operand_& op, uint32_t rId) noexcept { return isGpw(op) & (op.id() == rId); }
+  static inline bool isGpd(const Operand_& op, uint32_t rId) noexcept { return isGpd(op) & (op.id() == rId); }
+  static inline bool isGpq(const Operand_& op, uint32_t rId) noexcept { return isGpq(op) & (op.id() == rId); }
+  static inline bool isXmm(const Operand_& op, uint32_t rId) noexcept { return isXmm(op) & (op.id() == rId); }
+  static inline bool isYmm(const Operand_& op, uint32_t rId) noexcept { return isYmm(op) & (op.id() == rId); }
+  static inline bool isZmm(const Operand_& op, uint32_t rId) noexcept { return isZmm(op) & (op.id() == rId); }
+  static inline bool isMm(const Operand_& op, uint32_t rId) noexcept { return isMm(op) & (op.id() == rId); }
+  static inline bool isKReg(const Operand_& op, uint32_t rId) noexcept { return isKReg(op) & (op.id() == rId); }
+  static inline bool isSReg(const Operand_& op, uint32_t rId) noexcept { return isSReg(op) & (op.id() == rId); }
+  static inline bool isCReg(const Operand_& op, uint32_t rId) noexcept { return isCReg(op) & (op.id() == rId); }
+  static inline bool isDReg(const Operand_& op, uint32_t rId) noexcept { return isDReg(op) & (op.id() == rId); }
+  static inline bool isSt(const Operand_& op, uint32_t rId) noexcept { return isSt(op) & (op.id() == rId); }
+  static inline bool isBnd(const Operand_& op, uint32_t rId) noexcept { return isBnd(op) & (op.id() == rId); }
+  static inline bool isTmm(const Operand_& op, uint32_t rId) noexcept { return isTmm(op) & (op.id() == rId); }
+  static inline bool isRip(const Operand_& op, uint32_t rId) noexcept { return isRip(op) & (op.id() == rId); }
+};
+
+//! General purpose register (X86).
+class Gp : public Reg {
+public:
+  ASMJIT_DEFINE_ABSTRACT_REG(Gp, Reg)
+
+  //! Physical id (X86).
+  //!
+  //! \note Register indexes have been reduced to only support general purpose
+  //! registers. There is no need to have enumerations with number suffix that
+  //! expands to the exactly same value as the suffix value itself.
+  enum Id : uint32_t {
+    kIdAx  = 0,  //!< Physical id of AL|AH|AX|EAX|RAX registers.
+    kIdCx  = 1,  //!< Physical id of CL|CH|CX|ECX|RCX registers.
+    kIdDx  = 2,  //!< Physical id of DL|DH|DX|EDX|RDX registers.
+    kIdBx  = 3,  //!< Physical id of BL|BH|BX|EBX|RBX registers.
+    kIdSp  = 4,  //!< Physical id of SPL|SP|ESP|RSP registers.
+    kIdBp  = 5,  //!< Physical id of BPL|BP|EBP|RBP registers.
+    kIdSi  = 6,  //!< Physical id of SIL|SI|ESI|RSI registers.
+    kIdDi  = 7,  //!< Physical id of DIL|DI|EDI|RDI registers.
+    kIdR8  = 8,  //!< Physical id of R8B|R8W|R8D|R8 registers (64-bit only).
+    kIdR9  = 9,  //!< Physical id of R9B|R9W|R9D|R9 registers (64-bit only).
+    kIdR10 = 10, //!< Physical id of R10B|R10W|R10D|R10 registers (64-bit only).
+    kIdR11 = 11, //!< Physical id of R11B|R11W|R11D|R11 registers (64-bit only).
+    kIdR12 = 12, //!< Physical id of R12B|R12W|R12D|R12 registers (64-bit only).
+    kIdR13 = 13, //!< Physical id of R13B|R13W|R13D|R13 registers (64-bit only).
+    kIdR14 = 14, //!< Physical id of R14B|R14W|R14D|R14 registers (64-bit only).
+    kIdR15 = 15  //!< Physical id of R15B|R15W|R15D|R15 registers (64-bit only).
+  };
+
+  //! Casts this register to 8-bit (LO) part.
+  inline GpbLo r8() const noexcept;
+  //! Casts this register to 8-bit (LO) part.
+  inline GpbLo r8Lo() const noexcept;
+  //! Casts this register to 8-bit (HI) part.
+  inline GpbHi r8Hi() const noexcept;
+  //! Casts this register to 16-bit.
+  inline Gpw r16() const noexcept;
+  //! Casts this register to 32-bit.
+  inline Gpd r32() const noexcept;
+  //! Casts this register to 64-bit.
+  inline Gpq r64() const noexcept;
+};
+
+//! Vector register (XMM|YMM|ZMM) (X86).
+class Vec : public Reg {
+  ASMJIT_DEFINE_ABSTRACT_REG(Vec, Reg)
+
+  //! Casts this register to XMM (clone).
+  inline Xmm xmm() const noexcept;
+  //! Casts this register to YMM.
+  inline Ymm ymm() const noexcept;
+  //! Casts this register to ZMM.
+  inline Zmm zmm() const noexcept;
+
+  //! Casts this register to a register that has half the size (or XMM if it's already XMM).
+  inline Vec half() const noexcept {
+    return Vec(type() == kTypeZmm ? signatureOf(kTypeYmm) : signatureOf(kTypeXmm), id());
+  }
+};
+
+//! Segment register (X86).
+class SReg : public Reg {
+  ASMJIT_DEFINE_FINAL_REG(SReg, Reg, RegTraits<kTypeSReg>)
+
+  //! X86 segment id.
+  enum Id : uint32_t {
+    //! No segment (default).
+    kIdNone = 0,
+    //! ES segment.
+    kIdEs = 1,
+    //! CS segment.
+    kIdCs = 2,
+    //! SS segment.
+    kIdSs = 3,
+    //! DS segment.
+    kIdDs = 4,
+    //! FS segment.
+    kIdFs = 5,
+    //! GS segment.
+    kIdGs = 6,
+
+    //! Count of X86 segment registers supported by AsmJit.
+    //!
+    //! \note X86 architecture has 6 segment registers - ES, CS, SS, DS, FS, GS.
+    //! X64 architecture lowers them down to just FS and GS. AsmJit supports 7
+    //! segment registers - all addressable in both X86 and X64 modes and one
+    //! extra called `SReg::kIdNone`, which is AsmJit specific and means that
+    //! there is no segment register specified.
+    kIdCount = 7
+  };
+};
+
+//! GPB low or high register (X86).
+class Gpb : public Gp { ASMJIT_DEFINE_ABSTRACT_REG(Gpb, Gp) };
+//! GPB low register (X86).
+class GpbLo : public Gpb { ASMJIT_DEFINE_FINAL_REG(GpbLo, Gpb, RegTraits<kTypeGpbLo>) };
+//! GPB high register (X86).
+class GpbHi : public Gpb { ASMJIT_DEFINE_FINAL_REG(GpbHi, Gpb, RegTraits<kTypeGpbHi>) };
+//! GPW register (X86).
+class Gpw : public Gp { ASMJIT_DEFINE_FINAL_REG(Gpw, Gp, RegTraits<kTypeGpw>) };
+//! GPD register (X86).
+class Gpd : public Gp { ASMJIT_DEFINE_FINAL_REG(Gpd, Gp, RegTraits<kTypeGpd>) };
+//! GPQ register (X86_64).
+class Gpq : public Gp { ASMJIT_DEFINE_FINAL_REG(Gpq, Gp, RegTraits<kTypeGpq>) };
+
+//! 128-bit XMM register (SSE+).
+class Xmm : public Vec {
+  ASMJIT_DEFINE_FINAL_REG(Xmm, Vec, RegTraits<kTypeXmm>)
+  //! Casts this register to a register that has half the size (XMM).
+  inline Xmm half() const noexcept { return Xmm(id()); }
+};
+
+//! 256-bit YMM register (AVX+).
+class Ymm : public Vec {
+  ASMJIT_DEFINE_FINAL_REG(Ymm, Vec, RegTraits<kTypeYmm>)
+  //! Casts this register to a register that has half the size (XMM).
+  inline Xmm half() const noexcept { return Xmm(id()); }
+};
+
+//! 512-bit ZMM register (AVX512+).
+class Zmm : public Vec {
+  ASMJIT_DEFINE_FINAL_REG(Zmm, Vec, RegTraits<kTypeZmm>)
+  //! Casts this register to a register that has half the size (YMM).
+  inline Ymm half() const noexcept { return Ymm(id()); }
+};
+
+//! 64-bit MMX register (MMX+).
+class Mm : public Reg { ASMJIT_DEFINE_FINAL_REG(Mm, Reg, RegTraits<kTypeMm>) };
+//! 64-bit K register (AVX512+).
+class KReg : public Reg { ASMJIT_DEFINE_FINAL_REG(KReg, Reg, RegTraits<kTypeKReg>) };
+//! 32-bit or 64-bit control register (X86).
+class CReg : public Reg { ASMJIT_DEFINE_FINAL_REG(CReg, Reg, RegTraits<kTypeCReg>) };
+//! 32-bit or 64-bit debug register (X86).
+class DReg : public Reg { ASMJIT_DEFINE_FINAL_REG(DReg, Reg, RegTraits<kTypeDReg>) };
+//! 80-bit FPU register (X86).
+class St : public Reg { ASMJIT_DEFINE_FINAL_REG(St, Reg, RegTraits<kTypeSt>) };
+//! 128-bit BND register (BND+).
+class Bnd : public Reg { ASMJIT_DEFINE_FINAL_REG(Bnd, Reg, RegTraits<kTypeBnd>) };
+//! 8192-bit TMM register (AMX).
+class Tmm : public Reg { ASMJIT_DEFINE_FINAL_REG(Tmm, Reg, RegTraits<kTypeTmm>) };
+//! RIP register (X86).
+class Rip : public Reg { ASMJIT_DEFINE_FINAL_REG(Rip, Reg, RegTraits<kTypeRip>) };
+
+//! \cond
+inline GpbLo Gp::r8() const noexcept { return GpbLo(id()); }
+inline GpbLo Gp::r8Lo() const noexcept { return GpbLo(id()); }
+inline GpbHi Gp::r8Hi() const noexcept { return GpbHi(id()); }
+inline Gpw Gp::r16() const noexcept { return Gpw(id()); }
+inline Gpd Gp::r32() const noexcept { return Gpd(id()); }
+inline Gpq Gp::r64() const noexcept { return Gpq(id()); }
+inline Xmm Vec::xmm() const noexcept { return Xmm(id()); }
+inline Ymm Vec::ymm() const noexcept { return Ymm(id()); }
+inline Zmm Vec::zmm() const noexcept { return Zmm(id()); }
+//! \endcond
+
+//! \namespace asmjit::x86::regs
+//!
+//! Registers provided by X86 and X64 ISAs are in both `asmjit::x86` and
+//! `asmjit::x86::regs` namespaces so they can be included with using directive.
+//! For example `using namespace asmjit::x86::regs` would include all registers,
+//! but not other X86-specific API, whereas `using namespace asmjit::x86` would
+//! include everything X86-specific.
+#ifndef _DOXYGEN
+namespace regs {
+#endif
+
+//! Creates an 8-bit low GPB register operand.
+static constexpr GpbLo gpb(uint32_t rId) noexcept { return GpbLo(rId); }
+//! Creates an 8-bit low GPB register operand.
+static constexpr GpbLo gpb_lo(uint32_t rId) noexcept { return GpbLo(rId); }
+//! Creates an 8-bit high GPB register operand.
+static constexpr GpbHi gpb_hi(uint32_t rId) noexcept { return GpbHi(rId); }
+//! Creates a 16-bit GPW register operand.
+static constexpr Gpw gpw(uint32_t rId) noexcept { return Gpw(rId); }
+//! Creates a 32-bit GPD register operand.
+static constexpr Gpd gpd(uint32_t rId) noexcept { return Gpd(rId); }
+//! Creates a 64-bit GPQ register operand (64-bit).
+static constexpr Gpq gpq(uint32_t rId) noexcept { return Gpq(rId); }
+//! Creates a 128-bit XMM register operand.
+static constexpr Xmm xmm(uint32_t rId) noexcept { return Xmm(rId); }
+//! Creates a 256-bit YMM register operand.
+static constexpr Ymm ymm(uint32_t rId) noexcept { return Ymm(rId); }
+//! Creates a 512-bit ZMM register operand.
+static constexpr Zmm zmm(uint32_t rId) noexcept { return Zmm(rId); }
+//! Creates a 64-bit Mm register operand.
+static constexpr Mm mm(uint32_t rId) noexcept { return Mm(rId); }
+//! Creates a 64-bit K register operand.
+static constexpr KReg k(uint32_t rId) noexcept { return KReg(rId); }
+//! Creates a 32-bit or 64-bit control register operand.
+static constexpr CReg cr(uint32_t rId) noexcept { return CReg(rId); }
+//! Creates a 32-bit or 64-bit debug register operand.
+static constexpr DReg dr(uint32_t rId) noexcept { return DReg(rId); }
+//! Creates an 80-bit st register operand.
+static constexpr St st(uint32_t rId) noexcept { return St(rId); }
+//! Creates a 128-bit bound register operand.
+static constexpr Bnd bnd(uint32_t rId) noexcept { return Bnd(rId); }
+//! Creates a TMM register operand.
+static constexpr Tmm tmm(uint32_t rId) noexcept { return Tmm(rId); }
+
+static constexpr Gp al = Gp(GpbLo::kSignature, Gp::kIdAx);
+static constexpr Gp bl = Gp(GpbLo::kSignature, Gp::kIdBx);
+static constexpr Gp cl = Gp(GpbLo::kSignature, Gp::kIdCx);
+static constexpr Gp dl = Gp(GpbLo::kSignature, Gp::kIdDx);
+static constexpr Gp spl = Gp(GpbLo::kSignature, Gp::kIdSp);
+static constexpr Gp bpl = Gp(GpbLo::kSignature, Gp::kIdBp);
+static constexpr Gp sil = Gp(GpbLo::kSignature, Gp::kIdSi);
+static constexpr Gp dil = Gp(GpbLo::kSignature, Gp::kIdDi);
+static constexpr Gp r8b = Gp(GpbLo::kSignature, Gp::kIdR8);
+static constexpr Gp r9b = Gp(GpbLo::kSignature, Gp::kIdR9);
+static constexpr Gp r10b = Gp(GpbLo::kSignature, Gp::kIdR10);
+static constexpr Gp r11b = Gp(GpbLo::kSignature, Gp::kIdR11);
+static constexpr Gp r12b = Gp(GpbLo::kSignature, Gp::kIdR12);
+static constexpr Gp r13b = Gp(GpbLo::kSignature, Gp::kIdR13);
+static constexpr Gp r14b = Gp(GpbLo::kSignature, Gp::kIdR14);
+static constexpr Gp r15b = Gp(GpbLo::kSignature, Gp::kIdR15);
+
+static constexpr Gp ah = Gp(GpbHi::kSignature, Gp::kIdAx);
+static constexpr Gp bh = Gp(GpbHi::kSignature, Gp::kIdBx);
+static constexpr Gp ch = Gp(GpbHi::kSignature, Gp::kIdCx);
+static constexpr Gp dh = Gp(GpbHi::kSignature, Gp::kIdDx);
+
+static constexpr Gp ax = Gp(Gpw::kSignature, Gp::kIdAx);
+static constexpr Gp bx = Gp(Gpw::kSignature, Gp::kIdBx);
+static constexpr Gp cx = Gp(Gpw::kSignature, Gp::kIdCx);
+static constexpr Gp dx = Gp(Gpw::kSignature, Gp::kIdDx);
+static constexpr Gp sp = Gp(Gpw::kSignature, Gp::kIdSp);
+static constexpr Gp bp = Gp(Gpw::kSignature, Gp::kIdBp);
+static constexpr Gp si = Gp(Gpw::kSignature, Gp::kIdSi);
+static constexpr Gp di = Gp(Gpw::kSignature, Gp::kIdDi);
+static constexpr Gp r8w = Gp(Gpw::kSignature, Gp::kIdR8);
+static constexpr Gp r9w = Gp(Gpw::kSignature, Gp::kIdR9);
+static constexpr Gp r10w = Gp(Gpw::kSignature, Gp::kIdR10);
+static constexpr Gp r11w = Gp(Gpw::kSignature, Gp::kIdR11);
+static constexpr Gp r12w = Gp(Gpw::kSignature, Gp::kIdR12);
+static constexpr Gp r13w = Gp(Gpw::kSignature, Gp::kIdR13);
+static constexpr Gp r14w = Gp(Gpw::kSignature, Gp::kIdR14);
+static constexpr Gp r15w = Gp(Gpw::kSignature, Gp::kIdR15);
+
+static constexpr Gp eax = Gp(Gpd::kSignature, Gp::kIdAx);
+static constexpr Gp ebx = Gp(Gpd::kSignature, Gp::kIdBx);
+static constexpr Gp ecx = Gp(Gpd::kSignature, Gp::kIdCx);
+static constexpr Gp edx = Gp(Gpd::kSignature, Gp::kIdDx);
+static constexpr Gp esp = Gp(Gpd::kSignature, Gp::kIdSp);
+static constexpr Gp ebp = Gp(Gpd::kSignature, Gp::kIdBp);
+static constexpr Gp esi = Gp(Gpd::kSignature, Gp::kIdSi);
+static constexpr Gp edi = Gp(Gpd::kSignature, Gp::kIdDi);
+static constexpr Gp r8d = Gp(Gpd::kSignature, Gp::kIdR8);
+static constexpr Gp r9d = Gp(Gpd::kSignature, Gp::kIdR9);
+static constexpr Gp r10d = Gp(Gpd::kSignature, Gp::kIdR10);
+static constexpr Gp r11d = Gp(Gpd::kSignature, Gp::kIdR11);
+static constexpr Gp r12d = Gp(Gpd::kSignature, Gp::kIdR12);
+static constexpr Gp r13d = Gp(Gpd::kSignature, Gp::kIdR13);
+static constexpr Gp r14d = Gp(Gpd::kSignature, Gp::kIdR14);
+static constexpr Gp r15d = Gp(Gpd::kSignature, Gp::kIdR15);
+
+static constexpr Gp rax = Gp(Gpq::kSignature, Gp::kIdAx);
+static constexpr Gp rbx = Gp(Gpq::kSignature, Gp::kIdBx);
+static constexpr Gp rcx = Gp(Gpq::kSignature, Gp::kIdCx);
+static constexpr Gp rdx = Gp(Gpq::kSignature, Gp::kIdDx);
+static constexpr Gp rsp = Gp(Gpq::kSignature, Gp::kIdSp);
+static constexpr Gp rbp = Gp(Gpq::kSignature, Gp::kIdBp);
+static constexpr Gp rsi = Gp(Gpq::kSignature, Gp::kIdSi);
+static constexpr Gp rdi = Gp(Gpq::kSignature, Gp::kIdDi);
+static constexpr Gp r8 = Gp(Gpq::kSignature, Gp::kIdR8);
+static constexpr Gp r9 = Gp(Gpq::kSignature, Gp::kIdR9);
+static constexpr Gp r10 = Gp(Gpq::kSignature, Gp::kIdR10);
+static constexpr Gp r11 = Gp(Gpq::kSignature, Gp::kIdR11);
+static constexpr Gp r12 = Gp(Gpq::kSignature, Gp::kIdR12);
+static constexpr Gp r13 = Gp(Gpq::kSignature, Gp::kIdR13);
+static constexpr Gp r14 = Gp(Gpq::kSignature, Gp::kIdR14);
+static constexpr Gp r15 = Gp(Gpq::kSignature, Gp::kIdR15);
+
+static constexpr Xmm xmm0 = Xmm(0);
+static constexpr Xmm xmm1 = Xmm(1);
+static constexpr Xmm xmm2 = Xmm(2);
+static constexpr Xmm xmm3 = Xmm(3);
+static constexpr Xmm xmm4 = Xmm(4);
+static constexpr Xmm xmm5 = Xmm(5);
+static constexpr Xmm xmm6 = Xmm(6);
+static constexpr Xmm xmm7 = Xmm(7);
+static constexpr Xmm xmm8 = Xmm(8);
+static constexpr Xmm xmm9 = Xmm(9);
+static constexpr Xmm xmm10 = Xmm(10);
+static constexpr Xmm xmm11 = Xmm(11);
+static constexpr Xmm xmm12 = Xmm(12);
+static constexpr Xmm xmm13 = Xmm(13);
+static constexpr Xmm xmm14 = Xmm(14);
+static constexpr Xmm xmm15 = Xmm(15);
+static constexpr Xmm xmm16 = Xmm(16);
+static constexpr Xmm xmm17 = Xmm(17);
+static constexpr Xmm xmm18 = Xmm(18);
+static constexpr Xmm xmm19 = Xmm(19);
+static constexpr Xmm xmm20 = Xmm(20);
+static constexpr Xmm xmm21 = Xmm(21);
+static constexpr Xmm xmm22 = Xmm(22);
+static constexpr Xmm xmm23 = Xmm(23);
+static constexpr Xmm xmm24 = Xmm(24);
+static constexpr Xmm xmm25 = Xmm(25);
+static constexpr Xmm xmm26 = Xmm(26);
+static constexpr Xmm xmm27 = Xmm(27);
+static constexpr Xmm xmm28 = Xmm(28);
+static constexpr Xmm xmm29 = Xmm(29);
+static constexpr Xmm xmm30 = Xmm(30);
+static constexpr Xmm xmm31 = Xmm(31);
+
+static constexpr Ymm ymm0 = Ymm(0);
+static constexpr Ymm ymm1 = Ymm(1);
+static constexpr Ymm ymm2 = Ymm(2);
+static constexpr Ymm ymm3 = Ymm(3);
+static constexpr Ymm ymm4 = Ymm(4);
+static constexpr Ymm ymm5 = Ymm(5);
+static constexpr Ymm ymm6 = Ymm(6);
+static constexpr Ymm ymm7 = Ymm(7);
+static constexpr Ymm ymm8 = Ymm(8);
+static constexpr Ymm ymm9 = Ymm(9);
+static constexpr Ymm ymm10 = Ymm(10);
+static constexpr Ymm ymm11 = Ymm(11);
+static constexpr Ymm ymm12 = Ymm(12);
+static constexpr Ymm ymm13 = Ymm(13);
+static constexpr Ymm ymm14 = Ymm(14);
+static constexpr Ymm ymm15 = Ymm(15);
+static constexpr Ymm ymm16 = Ymm(16);
+static constexpr Ymm ymm17 = Ymm(17);
+static constexpr Ymm ymm18 = Ymm(18);
+static constexpr Ymm ymm19 = Ymm(19);
+static constexpr Ymm ymm20 = Ymm(20);
+static constexpr Ymm ymm21 = Ymm(21);
+static constexpr Ymm ymm22 = Ymm(22);
+static constexpr Ymm ymm23 = Ymm(23);
+static constexpr Ymm ymm24 = Ymm(24);
+static constexpr Ymm ymm25 = Ymm(25);
+static constexpr Ymm ymm26 = Ymm(26);
+static constexpr Ymm ymm27 = Ymm(27);
+static constexpr Ymm ymm28 = Ymm(28);
+static constexpr Ymm ymm29 = Ymm(29);
+static constexpr Ymm ymm30 = Ymm(30);
+static constexpr Ymm ymm31 = Ymm(31);
+
+static constexpr Zmm zmm0 = Zmm(0);
+static constexpr Zmm zmm1 = Zmm(1);
+static constexpr Zmm zmm2 = Zmm(2);
+static constexpr Zmm zmm3 = Zmm(3);
+static constexpr Zmm zmm4 = Zmm(4);
+static constexpr Zmm zmm5 = Zmm(5);
+static constexpr Zmm zmm6 = Zmm(6);
+static constexpr Zmm zmm7 = Zmm(7);
+static constexpr Zmm zmm8 = Zmm(8);
+static constexpr Zmm zmm9 = Zmm(9);
+static constexpr Zmm zmm10 = Zmm(10);
+static constexpr Zmm zmm11 = Zmm(11);
+static constexpr Zmm zmm12 = Zmm(12);
+static constexpr Zmm zmm13 = Zmm(13);
+static constexpr Zmm zmm14 = Zmm(14);
+static constexpr Zmm zmm15 = Zmm(15);
+static constexpr Zmm zmm16 = Zmm(16);
+static constexpr Zmm zmm17 = Zmm(17);
+static constexpr Zmm zmm18 = Zmm(18);
+static constexpr Zmm zmm19 = Zmm(19);
+static constexpr Zmm zmm20 = Zmm(20);
+static constexpr Zmm zmm21 = Zmm(21);
+static constexpr Zmm zmm22 = Zmm(22);
+static constexpr Zmm zmm23 = Zmm(23);
+static constexpr Zmm zmm24 = Zmm(24);
+static constexpr Zmm zmm25 = Zmm(25);
+static constexpr Zmm zmm26 = Zmm(26);
+static constexpr Zmm zmm27 = Zmm(27);
+static constexpr Zmm zmm28 = Zmm(28);
+static constexpr Zmm zmm29 = Zmm(29);
+static constexpr Zmm zmm30 = Zmm(30);
+static constexpr Zmm zmm31 = Zmm(31);
+
+static constexpr Mm mm0 = Mm(0);
+static constexpr Mm mm1 = Mm(1);
+static constexpr Mm mm2 = Mm(2);
+static constexpr Mm mm3 = Mm(3);
+static constexpr Mm mm4 = Mm(4);
+static constexpr Mm mm5 = Mm(5);
+static constexpr Mm mm6 = Mm(6);
+static constexpr Mm mm7 = Mm(7);
+
+static constexpr KReg k0 = KReg(0);
+static constexpr KReg k1 = KReg(1);
+static constexpr KReg k2 = KReg(2);
+static constexpr KReg k3 = KReg(3);
+static constexpr KReg k4 = KReg(4);
+static constexpr KReg k5 = KReg(5);
+static constexpr KReg k6 = KReg(6);
+static constexpr KReg k7 = KReg(7);
+
+static constexpr SReg no_seg = SReg(SReg::kIdNone);
+static constexpr SReg es = SReg(SReg::kIdEs);
+static constexpr SReg cs = SReg(SReg::kIdCs);
+static constexpr SReg ss = SReg(SReg::kIdSs);
+static constexpr SReg ds = SReg(SReg::kIdDs);
+static constexpr SReg fs = SReg(SReg::kIdFs);
+static constexpr SReg gs = SReg(SReg::kIdGs);
+
+static constexpr CReg cr0 = CReg(0);
+static constexpr CReg cr1 = CReg(1);
+static constexpr CReg cr2 = CReg(2);
+static constexpr CReg cr3 = CReg(3);
+static constexpr CReg cr4 = CReg(4);
+static constexpr CReg cr5 = CReg(5);
+static constexpr CReg cr6 = CReg(6);
+static constexpr CReg cr7 = CReg(7);
+static constexpr CReg cr8 = CReg(8);
+static constexpr CReg cr9 = CReg(9);
+static constexpr CReg cr10 = CReg(10);
+static constexpr CReg cr11 = CReg(11);
+static constexpr CReg cr12 = CReg(12);
+static constexpr CReg cr13 = CReg(13);
+static constexpr CReg cr14 = CReg(14);
+static constexpr CReg cr15 = CReg(15);
+
+static constexpr DReg dr0 = DReg(0);
+static constexpr DReg dr1 = DReg(1);
+static constexpr DReg dr2 = DReg(2);
+static constexpr DReg dr3 = DReg(3);
+static constexpr DReg dr4 = DReg(4);
+static constexpr DReg dr5 = DReg(5);
+static constexpr DReg dr6 = DReg(6);
+static constexpr DReg dr7 = DReg(7);
+static constexpr DReg dr8 = DReg(8);
+static constexpr DReg dr9 = DReg(9);
+static constexpr DReg dr10 = DReg(10);
+static constexpr DReg dr11 = DReg(11);
+static constexpr DReg dr12 = DReg(12);
+static constexpr DReg dr13 = DReg(13);
+static constexpr DReg dr14 = DReg(14);
+static constexpr DReg dr15 = DReg(15);
+
+static constexpr St st0 = St(0);
+static constexpr St st1 = St(1);
+static constexpr St st2 = St(2);
+static constexpr St st3 = St(3);
+static constexpr St st4 = St(4);
+static constexpr St st5 = St(5);
+static constexpr St st6 = St(6);
+static constexpr St st7 = St(7);
+
+static constexpr Bnd bnd0 = Bnd(0);
+static constexpr Bnd bnd1 = Bnd(1);
+static constexpr Bnd bnd2 = Bnd(2);
+static constexpr Bnd bnd3 = Bnd(3);
+
+static constexpr Tmm tmm0 = Tmm(0);
+static constexpr Tmm tmm1 = Tmm(1);
+static constexpr Tmm tmm2 = Tmm(2);
+static constexpr Tmm tmm3 = Tmm(3);
+static constexpr Tmm tmm4 = Tmm(4);
+static constexpr Tmm tmm5 = Tmm(5);
+static constexpr Tmm tmm6 = Tmm(6);
+static constexpr Tmm tmm7 = Tmm(7);
+
+static constexpr Rip rip = Rip(0);
+
+#ifndef _DOXYGEN
+} // {regs}
+
+// Make `x86::regs` accessible through `x86` namespace as well.
+using namespace regs;
+#endif
+
+// ============================================================================
+// [asmjit::x86::Mem]
+// ============================================================================
+
+//! Memory operand.
+class Mem : public BaseMem {
+public:
+  //! Additional bits of operand's signature used by `Mem`.
+  enum AdditionalBits : uint32_t {
+    kSignatureMemSegmentShift   = 16,
+    kSignatureMemSegmentMask    = 0x07u << kSignatureMemSegmentShift,
+
+    kSignatureMemShiftShift     = 19,
+    kSignatureMemShiftMask      = 0x03u << kSignatureMemShiftShift,
+
+    kSignatureMemBroadcastShift = 21,
+    kSignatureMemBroadcastMask  = 0x7u << kSignatureMemBroadcastShift
+  };
+
+  enum Broadcast : uint32_t {
+    kBroadcast1To1 = 0,
+    kBroadcast1To2 = 1,
+    kBroadcast1To4 = 2,
+    kBroadcast1To8 = 3,
+    kBroadcast1To16 = 4,
+    kBroadcast1To32 = 5,
+    kBroadcast1To64 = 6
+  };
+
+  // --------------------------------------------------------------------------
+  // [Construction / Destruction]
+  // --------------------------------------------------------------------------
+
+  //! Creates a default `Mem` operand that points to [0].
+  constexpr Mem() noexcept
+    : BaseMem() {}
+
+  constexpr Mem(const Mem& other) noexcept
+    : BaseMem(other) {}
+
+  //! \cond INTERNAL
+  //!
+  //! A constructor used internally to create `Mem` operand from `Decomposed` data.
+  constexpr explicit Mem(const Decomposed& d) noexcept
+    : BaseMem(d) {}
+  //! \endcond
+
+  constexpr Mem(const Label& base, int32_t off, uint32_t size = 0, uint32_t flags = 0) noexcept
+    : BaseMem(Decomposed { Label::kLabelTag, base.id(), 0, 0, off, size, flags }) {}
+
+  constexpr Mem(const Label& base, const BaseReg& index, uint32_t shift, int32_t off, uint32_t size = 0, uint32_t flags = 0) noexcept
+    : BaseMem(Decomposed { Label::kLabelTag, base.id(), index.type(), index.id(), off, size, flags | (shift << kSignatureMemShiftShift) }) {}
+
+  constexpr Mem(const BaseReg& base, int32_t off, uint32_t size = 0, uint32_t flags = 0) noexcept
+    : BaseMem(Decomposed { base.type(), base.id(), 0, 0, off, size, flags }) {}
+
+  constexpr Mem(const BaseReg& base, const BaseReg& index, uint32_t shift, int32_t off, uint32_t size = 0, uint32_t flags = 0) noexcept
+    : BaseMem(Decomposed { base.type(), base.id(), index.type(), index.id(), off, size, flags | (shift << kSignatureMemShiftShift) }) {}
+
+  constexpr explicit Mem(uint64_t base, uint32_t size = 0, uint32_t flags = 0) noexcept
+    : BaseMem(Decomposed { 0, uint32_t(base >> 32), 0, 0, int32_t(uint32_t(base & 0xFFFFFFFFu)), size, flags }) {}
+
+  constexpr Mem(uint64_t base, const BaseReg& index, uint32_t shift = 0, uint32_t size = 0, uint32_t flags = 0) noexcept
+    : BaseMem(Decomposed { 0, uint32_t(base >> 32), index.type(), index.id(), int32_t(uint32_t(base & 0xFFFFFFFFu)), size, flags | (shift << kSignatureMemShiftShift) }) {}
+
+  constexpr Mem(Globals::Init_, uint32_t u0, uint32_t u1, uint32_t u2, uint32_t u3) noexcept
+    : BaseMem(Globals::Init, u0, u1, u2, u3) {}
+
+  inline explicit Mem(Globals::NoInit_) noexcept
+    : BaseMem(Globals::NoInit) {}
+
+  //! Clones the memory operand.
+  constexpr Mem clone() const noexcept { return Mem(*this); }
+
+  //! Creates a new copy of this memory operand adjusted by `off`.
+  inline Mem cloneAdjusted(int64_t off) const noexcept {
+    Mem result(*this);
+    result.addOffset(off);
+    return result;
+  }
+
+  //! Converts memory `baseType` and `baseId` to `x86::Reg` instance.
+  //!
+  //! The memory must have a valid base register otherwise the result will be wrong.
+  inline Reg baseReg() const noexcept { return Reg::fromTypeAndId(baseType(), baseId()); }
+
+  //! Converts memory `indexType` and `indexId` to `x86::Reg` instance.
+  //!
+  //! The memory must have a valid index register otherwise the result will be wrong.
+  inline Reg indexReg() const noexcept { return Reg::fromTypeAndId(indexType(), indexId()); }
+
+  constexpr Mem _1to1() const noexcept { return Mem(Globals::Init, (_signature & ~kSignatureMemBroadcastMask) | (kBroadcast1To1 << kSignatureMemBroadcastShift), _baseId, _data[0], _data[1]); }
+  constexpr Mem _1to2() const noexcept { return Mem(Globals::Init, (_signature & ~kSignatureMemBroadcastMask) | (kBroadcast1To2 << kSignatureMemBroadcastShift), _baseId, _data[0], _data[1]); }
+  constexpr Mem _1to4() const noexcept { return Mem(Globals::Init, (_signature & ~kSignatureMemBroadcastMask) | (kBroadcast1To4 << kSignatureMemBroadcastShift), _baseId, _data[0], _data[1]); }
+  constexpr Mem _1to8() const noexcept { return Mem(Globals::Init, (_signature & ~kSignatureMemBroadcastMask) | (kBroadcast1To8 << kSignatureMemBroadcastShift), _baseId, _data[0], _data[1]); }
+  constexpr Mem _1to16() const noexcept { return Mem(Globals::Init, (_signature & ~kSignatureMemBroadcastMask) | (kBroadcast1To16 << kSignatureMemBroadcastShift), _baseId, _data[0], _data[1]); }
+  constexpr Mem _1to32() const noexcept { return Mem(Globals::Init, (_signature & ~kSignatureMemBroadcastMask) | (kBroadcast1To32 << kSignatureMemBroadcastShift), _baseId, _data[0], _data[1]); }
+  constexpr Mem _1to64() const noexcept { return Mem(Globals::Init, (_signature & ~kSignatureMemBroadcastMask) | (kBroadcast1To64 << kSignatureMemBroadcastShift), _baseId, _data[0], _data[1]); }
+
+  // --------------------------------------------------------------------------
+  // [Mem]
+  // --------------------------------------------------------------------------
+
+  using BaseMem::setIndex;
+
+  inline void setIndex(const BaseReg& index, uint32_t shift) noexcept {
+    setIndex(index);
+    setShift(shift);
+  }
+
+  //! Tests whether the memory operand has a segment override.
+  constexpr bool hasSegment() const noexcept { return _hasSignaturePart<kSignatureMemSegmentMask>(); }
+  //! Returns the associated segment override as `SReg` operand.
+  constexpr SReg segment() const noexcept { return SReg(segmentId()); }
+  //! Returns segment override register id, see `SReg::Id`.
+  constexpr uint32_t segmentId() const noexcept { return _getSignaturePart<kSignatureMemSegmentMask>(); }
+
+  //! Sets the segment override to `seg`.
+  inline void setSegment(const SReg& seg) noexcept { setSegment(seg.id()); }
+  //! Sets the segment override to `id`.
+  inline void setSegment(uint32_t rId) noexcept { _setSignaturePart<kSignatureMemSegmentMask>(rId); }
+  //! Resets the segment override.
+  inline void resetSegment() noexcept { _setSignaturePart<kSignatureMemSegmentMask>(0); }
+
+  //! Tests whether the memory operand has shift (aka scale) value.
+  constexpr bool hasShift() const noexcept { return _hasSignaturePart<kSignatureMemShiftMask>(); }
+  //! Returns the memory operand's shift (aka scale) value.
+  constexpr uint32_t shift() const noexcept { return _getSignaturePart<kSignatureMemShiftMask>(); }
+  //! Sets the memory operand's shift (aka scale) value.
+  inline void setShift(uint32_t shift) noexcept { _setSignaturePart<kSignatureMemShiftMask>(shift); }
+  //! Resets the memory operand's shift (aka scale) value to zero.
+  inline void resetShift() noexcept { _setSignaturePart<kSignatureMemShiftMask>(0); }
+
+  //! Tests whether the memory operand has broadcast {1tox}.
+  constexpr bool hasBroadcast() const noexcept { return _hasSignaturePart<kSignatureMemBroadcastMask>(); }
+  //! Returns the memory operand's broadcast.
+  constexpr uint32_t getBroadcast() const noexcept { return _getSignaturePart<kSignatureMemBroadcastMask>(); }
+  //! Sets the memory operand's broadcast.
+  inline void setBroadcast(uint32_t bcst) noexcept { _setSignaturePart<kSignatureMemBroadcastMask>(bcst); }
+  //! Resets the memory operand's broadcast to none.
+  inline void resetBroadcast() noexcept { _setSignaturePart<kSignatureMemBroadcastMask>(0); }
+
+  // --------------------------------------------------------------------------
+  // [Operator Overload]
+  // --------------------------------------------------------------------------
+
+  inline Mem& operator=(const Mem& other) noexcept = default;
+};
+
+//! Creates `[base.reg + offset]` memory operand.
+static constexpr Mem ptr(const Gp& base, int32_t offset = 0, uint32_t size = 0) noexcept {
+  return Mem(base, offset, size);
+}
+//! Creates `[base.reg + (index << shift) + offset]` memory operand (scalar index).
+static constexpr Mem ptr(const Gp& base, const Gp& index, uint32_t shift = 0, int32_t offset = 0, uint32_t size = 0) noexcept {
+  return Mem(base, index, shift, offset, size);
+}
+//! Creates `[base.reg + (index << shift) + offset]` memory operand (vector index).
+static constexpr Mem ptr(const Gp& base, const Vec& index, uint32_t shift = 0, int32_t offset = 0, uint32_t size = 0) noexcept {
+  return Mem(base, index, shift, offset, size);
+}
+
+//! Creates `[base + offset]` memory operand.
+static constexpr Mem ptr(const Label& base, int32_t offset = 0, uint32_t size = 0) noexcept {
+  return Mem(base, offset, size);
+}
+//! Creates `[base + (index << shift) + offset]` memory operand.
+static constexpr Mem ptr(const Label& base, const Gp& index, uint32_t shift = 0, int32_t offset = 0, uint32_t size = 0) noexcept {
+  return Mem(base, index, shift, offset, size);
+}
+//! Creates `[base + (index << shift) + offset]` memory operand.
+static constexpr Mem ptr(const Label& base, const Vec& index, uint32_t shift = 0, int32_t offset = 0, uint32_t size = 0) noexcept {
+  return Mem(base, index, shift, offset, size);
+}
+
+//! Creates `[rip + offset]` memory operand.
+static constexpr Mem ptr(const Rip& rip_, int32_t offset = 0, uint32_t size = 0) noexcept {
+  return Mem(rip_, offset, size);
+}
+
+//! Creates `[base]` absolute memory operand.
+static constexpr Mem ptr(uint64_t base, uint32_t size = 0) noexcept {
+  return Mem(base, size);
+}
+//! Creates `[base + (index.reg << shift)]` absolute memory operand.
+static constexpr Mem ptr(uint64_t base, const Reg& index, uint32_t shift = 0, uint32_t size = 0) noexcept {
+  return Mem(base, index, shift, size);
+}
+//! Creates `[base + (index.reg << shift)]` absolute memory operand.
+static constexpr Mem ptr(uint64_t base, const Vec& index, uint32_t shift = 0, uint32_t size = 0) noexcept {
+  return Mem(base, index, shift, size);
+}
+
+//! Creates `[base]` absolute memory operand (absolute).
+static constexpr Mem ptr_abs(uint64_t base, uint32_t size = 0) noexcept {
+  return Mem(base, size, BaseMem::kSignatureMemAbs);
+}
+//! Creates `[base + (index.reg << shift)]` absolute memory operand (absolute).
+static constexpr Mem ptr_abs(uint64_t base, const Reg& index, uint32_t shift = 0, uint32_t size = 0) noexcept {
+  return Mem(base, index, shift, size, BaseMem::kSignatureMemAbs);
+}
+//! Creates `[base + (index.reg << shift)]` absolute memory operand (absolute).
+static constexpr Mem ptr_abs(uint64_t base, const Vec& index, uint32_t shift = 0, uint32_t size = 0) noexcept {
+  return Mem(base, index, shift, size, BaseMem::kSignatureMemAbs);
+}
+
+//! Creates `[base]` relative memory operand (relative).
+static constexpr Mem ptr_rel(uint64_t base, uint32_t size = 0) noexcept {
+  return Mem(base, size, BaseMem::kSignatureMemRel);
+}
+//! Creates `[base + (index.reg << shift)]` relative memory operand (relative).
+static constexpr Mem ptr_rel(uint64_t base, const Reg& index, uint32_t shift = 0, uint32_t size = 0) noexcept {
+  return Mem(base, index, shift, size, BaseMem::kSignatureMemRel);
+}
+//! Creates `[base + (index.reg << shift)]` relative memory operand (relative).
+static constexpr Mem ptr_rel(uint64_t base, const Vec& index, uint32_t shift = 0, uint32_t size = 0) noexcept {
+  return Mem(base, index, shift, size, BaseMem::kSignatureMemRel);
+}
+
+// Definition of memory operand constructors that use platform independent naming.
+ASMJIT_MEM_PTR(ptr_8, 1)
+ASMJIT_MEM_PTR(ptr_16, 2)
+ASMJIT_MEM_PTR(ptr_32, 4)
+ASMJIT_MEM_PTR(ptr_48, 6)
+ASMJIT_MEM_PTR(ptr_64, 8)
+ASMJIT_MEM_PTR(ptr_80, 10)
+ASMJIT_MEM_PTR(ptr_128, 16)
+ASMJIT_MEM_PTR(ptr_256, 32)
+ASMJIT_MEM_PTR(ptr_512, 64)
+
+// Definition of memory operand constructors that use X86-specific convention.
+ASMJIT_MEM_PTR(byte_ptr, 1)
+ASMJIT_MEM_PTR(word_ptr, 2)
+ASMJIT_MEM_PTR(dword_ptr, 4)
+ASMJIT_MEM_PTR(qword_ptr, 8)
+ASMJIT_MEM_PTR(tword_ptr, 10)
+ASMJIT_MEM_PTR(oword_ptr, 16)
+ASMJIT_MEM_PTR(dqword_ptr, 16)
+ASMJIT_MEM_PTR(qqword_ptr, 32)
+ASMJIT_MEM_PTR(xmmword_ptr, 16)
+ASMJIT_MEM_PTR(ymmword_ptr, 32)
+ASMJIT_MEM_PTR(zmmword_ptr, 64)
+
+// ============================================================================
+// [asmjit::x86::OpData]
+// ============================================================================
+
+struct OpData {
+  //! Information about all architecture registers.
+  ArchRegs archRegs;
+};
+ASMJIT_VARAPI const OpData opData;
+
+//! \cond
+// ... Reg methods that require `opData`.
+inline uint32_t Reg::groupOf(uint32_t rType) noexcept {
+  ASMJIT_ASSERT(rType <= BaseReg::kTypeMax);
+  return opData.archRegs.regInfo[rType].group();
+}
+
+inline uint32_t Reg::typeIdOf(uint32_t rType) noexcept {
+  ASMJIT_ASSERT(rType <= BaseReg::kTypeMax);
+  return opData.archRegs.regTypeToTypeId[rType];
+}
+
+inline uint32_t Reg::signatureOf(uint32_t rType) noexcept {
+  ASMJIT_ASSERT(rType <= BaseReg::kTypeMax);
+  return opData.archRegs.regInfo[rType].signature();
+}
+//! \endcond
+
+//! \}
+
+ASMJIT_END_SUB_NAMESPACE
+
+// ============================================================================
+// [asmjit::Type::IdOfT<x86::Reg>]
+// ============================================================================
+
+//! \cond INTERNAL
+ASMJIT_BEGIN_NAMESPACE
+ASMJIT_DEFINE_TYPE_ID(x86::Gpb, kIdI8);
+ASMJIT_DEFINE_TYPE_ID(x86::Gpw, kIdI16);
+ASMJIT_DEFINE_TYPE_ID(x86::Gpd, kIdI32);
+ASMJIT_DEFINE_TYPE_ID(x86::Gpq, kIdI64);
+ASMJIT_DEFINE_TYPE_ID(x86::Mm , kIdMmx64);
+ASMJIT_DEFINE_TYPE_ID(x86::Xmm, kIdI32x4);
+ASMJIT_DEFINE_TYPE_ID(x86::Ymm, kIdI32x8);
+ASMJIT_DEFINE_TYPE_ID(x86::Zmm, kIdI32x16);
+ASMJIT_END_NAMESPACE
+//! \endcond
+
+#undef ASMJIT_MEM_PTR
+
+#endif // ASMJIT_X86_X86OPERAND_H_INCLUDED
diff --git a/client/asmjit/x86/x86rapass.cpp b/client/asmjit/x86/x86rapass.cpp
new file mode 100644
index 0000000..6cbb006
--- /dev/null
+++ b/client/asmjit/x86/x86rapass.cpp
@@ -0,0 +1,1279 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#include "../core/api-build_p.h"
+#if defined(ASMJIT_BUILD_X86) && !defined(ASMJIT_NO_COMPILER)
+
+#include "../core/cpuinfo.h"
+#include "../core/support.h"
+#include "../core/type.h"
+#include "../x86/x86assembler.h"
+#include "../x86/x86compiler.h"
+#include "../x86/x86instapi_p.h"
+#include "../x86/x86instdb_p.h"
+#include "../x86/x86internal_p.h"
+#include "../x86/x86rapass_p.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+// ============================================================================
+// [asmjit::x86::X86RAPass - Helpers]
+// ============================================================================
+
+static ASMJIT_INLINE uint64_t raImmMaskFromSize(uint32_t size) noexcept {
+  ASMJIT_ASSERT(size > 0 && size < 256);
+  static const uint64_t masks[] = {
+    0x00000000000000FFu, //   1
+    0x000000000000FFFFu, //   2
+    0x00000000FFFFFFFFu, //   4
+    0xFFFFFFFFFFFFFFFFu, //   8
+    0x0000000000000000u, //  16
+    0x0000000000000000u, //  32
+    0x0000000000000000u, //  64
+    0x0000000000000000u, // 128
+    0x0000000000000000u  // 256
+  };
+  return masks[Support::ctz(size)];
+}
+
+static ASMJIT_INLINE uint32_t raUseOutFlagsFromRWFlags(uint32_t rwFlags) noexcept {
+  static const uint32_t map[] = {
+    0,
+    RATiedReg::kRead  | RATiedReg::kUse,                     // kRead
+    RATiedReg::kWrite | RATiedReg::kOut,                     // kWrite
+    RATiedReg::kRW    | RATiedReg::kUse,                     // kRW
+    0,
+    RATiedReg::kRead  | RATiedReg::kUse | RATiedReg::kUseRM, // kRead  | kRegMem
+    RATiedReg::kWrite | RATiedReg::kOut | RATiedReg::kOutRM, // kWrite | kRegMem
+    RATiedReg::kRW    | RATiedReg::kUse | RATiedReg::kUseRM  // kRW    | kRegMem
+  };
+
+  return map[rwFlags & (OpRWInfo::kRW | OpRWInfo::kRegMem)];
+}
+
+static ASMJIT_INLINE uint32_t raRegRwFlags(uint32_t flags) noexcept {
+  return raUseOutFlagsFromRWFlags(flags);
+}
+
+static ASMJIT_INLINE uint32_t raMemBaseRwFlags(uint32_t flags) noexcept {
+  constexpr uint32_t shift = Support::constCtz(OpRWInfo::kMemBaseRW);
+  return raUseOutFlagsFromRWFlags((flags >> shift) & OpRWInfo::kRW);
+}
+
+static ASMJIT_INLINE uint32_t raMemIndexRwFlags(uint32_t flags) noexcept {
+  constexpr uint32_t shift = Support::constCtz(OpRWInfo::kMemIndexRW);
+  return raUseOutFlagsFromRWFlags((flags >> shift) & OpRWInfo::kRW);
+}
+
+// ============================================================================
+// [asmjit::x86::X86RACFGBuilder]
+// ============================================================================
+
+class X86RACFGBuilder : public RACFGBuilder<X86RACFGBuilder> {
+public:
+  uint32_t _arch;
+  bool _is64Bit;
+  bool _avxEnabled;
+
+  inline X86RACFGBuilder(X86RAPass* pass) noexcept
+    : RACFGBuilder<X86RACFGBuilder>(pass),
+      _arch(pass->cc()->arch()),
+      _is64Bit(pass->registerSize() == 8),
+      _avxEnabled(pass->_avxEnabled) {
+  }
+
+  inline Compiler* cc() const noexcept { return static_cast<Compiler*>(_cc); }
+
+  inline uint32_t choose(uint32_t sseInst, uint32_t avxInst) const noexcept {
+    return _avxEnabled ? avxInst : sseInst;
+  }
+
+  Error onInst(InstNode* inst, uint32_t& controlType, RAInstBuilder& ib) noexcept;
+
+  Error onBeforeInvoke(InvokeNode* invokeNode) noexcept;
+  Error onInvoke(InvokeNode* invokeNode, RAInstBuilder& ib) noexcept;
+
+  Error moveVecToPtr(InvokeNode* invokeNode, const FuncValue& arg, const Vec& src, BaseReg* out) noexcept;
+  Error moveImmToRegArg(InvokeNode* invokeNode, const FuncValue& arg, const Imm& imm_, BaseReg* out) noexcept;
+  Error moveImmToStackArg(InvokeNode* invokeNode, const FuncValue& arg, const Imm& imm_) noexcept;
+  Error moveRegToStackArg(InvokeNode* invokeNode, const FuncValue& arg, const BaseReg& reg) noexcept;
+
+  Error onBeforeRet(FuncRetNode* funcRet) noexcept;
+  Error onRet(FuncRetNode* funcRet, RAInstBuilder& ib) noexcept;
+};
+
+// ============================================================================
+// [asmjit::x86::X86RACFGBuilder - OnInst]
+// ============================================================================
+
+Error X86RACFGBuilder::onInst(InstNode* inst, uint32_t& controlType, RAInstBuilder& ib) noexcept {
+  InstRWInfo rwInfo;
+
+  uint32_t instId = inst->id();
+  if (Inst::isDefinedId(instId)) {
+    uint32_t opCount = inst->opCount();
+    const Operand* opArray = inst->operands();
+    ASMJIT_PROPAGATE(InstInternal::queryRWInfo(_arch, inst->baseInst(), opArray, opCount, &rwInfo));
+
+    const InstDB::InstInfo& instInfo = InstDB::infoById(instId);
+    bool hasGpbHiConstraint = false;
+    uint32_t singleRegOps = 0;
+
+    if (opCount) {
+      for (uint32_t i = 0; i < opCount; i++) {
+        const Operand& op = opArray[i];
+        const OpRWInfo& opRwInfo = rwInfo.operand(i);
+
+        if (op.isReg()) {
+          // Register Operand
+          // ----------------
+          const Reg& reg = op.as<Reg>();
+
+          uint32_t flags = raRegRwFlags(opRwInfo.opFlags());
+          uint32_t allowedRegs = 0xFFFFFFFFu;
+
+          // X86-specific constraints related to LO|HI general purpose registers.
+          // This is only required when the register is part of the encoding. If
+          // the register is fixed we won't restrict anything as it doesn't restrict
+          // encoding of other registers.
+          if (reg.isGpb() && !(opRwInfo.opFlags() & OpRWInfo::kRegPhysId)) {
+            flags |= RATiedReg::kX86Gpb;
+            if (!_is64Bit) {
+              // Restrict to first four - AL|AH|BL|BH|CL|CH|DL|DH. In 32-bit mode
+              // it's not possible to access SIL|DIL, etc, so this is just enough.
+              allowedRegs = 0x0Fu;
+            }
+            else {
+              // If we encountered GPB-HI register the situation is much more
+              // complicated than in 32-bit mode. We need to patch all registers
+              // to not use ID higher than 7 and all GPB-LO registers to not use
+              // index higher than 3. Instead of doing the patching here we just
+              // set a flag and will do it later, to not complicate this loop.
+              if (reg.isGpbHi()) {
+                hasGpbHiConstraint = true;
+                allowedRegs = 0x0Fu;
+              }
+            }
+          }
+
+          uint32_t vIndex = Operand::virtIdToIndex(reg.id());
+          if (vIndex < Operand::kVirtIdCount) {
+            RAWorkReg* workReg;
+            ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(vIndex, &workReg));
+
+            // Use RW instead of Write in case that not the whole register is
+            // overwritten. This is important for liveness as we cannot kill a
+            // register that will be used. For example `mov al, 0xFF` is not a
+            // write-only operation if user allocated the whole `rax` register.
+            if ((flags & RATiedReg::kRW) == RATiedReg::kWrite) {
+              if (workReg->regByteMask() & ~(opRwInfo.writeByteMask() | opRwInfo.extendByteMask())) {
+                // Not write-only operation.
+                flags = (flags & ~RATiedReg::kOut) | (RATiedReg::kRead | RATiedReg::kUse);
+              }
+            }
+
+            // Do not use RegMem flag if changing Reg to Mem requires additional
+            // CPU feature that may not be enabled.
+            if (rwInfo.rmFeature() && (flags & (RATiedReg::kUseRM | RATiedReg::kOutRM))) {
+              flags &= ~(RATiedReg::kUseRM | RATiedReg::kOutRM);
+            }
+
+            uint32_t group = workReg->group();
+            uint32_t allocable = _pass->_availableRegs[group] & allowedRegs;
+
+            uint32_t useId = BaseReg::kIdBad;
+            uint32_t outId = BaseReg::kIdBad;
+
+            uint32_t useRewriteMask = 0;
+            uint32_t outRewriteMask = 0;
+
+            if (flags & RATiedReg::kUse) {
+              useRewriteMask = Support::bitMask(inst->getRewriteIndex(&reg._baseId));
+              if (opRwInfo.opFlags() & OpRWInfo::kRegPhysId) {
+                useId = opRwInfo.physId();
+                flags |= RATiedReg::kUseFixed;
+              }
+            }
+            else {
+              outRewriteMask = Support::bitMask(inst->getRewriteIndex(&reg._baseId));
+              if (opRwInfo.opFlags() & OpRWInfo::kRegPhysId) {
+                outId = opRwInfo.physId();
+                flags |= RATiedReg::kOutFixed;
+              }
+            }
+
+            ASMJIT_PROPAGATE(ib.add(workReg, flags, allocable, useId, useRewriteMask, outId, outRewriteMask, opRwInfo.rmSize()));
+            if (singleRegOps == i)
+              singleRegOps++;
+          }
+        }
+        else if (op.isMem()) {
+          // Memory Operand
+          // --------------
+          const Mem& mem = op.as<Mem>();
+          ib.addForbiddenFlags(RATiedReg::kUseRM | RATiedReg::kOutRM);
+
+          if (mem.isRegHome()) {
+            RAWorkReg* workReg;
+            ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(Operand::virtIdToIndex(mem.baseId()), &workReg));
+            _pass->getOrCreateStackSlot(workReg);
+          }
+          else if (mem.hasBaseReg()) {
+            uint32_t vIndex = Operand::virtIdToIndex(mem.baseId());
+            if (vIndex < Operand::kVirtIdCount) {
+              RAWorkReg* workReg;
+              ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(vIndex, &workReg));
+
+              uint32_t flags = raMemBaseRwFlags(opRwInfo.opFlags());
+              uint32_t group = workReg->group();
+              uint32_t allocable = _pass->_availableRegs[group];
+
+              uint32_t useId = BaseReg::kIdBad;
+              uint32_t outId = BaseReg::kIdBad;
+
+              uint32_t useRewriteMask = 0;
+              uint32_t outRewriteMask = 0;
+
+              if (flags & RATiedReg::kUse) {
+                useRewriteMask = Support::bitMask(inst->getRewriteIndex(&mem._baseId));
+                if (opRwInfo.opFlags() & OpRWInfo::kMemPhysId) {
+                  useId = opRwInfo.physId();
+                  flags |= RATiedReg::kUseFixed;
+                }
+              }
+              else {
+                outRewriteMask = Support::bitMask(inst->getRewriteIndex(&mem._baseId));
+                if (opRwInfo.opFlags() & OpRWInfo::kMemPhysId) {
+                  outId = opRwInfo.physId();
+                  flags |= RATiedReg::kOutFixed;
+                }
+              }
+
+              ASMJIT_PROPAGATE(ib.add(workReg, flags, allocable, useId, useRewriteMask, outId, outRewriteMask));
+            }
+          }
+
+          if (mem.hasIndexReg()) {
+            uint32_t vIndex = Operand::virtIdToIndex(mem.indexId());
+            if (vIndex < Operand::kVirtIdCount) {
+              RAWorkReg* workReg;
+              ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(vIndex, &workReg));
+
+              uint32_t flags = raMemIndexRwFlags(opRwInfo.opFlags());
+              uint32_t group = workReg->group();
+              uint32_t allocable = _pass->_availableRegs[group];
+
+              // Index registers have never fixed id on X86/x64.
+              const uint32_t useId = BaseReg::kIdBad;
+              const uint32_t outId = BaseReg::kIdBad;
+
+              uint32_t useRewriteMask = 0;
+              uint32_t outRewriteMask = 0;
+
+              if (flags & RATiedReg::kUse)
+                useRewriteMask = Support::bitMask(inst->getRewriteIndex(&mem._data[Operand::kDataMemIndexId]));
+              else
+                outRewriteMask = Support::bitMask(inst->getRewriteIndex(&mem._data[Operand::kDataMemIndexId]));
+
+              ASMJIT_PROPAGATE(ib.add(workReg, RATiedReg::kUse | RATiedReg::kRead, allocable, useId, useRewriteMask, outId, outRewriteMask));
+            }
+          }
+        }
+      }
+    }
+
+    // Handle extra operand (either REP {cx|ecx|rcx} or AVX-512 {k} selector).
+    if (inst->hasExtraReg()) {
+      uint32_t vIndex = Operand::virtIdToIndex(inst->extraReg().id());
+      if (vIndex < Operand::kVirtIdCount) {
+        RAWorkReg* workReg;
+        ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(vIndex, &workReg));
+
+        uint32_t group = workReg->group();
+        uint32_t rewriteMask = Support::bitMask(inst->getRewriteIndex(&inst->extraReg()._id));
+
+        if (group == Gp::kGroupKReg) {
+          // AVX-512 mask selector {k} register - read-only, allocable to any register except {k0}.
+          uint32_t allocableRegs= _pass->_availableRegs[group] & ~Support::bitMask(0);
+          ASMJIT_PROPAGATE(ib.add(workReg, RATiedReg::kUse | RATiedReg::kRead, allocableRegs, BaseReg::kIdBad, rewriteMask, BaseReg::kIdBad, 0));
+          singleRegOps = 0;
+        }
+        else {
+          // REP {cx|ecx|rcx} register - read & write, allocable to {cx|ecx|rcx} only.
+          ASMJIT_PROPAGATE(ib.add(workReg, RATiedReg::kUse | RATiedReg::kRW, 0, Gp::kIdCx, rewriteMask, Gp::kIdBad, 0));
+        }
+      }
+      else {
+        uint32_t group = inst->extraReg().group();
+        if (group == Gp::kGroupKReg && inst->extraReg().id() != 0)
+          singleRegOps = 0;
+      }
+    }
+
+    // Handle X86 constraints.
+    if (hasGpbHiConstraint) {
+      for (RATiedReg& tiedReg : ib) {
+        tiedReg._allocableRegs &= tiedReg.hasFlag(RATiedReg::kX86Gpb) ? 0x0Fu : 0xFFu;
+      }
+    }
+
+    if (ib.tiedRegCount() == 1) {
+      // Handle special cases of some instructions where all operands share the same
+      // register. In such case the single operand becomes read-only or write-only.
+      uint32_t singleRegCase = InstDB::kSingleRegNone;
+      if (singleRegOps == opCount) {
+        singleRegCase = instInfo.singleRegCase();
+      }
+      else if (opCount == 2 && inst->op(1).isImm()) {
+        // Handle some tricks used by X86 asm.
+        const BaseReg& reg = inst->op(0).as<BaseReg>();
+        const Imm& imm = inst->op(1).as<Imm>();
+
+        const RAWorkReg* workReg = _pass->workRegById(ib[0]->workId());
+        uint32_t workRegSize = workReg->info().size();
+
+        switch (inst->id()) {
+          case Inst::kIdOr: {
+            // Sets the value of the destination register to -1, previous content unused.
+            if (reg.size() >= 4 || reg.size() >= workRegSize) {
+              if (imm.value() == -1 || imm.valueAs<uint64_t>() == raImmMaskFromSize(reg.size()))
+                singleRegCase = InstDB::kSingleRegWO;
+            }
+            ASMJIT_FALLTHROUGH;
+          }
+
+          case Inst::kIdAdd:
+          case Inst::kIdAnd:
+          case Inst::kIdRol:
+          case Inst::kIdRor:
+          case Inst::kIdSar:
+          case Inst::kIdShl:
+          case Inst::kIdShr:
+          case Inst::kIdSub:
+          case Inst::kIdXor: {
+            // Updates [E|R]FLAGS without changing the content.
+            if (reg.size() != 4 || reg.size() >= workRegSize) {
+              if (imm.value() == 0)
+                singleRegCase = InstDB::kSingleRegRO;
+            }
+            break;
+          }
+        }
+      }
+
+      switch (singleRegCase) {
+        case InstDB::kSingleRegNone:
+          break;
+        case InstDB::kSingleRegRO:
+          ib[0]->makeReadOnly();
+          break;
+        case InstDB::kSingleRegWO:
+          ib[0]->makeWriteOnly();
+          break;
+      }
+    }
+
+    controlType = instInfo.controlType();
+  }
+
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::x86::X86RACFGBuilder - OnCall]
+// ============================================================================
+
+Error X86RACFGBuilder::onBeforeInvoke(InvokeNode* invokeNode) noexcept {
+  uint32_t argCount = invokeNode->argCount();
+  uint32_t retCount = invokeNode->retCount();
+  const FuncDetail& fd = invokeNode->detail();
+
+  cc()->_setCursor(invokeNode->prev());
+
+  uint32_t nativeRegType = cc()->_gpRegInfo.type();
+
+  for (uint32_t loIndex = 0; loIndex < argCount; loIndex++) {
+    for (uint32_t hiIndex = 0; hiIndex <= kFuncArgHi; hiIndex += kFuncArgHi) {
+      uint32_t argIndex = loIndex + hiIndex;
+      if (!fd.hasArg(argIndex))
+        continue;
+
+      const FuncValue& arg = fd.arg(argIndex);
+      const Operand& op = invokeNode->arg(argIndex);
+
+      if (op.isNone())
+        continue;
+
+      if (op.isReg()) {
+        const Reg& reg = op.as<Reg>();
+        RAWorkReg* workReg;
+        ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(Operand::virtIdToIndex(reg.id()), &workReg));
+
+        if (arg.isReg()) {
+          uint32_t regGroup = workReg->group();
+          uint32_t argGroup = Reg::groupOf(arg.regType());
+
+          if (arg.isIndirect()) {
+            if (reg.isGp()) {
+              if (reg.type() != nativeRegType)
+                return DebugUtils::errored(kErrorInvalidAssignment);
+              // It's considered allocated if this is an indirect argument and the user used GP.
+              continue;
+            }
+
+            BaseReg indirectReg;
+            moveVecToPtr(invokeNode, arg, reg.as<Vec>(), &indirectReg);
+            invokeNode->_args[argIndex] = indirectReg;
+          }
+          else {
+            if (regGroup != argGroup) {
+              // TODO: Conversion is not supported.
+              return DebugUtils::errored(kErrorInvalidAssignment);
+            }
+          }
+        }
+        else {
+          if (arg.isIndirect()) {
+            if (reg.isGp()) {
+              if (reg.type() != nativeRegType)
+                return DebugUtils::errored(kErrorInvalidAssignment);
+
+              ASMJIT_PROPAGATE(moveRegToStackArg(invokeNode, arg, reg));
+              continue;
+            }
+
+            BaseReg indirectReg;
+            moveVecToPtr(invokeNode, arg, reg.as<Vec>(), &indirectReg);
+            ASMJIT_PROPAGATE(moveRegToStackArg(invokeNode, arg, indirectReg));
+          }
+          else {
+            ASMJIT_PROPAGATE(moveRegToStackArg(invokeNode, arg, reg));
+          }
+        }
+      }
+      else if (op.isImm()) {
+        if (arg.isReg()) {
+          BaseReg reg;
+          ASMJIT_PROPAGATE(moveImmToRegArg(invokeNode, arg, op.as<Imm>(), &reg));
+          invokeNode->_args[argIndex] = reg;
+        }
+        else {
+          ASMJIT_PROPAGATE(moveImmToStackArg(invokeNode, arg, op.as<Imm>()));
+        }
+      }
+    }
+  }
+
+  cc()->_setCursor(invokeNode);
+  if (fd.hasFlag(CallConv::kFlagCalleePopsStack))
+    ASMJIT_PROPAGATE(cc()->sub(cc()->zsp(), fd.argStackSize()));
+
+  for (uint32_t retIndex = 0; retIndex < retCount; retIndex++) {
+    const FuncValue& ret = fd.ret(retIndex);
+    const Operand& op = invokeNode->ret(retIndex);
+
+    if (op.isReg()) {
+      const Reg& reg = op.as<Reg>();
+      RAWorkReg* workReg;
+      ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(Operand::virtIdToIndex(reg.id()), &workReg));
+
+      if (ret.isReg()) {
+        if (ret.regType() == Reg::kTypeSt) {
+          if (workReg->group() != Reg::kGroupVec)
+            return DebugUtils::errored(kErrorInvalidAssignment);
+
+          Reg dst = Reg(workReg->signature(), workReg->virtId());
+          Mem mem;
+
+          uint32_t typeId = Type::baseOf(workReg->typeId());
+          if (ret.hasTypeId())
+            typeId = ret.typeId();
+
+          switch (typeId) {
+            case Type::kIdF32:
+              ASMJIT_PROPAGATE(_pass->useTemporaryMem(mem, 4, 4));
+              mem.setSize(4);
+              ASMJIT_PROPAGATE(cc()->fstp(mem));
+              ASMJIT_PROPAGATE(cc()->emit(choose(Inst::kIdMovss, Inst::kIdVmovss), dst.as<Xmm>(), mem));
+              break;
+
+            case Type::kIdF64:
+              ASMJIT_PROPAGATE(_pass->useTemporaryMem(mem, 8, 4));
+              mem.setSize(8);
+              ASMJIT_PROPAGATE(cc()->fstp(mem));
+              ASMJIT_PROPAGATE(cc()->emit(choose(Inst::kIdMovsd, Inst::kIdVmovsd), dst.as<Xmm>(), mem));
+              break;
+
+            default:
+              return DebugUtils::errored(kErrorInvalidAssignment);
+          }
+        }
+        else {
+          uint32_t regGroup = workReg->group();
+          uint32_t retGroup = Reg::groupOf(ret.regType());
+
+          if (regGroup != retGroup) {
+            // TODO: Conversion is not supported.
+            return DebugUtils::errored(kErrorInvalidAssignment);
+          }
+        }
+      }
+    }
+  }
+
+  // This block has function invokeNode(s).
+  _curBlock->addFlags(RABlock::kFlagHasFuncCalls);
+  _pass->func()->frame().addAttributes(FuncFrame::kAttrHasFuncCalls);
+  _pass->func()->frame().updateCallStackSize(fd.argStackSize());
+
+  return kErrorOk;
+}
+
+Error X86RACFGBuilder::onInvoke(InvokeNode* invokeNode, RAInstBuilder& ib) noexcept {
+  uint32_t argCount = invokeNode->argCount();
+  uint32_t retCount = invokeNode->retCount();
+  const FuncDetail& fd = invokeNode->detail();
+
+  for (uint32_t argIndex = 0; argIndex < argCount; argIndex++) {
+    for (uint32_t argHi = 0; argHi <= kFuncArgHi; argHi += kFuncArgHi) {
+      if (!fd.hasArg(argIndex + argHi))
+        continue;
+
+      const FuncValue& arg = fd.arg(argIndex + argHi);
+      const Operand& op = invokeNode->arg(argIndex + argHi);
+
+      if (op.isNone())
+        continue;
+
+      if (op.isReg()) {
+        const Reg& reg = op.as<Reg>();
+        RAWorkReg* workReg;
+        ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(Operand::virtIdToIndex(reg.id()), &workReg));
+
+        if (arg.isIndirect()) {
+          uint32_t regGroup = workReg->group();
+          if (regGroup != BaseReg::kGroupGp)
+            return DebugUtils::errored(kErrorInvalidState);
+          ASMJIT_PROPAGATE(ib.addCallArg(workReg, arg.regId()));
+        }
+        else if (arg.isReg()) {
+          uint32_t regGroup = workReg->group();
+          uint32_t argGroup = Reg::groupOf(arg.regType());
+
+          if (regGroup == argGroup) {
+            ASMJIT_PROPAGATE(ib.addCallArg(workReg, arg.regId()));
+          }
+        }
+      }
+    }
+  }
+
+  for (uint32_t retIndex = 0; retIndex < retCount; retIndex++) {
+    const FuncValue& ret = fd.ret(retIndex);
+    const Operand& op = invokeNode->ret(retIndex);
+
+    // Not handled here...
+    if (ret.regType() == Reg::kTypeSt)
+      continue;
+
+    if (op.isReg()) {
+      const Reg& reg = op.as<Reg>();
+      RAWorkReg* workReg;
+      ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(Operand::virtIdToIndex(reg.id()), &workReg));
+
+      if (ret.isReg()) {
+        uint32_t regGroup = workReg->group();
+        uint32_t retGroup = Reg::groupOf(ret.regType());
+
+        if (regGroup == retGroup) {
+          ASMJIT_PROPAGATE(ib.addCallRet(workReg, ret.regId()));
+        }
+      }
+      else {
+        return DebugUtils::errored(kErrorInvalidAssignment);
+      }
+    }
+  }
+
+  // Setup clobbered registers.
+  ib._clobbered[0] = Support::lsbMask<uint32_t>(_pass->_physRegCount[0]) & ~fd.preservedRegs(0);
+  ib._clobbered[1] = Support::lsbMask<uint32_t>(_pass->_physRegCount[1]) & ~fd.preservedRegs(1);
+  ib._clobbered[2] = Support::lsbMask<uint32_t>(_pass->_physRegCount[2]) & ~fd.preservedRegs(2);
+  ib._clobbered[3] = Support::lsbMask<uint32_t>(_pass->_physRegCount[3]) & ~fd.preservedRegs(3);
+
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::x86::X86RACFGBuilder - MoveVecToPtr]
+// ============================================================================
+
+static uint32_t x86VecRegSignatureBySize(uint32_t size) noexcept {
+  if (size >= 64)
+    return Zmm::kSignature;
+  else if (size >= 32)
+    return Ymm::kSignature;
+  else
+    return Xmm::kSignature;
+}
+
+Error X86RACFGBuilder::moveVecToPtr(InvokeNode* invokeNode, const FuncValue& arg, const Vec& src, BaseReg* out) noexcept {
+  DebugUtils::unused(invokeNode);
+  ASMJIT_ASSERT(arg.isReg());
+
+  uint32_t argSize = Type::sizeOf(arg.typeId());
+  if (argSize == 0)
+    return DebugUtils::errored(kErrorInvalidState);
+
+  if (argSize < 16)
+    argSize = 16;
+
+  uint32_t argStackOffset = Support::alignUp(invokeNode->detail()._argStackSize, argSize);
+  _funcNode->frame().updateCallStackAlignment(argSize);
+  invokeNode->detail()._argStackSize = argStackOffset + argSize;
+
+  Vec vecReg(x86VecRegSignatureBySize(argSize), src.id());
+  Mem vecPtr = ptr(_pass->_sp.as<Gp>(), int32_t(argStackOffset));
+
+  uint32_t vMovInstId = choose(Inst::kIdMovaps, Inst::kIdVmovaps);
+  if (argSize > 16)
+    vMovInstId = Inst::kIdVmovaps;
+
+  ASMJIT_PROPAGATE(cc()->_newReg(out, cc()->_gpRegInfo.type(), nullptr));
+
+  VirtReg* vReg = cc()->virtRegById(out->id());
+  vReg->setWeight(RAPass::kCallArgWeight);
+
+  ASMJIT_PROPAGATE(cc()->lea(out->as<Gp>(), vecPtr));
+  ASMJIT_PROPAGATE(cc()->emit(vMovInstId, ptr(out->as<Gp>()), vecReg));
+
+  if (arg.isStack()) {
+    Mem stackPtr = ptr(_pass->_sp.as<Gp>(), arg.stackOffset());
+    ASMJIT_PROPAGATE(cc()->mov(stackPtr, out->as<Gp>()));
+  }
+
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::x86::X86RACFGBuilder - MoveImmToRegArg]
+// ============================================================================
+
+Error X86RACFGBuilder::moveImmToRegArg(InvokeNode* invokeNode, const FuncValue& arg, const Imm& imm_, BaseReg* out) noexcept {
+  DebugUtils::unused(invokeNode);
+  ASMJIT_ASSERT(arg.isReg());
+
+  Imm imm(imm_);
+  uint32_t rTypeId = Type::kIdU32;
+
+  switch (arg.typeId()) {
+    case Type::kIdI8: imm.signExtend8Bits(); goto MovU32;
+    case Type::kIdU8: imm.zeroExtend8Bits(); goto MovU32;
+    case Type::kIdI16: imm.signExtend16Bits(); goto MovU32;
+    case Type::kIdU16: imm.zeroExtend16Bits(); goto MovU32;
+
+    case Type::kIdI32:
+    case Type::kIdU32:
+MovU32:
+      imm.zeroExtend32Bits();
+      break;
+
+    case Type::kIdI64:
+    case Type::kIdU64:
+      // Moving to GPD automatically zero extends in 64-bit mode.
+      if (imm.isUInt32()) {
+        imm.zeroExtend32Bits();
+        break;
+      }
+
+      rTypeId = Type::kIdU64;
+      break;
+
+    default:
+      return DebugUtils::errored(kErrorInvalidAssignment);
+  }
+
+  ASMJIT_PROPAGATE(cc()->_newReg(out, rTypeId, nullptr));
+  cc()->virtRegById(out->id())->setWeight(RAPass::kCallArgWeight);
+
+  return cc()->mov(out->as<x86::Gp>(), imm);
+}
+
+// ============================================================================
+// [asmjit::x86::X86RACFGBuilder - MoveImmToStackArg]
+// ============================================================================
+
+Error X86RACFGBuilder::moveImmToStackArg(InvokeNode* invokeNode, const FuncValue& arg, const Imm& imm_) noexcept {
+  DebugUtils::unused(invokeNode);
+  ASMJIT_ASSERT(arg.isStack());
+
+  Mem stackPtr = ptr(_pass->_sp.as<Gp>(), arg.stackOffset());
+  Imm imm[2];
+
+  stackPtr.setSize(4);
+  imm[0] = imm_;
+  uint32_t nMovs = 0;
+
+  // One stack entry has the same size as the native register size. That means
+  // that if we want to move a 32-bit integer on the stack in 64-bit mode, we
+  // need to extend it to a 64-bit integer first. In 32-bit mode, pushing a
+  // 64-bit on stack is done in two steps by pushing low and high parts
+  // separately.
+  switch (arg.typeId()) {
+    case Type::kIdI8: imm[0].signExtend8Bits(); goto MovU32;
+    case Type::kIdU8: imm[0].zeroExtend8Bits(); goto MovU32;
+    case Type::kIdI16: imm[0].signExtend16Bits(); goto MovU32;
+    case Type::kIdU16: imm[0].zeroExtend16Bits(); goto MovU32;
+
+    case Type::kIdI32:
+    case Type::kIdU32:
+    case Type::kIdF32:
+MovU32:
+      imm[0].zeroExtend32Bits();
+      nMovs = 1;
+      break;
+
+    case Type::kIdI64:
+    case Type::kIdU64:
+    case Type::kIdF64:
+    case Type::kIdMmx32:
+    case Type::kIdMmx64:
+      if (_is64Bit && imm[0].isInt32()) {
+        stackPtr.setSize(8);
+        nMovs = 1;
+        break;
+      }
+
+      imm[1].setValue(imm[0].uint32Hi());
+      imm[0].zeroExtend32Bits();
+      nMovs = 2;
+      break;
+
+    default:
+      return DebugUtils::errored(kErrorInvalidAssignment);
+  }
+
+  for (uint32_t i = 0; i < nMovs; i++) {
+    ASMJIT_PROPAGATE(cc()->mov(stackPtr, imm[i]));
+    stackPtr.addOffsetLo32(int32_t(stackPtr.size()));
+  }
+
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::x86::X86RACFGBuilder - MoveRegToStackArg]
+// ============================================================================
+
+Error X86RACFGBuilder::moveRegToStackArg(InvokeNode* invokeNode, const FuncValue& arg, const BaseReg& reg) noexcept {
+  DebugUtils::unused(invokeNode);
+  ASMJIT_ASSERT(arg.isStack());
+
+  Mem stackPtr = ptr(_pass->_sp.as<Gp>(), arg.stackOffset());
+  Reg r0, r1;
+
+  VirtReg* vr = cc()->virtRegById(reg.id());
+  uint32_t registerSize = cc()->registerSize();
+  uint32_t instId = 0;
+
+  uint32_t dstTypeId = arg.typeId();
+  uint32_t srcTypeId = vr->typeId();
+
+  switch (dstTypeId) {
+    case Type::kIdI64:
+    case Type::kIdU64:
+      // Extend BYTE->QWORD (GP).
+      if (Type::isGp8(srcTypeId)) {
+        r1.setRegT<Reg::kTypeGpbLo>(reg.id());
+
+        instId = (dstTypeId == Type::kIdI64 && srcTypeId == Type::kIdI8) ? Inst::kIdMovsx : Inst::kIdMovzx;
+        goto ExtendMovGpXQ;
+      }
+
+      // Extend WORD->QWORD (GP).
+      if (Type::isGp16(srcTypeId)) {
+        r1.setRegT<Reg::kTypeGpw>(reg.id());
+
+        instId = (dstTypeId == Type::kIdI64 && srcTypeId == Type::kIdI16) ? Inst::kIdMovsx : Inst::kIdMovzx;
+        goto ExtendMovGpXQ;
+      }
+
+      // Extend DWORD->QWORD (GP).
+      if (Type::isGp32(srcTypeId)) {
+        r1.setRegT<Reg::kTypeGpd>(reg.id());
+
+        instId = Inst::kIdMovsxd;
+        if (dstTypeId == Type::kIdI64 && srcTypeId == Type::kIdI32)
+          goto ExtendMovGpXQ;
+        else
+          goto ZeroExtendGpDQ;
+      }
+
+      // Move QWORD (GP).
+      if (Type::isGp64(srcTypeId)) goto MovGpQ;
+      if (Type::isMmx(srcTypeId)) goto MovMmQ;
+      if (Type::isVec(srcTypeId)) goto MovXmmQ;
+      break;
+
+    case Type::kIdI32:
+    case Type::kIdU32:
+    case Type::kIdI16:
+    case Type::kIdU16:
+      // DWORD <- WORD (Zero|Sign Extend).
+      if (Type::isGp16(srcTypeId)) {
+        bool isDstSigned = dstTypeId == Type::kIdI16 || dstTypeId == Type::kIdI32;
+        bool isSrcSigned = srcTypeId == Type::kIdI8  || srcTypeId == Type::kIdI16;
+
+        r1.setRegT<Reg::kTypeGpw>(reg.id());
+        instId = isDstSigned && isSrcSigned ? Inst::kIdMovsx : Inst::kIdMovzx;
+        goto ExtendMovGpD;
+      }
+
+      // DWORD <- BYTE (Zero|Sign Extend).
+      if (Type::isGp8(srcTypeId)) {
+        bool isDstSigned = dstTypeId == Type::kIdI16 || dstTypeId == Type::kIdI32;
+        bool isSrcSigned = srcTypeId == Type::kIdI8  || srcTypeId == Type::kIdI16;
+
+        r1.setRegT<Reg::kTypeGpbLo>(reg.id());
+        instId = isDstSigned && isSrcSigned ? Inst::kIdMovsx : Inst::kIdMovzx;
+        goto ExtendMovGpD;
+      }
+      ASMJIT_FALLTHROUGH;
+
+    case Type::kIdI8:
+    case Type::kIdU8:
+      if (Type::isInt(srcTypeId)) goto MovGpD;
+      if (Type::isMmx(srcTypeId)) goto MovMmD;
+      if (Type::isVec(srcTypeId)) goto MovXmmD;
+      break;
+
+    case Type::kIdMmx32:
+    case Type::kIdMmx64:
+      // Extend BYTE->QWORD (GP).
+      if (Type::isGp8(srcTypeId)) {
+        r1.setRegT<Reg::kTypeGpbLo>(reg.id());
+
+        instId = Inst::kIdMovzx;
+        goto ExtendMovGpXQ;
+      }
+
+      // Extend WORD->QWORD (GP).
+      if (Type::isGp16(srcTypeId)) {
+        r1.setRegT<Reg::kTypeGpw>(reg.id());
+
+        instId = Inst::kIdMovzx;
+        goto ExtendMovGpXQ;
+      }
+
+      if (Type::isGp32(srcTypeId)) goto ExtendMovGpDQ;
+      if (Type::isGp64(srcTypeId)) goto MovGpQ;
+      if (Type::isMmx(srcTypeId)) goto MovMmQ;
+      if (Type::isVec(srcTypeId)) goto MovXmmQ;
+      break;
+
+    case Type::kIdF32:
+    case Type::kIdF32x1:
+      if (Type::isVec(srcTypeId)) goto MovXmmD;
+      break;
+
+    case Type::kIdF64:
+    case Type::kIdF64x1:
+      if (Type::isVec(srcTypeId)) goto MovXmmQ;
+      break;
+
+    default:
+      if (Type::isVec(dstTypeId) && reg.as<Reg>().isVec()) {
+        stackPtr.setSize(Type::sizeOf(dstTypeId));
+        uint32_t vMovInstId = choose(Inst::kIdMovaps, Inst::kIdVmovaps);
+
+        if (Type::isVec128(dstTypeId))
+          r0.setRegT<Reg::kTypeXmm>(reg.id());
+        else if (Type::isVec256(dstTypeId))
+          r0.setRegT<Reg::kTypeYmm>(reg.id());
+        else if (Type::isVec512(dstTypeId))
+          r0.setRegT<Reg::kTypeZmm>(reg.id());
+        else
+          break;
+
+        return cc()->emit(vMovInstId, stackPtr, r0);
+      }
+      break;
+  }
+  return DebugUtils::errored(kErrorInvalidAssignment);
+
+  // Extend+Move Gp.
+ExtendMovGpD:
+  stackPtr.setSize(4);
+  r0.setRegT<Reg::kTypeGpd>(reg.id());
+
+  ASMJIT_PROPAGATE(cc()->emit(instId, r0, r1));
+  ASMJIT_PROPAGATE(cc()->emit(Inst::kIdMov, stackPtr, r0));
+  return kErrorOk;
+
+ExtendMovGpXQ:
+  if (registerSize == 8) {
+    stackPtr.setSize(8);
+    r0.setRegT<Reg::kTypeGpq>(reg.id());
+
+    ASMJIT_PROPAGATE(cc()->emit(instId, r0, r1));
+    ASMJIT_PROPAGATE(cc()->emit(Inst::kIdMov, stackPtr, r0));
+  }
+  else {
+    stackPtr.setSize(4);
+    r0.setRegT<Reg::kTypeGpd>(reg.id());
+
+    ASMJIT_PROPAGATE(cc()->emit(instId, r0, r1));
+
+ExtendMovGpDQ:
+    ASMJIT_PROPAGATE(cc()->emit(Inst::kIdMov, stackPtr, r0));
+    stackPtr.addOffsetLo32(4);
+    ASMJIT_PROPAGATE(cc()->emit(Inst::kIdAnd, stackPtr, 0));
+  }
+  return kErrorOk;
+
+ZeroExtendGpDQ:
+  stackPtr.setSize(4);
+  r0.setRegT<Reg::kTypeGpd>(reg.id());
+  goto ExtendMovGpDQ;
+
+MovGpD:
+  stackPtr.setSize(4);
+  r0.setRegT<Reg::kTypeGpd>(reg.id());
+  return cc()->emit(Inst::kIdMov, stackPtr, r0);
+
+MovGpQ:
+  stackPtr.setSize(8);
+  r0.setRegT<Reg::kTypeGpq>(reg.id());
+  return cc()->emit(Inst::kIdMov, stackPtr, r0);
+
+MovMmD:
+  stackPtr.setSize(4);
+  r0.setRegT<Reg::kTypeMm>(reg.id());
+  return cc()->emit(choose(Inst::kIdMovd, Inst::kIdVmovd), stackPtr, r0);
+
+MovMmQ:
+  stackPtr.setSize(8);
+  r0.setRegT<Reg::kTypeMm>(reg.id());
+  return cc()->emit(choose(Inst::kIdMovq, Inst::kIdVmovq), stackPtr, r0);
+
+MovXmmD:
+  stackPtr.setSize(4);
+  r0.setRegT<Reg::kTypeXmm>(reg.id());
+  return cc()->emit(choose(Inst::kIdMovss, Inst::kIdVmovss), stackPtr, r0);
+
+MovXmmQ:
+  stackPtr.setSize(8);
+  r0.setRegT<Reg::kTypeXmm>(reg.id());
+  return cc()->emit(choose(Inst::kIdMovlps, Inst::kIdVmovlps), stackPtr, r0);
+}
+
+// ============================================================================
+// [asmjit::x86::X86RACFGBuilder - OnReg]
+// ============================================================================
+
+Error X86RACFGBuilder::onBeforeRet(FuncRetNode* funcRet) noexcept {
+  const FuncDetail& funcDetail = _pass->func()->detail();
+  const Operand* opArray = funcRet->operands();
+  uint32_t opCount = funcRet->opCount();
+
+  cc()->_setCursor(funcRet->prev());
+
+  for (uint32_t i = 0; i < opCount; i++) {
+    const Operand& op = opArray[i];
+    const FuncValue& ret = funcDetail.ret(i);
+
+    if (!op.isReg())
+      continue;
+
+    if (ret.regType() == Reg::kTypeSt) {
+      const Reg& reg = op.as<Reg>();
+      uint32_t vIndex = Operand::virtIdToIndex(reg.id());
+
+      if (vIndex < Operand::kVirtIdCount) {
+        RAWorkReg* workReg;
+        ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(vIndex, &workReg));
+
+        if (workReg->group() != Reg::kGroupVec)
+          return DebugUtils::errored(kErrorInvalidAssignment);
+
+        Reg src = Reg(workReg->signature(), workReg->virtId());
+        Mem mem;
+
+        uint32_t typeId = Type::baseOf(workReg->typeId());
+        if (ret.hasTypeId())
+          typeId = ret.typeId();
+
+        switch (typeId) {
+          case Type::kIdF32:
+            ASMJIT_PROPAGATE(_pass->useTemporaryMem(mem, 4, 4));
+            mem.setSize(4);
+            ASMJIT_PROPAGATE(cc()->emit(choose(Inst::kIdMovss, Inst::kIdVmovss), mem, src.as<Xmm>()));
+            ASMJIT_PROPAGATE(cc()->fld(mem));
+            break;
+
+          case Type::kIdF64:
+            ASMJIT_PROPAGATE(_pass->useTemporaryMem(mem, 8, 4));
+            mem.setSize(8);
+            ASMJIT_PROPAGATE(cc()->emit(choose(Inst::kIdMovsd, Inst::kIdVmovsd), mem, src.as<Xmm>()));
+            ASMJIT_PROPAGATE(cc()->fld(mem));
+            break;
+
+          default:
+            return DebugUtils::errored(kErrorInvalidAssignment);
+        }
+      }
+    }
+  }
+
+  return kErrorOk;
+}
+
+Error X86RACFGBuilder::onRet(FuncRetNode* funcRet, RAInstBuilder& ib) noexcept {
+  const FuncDetail& funcDetail = _pass->func()->detail();
+  const Operand* opArray = funcRet->operands();
+  uint32_t opCount = funcRet->opCount();
+
+  for (uint32_t i = 0; i < opCount; i++) {
+    const Operand& op = opArray[i];
+    if (op.isNone()) continue;
+
+    const FuncValue& ret = funcDetail.ret(i);
+    if (ASMJIT_UNLIKELY(!ret.isReg()))
+      return DebugUtils::errored(kErrorInvalidAssignment);
+
+    // Not handled here...
+    if (ret.regType() == Reg::kTypeSt)
+      continue;
+
+    if (op.isReg()) {
+      // Register return value.
+      const Reg& reg = op.as<Reg>();
+      uint32_t vIndex = Operand::virtIdToIndex(reg.id());
+
+      if (vIndex < Operand::kVirtIdCount) {
+        RAWorkReg* workReg;
+        ASMJIT_PROPAGATE(_pass->virtIndexAsWorkReg(vIndex, &workReg));
+
+        uint32_t group = workReg->group();
+        uint32_t allocable = _pass->_availableRegs[group];
+        ASMJIT_PROPAGATE(ib.add(workReg, RATiedReg::kUse | RATiedReg::kRead, allocable, ret.regId(), 0, BaseReg::kIdBad, 0));
+      }
+    }
+    else {
+      return DebugUtils::errored(kErrorInvalidAssignment);
+    }
+  }
+
+  return kErrorOk;
+}
+
+// ============================================================================
+// [asmjit::x86::X86RAPass - Construction / Destruction]
+// ============================================================================
+
+X86RAPass::X86RAPass() noexcept
+  : RAPass(),
+    _avxEnabled(false) {}
+X86RAPass::~X86RAPass() noexcept {}
+
+// ============================================================================
+// [asmjit::x86::X86RAPass - OnInit / OnDone]
+// ============================================================================
+
+void X86RAPass::onInit() noexcept {
+  uint32_t arch = cc()->arch();
+  uint32_t baseRegCount = Environment::is32Bit(arch) ? 8u : 16u;
+
+  _archRegsInfo = &opData.archRegs;
+  _archTraits[Reg::kGroupGp] |= RAArchTraits::kHasSwap;
+
+  _physRegCount.set(Reg::kGroupGp  , baseRegCount);
+  _physRegCount.set(Reg::kGroupVec , baseRegCount);
+  _physRegCount.set(Reg::kGroupMm  , 8);
+  _physRegCount.set(Reg::kGroupKReg, 8);
+  _buildPhysIndex();
+
+  _availableRegCount = _physRegCount;
+  _availableRegs[Reg::kGroupGp  ] = Support::lsbMask<uint32_t>(_physRegCount.get(Reg::kGroupGp  ));
+  _availableRegs[Reg::kGroupVec ] = Support::lsbMask<uint32_t>(_physRegCount.get(Reg::kGroupVec ));
+  _availableRegs[Reg::kGroupMm  ] = Support::lsbMask<uint32_t>(_physRegCount.get(Reg::kGroupMm  ));
+  _availableRegs[Reg::kGroupKReg] = Support::lsbMask<uint32_t>(_physRegCount.get(Reg::kGroupKReg));
+
+  _scratchRegIndexes[0] = uint8_t(Gp::kIdCx);
+  _scratchRegIndexes[1] = uint8_t(baseRegCount - 1);
+
+  // The architecture specific setup makes implicitly all registers available. So
+  // make unavailable all registers that are special and cannot be used in general.
+  bool hasFP = _func->frame().hasPreservedFP();
+
+  makeUnavailable(Reg::kGroupGp, Gp::kIdSp);            // ESP|RSP used as a stack-pointer (SP).
+  if (hasFP) makeUnavailable(Reg::kGroupGp, Gp::kIdBp); // EBP|RBP used as a frame-pointer (FP).
+
+  _sp = cc()->zsp();
+  _fp = cc()->zbp();
+  _avxEnabled = _func->frame().isAvxEnabled();
+}
+
+void X86RAPass::onDone() noexcept {}
+
+// ============================================================================
+// [asmjit::x86::X86RAPass - BuildCFG]
+// ============================================================================
+
+Error X86RAPass::buildCFG() noexcept {
+  return X86RACFGBuilder(this).run();
+}
+
+// ============================================================================
+// [asmjit::x86::X86RAPass - OnEmit]
+// ============================================================================
+
+Error X86RAPass::onEmitMove(uint32_t workId, uint32_t dstPhysId, uint32_t srcPhysId) noexcept {
+  RAWorkReg* wReg = workRegById(workId);
+  BaseReg dst(wReg->info().signature(), dstPhysId);
+  BaseReg src(wReg->info().signature(), srcPhysId);
+
+  const char* comment = nullptr;
+
+#ifndef ASMJIT_NO_LOGGING
+  if (_loggerFlags & FormatOptions::kFlagAnnotations) {
+    _tmpString.assignFormat("<MOVE> %s", workRegById(workId)->name());
+    comment = _tmpString.data();
+  }
+#endif
+
+  return X86Internal::emitRegMove(cc()->as<Emitter>(), dst, src, wReg->typeId(), _avxEnabled, comment);
+}
+
+Error X86RAPass::onEmitSwap(uint32_t aWorkId, uint32_t aPhysId, uint32_t bWorkId, uint32_t bPhysId) noexcept {
+  RAWorkReg* waReg = workRegById(aWorkId);
+  RAWorkReg* wbReg = workRegById(bWorkId);
+
+  bool is64Bit = Support::max(waReg->typeId(), wbReg->typeId()) >= Type::kIdI64;
+  uint32_t sign = is64Bit ? uint32_t(RegTraits<Reg::kTypeGpq>::kSignature)
+                          : uint32_t(RegTraits<Reg::kTypeGpd>::kSignature);
+
+#ifndef ASMJIT_NO_LOGGING
+  if (_loggerFlags & FormatOptions::kFlagAnnotations) {
+    _tmpString.assignFormat("<SWAP> %s, %s", waReg->name(), wbReg->name());
+    cc()->setInlineComment(_tmpString.data());
+  }
+#endif
+
+  return cc()->emit(Inst::kIdXchg, Reg(sign, aPhysId), Reg(sign, bPhysId));
+}
+
+Error X86RAPass::onEmitLoad(uint32_t workId, uint32_t dstPhysId) noexcept {
+  RAWorkReg* wReg = workRegById(workId);
+  BaseReg dstReg(wReg->info().signature(), dstPhysId);
+  BaseMem srcMem(workRegAsMem(wReg));
+
+  const char* comment = nullptr;
+
+#ifndef ASMJIT_NO_LOGGING
+  if (_loggerFlags & FormatOptions::kFlagAnnotations) {
+    _tmpString.assignFormat("<LOAD> %s", workRegById(workId)->name());
+    comment = _tmpString.data();
+  }
+#endif
+
+  return X86Internal::emitRegMove(cc()->as<Emitter>(), dstReg, srcMem, wReg->typeId(), _avxEnabled, comment);
+}
+
+Error X86RAPass::onEmitSave(uint32_t workId, uint32_t srcPhysId) noexcept {
+  RAWorkReg* wReg = workRegById(workId);
+  BaseMem dstMem(workRegAsMem(wReg));
+  BaseReg srcReg(wReg->info().signature(), srcPhysId);
+
+  const char* comment = nullptr;
+
+#ifndef ASMJIT_NO_LOGGING
+  if (_loggerFlags & FormatOptions::kFlagAnnotations) {
+    _tmpString.assignFormat("<SAVE> %s", workRegById(workId)->name());
+    comment = _tmpString.data();
+  }
+#endif
+
+  return X86Internal::emitRegMove(cc()->as<Emitter>(), dstMem, srcReg, wReg->typeId(), _avxEnabled, comment);
+}
+
+Error X86RAPass::onEmitJump(const Label& label) noexcept {
+  return cc()->jmp(label);
+}
+
+Error X86RAPass::onEmitPreCall(InvokeNode* invokeNode) noexcept {
+  if (invokeNode->detail().hasVarArgs() && cc()->is64Bit()) {
+    uint32_t argCount = invokeNode->argCount();
+    const FuncDetail& fd = invokeNode->detail();
+
+    switch (invokeNode->detail().callConv().id()) {
+      case CallConv::kIdX64SystemV: {
+        // AL register contains the number of arguments passed in XMM register(s).
+        uint32_t n = 0;
+        for (uint32_t argIndex = 0; argIndex < argCount; argIndex++) {
+          for (uint32_t argHi = 0; argHi <= kFuncArgHi; argHi += kFuncArgHi) {
+            if (!fd.hasArg(argIndex + argHi))
+              continue;
+
+            const FuncValue& arg = fd.arg(argIndex + argHi);
+            if (arg.isReg() && Reg::groupOf(arg.regType()) == Reg::kGroupVec)
+              n++;
+          }
+        }
+
+        if (!n)
+          ASMJIT_PROPAGATE(cc()->xor_(eax, eax));
+        else
+          ASMJIT_PROPAGATE(cc()->mov(eax, n));
+        break;
+      }
+
+      case CallConv::kIdX64Windows: {
+        // Each double-precision argument passed in XMM must be also passed in GP.
+        for (uint32_t argIndex = 0; argIndex < argCount; argIndex++) {
+          for (uint32_t argHi = 0; argHi <= kFuncArgHi; argHi += kFuncArgHi) {
+            if (!fd.hasArg(argIndex + argHi))
+              continue;
+
+            const FuncValue& arg = fd.arg(argIndex + argHi);
+            if (arg.isReg() && Reg::groupOf(arg.regType()) == Reg::kGroupVec) {
+              Gp dst = gpq(fd.callConv().passedOrder(Reg::kGroupGp)[argIndex]);
+              Xmm src = xmm(arg.regId());
+              ASMJIT_PROPAGATE(cc()->emit(choose(Inst::kIdMovq, Inst::kIdVmovq), dst, src));
+            }
+          }
+        }
+        break;
+      }
+
+      default:
+        return DebugUtils::errored(kErrorInvalidState);
+    }
+  }
+
+  return kErrorOk;
+}
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // ASMJIT_BUILD_X86 && !ASMJIT_NO_COMPILER
diff --git a/client/asmjit/x86/x86rapass_p.h b/client/asmjit/x86/x86rapass_p.h
new file mode 100644
index 0000000..99093ab
--- /dev/null
+++ b/client/asmjit/x86/x86rapass_p.h
@@ -0,0 +1,115 @@
+// AsmJit - Machine code generation for C++
+//
+//  * Official AsmJit Home Page: https://asmjit.com
+//  * Official Github Repository: https://github.com/asmjit/asmjit
+//
+// Copyright (c) 2008-2020 The AsmJit Authors
+//
+// This software is provided 'as-is', without any express or implied
+// warranty. In no event will the authors be held liable for any damages
+// arising from the use of this software.
+//
+// Permission is granted to anyone to use this software for any purpose,
+// including commercial applications, and to alter it and redistribute it
+// freely, subject to the following restrictions:
+//
+// 1. The origin of this software must not be misrepresented; you must not
+//    claim that you wrote the original software. If you use this software
+//    in a product, an acknowledgment in the product documentation would be
+//    appreciated but is not required.
+// 2. Altered source versions must be plainly marked as such, and must not be
+//    misrepresented as being the original software.
+// 3. This notice may not be removed or altered from any source distribution.
+
+#ifndef ASMJIT_X86_X86RAPASS_P_H_INCLUDED
+#define ASMJIT_X86_X86RAPASS_P_H_INCLUDED
+
+#include "../core/api-config.h"
+#ifndef ASMJIT_NO_COMPILER
+
+#include "../core/compiler.h"
+#include "../core/rabuilders_p.h"
+#include "../core/rapass_p.h"
+#include "../x86/x86assembler.h"
+#include "../x86/x86compiler.h"
+
+ASMJIT_BEGIN_SUB_NAMESPACE(x86)
+
+//! \cond INTERNAL
+
+//! \brief X86/X64 register allocation.
+
+//! \addtogroup asmjit_ra
+//! \{
+
+// ============================================================================
+// [asmjit::X86RAPass]
+// ============================================================================
+
+//! X86 register allocation pass.
+//!
+//! Takes care of generating function prologs and epilogs, and also performs
+//! register allocation.
+class X86RAPass : public RAPass {
+public:
+  ASMJIT_NONCOPYABLE(X86RAPass)
+  typedef RAPass Base;
+
+  bool _avxEnabled;
+
+  // --------------------------------------------------------------------------
+  // [Construction / Destruction]
+  // --------------------------------------------------------------------------
+
+  X86RAPass() noexcept;
+  virtual ~X86RAPass() noexcept;
+
+  // --------------------------------------------------------------------------
+  // [Accessors]
+  // --------------------------------------------------------------------------
+
+  //! Returns the compiler casted to `x86::Compiler`.
+  inline Compiler* cc() const noexcept { return static_cast<Compiler*>(_cb); }
+
+  // --------------------------------------------------------------------------
+  // [Utilities]
+  // --------------------------------------------------------------------------
+
+  inline uint32_t choose(uint32_t sseInstId, uint32_t avxInstId) noexcept {
+    return _avxEnabled ? avxInstId : sseInstId;
+  }
+
+  // --------------------------------------------------------------------------
+  // [OnInit / OnDone]
+  // --------------------------------------------------------------------------
+
+  void onInit() noexcept override;
+  void onDone() noexcept override;
+
+  // --------------------------------------------------------------------------
+  // [CFG]
+  // --------------------------------------------------------------------------
+
+  Error buildCFG() noexcept override;
+
+  // --------------------------------------------------------------------------
+  // [Emit]
+  // --------------------------------------------------------------------------
+
+  Error onEmitMove(uint32_t workId, uint32_t dstPhysId, uint32_t srcPhysId) noexcept override;
+  Error onEmitSwap(uint32_t aWorkId, uint32_t aPhysId, uint32_t bWorkId, uint32_t bPhysId) noexcept override;
+
+  Error onEmitLoad(uint32_t workId, uint32_t dstPhysId) noexcept override;
+  Error onEmitSave(uint32_t workId, uint32_t srcPhysId) noexcept override;
+
+  Error onEmitJump(const Label& label) noexcept override;
+  Error onEmitPreCall(InvokeNode* invokeNode) noexcept override;
+};
+
+//! \}
+//! \endcond
+
+ASMJIT_END_SUB_NAMESPACE
+
+#endif // !ASMJIT_NO_COMPILER
+#endif // ASMJIT_X86_X86RAPASS_P_H_INCLUDED