Merge pull request #4 from FenrirWolf/master

Compatibility fixes + new bindings + refactoring

6 files changed, 1093 insertions, 0 deletions

diff --git a/ctru-sys/src/gpu/gpu.rs b/ctru-sys/src/gpu/gpu.rs
new file mode 100644
index 0000000..30e7a03
--- /dev/null
+++ b/ctru-sys/src/gpu/gpu.rs
@@ -0,0 +1,26 @@
+/* automatically generated by rust-bindgen */
+
+#[inline]
+pub fn GPUCMD_HEADER(incremental: u32, mask: u32, reg: u32) -> u32{
+    (((incremental)<<31)|(((mask)&0xF)<<16)|((reg)&0x3FF))
+}
+
+extern "C" {
+    pub static mut gpuCmdBuf: *mut u32;
+    pub static mut gpuCmdBufSize: u32;
+    pub static mut gpuCmdBufOffset: u32;
+
+    pub fn GPUCMD_SetBuffer(adr: *mut u32, size: u32, offset: u32);
+    pub fn GPUCMD_SetBufferOffset(offset: u32);
+    pub fn GPUCMD_GetBuffer(adr: *mut *mut u32, size: *mut u32,
+                            offset: *mut u32);
+    pub fn GPUCMD_AddRawCommands(cmd: *mut u32, size: u32);
+    pub fn GPUCMD_Run();
+    pub fn GPUCMD_FlushAndRun();
+    pub fn GPUCMD_Add(header: u32, param: *mut u32, paramlength: u32);
+    pub fn GPUCMD_Finalize();
+    pub fn f32tof16(f: f32) -> u32;
+    pub fn f32tof20(f: f32) -> u32;
+    pub fn f32tof24(f: f32) -> u32;
+    pub fn f32tof31(f: f32) -> u32; 
+}
diff --git a/ctru-sys/src/gpu/gx.rs b/ctru-sys/src/gpu/gx.rs
new file mode 100644
index 0000000..69eeddf
--- /dev/null
+++ b/ctru-sys/src/gpu/gx.rs
@@ -0,0 +1,94 @@
+use ::Result;
+
+#[inline]
+pub fn GX_BUFFER_DIM(w: u32, h: u32) {
+    (((h)<<16)|((w)&0xFFFF));
+}
+
+#[repr(C)]
+pub enum GX_TRANSFER_FORMAT
+{
+	GX_TRANSFER_FMT_RGBA8  = 0,
+	GX_TRANSFER_FMT_RGB8   = 1,
+	GX_TRANSFER_FMT_RGB565 = 2,
+	GX_TRANSFER_FMT_RGB5A1 = 3,
+	GX_TRANSFER_FMT_RGBA4  = 4,
+}
+
+#[repr(C)]
+pub enum GX_TRANSFER_SCALE
+{
+	GX_TRANSFER_SCALE_NO = 0,
+	GX_TRANSFER_SCALE_X  = 1,
+	GX_TRANSFER_SCALE_Y  = 2,
+}
+
+#[repr(C)]
+pub enum GX_FILL_CONTROL {
+	GX_FILL_TRIGGER     = 0x001,
+	GX_FILL_FINISHED    = 0x002,
+	GX_FILL_16BIT_DEPTH = 0x000,
+	GX_FILL_24BIT_DEPTH = 0x100,
+	GX_FILL_32BIT_DEPTH = 0x200,
+}
+
+#[inline]
+pub fn GX_TRANSFER_FLIP_VERT(x: i32) {
+    ((x)<<0);
+}
+
+#[inline]
+pub fn GX_TRANSFER_OUT_TILED(x: i32) {
+    ((x)<<1);
+}
+
+#[inline]
+pub fn GX_TRANSFER_RAW_COPY(x: i32) {
+    ((x)<<3);
+}
+
+#[inline]
+pub fn GX_TRANSFER_IN_FORMAT(x: i32)  {
+    ((x)<<8);
+}
+
+#[inline]
+pub fn GX_TRANSFER_OUT_FORMAT(x: i32) {
+    ((x)<<12);
+}
+
+#[inline]
+pub fn GX_TRANSFER_SCALING(x: i32) {
+    ((x)<<24);
+}
+
+#[inline]
+pub fn GX_CMDLIST_BIT0() {
+    (1u32<<(0));
+}
+
+#[inline]
+pub fn GX_CMNDLIST_FLUSH() {
+    (1u32<<(1));
+}
+
+extern "C" {
+    pub static mut gxCmdBuf: *mut u32;
+
+    pub fn GX_RequestDma(src: *mut u32, dst: *mut u32, length: u32)
+     -> Result;
+    pub fn GX_ProcessCommandList(buf0a: *mut u32, buf0s: u32, flags: u8)
+     -> Result;
+    pub fn GX_MemoryFill(buf0a: *mut u32, buf0v: u32, buf0e: *mut u32,
+                         control0: u16, buf1a: *mut u32, buf1v: u32,
+                         buf1e: *mut u32, control1: u16) -> Result;
+    pub fn GX_DisplayTransfer(inadr: *mut u32, indim: u32,
+                              outadr: *mut u32, outdim: u32, flags: u32)
+     -> Result;
+    pub fn GX_TextureCopy(inadr: *mut u32, indim: u32, outadr: *mut u32,
+                          outdim: u32, size: u32, flags: u32) -> Result;
+    pub fn GX_FlushCacheRegions(buf0a: *mut u32, buf0s: u32,
+                                buf1a: *mut u32, buf1s: u32,
+                                buf2a: *mut u32, buf2s: u32) -> Result;
+}
+
diff --git a/ctru-sys/src/gpu/mod.rs b/ctru-sys/src/gpu/mod.rs
new file mode 100644
index 0000000..2b9cb99
--- /dev/null
+++ b/ctru-sys/src/gpu/mod.rs
@@ -0,0 +1,5 @@
+pub mod gpu;
+pub mod gx;
+pub mod registers;
+pub mod shaderProgram;
+pub mod shbin;
diff --git a/ctru-sys/src/gpu/registers.rs b/ctru-sys/src/gpu/registers.rs
new file mode 100644
index 0000000..98b2a3b
--- /dev/null
+++ b/ctru-sys/src/gpu/registers.rs
@@ -0,0 +1,743 @@
+//Miscellaneous registers (0x000-0x03F)
+pub const GPUREG_0000: i32 = 0x0000;
+pub const GPUREG_0001: i32 = 0x0001;
+pub const GPUREG_0002: i32 = 0x0002;
+pub const GPUREG_0003: i32 = 0x0003;
+pub const GPUREG_0004: i32 = 0x0004;
+pub const GPUREG_0005: i32 = 0x0005;
+pub const GPUREG_0006: i32 = 0x0006;
+pub const GPUREG_0007: i32 = 0x0007;
+pub const GPUREG_0008: i32 = 0x0008;
+pub const GPUREG_0009: i32 = 0x0009;
+pub const GPUREG_000A: i32 = 0x000A;
+pub const GPUREG_000B: i32 = 0x000B;
+pub const GPUREG_000C: i32 = 0x000C;
+pub const GPUREG_000D: i32 = 0x000D;
+pub const GPUREG_000E: i32 = 0x000E;
+pub const GPUREG_000F: i32 = 0x000F;
+pub const GPUREG_FINALIZE: i32 = 0x0010;
+pub const GPUREG_0011: i32 = 0x0011;
+pub const GPUREG_0012: i32 = 0x0012;
+pub const GPUREG_0013: i32 = 0x0013;
+pub const GPUREG_0014: i32 = 0x0014;
+pub const GPUREG_0015: i32 = 0x0015;
+pub const GPUREG_0016: i32 = 0x0016;
+pub const GPUREG_0017: i32 = 0x0017;
+pub const GPUREG_0018: i32 = 0x0018;
+pub const GPUREG_0019: i32 = 0x0019;
+pub const GPUREG_001A: i32 = 0x001A;
+pub const GPUREG_001B: i32 = 0x001B;
+pub const GPUREG_001C: i32 = 0x001C;
+pub const GPUREG_001D: i32 = 0x001D;
+pub const GPUREG_001E: i32 = 0x001E;
+pub const GPUREG_001F: i32 = 0x001F;
+pub const GPUREG_0020: i32 = 0x0020;
+pub const GPUREG_0021: i32 = 0x0021;
+pub const GPUREG_0022: i32 = 0x0022;
+pub const GPUREG_0023: i32 = 0x0023;
+pub const GPUREG_0024: i32 = 0x0024;
+pub const GPUREG_0025: i32 = 0x0025;
+pub const GPUREG_0026: i32 = 0x0026;
+pub const GPUREG_0027: i32 = 0x0027;
+pub const GPUREG_0028: i32 = 0x0028;
+pub const GPUREG_0029: i32 = 0x0029;
+pub const GPUREG_002A: i32 = 0x002A;
+pub const GPUREG_002B: i32 = 0x002B;
+pub const GPUREG_002C: i32 = 0x002C;
+pub const GPUREG_002D: i32 = 0x002D;
+pub const GPUREG_002E: i32 = 0x002E;
+pub const GPUREG_002F: i32 = 0x002F;
+pub const GPUREG_0030: i32 = 0x0030;
+pub const GPUREG_0031: i32 = 0x0031;
+pub const GPUREG_0032: i32 = 0x0032;
+pub const GPUREG_0033: i32 = 0x0033;
+pub const GPUREG_0034: i32 = 0x0034;
+pub const GPUREG_0035: i32 = 0x0035;
+pub const GPUREG_0036: i32 = 0x0036;
+pub const GPUREG_0037: i32 = 0x0037;
+pub const GPUREG_0038: i32 = 0x0038;
+pub const GPUREG_0039: i32 = 0x0039;
+pub const GPUREG_003A: i32 = 0x003A;
+pub const GPUREG_003B: i32 = 0x003B;
+pub const GPUREG_003C: i32 = 0x003C;
+pub const GPUREG_003D: i32 = 0x003D;
+pub const GPUREG_003E: i32 = 0x003E;
+pub const GPUREG_003F: i32 = 0x003F;
+
+//Rasterizer registers (0x040-0x07F)
+pub const GPUREG_FACECULLING_CONFIG: i32 = 0x0040;
+pub const GPUREG_0041: i32 = 0x0041;
+pub const GPUREG_0042: i32 = 0x0042;
+pub const GPUREG_0043: i32 = 0x0043;
+pub const GPUREG_0044: i32 = 0x0044;
+pub const GPUREG_0045: i32 = 0x0045;
+pub const GPUREG_0046: i32 = 0x0046;
+pub const GPUREG_0047: i32 = 0x0047;
+pub const GPUREG_0048: i32 = 0x0048;
+pub const GPUREG_0049: i32 = 0x0049;
+pub const GPUREG_004A: i32 = 0x004A;
+pub const GPUREG_004B: i32 = 0x004B;
+pub const GPUREG_004C: i32 = 0x004C;
+pub const GPUREG_DEPTHMAP_SCALE: i32 = 0x004D;
+pub const GPUREG_DEPTHMAP_OFFSET: i32 = 0x004E;
+pub const GPUREG_SH_OUTMAP_TOTAL: i32 = 0x004F;
+pub const GPUREG_SH_OUTMAP_O0: i32 = 0x0050;
+pub const GPUREG_SH_OUTMAP_O1: i32 = 0x0051;
+pub const GPUREG_SH_OUTMAP_O2: i32 = 0x0052;
+pub const GPUREG_SH_OUTMAP_O3: i32 = 0x0053;
+pub const GPUREG_SH_OUTMAP_O4: i32 = 0x0054;
+pub const GPUREG_SH_OUTMAP_O5: i32 = 0x0055;
+pub const GPUREG_SH_OUTMAP_O6: i32 = 0x0056;
+pub const GPUREG_0057: i32 = 0x0057;
+pub const GPUREG_0058: i32 = 0x0058;
+pub const GPUREG_0059: i32 = 0x0059;
+pub const GPUREG_005A: i32 = 0x005A;
+pub const GPUREG_005B: i32 = 0x005B;
+pub const GPUREG_005C: i32 = 0x005C;
+pub const GPUREG_005D: i32 = 0x005D;
+pub const GPUREG_005E: i32 = 0x005E;
+pub const GPUREG_005F: i32 = 0x005F;
+pub const GPUREG_0060: i32 = 0x0060;
+pub const GPUREG_0061: i32 = 0x0061;
+pub const GPUREG_0062: i32 = 0x0062;
+pub const GPUREG_0063: i32 = 0x0063;
+pub const GPUREG_0064: i32 = 0x0064;
+pub const GPUREG_SCISSORTEST_MODE: i32 = 0x0065;
+pub const GPUREG_SCISSORTEST_POS: i32 = 0x0066;
+pub const GPUREG_SCISSORTEST_DIM: i32 = 0x0067;
+pub const GPUREG_0068: i32 = 0x0068;
+pub const GPUREG_0069: i32 = 0x0069;
+pub const GPUREG_006A: i32 = 0x006A;
+pub const GPUREG_006B: i32 = 0x006B;
+pub const GPUREG_006C: i32 = 0x006C;
+pub const GPUREG_006D: i32 = 0x006D;
+pub const GPUREG_006E: i32 = 0x006E;
+pub const GPUREG_006F: i32 = 0x006F;
+pub const GPUREG_0070: i32 = 0x0070;
+pub const GPUREG_0071: i32 = 0x0071;
+pub const GPUREG_0072: i32 = 0x0072;
+pub const GPUREG_0073: i32 = 0x0073;
+pub const GPUREG_0074: i32 = 0x0074;
+pub const GPUREG_0075: i32 = 0x0075;
+pub const GPUREG_0076: i32 = 0x0076;
+pub const GPUREG_0077: i32 = 0x0077;
+pub const GPUREG_0078: i32 = 0x0078;
+pub const GPUREG_0079: i32 = 0x0079;
+pub const GPUREG_007A: i32 = 0x007A;
+pub const GPUREG_007B: i32 = 0x007B;
+pub const GPUREG_007C: i32 = 0x007C;
+pub const GPUREG_007D: i32 = 0x007D;
+pub const GPUREG_007E: i32 = 0x007E;
+pub const GPUREG_007F: i32 = 0x007F;
+
+//Texturing registers (0x080-0x0FF)
+pub const GPUREG_TEXUNITS_CONFIG: i32 = 0x0080;
+pub const GPUREG_0081: i32 = 0x0081;
+pub const GPUREG_TEXUNIT0_DIM: i32 = 0x0082;
+pub const GPUREG_TEXUNIT0_PARAM: i32 = 0x0083;
+pub const GPUREG_0084: i32 = 0x0084;
+pub const GPUREG_TEXUNIT0_LOC: i32 = 0x0085;
+pub const GPUREG_0086: i32 = 0x0086;
+pub const GPUREG_0087: i32 = 0x0087;
+pub const GPUREG_0088: i32 = 0x0088;
+pub const GPUREG_0089: i32 = 0x0089;
+pub const GPUREG_008A: i32 = 0x008A;
+pub const GPUREG_008B: i32 = 0x008B;
+pub const GPUREG_008C: i32 = 0x008C;
+pub const GPUREG_008D: i32 = 0x008D;
+pub const GPUREG_TEXUNIT0_TYPE: i32 = 0x008E;
+pub const GPUREG_008F: i32 = 0x008F;
+pub const GPUREG_0090: i32 = 0x0090;
+pub const GPUREG_0091: i32 = 0x0091;
+pub const GPUREG_TEXUNIT1_DIM: i32 = 0x0092;
+pub const GPUREG_TEXUNIT1_PARAM: i32 = 0x0093;
+pub const GPUREG_0094: i32 = 0x0094;
+pub const GPUREG_TEXUNIT1_LOC: i32 = 0x0095;
+pub const GPUREG_TEXUNIT1_TYPE: i32 = 0x0096;
+pub const GPUREG_0097: i32 = 0x0097;
+pub const GPUREG_0098: i32 = 0x0098;
+pub const GPUREG_0099: i32 = 0x0099;
+pub const GPUREG_TEXUNIT2_DIM: i32 = 0x009A;
+pub const GPUREG_TEXUNIT2_PARAM: i32 = 0x009B;
+pub const GPUREG_009C: i32 = 0x009C;
+pub const GPUREG_TEXUNIT2_LOC: i32 = 0x009D;
+pub const GPUREG_TEXUNIT2_TYPE: i32 = 0x009E;
+pub const GPUREG_009F: i32 = 0x009F;
+pub const GPUREG_00A0: i32 = 0x00A0;
+pub const GPUREG_00A1: i32 = 0x00A1;
+pub const GPUREG_00A2: i32 = 0x00A2;
+pub const GPUREG_00A3: i32 = 0x00A3;
+pub const GPUREG_00A4: i32 = 0x00A4;
+pub const GPUREG_00A5: i32 = 0x00A5;
+pub const GPUREG_00A6: i32 = 0x00A6;
+pub const GPUREG_00A7: i32 = 0x00A7;
+pub const GPUREG_00A8: i32 = 0x00A8;
+pub const GPUREG_00A9: i32 = 0x00A9;
+pub const GPUREG_00AA: i32 = 0x00AA;
+pub const GPUREG_00AB: i32 = 0x00AB;
+pub const GPUREG_00AC: i32 = 0x00AC;
+pub const GPUREG_00AD: i32 = 0x00AD;
+pub const GPUREG_00AE: i32 = 0x00AE;
+pub const GPUREG_00AF: i32 = 0x00AF;
+pub const GPUREG_00B0: i32 = 0x00B0;
+pub const GPUREG_00B1: i32 = 0x00B1;
+pub const GPUREG_00B2: i32 = 0x00B2;
+pub const GPUREG_00B3: i32 = 0x00B3;
+pub const GPUREG_00B4: i32 = 0x00B4;
+pub const GPUREG_00B5: i32 = 0x00B5;
+pub const GPUREG_00B6: i32 = 0x00B6;
+pub const GPUREG_00B7: i32 = 0x00B7;
+pub const GPUREG_00B8: i32 = 0x00B8;
+pub const GPUREG_00B9: i32 = 0x00B9;
+pub const GPUREG_00BA: i32 = 0x00BA;
+pub const GPUREG_00BB: i32 = 0x00BB;
+pub const GPUREG_00BC: i32 = 0x00BC;
+pub const GPUREG_00BD: i32 = 0x00BD;
+pub const GPUREG_00BE: i32 = 0x00BE;
+pub const GPUREG_00BF: i32 = 0x00BF;
+pub const GPUREG_TEXENV0_CONFIG0: i32 = 0x00C0;
+pub const GPUREG_TEXENV0_CONFIG1: i32 = 0x00C1;
+pub const GPUREG_TEXENV0_CONFIG2: i32 = 0x00C2;
+pub const GPUREG_TEXENV0_CONFIG3: i32 = 0x00C3;
+pub const GPUREG_TEXENV0_CONFIG4: i32 = 0x00C4;
+pub const GPUREG_00C5: i32 = 0x00C5;
+pub const GPUREG_00C6: i32 = 0x00C6;
+pub const GPUREG_00C7: i32 = 0x00C7;
+pub const GPUREG_TEXENV1_CONFIG0: i32 = 0x00C8;
+pub const GPUREG_TEXENV1_CONFIG1: i32 = 0x00C9;
+pub const GPUREG_TEXENV1_CONFIG2: i32 = 0x00CA;
+pub const GPUREG_TEXENV1_CONFIG3: i32 = 0x00CB;
+pub const GPUREG_TEXENV1_CONFIG4: i32 = 0x00CC;
+pub const GPUREG_00CD: i32 = 0x00CD;
+pub const GPUREG_00CE: i32 = 0x00CE;
+pub const GPUREG_00CF: i32 = 0x00CF;
+pub const GPUREG_TEXENV2_CONFIG0: i32 = 0x00D0;
+pub const GPUREG_TEXENV2_CONFIG1: i32 = 0x00D1;
+pub const GPUREG_TEXENV2_CONFIG2: i32 = 0x00D2;
+pub const GPUREG_TEXENV2_CONFIG3: i32 = 0x00D3;
+pub const GPUREG_TEXENV2_CONFIG4: i32 = 0x00D4;
+pub const GPUREG_00D5: i32 = 0x00D5;
+pub const GPUREG_00D6: i32 = 0x00D6;
+pub const GPUREG_00D7: i32 = 0x00D7;
+pub const GPUREG_TEXENV3_CONFIG0: i32 = 0x00D8;
+pub const GPUREG_TEXENV3_CONFIG1: i32 = 0x00D9;
+pub const GPUREG_TEXENV3_CONFIG2: i32 = 0x00DA;
+pub const GPUREG_TEXENV3_CONFIG3: i32 = 0x00DB;
+pub const GPUREG_TEXENV3_CONFIG4: i32 = 0x00DC;
+pub const GPUREG_00DD: i32 = 0x00DD;
+pub const GPUREG_00DE: i32 = 0x00DE;
+pub const GPUREG_00DF: i32 = 0x00DF;
+pub const GPUREG_00E0: i32 = 0x00E0;
+pub const GPUREG_00E1: i32 = 0x00E1;
+pub const GPUREG_00E2: i32 = 0x00E2;
+pub const GPUREG_00E3: i32 = 0x00E3;
+pub const GPUREG_00E4: i32 = 0x00E4;
+pub const GPUREG_00E5: i32 = 0x00E5;
+pub const GPUREG_00E6: i32 = 0x00E6;
+pub const GPUREG_00E7: i32 = 0x00E7;
+pub const GPUREG_00E8: i32 = 0x00E8;
+pub const GPUREG_00E9: i32 = 0x00E9;
+pub const GPUREG_00EA: i32 = 0x00EA;
+pub const GPUREG_00EB: i32 = 0x00EB;
+pub const GPUREG_00EC: i32 = 0x00EC;
+pub const GPUREG_00ED: i32 = 0x00ED;
+pub const GPUREG_00EE: i32 = 0x00EE;
+pub const GPUREG_00EF: i32 = 0x00EF;
+pub const GPUREG_TEXENV4_CONFIG0: i32 = 0x00F0;
+pub const GPUREG_TEXENV4_CONFIG1: i32 = 0x00F1;
+pub const GPUREG_TEXENV4_CONFIG2: i32 = 0x00F2;
+pub const GPUREG_TEXENV4_CONFIG3: i32 = 0x00F3;
+pub const GPUREG_TEXENV4_CONFIG4: i32 = 0x00F4;
+pub const GPUREG_00F5: i32 = 0x00F5;
+pub const GPUREG_00F6: i32 = 0x00F6;
+pub const GPUREG_00F7: i32 = 0x00F7;
+pub const GPUREG_TEXENV5_CONFIG0: i32 = 0x00F8;
+pub const GPUREG_TEXENV5_CONFIG1: i32 = 0x00F9;
+pub const GPUREG_TEXENV5_CONFIG2: i32 = 0x00FA;
+pub const GPUREG_TEXENV5_CONFIG3: i32 = 0x00FB;
+pub const GPUREG_TEXENV5_CONFIG4: i32 = 0x00FC;
+pub const GPUREG_00FD: i32 = 0x00FD;
+pub const GPUREG_00FE: i32 = 0x00FE;
+pub const GPUREG_00FF: i32 = 0x00FF;
+
+//Framebuffer registers (0x100-0x13F)
+pub const GPUREG_COLOROUTPUT_CONFIG: i32 = 0x0100;
+pub const GPUREG_BLEND_CONFIG: i32 = 0x0101;
+pub const GPUREG_COLORLOGICOP_CONFIG: i32 = 0x0102;
+pub const GPUREG_BLEND_COLOR: i32 = 0x0103;
+pub const GPUREG_ALPHATEST_CONFIG: i32 = 0x0104;
+pub const GPUREG_STENCILTEST_CONFIG: i32 = 0x0105;
+pub const GPUREG_STENCILOP_CONFIG: i32 = 0x0106;
+pub const GPUREG_DEPTHTEST_CONFIG: i32 = 0x0107;
+pub const GPUREG_0108: i32 = 0x0108;
+pub const GPUREG_0109: i32 = 0x0109;
+pub const GPUREG_010A: i32 = 0x010A;
+pub const GPUREG_010B: i32 = 0x010B;
+pub const GPUREG_010C: i32 = 0x010C;
+pub const GPUREG_010D: i32 = 0x010D;
+pub const GPUREG_010E: i32 = 0x010E;
+pub const GPUREG_010F: i32 = 0x010F;
+pub const GPUREG_0110: i32 = 0x0110;
+pub const GPUREG_0111: i32 = 0x0111;
+pub const GPUREG_0112: i32 = 0x0112;
+pub const GPUREG_0113: i32 = 0x0113;
+pub const GPUREG_0114: i32 = 0x0114;
+pub const GPUREG_0115: i32 = 0x0115;
+pub const GPUREG_DEPTHBUFFER_FORMAT: i32 = 0x0116;
+pub const GPUREG_COLORBUFFER_FORMAT: i32 = 0x0117;
+pub const GPUREG_0118: i32 = 0x0118;
+pub const GPUREG_0119: i32 = 0x0119;
+pub const GPUREG_011A: i32 = 0x011A;
+pub const GPUREG_011B: i32 = 0x011B;
+pub const GPUREG_DEPTHBUFFER_LOC: i32 = 0x011C;
+pub const GPUREG_COLORBUFFER_LOC: i32 = 0x011D;
+pub const GPUREG_OUTBUFFER_DIM: i32 = 0x011E;
+pub const GPUREG_011F: i32 = 0x011F;
+pub const GPUREG_0120: i32 = 0x0120;
+pub const GPUREG_0121: i32 = 0x0121;
+pub const GPUREG_0122: i32 = 0x0122;
+pub const GPUREG_0123: i32 = 0x0123;
+pub const GPUREG_0124: i32 = 0x0124;
+pub const GPUREG_0125: i32 = 0x0125;
+pub const GPUREG_0126: i32 = 0x0126;
+pub const GPUREG_0127: i32 = 0x0127;
+pub const GPUREG_0128: i32 = 0x0128;
+pub const GPUREG_0129: i32 = 0x0129;
+pub const GPUREG_012A: i32 = 0x012A;
+pub const GPUREG_012B: i32 = 0x012B;
+pub const GPUREG_012C: i32 = 0x012C;
+pub const GPUREG_012D: i32 = 0x012D;
+pub const GPUREG_012E: i32 = 0x012E;
+pub const GPUREG_012F: i32 = 0x012F;
+pub const GPUREG_0130: i32 = 0x0130;
+pub const GPUREG_0131: i32 = 0x0131;
+pub const GPUREG_0132: i32 = 0x0132;
+pub const GPUREG_0133: i32 = 0x0133;
+pub const GPUREG_0134: i32 = 0x0134;
+pub const GPUREG_0135: i32 = 0x0135;
+pub const GPUREG_0136: i32 = 0x0136;
+pub const GPUREG_0137: i32 = 0x0137;
+pub const GPUREG_0138: i32 = 0x0138;
+pub const GPUREG_0139: i32 = 0x0139;
+pub const GPUREG_013A: i32 = 0x013A;
+pub const GPUREG_013B: i32 = 0x013B;
+pub const GPUREG_013C: i32 = 0x013C;
+pub const GPUREG_013D: i32 = 0x013D;
+pub const GPUREG_013E: i32 = 0x013E;
+pub const GPUREG_013F: i32 = 0x013F;
+
+//Fragment lighting registers (0x140-0x1FF)
+pub const GPUREG_0140: i32 = 0x0140;
+pub const GPUREG_0141: i32 = 0x0141;
+pub const GPUREG_0142: i32 = 0x0142;
+pub const GPUREG_0143: i32 = 0x0143;
+pub const GPUREG_0144: i32 = 0x0144;
+pub const GPUREG_0145: i32 = 0x0145;
+pub const GPUREG_0146: i32 = 0x0146;
+pub const GPUREG_0147: i32 = 0x0147;
+pub const GPUREG_0148: i32 = 0x0148;
+pub const GPUREG_0149: i32 = 0x0149;
+pub const GPUREG_014A: i32 = 0x014A;
+pub const GPUREG_014B: i32 = 0x014B;
+pub const GPUREG_014C: i32 = 0x014C;
+pub const GPUREG_014D: i32 = 0x014D;
+pub const GPUREG_014E: i32 = 0x014E;
+pub const GPUREG_014F: i32 = 0x014F;
+pub const GPUREG_0150: i32 = 0x0150;
+pub const GPUREG_0151: i32 = 0x0151;
+pub const GPUREG_0152: i32 = 0x0152;
+pub const GPUREG_0153: i32 = 0x0153;
+pub const GPUREG_0154: i32 = 0x0154;
+pub const GPUREG_0155: i32 = 0x0155;
+pub const GPUREG_0156: i32 = 0x0156;
+pub const GPUREG_0157: i32 = 0x0157;
+pub const GPUREG_0158: i32 = 0x0158;
+pub const GPUREG_0159: i32 = 0x0159;
+pub const GPUREG_015A: i32 = 0x015A;
+pub const GPUREG_015B: i32 = 0x015B;
+pub const GPUREG_015C: i32 = 0x015C;
+pub const GPUREG_015D: i32 = 0x015D;
+pub const GPUREG_015E: i32 = 0x015E;
+pub const GPUREG_015F: i32 = 0x015F;
+pub const GPUREG_0160: i32 = 0x0160;
+pub const GPUREG_0161: i32 = 0x0161;
+pub const GPUREG_0162: i32 = 0x0162;
+pub const GPUREG_0163: i32 = 0x0163;
+pub const GPUREG_0164: i32 = 0x0164;
+pub const GPUREG_0165: i32 = 0x0165;
+pub const GPUREG_0166: i32 = 0x0166;
+pub const GPUREG_0167: i32 = 0x0167;
+pub const GPUREG_0168: i32 = 0x0168;
+pub const GPUREG_0169: i32 = 0x0169;
+pub const GPUREG_016A: i32 = 0x016A;
+pub const GPUREG_016B: i32 = 0x016B;
+pub const GPUREG_016C: i32 = 0x016C;
+pub const GPUREG_016D: i32 = 0x016D;
+pub const GPUREG_016E: i32 = 0x016E;
+pub const GPUREG_016F: i32 = 0x016F;
+pub const GPUREG_0170: i32 = 0x0170;
+pub const GPUREG_0171: i32 = 0x0171;
+pub const GPUREG_0172: i32 = 0x0172;
+pub const GPUREG_0173: i32 = 0x0173;
+pub const GPUREG_0174: i32 = 0x0174;
+pub const GPUREG_0175: i32 = 0x0175;
+pub const GPUREG_0176: i32 = 0x0176;
+pub const GPUREG_0177: i32 = 0x0177;
+pub const GPUREG_0178: i32 = 0x0178;
+pub const GPUREG_0179: i32 = 0x0179;
+pub const GPUREG_017A: i32 = 0x017A;
+pub const GPUREG_017B: i32 = 0x017B;
+pub const GPUREG_017C: i32 = 0x017C;
+pub const GPUREG_017D: i32 = 0x017D;
+pub const GPUREG_017E: i32 = 0x017E;
+pub const GPUREG_017F: i32 = 0x017F;
+pub const GPUREG_0180: i32 = 0x0180;
+pub const GPUREG_0181: i32 = 0x0181;
+pub const GPUREG_0182: i32 = 0x0182;
+pub const GPUREG_0183: i32 = 0x0183;
+pub const GPUREG_0184: i32 = 0x0184;
+pub const GPUREG_0185: i32 = 0x0185;
+pub const GPUREG_0186: i32 = 0x0186;
+pub const GPUREG_0187: i32 = 0x0187;
+pub const GPUREG_0188: i32 = 0x0188;
+pub const GPUREG_0189: i32 = 0x0189;
+pub const GPUREG_018A: i32 = 0x018A;
+pub const GPUREG_018B: i32 = 0x018B;
+pub const GPUREG_018C: i32 = 0x018C;
+pub const GPUREG_018D: i32 = 0x018D;
+pub const GPUREG_018E: i32 = 0x018E;
+pub const GPUREG_018F: i32 = 0x018F;
+pub const GPUREG_0190: i32 = 0x0190;
+pub const GPUREG_0191: i32 = 0x0191;
+pub const GPUREG_0192: i32 = 0x0192;
+pub const GPUREG_0193: i32 = 0x0193;
+pub const GPUREG_0194: i32 = 0x0194;
+pub const GPUREG_0195: i32 = 0x0195;
+pub const GPUREG_0196: i32 = 0x0196;
+pub const GPUREG_0197: i32 = 0x0197;
+pub const GPUREG_0198: i32 = 0x0198;
+pub const GPUREG_0199: i32 = 0x0199;
+pub const GPUREG_019A: i32 = 0x019A;
+pub const GPUREG_019B: i32 = 0x019B;
+pub const GPUREG_019C: i32 = 0x019C;
+pub const GPUREG_019D: i32 = 0x019D;
+pub const GPUREG_019E: i32 = 0x019E;
+pub const GPUREG_019F: i32 = 0x019F;
+pub const GPUREG_01A0: i32 = 0x01A0;
+pub const GPUREG_01A1: i32 = 0x01A1;
+pub const GPUREG_01A2: i32 = 0x01A2;
+pub const GPUREG_01A3: i32 = 0x01A3;
+pub const GPUREG_01A4: i32 = 0x01A4;
+pub const GPUREG_01A5: i32 = 0x01A5;
+pub const GPUREG_01A6: i32 = 0x01A6;
+pub const GPUREG_01A7: i32 = 0x01A7;
+pub const GPUREG_01A8: i32 = 0x01A8;
+pub const GPUREG_01A9: i32 = 0x01A9;
+pub const GPUREG_01AA: i32 = 0x01AA;
+pub const GPUREG_01AB: i32 = 0x01AB;
+pub const GPUREG_01AC: i32 = 0x01AC;
+pub const GPUREG_01AD: i32 = 0x01AD;
+pub const GPUREG_01AE: i32 = 0x01AE;
+pub const GPUREG_01AF: i32 = 0x01AF;
+pub const GPUREG_01B0: i32 = 0x01B0;
+pub const GPUREG_01B1: i32 = 0x01B1;
+pub const GPUREG_01B2: i32 = 0x01B2;
+pub const GPUREG_01B3: i32 = 0x01B3;
+pub const GPUREG_01B4: i32 = 0x01B4;
+pub const GPUREG_01B5: i32 = 0x01B5;
+pub const GPUREG_01B6: i32 = 0x01B6;
+pub const GPUREG_01B7: i32 = 0x01B7;
+pub const GPUREG_01B8: i32 = 0x01B8;
+pub const GPUREG_01B9: i32 = 0x01B9;
+pub const GPUREG_01BA: i32 = 0x01BA;
+pub const GPUREG_01BB: i32 = 0x01BB;
+pub const GPUREG_01BC: i32 = 0x01BC;
+pub const GPUREG_01BD: i32 = 0x01BD;
+pub const GPUREG_01BE: i32 = 0x01BE;
+pub const GPUREG_01BF: i32 = 0x01BF;
+pub const GPUREG_01C0: i32 = 0x01C0;
+pub const GPUREG_01C1: i32 = 0x01C1;
+pub const GPUREG_01C2: i32 = 0x01C2;
+pub const GPUREG_01C3: i32 = 0x01C3;
+pub const GPUREG_01C4: i32 = 0x01C4;
+pub const GPUREG_01C5: i32 = 0x01C5;
+pub const GPUREG_01C6: i32 = 0x01C6;
+pub const GPUREG_01C7: i32 = 0x01C7;
+pub const GPUREG_01C8: i32 = 0x01C8;
+pub const GPUREG_01C9: i32 = 0x01C9;
+pub const GPUREG_01CA: i32 = 0x01CA;
+pub const GPUREG_01CB: i32 = 0x01CB;
+pub const GPUREG_01CC: i32 = 0x01CC;
+pub const GPUREG_01CD: i32 = 0x01CD;
+pub const GPUREG_01CE: i32 = 0x01CE;
+pub const GPUREG_01CF: i32 = 0x01CF;
+pub const GPUREG_01D0: i32 = 0x01D0;
+pub const GPUREG_01D1: i32 = 0x01D1;
+pub const GPUREG_01D2: i32 = 0x01D2;
+pub const GPUREG_01D3: i32 = 0x01D3;
+pub const GPUREG_01D4: i32 = 0x01D4;
+pub const GPUREG_01D5: i32 = 0x01D5;
+pub const GPUREG_01D6: i32 = 0x01D6;
+pub const GPUREG_01D7: i32 = 0x01D7;
+pub const GPUREG_01D8: i32 = 0x01D8;
+pub const GPUREG_01D9: i32 = 0x01D9;
+pub const GPUREG_01DA: i32 = 0x01DA;
+pub const GPUREG_01DB: i32 = 0x01DB;
+pub const GPUREG_01DC: i32 = 0x01DC;
+pub const GPUREG_01DD: i32 = 0x01DD;
+pub const GPUREG_01DE: i32 = 0x01DE;
+pub const GPUREG_01DF: i32 = 0x01DF;
+pub const GPUREG_01E0: i32 = 0x01E0;
+pub const GPUREG_01E1: i32 = 0x01E1;
+pub const GPUREG_01E2: i32 = 0x01E2;
+pub const GPUREG_01E3: i32 = 0x01E3;
+pub const GPUREG_01E4: i32 = 0x01E4;
+pub const GPUREG_01E5: i32 = 0x01E5;
+pub const GPUREG_01E6: i32 = 0x01E6;
+pub const GPUREG_01E7: i32 = 0x01E7;
+pub const GPUREG_01E8: i32 = 0x01E8;
+pub const GPUREG_01E9: i32 = 0x01E9;
+pub const GPUREG_01EA: i32 = 0x01EA;
+pub const GPUREG_01EB: i32 = 0x01EB;
+pub const GPUREG_01EC: i32 = 0x01EC;
+pub const GPUREG_01ED: i32 = 0x01ED;
+pub const GPUREG_01EE: i32 = 0x01EE;
+pub const GPUREG_01EF: i32 = 0x01EF;
+pub const GPUREG_01F0: i32 = 0x01F0;
+pub const GPUREG_01F1: i32 = 0x01F1;
+pub const GPUREG_01F2: i32 = 0x01F2;
+pub const GPUREG_01F3: i32 = 0x01F3;
+pub const GPUREG_01F4: i32 = 0x01F4;
+pub const GPUREG_01F5: i32 = 0x01F5;
+pub const GPUREG_01F6: i32 = 0x01F6;
+pub const GPUREG_01F7: i32 = 0x01F7;
+pub const GPUREG_01F8: i32 = 0x01F8;
+pub const GPUREG_01F9: i32 = 0x01F9;
+pub const GPUREG_01FA: i32 = 0x01FA;
+pub const GPUREG_01FB: i32 = 0x01FB;
+pub const GPUREG_01FC: i32 = 0x01FC;
+pub const GPUREG_01FD: i32 = 0x01FD;
+pub const GPUREG_01FE: i32 = 0x01FE;
+pub const GPUREG_01FF: i32 = 0x01FF;
+
+//Geometry pipeline registers (0x200-0x27F)
+pub const GPUREG_ATTRIBBUFFERS_LOC: i32 = 0x0200;
+pub const GPUREG_ATTRIBBUFFERS_FORMAT_LOW: i32 = 0x0201;
+pub const GPUREG_ATTRIBBUFFERS_FORMAT_HIGH: i32 = 0x0202;
+pub const GPUREG_ATTRIBBUFFER0_CONFIG0: i32 = 0x0203;
+pub const GPUREG_ATTRIBBUFFER0_CONFIG1: i32 = 0x0204;
+pub const GPUREG_ATTRIBBUFFER0_CONFIG2: i32 = 0x0205;
+pub const GPUREG_ATTRIBBUFFER1_CONFIG0: i32 = 0x0206;
+pub const GPUREG_ATTRIBBUFFER1_CONFIG1: i32 = 0x0207;
+pub const GPUREG_ATTRIBBUFFER1_CONFIG2: i32 = 0x0208;
+pub const GPUREG_ATTRIBBUFFER2_CONFIG0: i32 = 0x0209;
+pub const GPUREG_ATTRIBBUFFER2_CONFIG1: i32 = 0x020A;
+pub const GPUREG_ATTRIBBUFFER2_CONFIG2: i32 = 0x020B;
+pub const GPUREG_ATTRIBBUFFER3_CONFIG0: i32 = 0x020C;
+pub const GPUREG_ATTRIBBUFFER3_CONFIG1: i32 = 0x020D;
+pub const GPUREG_ATTRIBBUFFER3_CONFIG2: i32 = 0x020E;
+pub const GPUREG_ATTRIBBUFFER4_CONFIG0: i32 = 0x020F;
+pub const GPUREG_ATTRIBBUFFER4_CONFIG1: i32 = 0x0210;
+pub const GPUREG_ATTRIBBUFFER4_CONFIG2: i32 = 0x0211;
+pub const GPUREG_ATTRIBBUFFER5_CONFIG0: i32 = 0x0212;
+pub const GPUREG_ATTRIBBUFFER5_CONFIG1: i32 = 0x0213;
+pub const GPUREG_ATTRIBBUFFER5_CONFIG2: i32 = 0x0214;
+pub const GPUREG_ATTRIBBUFFER6_CONFIG0: i32 = 0x0215;
+pub const GPUREG_ATTRIBBUFFER6_CONFIG1: i32 = 0x0216;
+pub const GPUREG_ATTRIBBUFFER6_CONFIG2: i32 = 0x0217;
+pub const GPUREG_ATTRIBBUFFER7_CONFIG0: i32 = 0x0218;
+pub const GPUREG_ATTRIBBUFFER7_CONFIG1: i32 = 0x0219;
+pub const GPUREG_ATTRIBBUFFER7_CONFIG2: i32 = 0x021A;
+pub const GPUREG_ATTRIBBUFFER8_CONFIG0: i32 = 0x021B;
+pub const GPUREG_ATTRIBBUFFER8_CONFIG1: i32 = 0x021C;
+pub const GPUREG_ATTRIBBUFFER8_CONFIG2: i32 = 0x021D;
+pub const GPUREG_ATTRIBBUFFER9_CONFIG0: i32 = 0x021E;
+pub const GPUREG_ATTRIBBUFFER9_CONFIG1: i32 = 0x021F;
+pub const GPUREG_ATTRIBBUFFER9_CONFIG2: i32 = 0x0220;
+pub const GPUREG_ATTRIBBUFFERA_CONFIG0: i32 = 0x0221;
+pub const GPUREG_ATTRIBBUFFERA_CONFIG1: i32 = 0x0222;
+pub const GPUREG_ATTRIBBUFFERA_CONFIG2: i32 = 0x0223;
+pub const GPUREG_ATTRIBBUFFERB_CONFIG0: i32 = 0x0224;
+pub const GPUREG_ATTRIBBUFFERB_CONFIG1: i32 = 0x0225;
+pub const GPUREG_ATTRIBBUFFERB_CONFIG2: i32 = 0x0226;
+pub const GPUREG_INDEXBUFFER_CONFIG: i32 = 0x0227;
+pub const GPUREG_NUMVERTICES: i32 = 0x0228;
+pub const GPUREG_GEOSTAGE_CONFIG: i32 = 0x0229;
+pub const GPUREG_022A: i32 = 0x022A;
+pub const GPUREG_022B: i32 = 0x022B;
+pub const GPUREG_022C: i32 = 0x022C;
+pub const GPUREG_022D: i32 = 0x022D;
+pub const GPUREG_DRAWARRAYS: i32 = 0x022E;
+pub const GPUREG_DRAWELEMENTS: i32 = 0x022F;
+pub const GPUREG_0230: i32 = 0x0230;
+pub const GPUREG_0231: i32 = 0x0231;
+pub const GPUREG_0232: i32 = 0x0232;
+pub const GPUREG_0233: i32 = 0x0233;
+pub const GPUREG_0234: i32 = 0x0234;
+pub const GPUREG_0235: i32 = 0x0235;
+pub const GPUREG_0236: i32 = 0x0236;
+pub const GPUREG_0237: i32 = 0x0237;
+pub const GPUREG_0238: i32 = 0x0238;
+pub const GPUREG_0239: i32 = 0x0239;
+pub const GPUREG_023A: i32 = 0x023A;
+pub const GPUREG_023B: i32 = 0x023B;
+pub const GPUREG_023C: i32 = 0x023C;
+pub const GPUREG_023D: i32 = 0x023D;
+pub const GPUREG_023E: i32 = 0x023E;
+pub const GPUREG_023F: i32 = 0x023F;
+pub const GPUREG_0240: i32 = 0x0240;
+pub const GPUREG_0241: i32 = 0x0241;
+pub const GPUREG_0242: i32 = 0x0242;
+pub const GPUREG_0243: i32 = 0x0243;
+pub const GPUREG_0244: i32 = 0x0244;
+pub const GPUREG_0245: i32 = 0x0245;
+pub const GPUREG_0246: i32 = 0x0246;
+pub const GPUREG_0247: i32 = 0x0247;
+pub const GPUREG_0248: i32 = 0x0248;
+pub const GPUREG_0249: i32 = 0x0249;
+pub const GPUREG_024A: i32 = 0x024A;
+pub const GPUREG_024B: i32 = 0x024B;
+pub const GPUREG_024C: i32 = 0x024C;
+pub const GPUREG_024D: i32 = 0x024D;
+pub const GPUREG_024E: i32 = 0x024E;
+pub const GPUREG_024F: i32 = 0x024F;
+pub const GPUREG_0250: i32 = 0x0250;
+pub const GPUREG_0251: i32 = 0x0251;
+pub const GPUREG_0252: i32 = 0x0252;
+pub const GPUREG_0253: i32 = 0x0253;
+pub const GPUREG_0254: i32 = 0x0254;
+pub const GPUREG_0255: i32 = 0x0255;
+pub const GPUREG_0256: i32 = 0x0256;
+pub const GPUREG_0257: i32 = 0x0257;
+pub const GPUREG_0258: i32 = 0x0258;
+pub const GPUREG_0259: i32 = 0x0259;
+pub const GPUREG_025A: i32 = 0x025A;
+pub const GPUREG_025B: i32 = 0x025B;
+pub const GPUREG_025C: i32 = 0x025C;
+pub const GPUREG_025D: i32 = 0x025D;
+pub const GPUREG_PRIMITIVE_CONFIG: i32 = 0x025E;
+pub const GPUREG_025F: i32 = 0x025F;
+pub const GPUREG_0260: i32 = 0x0260;
+pub const GPUREG_0261: i32 = 0x0261;
+pub const GPUREG_0262: i32 = 0x0262;
+pub const GPUREG_0263: i32 = 0x0263;
+pub const GPUREG_0264: i32 = 0x0264;
+pub const GPUREG_0265: i32 = 0x0265;
+pub const GPUREG_0266: i32 = 0x0266;
+pub const GPUREG_0267: i32 = 0x0267;
+pub const GPUREG_0268: i32 = 0x0268;
+pub const GPUREG_0269: i32 = 0x0269;
+pub const GPUREG_026A: i32 = 0x026A;
+pub const GPUREG_026B: i32 = 0x026B;
+pub const GPUREG_026C: i32 = 0x026C;
+pub const GPUREG_026D: i32 = 0x026D;
+pub const GPUREG_026E: i32 = 0x026E;
+pub const GPUREG_026F: i32 = 0x026F;
+pub const GPUREG_0270: i32 = 0x0270;
+pub const GPUREG_0271: i32 = 0x0271;
+pub const GPUREG_0272: i32 = 0x0272;
+pub const GPUREG_0273: i32 = 0x0273;
+pub const GPUREG_0274: i32 = 0x0274;
+pub const GPUREG_0275: i32 = 0x0275;
+pub const GPUREG_0276: i32 = 0x0276;
+pub const GPUREG_0277: i32 = 0x0277;
+pub const GPUREG_0278: i32 = 0x0278;
+pub const GPUREG_0279: i32 = 0x0279;
+pub const GPUREG_027A: i32 = 0x027A;
+pub const GPUREG_027B: i32 = 0x027B;
+pub const GPUREG_027C: i32 = 0x027C;
+pub const GPUREG_027D: i32 = 0x027D;
+pub const GPUREG_027E: i32 = 0x027E;
+pub const GPUREG_027F: i32 = 0x027F;
+
+//Geometry shader registers (0x280-0x2AF)
+pub const GPUREG_GSH_BOOLUNIFORM: i32 = 0x0280;
+pub const GPUREG_GSH_INTUNIFORM_I0: i32 = 0x0281;
+pub const GPUREG_GSH_INTUNIFORM_I1: i32 = 0x0282;
+pub const GPUREG_GSH_INTUNIFORM_I2: i32 = 0x0283;
+pub const GPUREG_GSH_INTUNIFORM_I3: i32 = 0x0284;
+pub const GPUREG_0285: i32 = 0x0285;
+pub const GPUREG_0286: i32 = 0x0286;
+pub const GPUREG_0287: i32 = 0x0287;
+pub const GPUREG_0288: i32 = 0x0288;
+pub const GPUREG_GSH_INPUTBUFFER_CONFIG: i32 = 0x0289;
+pub const GPUREG_GSH_ENTRYPOINT: i32 = 0x028A;
+pub const GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW: i32 = 0x028B;
+pub const GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH: i32 = 0x028C;
+pub const GPUREG_GSH_OUTMAP_MASK: i32 = 0x028D;
+pub const GPUREG_028E: i32 = 0x028E;
+pub const GPUREG_GSH_CODETRANSFER_END: i32 = 0x028F;
+pub const GPUREG_GSH_FLOATUNIFORM_CONFIG: i32 = 0x0290;
+pub const GPUREG_GSH_FLOATUNIFORM_DATA: i32 = 0x0291;
+pub const GPUREG_0299: i32 = 0x0299;
+pub const GPUREG_029A: i32 = 0x029A;
+pub const GPUREG_GSH_CODETRANSFER_CONFIG: i32 = 0x029B;
+pub const GPUREG_GSH_CODETRANSFER_DATA: i32 = 0x029C;
+pub const GPUREG_02A4: i32 = 0x02A4;
+pub const GPUREG_GSH_OPDESCS_CONFIG: i32 = 0x02A5;
+pub const GPUREG_GSH_OPDESCS_DATA: i32 = 0x02A6;
+pub const GPUREG_02AE: i32 = 0x02AE;
+pub const GPUREG_02AF: i32 = 0x02AF;
+
+//Vertex shader registers (0x2B0-0x2DF)
+pub const GPUREG_VSH_BOOLUNIFORM: i32 = 0x02B0;
+pub const GPUREG_VSH_INTUNIFORM_I0: i32 = 0x02B1;
+pub const GPUREG_VSH_INTUNIFORM_I1: i32 = 0x02B2;
+pub const GPUREG_VSH_INTUNIFORM_I2: i32 = 0x02B3;
+pub const GPUREG_VSH_INTUNIFORM_I3: i32 = 0x02B4;
+pub const GPUREG_02B5: i32 = 0x02B5;
+pub const GPUREG_02B6: i32 = 0x02B6;
+pub const GPUREG_02B7: i32 = 0x02B7;
+pub const GPUREG_02B8: i32 = 0x02B8;
+pub const GPUREG_VSH_INPUTBUFFER_CONFIG: i32 = 0x02B9;
+pub const GPUREG_VSH_ENTRYPOINT: i32 = 0x02BA;
+pub const GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW: i32 = 0x02BB;
+pub const GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH: i32 = 0x02BC;
+pub const GPUREG_VSH_OUTMAP_MASK: i32 = 0x02BD;
+pub const GPUREG_02BE: i32 = 0x02BE;
+pub const GPUREG_VSH_CODETRANSFER_END: i32 = 0x02BF;
+pub const GPUREG_VSH_FLOATUNIFORM_CONFIG: i32 = 0x02C0;
+pub const GPUREG_VSH_FLOATUNIFORM_DATA: i32 = 0x02C1;
+pub const GPUREG_02C9: i32 = 0x02C9;
+pub const GPUREG_02CA: i32 = 0x02CA;
+pub const GPUREG_VSH_CODETRANSFER_CONFIG: i32 = 0x02CB;
+pub const GPUREG_VSH_CODETRANSFER_DATA: i32 = 0x02CC;
+pub const GPUREG_02D4: i32 = 0x02D4;
+pub const GPUREG_VSH_OPDESCS_CONFIG: i32 = 0x02D5;
+pub const GPUREG_VSH_OPDESCS_DATA: i32 = 0x02D6;
+pub const GPUREG_02DE: i32 = 0x02DE;
+pub const GPUREG_02DF: i32 = 0x02DF;
+
+//Unknown registers (0x2E0-0x2FF)
+pub const GPUREG_02E0: i32 = 0x02E0;
+pub const GPUREG_02E1: i32 = 0x02E1;
+pub const GPUREG_02E2: i32 = 0x02E2;
+pub const GPUREG_02E3: i32 = 0x02E3;
+pub const GPUREG_02E4: i32 = 0x02E4;
+pub const GPUREG_02E5: i32 = 0x02E5;
+pub const GPUREG_02E6: i32 = 0x02E6;
+pub const GPUREG_02E7: i32 = 0x02E7;
+pub const GPUREG_02E8: i32 = 0x02E8;
+pub const GPUREG_02E9: i32 = 0x02E9;
+pub const GPUREG_02EA: i32 = 0x02EA;
+pub const GPUREG_02EB: i32 = 0x02EB;
+pub const GPUREG_02EC: i32 = 0x02EC;
+pub const GPUREG_02ED: i32 = 0x02ED;
+pub const GPUREG_02EE: i32 = 0x02EE;
+pub const GPUREG_02EF: i32 = 0x02EF;
+pub const GPUREG_02F0: i32 = 0x02F0;
+pub const GPUREG_02F1: i32 = 0x02F1;
+pub const GPUREG_02F2: i32 = 0x02F2;
+pub const GPUREG_02F3: i32 = 0x02F3;
+pub const GPUREG_02F4: i32 = 0x02F4;
+pub const GPUREG_02F5: i32 = 0x02F5;
+pub const GPUREG_02F6: i32 = 0x02F6;
+pub const GPUREG_02F7: i32 = 0x02F7;
+pub const GPUREG_02F8: i32 = 0x02F8;
+pub const GPUREG_02F9: i32 = 0x02F9;
+pub const GPUREG_02FA: i32 = 0x02FA;
+pub const GPUREG_02FB: i32 = 0x02FB;
+pub const GPUREG_02FC: i32 = 0x02FC;
+pub const GPUREG_02FD: i32 = 0x02FD;
+pub const GPUREG_02FE: i32 = 0x02FE;
+pub const GPUREG_02FF: i32 = 0x02FF;
diff --git a/ctru-sys/src/gpu/shaderProgram.rs b/ctru-sys/src/gpu/shaderProgram.rs
new file mode 100644
index 0000000..f81f772
--- /dev/null
+++ b/ctru-sys/src/gpu/shaderProgram.rs
@@ -0,0 +1,89 @@
+use ::Result;
+use ::types::*;
+use gpu::shbin::*;
+
+
+#[repr(C)]
+#[derive(Copy)]
+pub struct Struct_Unnamed1 {
+    pub id: u32,
+    pub data: [u32; 3usize],
+}
+impl ::core::clone::Clone for Struct_Unnamed1 {
+    fn clone(&self) -> Self { *self }
+}
+impl ::core::default::Default for Struct_Unnamed1 {
+    fn default() -> Self { unsafe { ::core::mem::zeroed() } }
+}
+pub type float24Uniform_s = Struct_Unnamed1;
+#[repr(C)]
+#[derive(Copy)]
+pub struct Struct_Unnamed2 {
+    pub dvle: *mut DVLE_s,
+    pub boolUniforms: u16,
+    pub boolUniformMask: u16,
+    pub intUniforms: [u32; 4usize],
+    pub float24Uniforms: *mut float24Uniform_s,
+    pub intUniformMask: u8,
+    pub numFloat24Uniforms: u8,
+}
+impl ::core::clone::Clone for Struct_Unnamed2 {
+    fn clone(&self) -> Self { *self }
+}
+impl ::core::default::Default for Struct_Unnamed2 {
+    fn default() -> Self { unsafe { ::core::mem::zeroed() } }
+}
+pub type shaderInstance_s = Struct_Unnamed2;
+#[repr(C)]
+#[derive(Copy)]
+pub struct Struct_Unnamed3 {
+    pub vertexShader: *mut shaderInstance_s,
+    pub geometryShader: *mut shaderInstance_s,
+    pub geoShaderInputPermutation: [u32; 2usize],
+    pub geoShaderInputStride: u8,
+    pub geoShaderMode: u8,
+}
+impl ::core::clone::Clone for Struct_Unnamed3 {
+    fn clone(&self) -> Self { *self }
+}
+impl ::core::default::Default for Struct_Unnamed3 {
+    fn default() -> Self { unsafe { ::core::mem::zeroed() } }
+}
+pub type shaderProgram_s = Struct_Unnamed3;
+#[derive(Clone, Copy)]
+#[repr(u32)]
+pub enum Enum_Unnamed4 {
+    GSH_NORMAL = 0,
+    GSH_PARTICLE = 1,
+    GSH_SUBDIVISION_LOOP = 2,
+    GSH_SUBDIVISION_CATMULL_CLARK = 3,
+}
+pub type geoShaderMode = Enum_Unnamed4;
+extern "C" {
+    pub fn shaderInstanceInit(si: *mut shaderInstance_s, dvle: *mut DVLE_s)
+     -> Result;
+    pub fn shaderInstanceFree(si: *mut shaderInstance_s) -> Result;
+    pub fn shaderInstanceSetBool(si: *mut shaderInstance_s,
+                                 id: i32, value: u8)
+     -> Result;
+    pub fn shaderInstanceGetBool(si: *mut shaderInstance_s,
+                                 id: i32, value: *mut u8)
+     -> Result;
+    pub fn shaderInstanceGetUniformLocation(si: *mut shaderInstance_s,
+                                            name:
+                                                *const u8)
+     -> s8;
+    pub fn shaderProgramInit(sp: *mut shaderProgram_s) -> Result;
+    pub fn shaderProgramFree(sp: *mut shaderProgram_s) -> Result;
+    pub fn shaderProgramSetVsh(sp: *mut shaderProgram_s, dvle: *mut DVLE_s)
+     -> Result;
+    pub fn shaderProgramSetGsh(sp: *mut shaderProgram_s, dvle: *mut DVLE_s,
+                               stride: u8) -> Result;
+    pub fn shaderProgramSetGshInputPermutation(sp: *mut shaderProgram_s,
+                                               permutation: u64) -> Result;
+    pub fn shaderProgramSetGshMode(sp: *mut shaderProgram_s,
+                                   mode: geoShaderMode) -> Result;
+    pub fn shaderProgramConfigure(sp: *mut shaderProgram_s, sendVshCode: u8,
+                                  sendGshCode: u8) -> Result;
+    pub fn shaderProgramUse(sp: *mut shaderProgram_s) -> Result;
+}
diff --git a/ctru-sys/src/gpu/shbin.rs b/ctru-sys/src/gpu/shbin.rs
new file mode 100644
index 0000000..1c5a453
--- /dev/null
+++ b/ctru-sys/src/gpu/shbin.rs
@@ -0,0 +1,136 @@
+use ::types::*;
+
+#[derive(Clone, Copy)]
+#[repr(u32)]
+pub enum Enum_Unnamed1 {
+    VERTEX_SHDR = 0,
+    GEOMETRY_SHDR = 1,
+}
+pub type DVLE_type = Enum_Unnamed1;
+#[derive(Clone, Copy)]
+#[repr(u32)]
+pub enum Enum_Unnamed2 {
+    DVLE_CONST_BOOL = 0,
+    DVLE_CONST_u8 = 1,
+    DVLE_CONST_FLOAT24 = 2,
+}
+pub type DVLE_constantType = Enum_Unnamed2;
+#[derive(Clone, Copy)]
+#[repr(u32)]
+pub enum Enum_Unnamed3 {
+    RESULT_POSITION = 0,
+    RESULT_NORMALQUAT = 1,
+    RESULT_COLOR = 2,
+    RESULT_TEXCOORD0 = 3,
+    RESULT_TEXCOORD0W = 4,
+    RESULT_TEXCOORD1 = 5,
+    RESULT_TEXCOORD2 = 6,
+    RESULT_VIEW = 8,
+}
+pub type DVLE_outputAttribute_t = Enum_Unnamed3;
+#[repr(C)]
+#[derive(Copy)]
+pub struct Struct_Unnamed4 {
+    pub codeSize: u32,
+    pub codeData: *mut u32,
+    pub opdescSize: u32,
+    pub opcdescData: *mut u32,
+}
+impl ::core::clone::Clone for Struct_Unnamed4 {
+    fn clone(&self) -> Self { *self }
+}
+impl ::core::default::Default for Struct_Unnamed4 {
+    fn default() -> Self { unsafe { ::core::mem::zeroed() } }
+}
+pub type DVLP_s = Struct_Unnamed4;
+#[repr(C)]
+#[derive(Copy)]
+pub struct Struct_Unnamed5 {
+    pub _type: u16,
+    pub id: u16,
+    pub data: [u32; 4usize],
+}
+impl ::core::clone::Clone for Struct_Unnamed5 {
+    fn clone(&self) -> Self { *self }
+}
+impl ::core::default::Default for Struct_Unnamed5 {
+    fn default() -> Self { unsafe { ::core::mem::zeroed() } }
+}
+pub type DVLE_constEntry_s = Struct_Unnamed5;
+#[repr(C)]
+#[derive(Copy)]
+pub struct Struct_Unnamed6 {
+    pub _type: u16,
+    pub regID: u16,
+    pub mask: u8,
+    pub unk: [u8; 3usize],
+}
+impl ::core::clone::Clone for Struct_Unnamed6 {
+    fn clone(&self) -> Self { *self }
+}
+impl ::core::default::Default for Struct_Unnamed6 {
+    fn default() -> Self { unsafe { ::core::mem::zeroed() } }
+}
+pub type DVLE_outEntry_s = Struct_Unnamed6;
+#[repr(C)]
+#[derive(Copy)]
+pub struct Struct_Unnamed7 {
+    pub symbolOffset: u32,
+    pub startReg: u16,
+    pub endReg: u16,
+}
+impl ::core::clone::Clone for Struct_Unnamed7 {
+    fn clone(&self) -> Self { *self }
+}
+impl ::core::default::Default for Struct_Unnamed7 {
+    fn default() -> Self { unsafe { ::core::mem::zeroed() } }
+}
+pub type DVLE_uniformEntry_s = Struct_Unnamed7;
+#[repr(C)]
+#[derive(Copy)]
+pub struct Struct_Unnamed8 {
+    pub _type: DVLE_type,
+    pub dvlp: *mut DVLP_s,
+    pub mainOffset: u32,
+    pub endmainOffset: u32,
+    pub constTableSize: u32,
+    pub constTableData: *mut DVLE_constEntry_s,
+    pub outTableSize: u32,
+    pub outTableData: *mut DVLE_outEntry_s,
+    pub uniformTableSize: u32,
+    pub uniformTableData: *mut DVLE_uniformEntry_s,
+    pub symbolTableData: *mut u8,
+    pub outmapMask: u8,
+    pub outmapData: [u32; 8usize],
+    pub outmapMode: u32,
+    pub outmapClock: u32,
+}
+impl ::core::clone::Clone for Struct_Unnamed8 {
+    fn clone(&self) -> Self { *self }
+}
+impl ::core::default::Default for Struct_Unnamed8 {
+    fn default() -> Self { unsafe { ::core::mem::zeroed() } }
+}
+pub type DVLE_s = Struct_Unnamed8;
+#[repr(C)]
+#[derive(Copy)]
+pub struct Struct_Unnamed9 {
+    pub numDVLE: u32,
+    pub DVLP: DVLP_s,
+    pub DVLE: *mut DVLE_s,
+}
+impl ::core::clone::Clone for Struct_Unnamed9 {
+    fn clone(&self) -> Self { *self }
+}
+impl ::core::default::Default for Struct_Unnamed9 {
+    fn default() -> Self { unsafe { ::core::mem::zeroed() } }
+}
+pub type DVLB_s = Struct_Unnamed9;
+extern "C" {
+    pub fn DVLB_ParseFile(shbinData: *mut u32, shbinSize: u32)
+     -> *mut DVLB_s;
+    pub fn DVLB_Free(dvlb: *mut DVLB_s);
+    pub fn DVLE_GetUniformRegister(dvle: *mut DVLE_s,
+                                   name: *const u8) -> s8;
+    pub fn DVLE_GenerateOutmap(dvle: *mut DVLE_s);
+}