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authorJason Maskell <[email protected]>2016-05-09 10:39:54 +0200
committerJason Maskell <[email protected]>2016-05-09 10:39:54 +0200
commit79b3462799c28af8ba586349bd671b1b56e72353 (patch)
tree3b06e36c390254c0dc7f3733a0d32af213d87293 /src/generated/ComputeH0_cs_5_0.h
downloadwaveworks_archive-79b3462799c28af8ba586349bd671b1b56e72353.tar.xz
waveworks_archive-79b3462799c28af8ba586349bd671b1b56e72353.zip
Initial commit with PS4 and XBone stuff trimmed.
Diffstat (limited to 'src/generated/ComputeH0_cs_5_0.h')
-rw-r--r--src/generated/ComputeH0_cs_5_0.h316
1 files changed, 316 insertions, 0 deletions
diff --git a/src/generated/ComputeH0_cs_5_0.h b/src/generated/ComputeH0_cs_5_0.h
new file mode 100644
index 0000000..fd599b4
--- /dev/null
+++ b/src/generated/ComputeH0_cs_5_0.h
@@ -0,0 +1,316 @@
+#if 0
+//
+// Generated by Microsoft (R) D3D Shader Disassembler
+//
+//
+// Input signature:
+//
+// Name Index Mask Register SysValue Format Used
+// -------------------- ----- ------ -------- -------- ------- ------
+// no Input
+//
+// Output signature:
+//
+// Name Index Mask Register SysValue Format Used
+// -------------------- ----- ------ -------- -------- ------- ------
+// no Output
+cs_5_0
+dcl_globalFlags refactoringAllowed
+dcl_constantbuffer cb0[4], immediateIndexed
+dcl_resource_structured t0, 8
+dcl_uav_structured u0, 8
+dcl_input vThreadID.xy
+dcl_temps 2
+dcl_thread_group 512, 1, 1
+ult r0.x, vThreadID.x, cb0[0].x
+if_nz r0.x
+ iadd r0.xy, vThreadID.xyxx, -cb0[0].zzzz
+ imul null, r0.zw, r0.xxxy, r0.xxxy
+ iadd r0.z, r0.w, r0.z
+ itof r0.z, r0.z
+ sqrt r0.z, r0.z
+ or r0.w, r0.y, r0.x
+ ine r0.w, r0.w, l(0)
+ ge r1.x, r0.z, cb0[1].z
+ and r0.w, r0.w, r1.x
+ lt r0.z, r0.z, cb0[1].w
+ and r0.z, r0.z, r0.w
+ itof r0.xy, r0.xyxx
+ mul r0.xy, r0.xyxx, cb0[2].zzzz
+ mul r1.xy, r0.xyxx, r0.xyxx
+ add r0.w, r1.y, r1.x
+ mul r0.xy, r0.xyxx, cb0[2].xyxx
+ add r0.x, r0.y, r0.x
+ mul r0.y, r0.x, cb0[2].w
+ mul r1.x, r0.w, r0.w
+ mul r1.x, r0.w, r1.x
+ rsq r1.x, r1.x
+ mul r0.y, r0.y, r1.x
+ lt r0.x, r0.x, l(0.000000)
+ mul r1.x, r0.y, cb0[3].x
+ movc r0.x, r0.x, r1.x, r0.y
+ div r0.y, cb0[3].y, r0.w
+ mad r0.y, cb0[3].z, r0.w, r0.y
+ mul r0.y, r0.y, l(1.442695)
+ exp r0.y, r0.y
+ mul r0.x, r0.y, r0.x
+ and r0.x, r0.x, r0.z
+ imad r0.y, vThreadID.y, cb0[0].y, vThreadID.x
+ iadd r0.z, r0.y, -vThreadID.y
+ ld_structured_indexable(structured_buffer, stride=8)(mixed,mixed,mixed,mixed) r0.zw, r0.z, l(0), t0.xxxy
+ mul r0.xz, r0.zzwz, r0.xxxx
+ store_structured u0.xy, r0.y, l(0), r0.xzxx
+ ieq r0.xz, vThreadID.yyxy, l(0, 0, 0, 0)
+ or r0.x, r0.z, r0.x
+ if_nz r0.x
+ iadd r0.x, -r0.y, cb0[1].x
+ store_structured u0.xy, r0.x, l(0), l(0,0,0,0)
+ endif
+endif
+ret
+// Approximately 0 instruction slots used
+#endif
+
+const BYTE g_ComputeH0[] =
+{
+ 68, 88, 66, 67, 173, 99,
+ 70, 182, 150, 238, 12, 102,
+ 71, 253, 22, 74, 166, 66,
+ 118, 248, 1, 0, 0, 0,
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+ 8, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0,
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+ 30, 0, 0, 8, 50, 0,
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+ 70, 0, 2, 0, 166, 138,
+ 32, 128, 65, 0, 0, 0,
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+ 21, 0, 0, 1, 21, 0,
+ 0, 1, 62, 0, 0, 1
+};