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| author | Andrew Reidmeyer <[email protected]> | 2017-03-15 09:28:59 -0600 |
|---|---|---|
| committer | Andrew Reidmeyer <[email protected]> | 2017-03-15 09:28:59 -0600 |
| commit | f5f6a899903a309f1fc93b31c0297fc7b3b5cf46 (patch) | |
| tree | ed3dece338b579d5b51af494b2d543fb46c43fa3 /demo/Shaders/customEmitAllocCS.hlsl | |
| download | flow-1.0.0.tar.xz flow-1.0.0.zip | |
Initial 1.0.0 binary releasev1.0.0
Diffstat (limited to 'demo/Shaders/customEmitAllocCS.hlsl')
| -rw-r--r-- | demo/Shaders/customEmitAllocCS.hlsl | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/demo/Shaders/customEmitAllocCS.hlsl b/demo/Shaders/customEmitAllocCS.hlsl new file mode 100644 index 0000000..930ef4f --- /dev/null +++ b/demo/Shaders/customEmitAllocCS.hlsl @@ -0,0 +1,34 @@ +/* +* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. +* +* NVIDIA CORPORATION and its licensors retain all intellectual property +* and proprietary rights in and to this software, related documentation +* and any modifications thereto. Any use, reproduction, disclosure or +* distribution of this software and related documentation without an express +* license agreement from NVIDIA CORPORATION is strictly prohibited. +*/ + +#define THREAD_DIM_X 8 +#define THREAD_DIM_Y 8 +#define THREAD_DIM_Z 8 + +typedef uint4 NvFlowUint4; + +cbuffer params : register(b0) +{ + NvFlowUint4 minMaskIdx; + NvFlowUint4 maxMaskIdx; +}; + +RWTexture3D<uint> maskUAV : register(u0); + +[numthreads(THREAD_DIM_X, THREAD_DIM_Y, THREAD_DIM_Z)] +void customEmitAllocCS(uint3 tidx : SV_DispatchThreadID) +{ + int3 maskIdx = tidx + minMaskIdx.xyz; + + if (all(maskIdx >= int3(minMaskIdx.xyz)) && all(maskIdx < int3(maxMaskIdx.xyz))) + { + maskUAV[maskIdx] = 1u; + } +}
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