diff options
| author | Graydon Hoare <[email protected]> | 2010-07-22 12:11:39 -0700 |
|---|---|---|
| committer | Graydon Hoare <[email protected]> | 2010-07-22 12:11:39 -0700 |
| commit | c96634af4b17eb4c92df8c3b38e6ed74cfcf9628 (patch) | |
| tree | 6f949a3b5a8a5dc2a2f3fdfdc108f68d377dd84a /src/boot | |
| parent | Fix simple generic type parameters in LLVM. (diff) | |
| download | rust-c96634af4b17eb4c92df8c3b38e6ed74cfcf9628.tar.xz rust-c96634af4b17eb4c92df8c3b38e6ed74cfcf9628.zip | |
Fix mem op= mem bug in trans.ml (via not terribly good fix). Closes #111.
Diffstat (limited to 'src/boot')
| -rw-r--r-- | src/boot/me/trans.ml | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/boot/me/trans.ml b/src/boot/me/trans.ml index d8128196..be7adc1a 100644 --- a/src/boot/me/trans.ml +++ b/src/boot/me/trans.ml @@ -4343,8 +4343,15 @@ let trans_visitor trans_vec_append dst_cell dst_ty src_oper (atom_type cx a_src) | _ -> let (dst_cell, _) = deref_ty DEREF_none false dst_cell dst_ty in + let bits = Il.operand_bits word_bits src_oper in + (* + * FIXME: X86-ism going via a vreg; mem op= mem doesn't work and + * IL lacks sufficient brains to cope just now. + *) + let src = Il.Reg (Il.next_vreg (emitter()), Il.ValTy bits) in let op = trans_binop binop in - emit (Il.binary op dst_cell (Il.Cell dst_cell) src_oper); + mov src src_oper; + emit (Il.binary op dst_cell (Il.Cell dst_cell) (Il.Cell src)); and trans_call id dst flv args = |