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| author | Graydon Hoare <[email protected]> | 2010-09-09 18:56:51 -0700 |
|---|---|---|
| committer | Graydon Hoare <[email protected]> | 2010-09-09 18:56:51 -0700 |
| commit | 79dc07d6487612ebf9ac62e43a5729ea774488b9 (patch) | |
| tree | e9dd8b7266621e98476f1a2c9023e4556a186e7d /src/boot/be/x86.ml | |
| parent | Switch tags to purely nominal, removing TY_iso and TY_idx. Seems to mostly wo... (diff) | |
| download | rust-79dc07d6487612ebf9ac62e43a5729ea774488b9.tar.xz rust-79dc07d6487612ebf9ac62e43a5729ea774488b9.zip | |
Use hashtable rather than bitset for vreg constraints in ra; speeds compilation.
Diffstat (limited to 'src/boot/be/x86.ml')
| -rw-r--r-- | src/boot/be/x86.ml | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/boot/be/x86.ml b/src/boot/be/x86.ml index f4475894..eb96d0ac 100644 --- a/src/boot/be/x86.ml +++ b/src/boot/be/x86.ml @@ -385,7 +385,7 @@ let emit_target_specific ;; -let constrain_vregs (q:Il.quad) (hregs:Bits.t array) : unit = +let constrain_vregs (q:Il.quad) (hregs:(Il.vreg,Bits.t) Hashtbl.t) : unit = let involves_8bit_cell = let b = ref false in @@ -402,6 +402,10 @@ let constrain_vregs (q:Il.quad) (hregs:Bits.t array) : unit = !b in + let get_hregs v = + htab_search_or_add hregs v (fun _ -> Bits.create n_hardregs true) + in + let qp_mem _ m = m in let qp_cell _ c = begin @@ -409,7 +413,7 @@ let constrain_vregs (q:Il.quad) (hregs:Bits.t array) : unit = Il.Reg (Il.Vreg v, _) when involves_8bit_cell -> (* 8-bit register cells must only be al, cl, dl, bl. * Not esi/edi. *) - let hv = hregs.(v) in + let hv = get_hregs v in List.iter (fun bad -> Bits.set hv bad false) [esi; edi] | _ -> () end; @@ -425,7 +429,7 @@ let constrain_vregs (q:Il.quad) (hregs:Bits.t array) : unit = begin match b.Il.binary_rhs with Il.Cell (Il.Reg (Il.Vreg v, _)) -> - let hv = hregs.(v) in + let hv = get_hregs v in (* Shift src has to be ecx. *) List.iter (fun bad -> Bits.set hv bad false) |