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| author | Fuwn <[email protected]> | 2023-11-13 17:44:12 -0800 |
|---|---|---|
| committer | Fuwn <[email protected]> | 2023-11-13 17:44:12 -0800 |
| commit | e4f904587bf05dadc615f60d1f0b1519442451e4 (patch) | |
| tree | ba4e9658dbbaa6e0b9875ae38401200b6c7331f9 /bcd_adder.v | |
| download | iverilog-test-bench-main.tar.xz iverilog-test-bench-main.zip | |
Diffstat (limited to 'bcd_adder.v')
| -rw-r--r-- | bcd_adder.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/bcd_adder.v b/bcd_adder.v new file mode 100644 index 0000000..16790bd --- /dev/null +++ b/bcd_adder.v @@ -0,0 +1,13 @@ +module bcd_adder( + input wire [3:0] a, + input wire [3:0] b, + output reg [7:0] x +); + always @(*) begin + assign x = a + b; + + if (x > 9) begin + x = x + 6; + end + end +endmodule |