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authorFuwn <[email protected]>2023-11-13 17:44:12 -0800
committerFuwn <[email protected]>2023-11-13 17:44:12 -0800
commite4f904587bf05dadc615f60d1f0b1519442451e4 (patch)
treeba4e9658dbbaa6e0b9875ae38401200b6c7331f9 /Makefile
downloadiverilog-test-bench-main.tar.xz
iverilog-test-bench-main.zip
feat: initial releaseHEADmain
Diffstat (limited to 'Makefile')
-rw-r--r--Makefile17
1 files changed, 17 insertions, 0 deletions
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..79eeef9
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,17 @@
+TOP = bcd_to_seven_test
+SRC = bcd_to_seven.v bcd_adder.v
+TEST_SRC = bcd_to_seven_test.v
+BIN = $(TOP).vvp
+
+$(BIN): $(SRC) $(TEST_SRC)
+ iverilog -gsupported-assertions -o $(BIN) -s $(TOP) $(SRC) $(TEST_SRC)
+
+.PHONY: all clean test
+
+all: $(BIN)
+
+test: $(BIN)
+ vvp $(BIN)
+
+clean:
+ rm -f *.vvp *.vcd