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# CST456-Midterm Exam
**CST456 – Midterm Exam**
Write a hierarchical testbench for following ALU:
**Design Under Verification (DUV)**
The ALU contains the following ports:
| **Port Name** | **Signal Type** | **Direction** | **Number of Bits** |
| --- | --- | --- | --- |
| clk | Clock | Input | 1 |
| op_start | Control | Input | 1 |
| operation | Control | Input | 2 |
| operand_a | Data | Input | 8 |
| operand_b | Data | Input | 8 |
| result | Data | Output | 16 |
At the rising edge of the clock, if op_start is asserted (== 1’b1)
then the operation, operand_a, and operand_b signals are latched into
the ALU. Exactly two clock cycles later the result of the operation is
read from the result port. The ALU supports the following operations:
| **Name** | **Value** | **Description** |
| --- | --- | --- |
| ADD | 2’b00 | operand_a is added to operand_b. Only the lower nine bits of the result are used. |
| MULT | 2’b01 | operand_a is multiplied with operand_b. This is an unsigned operation and all sixteen bits of the result are used. |
| OR | 2’b10 | operand_a is bitwise ORed with operand_b. Only the lower eight bits of the result are used. |
| AND | 2’b11 | operand_a is bitwise ANDed with operand_b. Only the lower eight bits of the result are used. |
Figure 1 shows a timing diagram for the addition operation, where 1 + 3 = 4.
**Figure 1 - Timing diagram for an addition operation.**
**Hierarchical Testbench**
The hierarchical testbench should consists of following modules:
1.Interface module:
The interface is a module that holds all the signals of the DUT. Interface should not have any task or function. But should have a clocking block
2.Transaction module:
Transaction module should define the variables to be randomized. Also any print, info, etc. should be defined within transaction module.
3.Scoreboard and Monitor combined module:
This module must have one function and one task. Function
(compute_expected_value) should receive the input values
from transaction module and calculate the expected values
and perform the comparison of the expected output and DUV
output. The task (check) should receive the values of input
and output from interface and should pass them to
transaction module. Task should call the
compute_expected_value function to calculate expected
output.
4.Bus functional module (BFM):
Bus functional model should perform the randomization
process in a task (drive). It should also perform the data
transfer from transaction module to interface and interface
to transaction module in another task(drive_trxn).
Testbench should not contain any program block. BFM’s drive task
and scoreboard’s check task must be the only ones called within
testbench. Testbench should use fork statement. The clock must
be also created within the testbench. Every combination of
inputs, expected result, and real result must be printed to the
command window using a print function defined in the transaction
module.
**(You can use the example in Lecture 4 (pp.30-34) as a reference)**
**Midterm Submission**
Zip the entire contents of the midterm directory and submit it to
canvas.
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