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// Contains the FAIL_UNLESS_EQUAL and RND_CHECK macros.
`include "macro.svh"
`include "typedef_pkg.sv"
`include "interface.sv"
`include "scoreboard.sv"
`include "monitor.sv"
`include "generator.sv"
module tb;
import typedef_pkg::*;
// [Step 1] Declare signals that connect to DUV. Initialise the clk signal with a value of 1'b0
logic clk = 1'b0;
// [Step 2] Instantiate the interface, scoreboard, monitor and generator.
intf intf0 (.clk(clk));
scoreboard sb;
monitor mon;
generator gen;
// [Step 3] Instantiate the DUV module.
duv ALU0 (
.clk(clk),
.op_start(intf0.op_start),
.operation(intf0.operation),
.operand_a(intf0.operand_a),
.operand_b(intf0.operand_b),
.result(intf0.result)
);
// [Step 4] Always block to generate the clock.
always #1ns clk = ~clk;
// [Step 5] Create the covergroup for functional coverage.
covergroup alu_cg;
cp_op: coverpoint gen.op;
cp_a: coverpoint gen.a;
cp_b: coverpoint gen.b;
endgroup
// [Step 6] Instantiate the covergroup.
alu_cg cg;
initial begin
// Create class instances
sb = new();
mon = new(sb);
gen = new(intf0);
// [Step 7] Create a new instance of covergroup.
cg = new();
repeat (500) begin
@(negedge clk);
// [Step 8] Call sitimulus task from generator.
gen.sitimulus();
// [Step 9] Pass randomised variables to scoreboard.
sb.operation = gen.op;
sb.operand_a = gen.a;
sb.operand_b = gen.b;
@(negedge clk);
// [Step 10] Pass result to scoreboard.
sb.result = gen.out_put;
// [Step 11] Start sampling of the functional coverage.
cg.sample();
// Write randomised parameters and result on screen (in decimal)
$display("op=%s a=%0d b=%0d result=%0d", sb.operation.name(), sb.operand_a, sb.operand_b,
sb.result);
// [Step 12] Call check task from monitor.
mon.check();
end //Repeat
end //Initial;
initial begin : B
#10300;
$display("finished successfully");
$finish();
end : B
endmodule : tb
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