homework_2/SRC/tb.sv


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`include "uvm_macros.svh"
import uvm_pkg::*;

`include "interface.sv"
`include "item.sv"
`include "gen_item_seq.sv"
`include "monitor.sv"
`include "scoreboard.sv"
`include "driver.sv"
`include "agent.sv"
`include "env.sv"
`include "base_test.sv"

module tb;
  reg clk;

  always #10 clk = ~clk;

  des_if _if (clk);

  duv u0 (
      .clk  (clk),
      .reset(_if.reset),
      .inp  (_if.inp),
      .outp (_if.outp)
  );

  initial begin
    clk <= 0;

    uvm_config_db#(virtual des_if)::set(null, "uvm_test_top", "des_vif", _if);

    run_test("test_both_patterns");
  end
endmodule