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module duv (
input logic clock,
input logic reset,
input logic input_,
output logic output_
);
localparam S0 = 3'b000, // Initial
S1 = 3'b001, // Seen "1"
S2 = 3'b010, // Seen "11"
S3 = 3'b011, // Seen "10"
S4 = 3'b100, // Seen "110"
S5 = 3'b101; // Seen "101"
logic [2:0] state, next_state;
// State register with asynchronous reset
always_ff @(posedge clock or posedge reset) begin
if (reset) state <= S0;
else state <= next_state;
end
// Next state and output logic
always_comb begin
next_state = state;
output_ = 1'b0;
case (state)
S0: next_state = input_ ? S1 : S0;
S1: next_state = input_ ? S2 : S3;
S2: next_state = input_ ? S2 : S4;
S3: next_state = input_ ? S5 : S0;
S4: begin
if (input_) begin
next_state = S5;
end else begin
next_state = S0;
output_ = 1'b1; // Detected "1100"
end
end
S5: begin
if (input_) begin
next_state = S2;
output_ = 1'b1; // Detected "1011"
end else begin
next_state = S3;
end
end
default: next_state = S0;
endcase
end
endmodule
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