1 files changed, 67 insertions, 0 deletions
diff --git a/lab_5/SRC/tb.sv b/lab_5/SRC/tb.sv
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+++ b/lab_5/SRC/tb.sv
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+// Contains the FAIL_UNLESS_EQUAL and RND_CHECK macros.
+`include "macro.svh"
+`include "typedef_pkg.sv"
+`include "interface.sv"
+`include "scoreboard.sv"
+`include "monitor.sv"
+`include "generator.sv"
+module tb;
+import typedef_pkg::*;
+
+// [Step 1] Declare signals that connect to DUV. Intialize the clk signal with a value of 1'b0	
+
+// [Step 2] Instantiate the interface, scoreboard, monitor and generator.	
+		   
+ 
+// [Step 3] Instantiate the DUV module.
+		
+	
+// [Step 4] Always block to generate the clock.
+
+		
+// [Step 5] Create the covergroup for functional covarege.
+
+	
+// [Step 6] Instantiate the covergroup.	
+
+	
+	initial begin	
+		
+
+	// [Step 7] Create a new isntance of covergroup.
+ 
+		repeat (500) begin
+			@(negedge clk);		
+				
+				// [Step 8] Call sitimulus task from generator.
+				
+				// [Step 9] Pass randomized variables to scoreboard.
+				
+				
+			@(negedge clk);	
+				// [Step 10] Pass result to scoreboard.
+				
+				// [Step 11] Start sampling of the functional covarege.
+			
+			// Write a randomized parameters and result on screen (in decimal)	
+			
+			
+			// [Step 12] call check task from monitor.
+					
+		end //Repeat
+		
+		
+		
+	end //Initial;
+	
+	
+	
+	
+initial begin: B
+		
+		#10300;
+		$display ("finished successfully");
+		$finish();
+      
+	end: B
+endmodule : tb
+\ No newline at end of file