1 files changed, 65 insertions, 86 deletions
diff --git a/homework_2/SRC/duv.sv b/homework_2/SRC/duv.sv
index e7e0c0f..62e5b99 100644
--- a/homework_2/SRC/duv.sv
+++ b/homework_2/SRC/duv.sv
@@ -1,86 +1,65 @@
-module duv ( input clk,
-                  input rstn,
-                  input in,
-                  output out );
-  
-  parameter IDLE 	= 0,
-  			S1 		= 1,
-  			S10 	= 2,
-  			S101 	= 3,
-  			S1011 	= 4;
-  
-  reg [2:0] cur_state, next_state;
-  
-  assign out = cur_state == S1011 ? 1 : 0;
-  
-  always @ (posedge clk) begin
-    if (!rstn)
-      	cur_state <= IDLE;
-     else 
-     	cur_state <= next_state;
-  end
-  
-  always @ (cur_state or in) begin
-    case (cur_state)
-      IDLE : begin
-        if (in) next_state = S1;
-        else next_state = IDLE;
-      end
-      
-      S1: begin
-`ifdef BUG_FIX_1        
-        // Designer assumed that if next input is 1,
-        // state should start from IDLE. But he forgot
-        // that it should stay in same state since it
-        // already matched part of the pattern which 
-        // is the starting "1"        
-        if (in) next_state = S1;
-`else
-        if (in) next_state = IDLE;
-`endif        
-        else 	next_state = S10;
-      end
-      
-      S10 : begin
-        if (in) next_state = S101;        
-        else 	next_state = IDLE;
-      end
-      
-      S101 : begin
-        if (in) next_state = S1011;
-`ifdef BUG_FIX_2        
-        // Designer assumed that if next input is 0, 
-        // then pattern fails to match and should
-        // restart. But he forgot that S101 followed
-        // by 0 actually matches part of the pattern
-        // which is "10" and only "11" is remaining
-        // So it should actually go back to S10        
-		else 	next_state = S10;
-`else        
-        else 	next_state = IDLE;
-`endif        
-      end
-      
-      S1011: begin
-`ifdef BUG_FIX_3       
-        // Designer assumed next state should always
-        // be IDLE since the pattern has matched. But
-        // he forgot that if next input is 1, it is
-        // already the start of another sequence and
-        // instead should go to S1.        
-        if (in) next_state = S1; 
-	`ifdef BUG_FIX_4        
-        // Designer forgot again that if next input is 0
-        // then pattern still matches "10" and should
-        // go to S10 instead of IDLE.
-        else    next_state = S10;
-    `else
-        else    next_state = IDLE;
-	`endif
-`else
-       	next_state = IDLE;
-`endif        
-      end
-    endcase
-  end
-endmodule
-\ No newline at end of file
+module duv (
+    input  logic clk,
+    input  logic reset,
+    input  logic inp,
+    output logic outp
+);
+  localparam S0 = 3'b000, S1 = 3'b001, S11 = 3'b010, S10 = 3'b011, S110 = 3'b100, S101 = 3'b101;
+
+  logic [2:0] state;
+  logic [2:0] next_state;
+
+  // State register with asynchronous active-high reset
+  always_ff @(posedge clk or posedge reset) begin
+    if (reset) state <= S0;
+    else state <= next_state;
+  end
+
+  // Mealy next-state and output logic for 1011 and 1100
+  always_comb begin
+    next_state = state;
+    outp = 1'b0;
+
+    case (state)
+      S0: begin
+        if (inp) next_state = S1;
+        else next_state = S0;
+      end
+
+      S1: begin
+        if (inp) next_state = S11;
+        else next_state = S10;
+      end
+
+      S11: begin
+        if (inp) next_state = S11;
+        else next_state = S110;
+      end
+
+      S10: begin
+        if (inp) next_state = S101;
+        else next_state = S0;
+      end
+
+      S110: begin
+        if (inp) begin
+          next_state = S101;
+        end else begin
+          next_state = S0;
+          outp = 1'b1;  // Detected 1100
+        end
+      end
+
+      S101: begin
+        if (inp) begin
+          next_state = S11;
+          outp = 1'b1;  // Detected 1011
+        end else begin
+          next_state = S10;
+        end
+      end
+
+      default: next_state = S0;
+    endcase
+  end
+endmodule