feat(lab_5): Implement lab

6 files changed, 126 insertions, 55 deletions

diff --git a/lab_5/SIM/run_sim_cli.bat b/lab_5/SIM/run_sim_cli.bat
new file mode 100644
index 0000000..eee735f
--- /dev/null
+++ b/lab_5/SIM/run_sim_cli.bat
@@ -0,0 +1,4 @@
+call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv -i ../SRC ../SRC/tb.sv ../SRC/duv.sv
+if %ERRORLEVEL% EQU 0 call C:\Xilinx\Vivado\2022.1\bin\xelab -nolog -debug all tb
+if %ERRORLEVEL% EQU 0 call C:\Xilinx\Vivado\2022.1\bin\xsim tb -R
+pause
diff --git a/lab_5/SIM/run_sim_gui.bat b/lab_5/SIM/run_sim_gui.bat
new file mode 100644
index 0000000..1af4eeb
--- /dev/null
+++ b/lab_5/SIM/run_sim_gui.bat
@@ -0,0 +1,3 @@
+call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv -i ../SRC ../SRC/tb.sv ../SRC/duv.sv
+if %ERRORLEVEL% EQU 0 call C:\Xilinx\Vivado\2022.1\bin\xelab -nolog -debug all tb
+if %ERRORLEVEL% EQU 0 call C:\Xilinx\Vivado\2022.1\bin\xsim tb -gui
diff --git a/lab_5/SRC/macro.svh b/lab_5/SRC/macro.svh
index 72bf471..4b9083b 100644
--- a/lab_5/SRC/macro.svh
+++ b/lab_5/SRC/macro.svh
@@ -11,4 +11,9 @@
         $display ("Randomization failure. Simulation halted."); \
         $finish; \
     end
+
+    `define FAIL(msg="") \
+    begin \
+        $display ("FAIL: %s", msg); \
+    end
 `endif
diff --git a/lab_5/SRC/monitor.sv b/lab_5/SRC/monitor.sv
index 2ce97c7..2980125 100644
--- a/lab_5/SRC/monitor.sv
+++ b/lab_5/SRC/monitor.sv
@@ -1 +1,38 @@
-//create a monitor class
\ No newline at end of file
+//create a monitor class
+import typedef_pkg::*;
+
+class monitor;
+  scoreboard sb;
+
+  function new(scoreboard sb_in);
+    sb = sb_in;
+  endfunction
+
+  task check();
+    automatic result_t expected_result;
+
+    case (sb.operation)
+      ADD: begin
+        expected_result = (sb.operand_a + sb.operand_b) & 16'h01FF;
+        `FAIL_UNLESS_EQUAL(expected_result, sb.result & 16'h01FF, $sformatf(
+                           "ADD a=%0d b=%0d", sb.operand_a, sb.operand_b))
+      end
+      MULT: begin
+        expected_result = sb.operand_a * sb.operand_b;
+        `FAIL_UNLESS_EQUAL(expected_result, sb.result, $sformatf(
+                           "MULT a=%0d b=%0d", sb.operand_a, sb.operand_b))
+      end
+      OR: begin
+        expected_result = (sb.operand_a | sb.operand_b) & 16'h00FF;
+        `FAIL_UNLESS_EQUAL(expected_result, sb.result & 16'h00FF, $sformatf(
+                           "OR a=%0d b=%0d", sb.operand_a, sb.operand_b))
+      end
+      AND: begin
+        expected_result = (sb.operand_a & sb.operand_b) & 16'h00FF;
+        `FAIL_UNLESS_EQUAL(expected_result, sb.result & 16'h00FF, $sformatf(
+                           "AND a=%0d b=%0d", sb.operand_a, sb.operand_b))
+      end
+      default: `FAIL($sformatf("Unknown operation: %0d", sb.operation))
+    endcase
+  endtask
+endclass
diff --git a/lab_5/SRC/scoreboard.sv b/lab_5/SRC/scoreboard.sv
index 9d05cc0..1dc09d0 100644
--- a/lab_5/SRC/scoreboard.sv
+++ b/lab_5/SRC/scoreboard.sv
@@ -1 +1,9 @@
-// create scoreboard class
\ No newline at end of file
+// create scoreboard class
+import typedef_pkg::*;
+
+class scoreboard;
+  operation_t operation;
+  operand_t operand_a;
+  operand_t operand_b;
+  result_t result;
+endclass
diff --git a/lab_5/SRC/tb.sv b/lab_5/SRC/tb.sv
index 6ace7a4..6fea6cb 100644
--- a/lab_5/SRC/tb.sv
+++ b/lab_5/SRC/tb.sv
@@ -6,62 +6,76 @@
 `include "monitor.sv"

 `include "generator.sv"

 module tb;

-import typedef_pkg::*;

+  import typedef_pkg::*;

 

-// [Step 1] Declare signals that connect to DUV. Intialize the clk signal with a value of 1'b0	

+  // [Step 1] Declare signals that connect to DUV. Initialise the clk signal with a value of 1'b0

+  logic clk = 1'b0;

 

-// [Step 2] Instantiate the interface, scoreboard, monitor and generator.	

-		   

- 

-// [Step 3] Instantiate the DUV module.

-		

-	

-// [Step 4] Always block to generate the clock.

+  // [Step 2] Instantiate the interface, scoreboard, monitor and generator.

+  intf intf0 (.clk(clk));

+  scoreboard sb;

+  monitor mon;

+  generator gen;

 

-		

-// [Step 5] Create the covergroup for functional covarege.

+  // [Step 3] Instantiate the DUV module.

+  duv ALU0 (

+      .clk(clk),

+      .op_start(intf0.op_start),

+      .operation(intf0.operation),

+      .operand_a(intf0.operand_a),

+      .operand_b(intf0.operand_b),

+      .result(intf0.result)

+  );

 

-	

-// [Step 6] Instantiate the covergroup.	

+  // [Step 4] Always block to generate the clock.

+  always #1ns clk = ~clk;

 

-	

-	initial begin	

-		

+  // [Step 5] Create the covergroup for functional coverage.

+  covergroup alu_cg;

+    cp_op: coverpoint gen.op;

+    cp_a: coverpoint gen.a;

+    cp_b: coverpoint gen.b;

+  endgroup

 

-	// [Step 7] Create a new isntance of covergroup.

- 

-		repeat (500) begin

-			@(negedge clk);		

-				

-				// [Step 8] Call sitimulus task from generator.

-				

-				// [Step 9] Pass randomized variables to scoreboard.

-				

-				

-			@(negedge clk);	

-				// [Step 10] Pass result to scoreboard.

-				

-				// [Step 11] Start sampling of the functional covarege.

-			

-			// Write a randomized parameters and result on screen (in decimal)	

-			

-			

-			// [Step 12] call check task from monitor.

-					

-		end //Repeat

-		

-		

-		

-	end //Initial;

-	

-	

-	

-	

-initial begin: B

-		

-		#10300;

-		$display ("finished successfully");

-		$finish();

-      

-	end: B

-endmodule : tb
\ No newline at end of file
+  // [Step 6] Instantiate the covergroup.

+  alu_cg cg;

+

+  initial begin

+    // Create class instances

+    sb  = new();

+    mon = new(sb);

+    gen = new(intf0);

+    // [Step 7] Create a new instance of covergroup.

+    cg  = new();

+

+    repeat (500) begin

+      @(negedge clk);

+

+      // [Step 8] Call sitimulus task from generator.

+      gen.sitimulus();

+

+      // [Step 9] Pass randomised variables to scoreboard.

+      sb.operation = gen.op;

+      sb.operand_a = gen.a;

+      sb.operand_b = gen.b;

+

+      @(negedge clk);

+      // [Step 10] Pass result to scoreboard.

+      sb.result = gen.out_put;

+

+      // [Step 11] Start sampling of the functional coverage.

+      cg.sample();

+      // Write randomised parameters and result on screen (in decimal)

+      $display("op=%s a=%0d b=%0d result=%0d", sb.operation.name(), sb.operand_a, sb.operand_b,

+               sb.result);

+      // [Step 12] Call check task from monitor.

+      mon.check();

+    end  //Repeat

+  end  //Initial;

+

+  initial begin : B

+    #10300;

+    $display("finished successfully");

+    $finish();

+  end : B

+endmodule : tb