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| author | Fuwn <[email protected]> | 2026-02-13 23:26:29 -0800 |
|---|---|---|
| committer | Fuwn <[email protected]> | 2026-02-13 23:26:29 -0800 |
| commit | db40dbfb19b40d4c245407bbb289cb184e516f51 (patch) | |
| tree | 0bc5da6db24e62216500789ea2c5790408246ffa /lab_5/SRC/duv.sv | |
| parent | Initial commit (diff) | |
| download | cst456-db40dbfb19b40d4c245407bbb289cb184e516f51.tar.xz cst456-db40dbfb19b40d4c245407bbb289cb184e516f51.zip | |
feat(lab_5): Add initial files
Diffstat (limited to 'lab_5/SRC/duv.sv')
| -rw-r--r-- | lab_5/SRC/duv.sv | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/lab_5/SRC/duv.sv b/lab_5/SRC/duv.sv new file mode 100644 index 0000000..0829654 --- /dev/null +++ b/lab_5/SRC/duv.sv @@ -0,0 +1,28 @@ +
+module duv (
+input logic clk,
+input logic op_start,
+input logic [1:0] operation,
+input logic [7:0] operand_a,
+input logic [7:0] operand_b,
+output logic [15:0] result
+);
+
+logic [15:0] result_tmp;
+
+always_ff @(posedge clk)
+begin
+if( op_start == 1'b1)
+begin
+case (operation)
+ 0: result_tmp = operand_a + operand_b;
+ 1: result_tmp = operand_a * operand_b;
+ 2: result_tmp = operand_a | operand_b;
+ 3: result_tmp = operand_a & operand_b;
+ endcase
+ end
+
+ result <= result_tmp;
+end
+
+endmodule : duv
\ No newline at end of file |