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diff --git a/lab_4/CST456 LAB4.rar b/lab_4/CST456 LAB4.rar
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+++ b/lab_4/CST456 LAB4.rar
diff --git a/lab_4/CST456 Lab4.md b/lab_4/CST456 Lab4.md
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+# CST456 Lab4
+
+**CST456 – Lab 4**
+
+**Simple Randomized Testbench with Scoreboard and Checker**
+
+**Objective**
+
+The objective of this lab is to implement a simple randomized testbench to test the operations and operands of a synchronous arithmetic and logic unit (ALU).
+
+**Design Under Verification (DUV)**
+
+The ALU contains the following ports:
+
+| **Port Name** | **Signal Type** | **Direction** | **Number of Bits** |
+| --- | --- | --- | --- |
+| clk | Clock | Input | 1 |
+| op_start | Control | Input | 1 |
+| operation | Control | Input | 2 |
+| operand_a | Data | Input | 8 |
+| operand_b | Data | Input | 8 |
+| result | Data | Output | 16 |
+
+At the rising edge of the clock, if op_start is asserted (== 1’b1) then the operation, operand_a, and operand_b signals are latched into the ALU. Exactly two clock cycles later the result of the operation is read from the result port. The ALU supports the following operations:
+
+| **Name** | **Value** | **Description** |
+| --- | --- | --- |
+| ADD | 2’b00 | operand_a is added to operand_b. Only the lower 49 bits of the result are used. |
+| MULT | 2’b01 | operand_a is multiplied with operand_b. This is an unsigned operation and all 96 bits of the result are used. |
+| OR | 2’b10 | operand_a is bitwise ORed with operand_b. Only the lower 48 bits of the result are used. |
+| AND | 2’b11 | operand_a is bitwised ANDed with operand_b. Only the lower 48 bits of the result are used. |
+
+**Testbench**
+
+Edit the tb.sv file and create a testbench to test all the operations
+
+for a randomly generated subset of operand values. The testbench will
+
+include a scoreboard struct to log the operation, operand_a,
+
+operand_b, and result values, as well as a checker task that checks
+
+the scoreboard once an operation has completed.
+
+Create a repeat loop to continually generate random values for the
+
+operation, operand_a, and operand_b signals. Use the std::randomize
+
+function and the `RND_CHECK macro to check that randomization was
+
+successful. At the appropriate times log the operation, operand_a,
+
+operand_b, and result values to the scoreboard, and call the checker
+
+task once the scoreboard has been completed. Use the
+
+`FAIL_UNLESS_EQUAL macro to check the expected result with the tested
+
+result. Note that the `FAIL_UNLESS_EQUAL macro does not stop the test
+
+in the event of a failure. To run the simulation in Xilinx Vivado for
+
+Windows execute the following **bat** files under the **SIM** directory:
+
+- run_sim_cli.bat (command line simulation)
+- run_sim_gui.bat (gui simulation with waveform viewer)
+
+**Lab Submission**
+
+Zip the entire contents of the lab directory and submit it to Canvas.
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diff --git a/lab_4/CST456 Lab4.pdf b/lab_4/CST456 Lab4.pdf
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+++ b/lab_4/CST456 Lab4.pdf
diff --git a/lab_4/SIM/run_sim_cli.bat b/lab_4/SIM/run_sim_cli.bat
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+++ b/lab_4/SIM/run_sim_cli.bat
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+call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv ../SRC/typedef_pkg.sv ../SRC/tb.sv ../SRC/duv.sv

+if %ERRORLEVEL% EQU 0 call C:\Xilinx\Vivado\2022.1\bin\xelab -nolog -debug all testbench

+if %ERRORLEVEL% EQU 0 call C:\Xilinx\Vivado\2022.1\bin\xsim testbench -R

+REM Uncomment the next line to keep the cmd window open if executing batch file from Windows Explorer.

+pause

diff --git a/lab_4/SIM/run_sim_gui.bat b/lab_4/SIM/run_sim_gui.bat
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+++ b/lab_4/SIM/run_sim_gui.bat
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+call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv ../SRC/typedef_pkg.sv ../SRC/tb.sv ../SRC/duv.sv

+if %ERRORLEVEL% EQU 0 call C:\Xilinx\Vivado\2022.1\bin\xelab -nolog -debug all testbench

+if %ERRORLEVEL% EQU 0 call C:\Xilinx\Vivado\2022.1\bin\xsim testbench -gui

diff --git a/lab_4/SRC/duv.sv b/lab_4/SRC/duv.sv
new file mode 100644
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+++ b/lab_4/SRC/duv.sv
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+

+module duv (

+input logic clk,

+input logic op_start,

+input logic  [1:0] operation,

+input  logic [7:0] operand_a,

+input  logic [7:0] operand_b,

+output logic [15:0] result

+);

+

+logic [15:0] result_temp;

+

+always_ff @(posedge clk) 

+begin

+if( op_start == 1'b1)

+begin

+case (operation)

+      0:             result_temp = operand_a + operand_b;

+      1:             result_temp = operand_a * operand_b;

+      2:             result_temp = operand_a | operand_b;

+      3:             result_temp = operand_a & operand_b;

+    endcase

+  end

+

+	// result <= result_temp;

+end

+always_ff @(posedge clk) 

+begin

+result = result_temp;

+end

+endmodule : duv
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diff --git a/lab_4/SRC/macro.svh b/lab_4/SRC/macro.svh
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+++ b/lab_4/SRC/macro.svh
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+`ifndef MACRO_SVH
+    `define MACRO_SVH
+
+    `define FAIL_UNLESS_EQUAL(a,b,c="") \
+    if ((a) !== (b)) begin \
+        $display ("FAIL_UNLESS_EQUAL[%s]: Expected %h but actual value is %h.", c, a, b); \
+    end
+
+    `define RND_CHECK(a) \
+    if (!a) begin \
+        $display ("Randomization failure. Simulation halted."); \
+        $finish; \
+    end
+`endif
diff --git a/lab_4/SRC/tb.sv b/lab_4/SRC/tb.sv
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+++ b/lab_4/SRC/tb.sv
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+// Contains the FAIL_UNLESS_EQUAL and RND_CHECK macros.

+`include "macro.svh"

+

+module testbench;

+  // [Step 1] Declare signals that connect to DUV. Intialize the clk signal with a value of 1'b0.

+  import typedef_pkg::*;

+

+  logic        clk = 1'b0;

+  logic        op_start;

+  logic [ 1:0] operation;

+  logic [ 7:0] operand_a;

+  logic [ 7:0] operand_b;

+  logic [15:0] result;

+

+  // [Step 2] Declare the scoreboard that holds the operation, operand_a, operand_b, and results values.

+  typedef struct {

+    operation_t  operation;

+    logic [7:0]  operand_a;

+    logic [7:0]  operand_b;

+    logic [15:0] result;

+  } scoreboard_t;

+

+  // [Step 3] Instantiate the DUV module.

+  duv ALU0 (

+      .clk(clk),

+      .op_start(op_start),

+      .operation(operation),

+      .operand_a(operand_a),

+      .operand_b(operand_b),

+      .result(result)

+  );

+

+  // [Step 4] Always block to generate the clock.

+  always #1ns clk = ~clk;

+

+  // [Step 5] Implement the check task to check the scoreboard.

+  task check(input scoreboard_t sb);

+    automatic logic [15:0] expected_result;

+

+    case (sb.operation)

+      ADD: begin

+        expected_result = (sb.operand_a + sb.operand_b) & 16'h01FF;

+        `FAIL_UNLESS_EQUAL(expected_result, sb.result & 16'h01FF, $sformatf(

+                           "ADD a=%0d b=%0d", sb.operand_a, sb.operand_b))

+      end

+      MULT: begin

+        expected_result = sb.operand_a * sb.operand_b;

+        `FAIL_UNLESS_EQUAL(expected_result, sb.result, $sformatf(

+                           "MULT a=%0d b=%0d", sb.operand_a, sb.operand_b))

+      end

+      OR: begin

+        expected_result = (sb.operand_a | sb.operand_b) & 16'h00FF;

+        `FAIL_UNLESS_EQUAL(expected_result, sb.result & 16'h00FF, $sformatf(

+                           "OR a=%0d b=%0d", sb.operand_a, sb.operand_b))

+      end

+      AND: begin

+        expected_result = (sb.operand_a & sb.operand_b) & 16'h00FF;

+        `FAIL_UNLESS_EQUAL(expected_result, sb.result & 16'h00FF, $sformatf(

+                           "AND a=%0d b=%0d", sb.operand_a, sb.operand_b))

+      end

+    endcase

+  endtask

+

+  // [Step 6] Test the DUV using an initial block. Be sure to initialize all DUV input variables,

+  // and use the $finish system task to halt simulation at the end of the test.

+  initial begin

+    automatic scoreboard_t sb;

+    automatic int test_count = 0;

+    automatic logic [1:0] rnd_op;

+    automatic logic [7:0] rnd_a;

+    automatic logic [7:0] rnd_b;

+

+    // Initialise all inputs

+    op_start  = 1'b0;

+    operation = ADD;

+    operand_a = 8'h00;

+    operand_b = 8'h00;

+

+    // Wait for initial setup

+    repeat (3) @(posedge clk);

+

+    // Randomised test loop

+    repeat (100) begin

+      `RND_CHECK(std::randomize(rnd_op, rnd_a, rnd_b))

+

+      // Log inputs to scoreboard

+      sb.operation = operation_t'(rnd_op);

+      sb.operand_a = rnd_a;

+      sb.operand_b = rnd_b;

+

+      // Drive DUV inputs and execute operation

+      operation = rnd_op;

+      operand_a = rnd_a;

+      operand_b = rnd_b;

+      op_start = 1'b1;

+

+      @(posedge clk);

+      op_start = 1'b0;

+

+      // Wait exactly two clock cycles for result

+      @(posedge clk);

+      @(posedge clk);

+

+      sb.result = result;

+      check(sb);

+

+      test_count += 1;

+    end

+

+    $display("All tests passed! Total tests: %0d", test_count);

+    $display("Finished Successfully!");

+    $finish;

+  end  //:initial

+endmodule : testbench

diff --git a/lab_4/SRC/typedef_pkg.sv b/lab_4/SRC/typedef_pkg.sv
new file mode 100644
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+++ b/lab_4/SRC/typedef_pkg.sv
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+// [Step 1] Create an enumeration typedef for the four operations: ADD, MULT, OR, and AND.
+// Name the typedef operation_t.
+package typedef_pkg;
+
+    typedef enum logic [1:0]
+    {
+        ADD = 2'b00,
+        MULT = 2'b01,
+        OR = 2'b10,
+        AND = 2'b11
+    } operation_t;
+
+endpackage : typedef_pkg
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diff --git a/lab_4/~$lab3.docx b/lab_4/~$lab3.docx
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+++ b/lab_4/~$lab3.docx