feat(lab_3): Implement lab 3old-main

6 files changed, 141 insertions, 46 deletions

diff --git a/lab_3/SIM/build_simulation.bat b/lab_3/SIM/build_simulation.bat
index b41e8c9..bcac078 100644
--- a/lab_3/SIM/build_simulation.bat
+++ b/lab_3/SIM/build_simulation.bat
@@ -1,4 +1,4 @@
 @echo off
-call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv ../SRC/duv.sv ../SRC/tb.sv
+call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv ../SRC/typedef_pkg.sv ../SRC/interface.sv ../SRC/duv.sv ../SRC/tb.sv
 call C:\Xilinx\Vivado\2022.1\bin\xelab -debug typical -top tb -snapshot duv_tb_snapshot
 pause
diff --git a/lab_3/SIM/run_simulation.bat b/lab_3/SIM/run_simulation.bat
index a1a1417..1ffb30d 100644
--- a/lab_3/SIM/run_simulation.bat
+++ b/lab_3/SIM/run_simulation.bat
@@ -1,5 +1,5 @@
 @echo off
-call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv ../SRC/duv.sv ../SRC/tb.sv
+call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv ../SRC/typedef_pkg.sv ../SRC/interface.sv ../SRC/duv.sv ../SRC/tb.sv
 call C:\Xilinx\Vivado\2022.1\bin\xelab -debug typical -top tb -snapshot duv_tb_snapshot
 call C:\Xilinx\Vivado\2022.1\bin\xsim duv_tb_snapshot -R
 call C:\Xilinx\Vivado\2022.1\bin\xsim duv_tb_snapshot --tclbatch xsim_cfg.tcl
diff --git a/lab_3/SRC/duv.sv b/lab_3/SRC/duv.sv
index 11a65bb..564fc46 100644
--- a/lab_3/SRC/duv.sv
+++ b/lab_3/SRC/duv.sv
@@ -1,28 +1,26 @@
 

 module duv (

-input logic clk,

-input logic op_start,

-input logic  [1:0] operation,

-input  logic [7:0] operand_a,

-input  logic [7:0] operand_b,

-output logic [15:0] result

+    input logic clk,

+    input logic op_start,

+    input logic [1:0] operation,

+    input logic [7:0] operand_a,

+    input logic [7:0] operand_b,

+    output logic [15:0] result

 );

 

-logic [15:0] result_tmp

+  logic [15:0] result_tmp;

 

-always_ff @(posedge clk) 

-begin

-if( op_start == 1'b1)

-begin

-case (operation)

-      0:             result_temp = operand_a + operand_b;

-      1:             result_temp = operand_a * operand_b;

-      2:             result_temp = operand_a | operand_b;

-      3:             result_temp = operand_a & operand_b;

-    endcase

-  end

+  always_ff @(posedge clk) begin

+    if (op_start == 1'b1) begin

+      case (operation)

+        0: result_tmp = operand_a + operand_b;

+        1: result_tmp = operand_a * operand_b;

+        2: result_tmp = operand_a | operand_b;

+        3: result_tmp = operand_a & operand_b;

+      endcase

+    end

 

-	result <= result_tmp;

-end

+    result <= result_tmp;

+  end

 

-endmodule : duv
\ No newline at end of file
+endmodule : duv

diff --git a/lab_3/SRC/interface.sv b/lab_3/SRC/interface.sv
index 0295c8f..aec4d93 100644
--- a/lab_3/SRC/interface.sv
+++ b/lab_3/SRC/interface.sv
@@ -1,10 +1,33 @@
+interface intf (
+    input logic clk
+);
+  // [Step 1] Wildcard import the enumeration typedef from the typedef_pkg package.
+  import typedef_pkg::*;
 
+  // [Step 2] Declare the signals, other than clk, that will connect to the DUV.
+  logic op_start;
+  logic [1:0] operation;
+  logic [7:0] operand_a;
+  logic [7:0] operand_b;
+  logic [15:0] result;
 
-interface intf (input logic clk);
-    // [Step 1] Wildcard import the enumeration typedef from the typedef_pkg package.
-	
-    // [Step 2] Declare the signals, other than clk, that will connect to the DUV.		
+  // [Step 3] Implement the execute_op task.
+  task execute_op(input operation_t op, input logic [7:0] op_a, input logic [7:0] op_b,
+                  output logic [15:0] res);
+    // Set inputs and start operation
+    operation = op;
+    operand_a = op_a;
+    operand_b = op_b;
+    op_start  = 1'b1;
 
-    // [Step 3] Implement the execute_op task.
+    @(posedge clk);
 
-endinterface : intf
\ No newline at end of file
+    op_start = 1'b0;
+
+    // Wait 2 cycles for result
+    @(posedge clk);
+    @(posedge clk);
+
+    res = result;
+  endtask
+endinterface : intf
diff --git a/lab_3/SRC/tb.sv b/lab_3/SRC/tb.sv
index baeab02..5623d17 100644
--- a/lab_3/SRC/tb.sv
+++ b/lab_3/SRC/tb.sv
@@ -1,17 +1,88 @@
 // Contains the FAIL_UNLESS_EQUAL macro.
 `include "macro.svh"
 
-
 module tb;
-    // [Step 1] Wildcard import the enumeration typedef from the typedef_pkg package.
-	
-    // [Step 2] Declare clk signal and initialize with value of 1'b0.
-
-    // [Step 3] Instantiate the interface and connect the clk signal.
-
-    // [Step 4] Instantiate the DUV module and connect the interface signals and the clk signal to the DUV ports.
-	
-    // [Step 5] Always block to generate the clock.
-		
-	end //:initial
-endmodule : tb
\ No newline at end of file
+  parameter FULL_TEST = 1;
+
+  // [Step 1] Wildcard import the enumeration typedef from the typedef_pkg package.
+  import typedef_pkg::*;
+
+  // [Step 2] Declare clk signal and initialize with value of 1'b0.
+  logic clk = 1'b0;
+
+  // [Step 3] Instantiate the interface and connect the clk signal.
+  intf intf0 (.clk(clk));
+
+  // [Step 4] Instantiate the DUV module and connect the interface signals and the clk signal to the DUV ports.
+  duv ALU0 (
+      .clk(clk),
+      .op_start(intf0.op_start),
+      .operation(intf0.operation),
+      .operand_a(intf0.operand_a),
+      .operand_b(intf0.operand_b),
+      .result(intf0.result)
+  );
+
+  // [Step 5] Always block to generate the clock.
+  always #1ns clk = ~clk;
+
+  initial begin
+    automatic logic [15:0] expected_result;
+    automatic logic [15:0] result;
+    automatic int test_count = 0;
+
+    // Initialise all inputs
+    intf0.op_start  = 1'b0;
+    intf0.operation = ADD;
+    intf0.operand_a = 8'h00;
+    intf0.operand_b = 8'h00;
+
+    // Wait for initial setup and reset
+    repeat (3) @(posedge clk);
+
+    // Exhaustively test all combinations
+    for (int op = 0; op < 4; op++) begin
+      for (int a = 0; a < (FULL_TEST ? 256 : 16); a++) begin
+        for (int b = 0; b < (FULL_TEST ? 256 : 16); b++) begin
+          // Set up inputs and calculate expected result first
+          intf0.operation = operation_t'(op);
+          intf0.operand_a = a[7:0];
+          intf0.operand_b = b[7:0];
+
+          // Calculate expected result before starting operation
+          case (intf0.operation)
+            ADD:  expected_result = (intf0.operand_a + intf0.operand_b) & 16'h01FF;  // ADD
+            MULT: expected_result = intf0.operand_a * intf0.operand_b;  // MULT
+            OR:   expected_result = (intf0.operand_a | intf0.operand_b) & 16'h00FF;  // OR
+            AND:  expected_result = (intf0.operand_a & intf0.operand_b) & 16'h00FF;  // AND
+          endcase
+
+          // Execute operation using interface task
+          intf0.execute_op(operation_t'(op), a[7:0], b[7:0], result);
+
+          // Compare only relevant bits based on operation
+          case (intf0.operation)
+            ADD:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h01FF, $sformatf(
+                               "ADD a=%0d b=%0d", intf0.operand_a, intf0.operand_b))
+            MULT:
+            `FAIL_UNLESS_EQUAL(expected_result, result, $sformatf(
+                               "MULT a=%0d b=%0d", intf0.operand_a, intf0.operand_b))
+            OR:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h00FF, $sformatf(
+                               "OR a=%0d b=%0d", intf0.operand_a, intf0.operand_b))
+            AND:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h00FF, $sformatf(
+                               "AND a=%0d b=%0d", intf0.operand_a, intf0.operand_b))
+          endcase
+
+          test_count += 1;
+        end
+      end
+    end
+
+    $display("All tests passed! Total tests: %0d", test_count);
+    $display("Finished Successfully!");
+    $finish;
+  end  //:initial
+endmodule : tb
diff --git a/lab_3/SRC/typedef_pkg.sv b/lab_3/SRC/typedef_pkg.sv
index 3b7b5e4..227f823 100644
--- a/lab_3/SRC/typedef_pkg.sv
+++ b/lab_3/SRC/typedef_pkg.sv
@@ -1,7 +1,10 @@
 // [Step 1] Create an enumeration typedef for the four operations: ADD, MULT, OR, and AND.
 // Name the typedef operation_t.
 package typedef_pkg;
-
-    
-
-endpackage : typedef_pkg
\ No newline at end of file
+  typedef enum logic [1:0] {
+    ADD  = 2'b00,
+    MULT = 2'b01,
+    OR   = 2'b10,
+    AND  = 2'b11
+  } operation_t;
+endpackage : typedef_pkg