Initial commit

1 files changed, 88 insertions, 0 deletions

diff --git a/lab_3/SRC/tb.sv b/lab_3/SRC/tb.sv
new file mode 100644
index 0000000..5623d17
--- /dev/null
+++ b/lab_3/SRC/tb.sv
@@ -0,0 +1,88 @@
+// Contains the FAIL_UNLESS_EQUAL macro.
+`include "macro.svh"
+
+module tb;
+  parameter FULL_TEST = 1;
+
+  // [Step 1] Wildcard import the enumeration typedef from the typedef_pkg package.
+  import typedef_pkg::*;
+
+  // [Step 2] Declare clk signal and initialize with value of 1'b0.
+  logic clk = 1'b0;
+
+  // [Step 3] Instantiate the interface and connect the clk signal.
+  intf intf0 (.clk(clk));
+
+  // [Step 4] Instantiate the DUV module and connect the interface signals and the clk signal to the DUV ports.
+  duv ALU0 (
+      .clk(clk),
+      .op_start(intf0.op_start),
+      .operation(intf0.operation),
+      .operand_a(intf0.operand_a),
+      .operand_b(intf0.operand_b),
+      .result(intf0.result)
+  );
+
+  // [Step 5] Always block to generate the clock.
+  always #1ns clk = ~clk;
+
+  initial begin
+    automatic logic [15:0] expected_result;
+    automatic logic [15:0] result;
+    automatic int test_count = 0;
+
+    // Initialise all inputs
+    intf0.op_start  = 1'b0;
+    intf0.operation = ADD;
+    intf0.operand_a = 8'h00;
+    intf0.operand_b = 8'h00;
+
+    // Wait for initial setup and reset
+    repeat (3) @(posedge clk);
+
+    // Exhaustively test all combinations
+    for (int op = 0; op < 4; op++) begin
+      for (int a = 0; a < (FULL_TEST ? 256 : 16); a++) begin
+        for (int b = 0; b < (FULL_TEST ? 256 : 16); b++) begin
+          // Set up inputs and calculate expected result first
+          intf0.operation = operation_t'(op);
+          intf0.operand_a = a[7:0];
+          intf0.operand_b = b[7:0];
+
+          // Calculate expected result before starting operation
+          case (intf0.operation)
+            ADD:  expected_result = (intf0.operand_a + intf0.operand_b) & 16'h01FF;  // ADD
+            MULT: expected_result = intf0.operand_a * intf0.operand_b;  // MULT
+            OR:   expected_result = (intf0.operand_a | intf0.operand_b) & 16'h00FF;  // OR
+            AND:  expected_result = (intf0.operand_a & intf0.operand_b) & 16'h00FF;  // AND
+          endcase
+
+          // Execute operation using interface task
+          intf0.execute_op(operation_t'(op), a[7:0], b[7:0], result);
+
+          // Compare only relevant bits based on operation
+          case (intf0.operation)
+            ADD:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h01FF, $sformatf(
+                               "ADD a=%0d b=%0d", intf0.operand_a, intf0.operand_b))
+            MULT:
+            `FAIL_UNLESS_EQUAL(expected_result, result, $sformatf(
+                               "MULT a=%0d b=%0d", intf0.operand_a, intf0.operand_b))
+            OR:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h00FF, $sformatf(
+                               "OR a=%0d b=%0d", intf0.operand_a, intf0.operand_b))
+            AND:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h00FF, $sformatf(
+                               "AND a=%0d b=%0d", intf0.operand_a, intf0.operand_b))
+          endcase
+
+          test_count += 1;
+        end
+      end
+    end
+
+    $display("All tests passed! Total tests: %0d", test_count);
+    $display("Finished Successfully!");
+    $finish;
+  end  //:initial
+endmodule : tb