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authorFuwn <[email protected]>2026-02-13 23:23:19 -0800
committerFuwn <[email protected]>2026-02-13 23:23:19 -0800
commit583bec7ffd3c2809ea41aa8a518f53403af3efaa (patch)
tree551fa62ee04d40616db4f2375176c362ae6f3cbc /lab_3/SRC/interface.sv
downloadcst456-583bec7ffd3c2809ea41aa8a518f53403af3efaa.tar.xz
cst456-583bec7ffd3c2809ea41aa8a518f53403af3efaa.zip
Initial commit
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1 files changed, 33 insertions, 0 deletions
diff --git a/lab_3/SRC/interface.sv b/lab_3/SRC/interface.sv
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+interface intf (
+ input logic clk
+);
+ // [Step 1] Wildcard import the enumeration typedef from the typedef_pkg package.
+ import typedef_pkg::*;
+
+ // [Step 2] Declare the signals, other than clk, that will connect to the DUV.
+ logic op_start;
+ logic [1:0] operation;
+ logic [7:0] operand_a;
+ logic [7:0] operand_b;
+ logic [15:0] result;
+
+ // [Step 3] Implement the execute_op task.
+ task execute_op(input operation_t op, input logic [7:0] op_a, input logic [7:0] op_b,
+ output logic [15:0] res);
+ // Set inputs and start operation
+ operation = op;
+ operand_a = op_a;
+ operand_b = op_b;
+ op_start = 1'b1;
+
+ @(posedge clk);
+
+ op_start = 1'b0;
+
+ // Wait 2 cycles for result
+ @(posedge clk);
+ @(posedge clk);
+
+ res = result;
+ endtask
+endinterface : intf