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diff --git a/lab_2/CST456 LAB2.rar b/lab_2/CST456 LAB2.rar
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diff --git a/lab_2/CST456 Lab2.md b/lab_2/CST456 Lab2.md
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+# CST456 Lab2
+
+**CST456 – Lab 2**
+
+**Simple Testbench with Data Types and Package**
+
+**Objective**
+
+The objective of this lab is to implement a simple testbench to exhaustively test the operations and operands of a synchronous arithmetic and logic unit (ALU) using data types from a package.
+
+**Design Under Verification (DUV)** The ALU contains the following ports:
+
+| **Port Name** | **Signal Type** | **Direction** | **Number of Bits** | **Data Type** |
+| --- | --- | --- | --- | --- |
+| clk | Clock | Input | 1 | logic |
+| op_start | Control | Input | 1 | logic |
+| operation | Control | Input | 2 | operation_t (enum) |
+| operand_a | Data | Input | 8 | operand_t |
+| operand_b | Data | Input | 8 | operand_t |
+| result | Data | Output | 16 | result_t |
+
+At the rising edge of the clock, if op_start is asserted (== 1’b1) then the operation, operand_a, and operand_b signals are latched into the ALU. Exactly two clock cycles later the result of the operation is read from the result port. The ALU supports the following operations:
+
+| **Name** | **Value** | **Description** |
+| --- | --- | --- |
+| ADD | 2’b00 | operand_a is added to operand_b. Only the lower nine bits of the result are used. |
+| MULT | 2’b01 | operand_a is multiplied with operand_b. This is an unsigned operation and all sixteen bits of the result are used. |
+| OR | 2’b10 | operand_a is bitwise ORed with operand_b. Only the lower eight bits of the result are used. |
+| AND | 2’b11 | operand_a is bitwise ANDed with operand_b. Only the lower eight bits of the result are used. |
+
+Figure 1 shows a timing diagram for the addition operation, where 1 +
+
+3 = 4.
+
+![](./image1.png)
+
+**Figure 1 - Timing diagram for an addition operation.**
+
+**Testbench**
+
+Edit the tb.sv file and create a testbench to exhaustively test all
+
+the operations and operand combinations that the ALU supports. The DUV
+
+uses data types from the typedef_pkg package declared in
+
+typedef_pkg.sv.
+
+Create a do-while loop and two nested for-loops. The do-while loop
+
+enumerates through all four operations, the first for-loop enumerates
+
+through all 256 values for operand_a, and the second for-loop
+
+enumerates through all 256 values for operand_b. Use the
+
+`FAIL_UNLESS_EQUAL macro to check the expected result with the tested
+
+result. The DUV does not contain any bugs, so the testing is expected
+
+to be successful.
+
+Simulate your testbench in Xilinx Vivado (**version 2023.2**) using
+
+following commands:
+
+(simulation commands must be run under SIM directory)
+
+*call C:\Xilinx\Vivado\2023.2\bin\xvlog -nolog -sv ../SRC/tb.sv ../SRC/duv.svp*
+
+*call C:\Xilinx\Vivado\2023.2\bin\xelab -debug typical -top tb -snapshot duv_tb_snapshot*
+
+*call C:\Xilinx\Vivado\2023.2\bin\xsim duv_tb_snapshot -R*
+
+*call C:\Xilinx\Vivado\2023.2\bin\xsim duv_tb_snapshot --tclbatch xsim_cfg.tcl*
+
+*call C:\Xilinx\Vivado\2023.2\bin\xsim --gui duv_tb_snapshot.wdb*
+
+**Lab Submission**
+
+Zip the entire contents of the lab directory and submit it to Canvas.
diff --git a/lab_2/CST456 Lab2.pdf b/lab_2/CST456 Lab2.pdf
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+++ b/lab_2/CST456 Lab2.pdf
diff --git a/lab_2/SIM/run_simulation.bat b/lab_2/SIM/run_simulation.bat
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+@echo off
+call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv ../SRC/typedef_pkg.sv ../SRC/tb.sv ../SRC/duv.sv
+call C:\Xilinx\Vivado\2022.1\bin\xelab -debug typical -top tb -snapshot duv_tb_snapshot
+call C:\Xilinx\Vivado\2022.1\bin\xsim duv_tb_snapshot -R
+call C:\Xilinx\Vivado\2022.1\bin\xsim duv_tb_snapshot --tclbatch xsim_cfg.tcl
+call C:\Xilinx\Vivado\2022.1\bin\xsim --gui duv_tb_snapshot.wdb
+pause
diff --git a/lab_2/SIM/run_waveform.bat b/lab_2/SIM/run_waveform.bat
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+++ b/lab_2/SIM/run_waveform.bat
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+@echo off
+call C:\Xilinx\Vivado\2022.1\bin\xsim duv_tb_snapshot --tclbatch xsim_cfg.tcl
+call C:\Xilinx\Vivado\2022.1\bin\xsim --gui duv_tb_snapshot.wdb
diff --git a/lab_2/SIM/xsim_cfg.tcl b/lab_2/SIM/xsim_cfg.tcl
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+++ b/lab_2/SIM/xsim_cfg.tcl
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+log_wave -recursive *

+run all

+exit
\ No newline at end of file
diff --git a/lab_2/SRC/duv.sv b/lab_2/SRC/duv.sv
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+++ b/lab_2/SRC/duv.sv
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+

+module duv (

+input logic clk,

+input logic op_start,

+input logic  [1:0] operation,

+input  logic [7:0] operand_a,

+input  logic [7:0] operand_b,

+output logic [15:0] result

+);

+

+logic [15:0] result_tmp;

+

+always_ff @(posedge clk) 

+begin

+if( op_start == 1'b1)

+begin

+case (operation)

+      0:             result_tmp = operand_a + operand_b;

+      1:             result_tmp = operand_a * operand_b;

+      2:             result_tmp = operand_a | operand_b;

+      3:             result_tmp = operand_a & operand_b;

+    endcase

+  end

+

+	result <= result_tmp;

+end

+

+endmodule : duv
\ No newline at end of file
diff --git a/lab_2/SRC/macro.svh b/lab_2/SRC/macro.svh
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+++ b/lab_2/SRC/macro.svh
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+`ifndef MACRO_SVH
+    `define MACRO_SVH
+
+    `define FAIL_UNLESS_EQUAL(a,b,c="") \
+    if ((a) !== (b)) \
+    begin \
+        $display ("FAIL_UNLESS_EQUAL[%s]: Expected %h but actual value is %h.", c, a, b); \
+		$finish; \
+    end
+`endif
diff --git a/lab_2/SRC/tb.sv b/lab_2/SRC/tb.sv
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+++ b/lab_2/SRC/tb.sv
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+// Contains the FAIL_UNLESS_EQUAL macro.
+`include "macro.svh"
+
+module tb;
+  parameter FULL_TEST = 0;
+
+  // [Step 1] Wildcard import the typedef_pkg package.
+  import typedef_pkg::*;
+
+  // [Step 2] Declare signals. The operation, operand_a, operand_b, and result signals must use the
+  // data types from the typedef_pkg package. Initialize the clk signal with a value of 1'b0.
+
+  logic clk = 1'b0;
+  logic op_start;
+  operation_t operation;
+  operand_t operand_a;
+  operand_t operand_b;
+  result_t result;
+
+  // [Step 3] Instantiate the DUV module. The module is declared as
+
+  /*
+        module duv
+        (
+            input logic clk,
+
+            input logic op_start,
+            input operation_t operation,
+            input operand_t operand_a,
+            input operand_t operand_b,
+
+            output result_t result
+        );
+    */
+
+  duv ALU0 (
+      .clk,
+      .op_start,
+      .operation,
+      .operand_a,
+      .operand_b,
+      .result
+  );
+
+  // [Step 4] Always block to generate the clock.
+
+  always #1ns clk = ~clk;
+
+  // [Step 5] Test the DUV using an initial block. Be sure to initialize all DUV input variables, and use the
+  // $finish system task to halt simulation at the end of the test.
+
+  initial begin
+    automatic result_t expected_result;
+    automatic int test_count = 0;
+
+    // Initialise all inputs
+    op_start  = 1'b0;
+    operation = ADD;
+    operand_a = 8'h00;
+    operand_b = 8'h00;
+
+    // Wait for initial setup and reset
+    repeat (3) @(posedge clk);
+
+    // Exhaustively test all combinations
+    for (int op = 0; op < 4; op++) begin
+      for (int a = 0; a < (FULL_TEST ? 256 : 16); a++) begin
+        for (int b = 0; b < (FULL_TEST ? 256 : 16); b++) begin
+          // Set up inputs and calculate expected result first
+          operation = operation_t'(op);
+          operand_a = a[7:0];
+          operand_b = b[7:0];
+
+          // Calculate expected result before starting operation
+          case (operation)
+            ADD:  expected_result = (operand_a + operand_b) & 16'h01FF;  // ADD
+            MULT: expected_result = operand_a * operand_b;  // MULT
+            OR:   expected_result = (operand_a | operand_b) & 16'h00FF;  // OR
+            AND:  expected_result = (operand_a & operand_b) & 16'h00FF;  // AND
+          endcase
+
+          // Start the operation
+          op_start = 1'b1;
+
+          // Wait for rising edge to latch inputs
+          @(posedge clk);
+
+          op_start = 1'b0;
+
+          // Wait 2 more clock cycles for result
+          @(posedge clk);
+          @(posedge clk);
+
+          // Compare only relevant bits based on operation
+          case (operation)
+            ADD:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h01FF, $sformatf(
+                               "ADD a=%0d b=%0d", operand_a, operand_b))
+            MULT:
+            `FAIL_UNLESS_EQUAL(expected_result, result, $sformatf(
+                               "MULT a=%0d b=%0d", operand_a, operand_b))
+            OR:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h00FF, $sformatf(
+                               "OR a=%0d b=%0d", operand_a, operand_b))
+            AND:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h00FF, $sformatf(
+                               "AND a=%0d b=%0d", operand_a, operand_b))
+          endcase
+
+          test_count += 1;
+        end
+      end
+    end
+
+    $display("All tests passed! Total tests: %0d", test_count);
+    $display("Finished Successfully!");
+    $finish;
+  end  // Initial end
+endmodule : tb
diff --git a/lab_2/SRC/typedef_pkg.sv b/lab_2/SRC/typedef_pkg.sv
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+++ b/lab_2/SRC/typedef_pkg.sv
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+package typedef_pkg;
+
+    typedef enum logic [1:0]
+    {
+        ADD = 2'b00,
+        MULT = 2'b01,
+        OR = 2'b10,
+        AND = 2'b11
+    } operation_t;
+
+    typedef logic [7:0] operand_t;
+    typedef logic [15:0] result_t;
+
+endpackage : typedef_pkg
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