feat(homework_2): Add implementation

1 files changed, 16 insertions, 15 deletions

diff --git a/homework_2/SRC/interface.sv b/homework_2/SRC/interface.sv
index a9906c8..47ed74a 100644
--- a/homework_2/SRC/interface.sv
+++ b/homework_2/SRC/interface.sv
@@ -1,15 +1,16 @@
-// using a virtual interface handle

-interface des_if (input bit clk);

-  	logic rstn;

-	logic in;

-	logic out;

-

-	clocking cb @(posedge clk);

-      default input #1step output #3ns;

-		input out;

-		output in;

-	endclocking

-

-endinterface

-    

-// Top level test
\ No newline at end of file
+// using a virtual interface handle
+interface des_if (
+    input bit clk
+);
+  logic reset;
+  logic inp;
+  logic outp;
+
+  clocking cb @(posedge clk);
+    default input #1step output #3ns;
+    input outp;
+    output inp;
+  endclocking
+endinterface
+
+// Top level test