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+# CST456 Lab5
+
+**CST456 – Lab 5**
+
+**Constrained Pseudo-random Testbench**
+
+**Objective**
+
+The objective of this lab is to implement a constrained pseudo-random testbench to test the operations and operands of a synchronous arithmetic and logic unit (ALU). The SRC directory contains the following System Verilog files:
+
+![](./image1.png)
+
+**Design Under Verification (DUV)**
+
+The ALU contains the following ports:
+
+| **Port Name** | **Signal Type** | **Direction** | **Number of Bits** |
+| --- | --- | --- | --- |
+| clk | Clock | Input | 1 |
+| op_start | Control | Input | 1 |
+| operation | Control | Input | 2 |
+| operand_a | Data | Input | 8 |
+| operand_b | Data | Input | 8 |
+| result | Data | Output | 16 |
+
+At the rising edge of the clock, if op_start is asserted (== 1’b1) then the operation, operand_a, and operand_b signals are latched into the ALU. Exactly two clock cycles later the upper eight bits of the result are read from the result port. The lower eight bits of the result are read from the result port one clock cycle later. The op_start signal is ignored during the middle of an operation. The ALU supports the following operations:
+
+| **Name** | **Value** | **Description** |
+| --- | --- | --- |
+| ADD | 2’b00 | operand_a is added to operand_b. Only the lower nine bits of the 16-bit result are used. |
+| MULT | 2’b01 | operand_a is multiplied with operand_b. This is an unsigned operation and all sixteen bits of the result are used. |
+| OR | 2’b10 | operand_a is bitwise ORed with operand_b. Only the lower eight bits of the 16-bit result are used. |
+| AND | 2’b11 | operand_a is bitwise ANDed with operand_b. Only the lower eight bits of the 16-bit result are used. |
+
+Figure 1 shows a timing diagram for the addition operation, where 255 + 255 = 510.
+
+![](./image2.png)
+
+**Figure 1 - Timing diagram for an addition operation.**
+
+**Generator**
+
+The generator is a class that contains the **stimulus** task. (**generator.sv** is given)
+
+**Scoreboard**
+
+The scoreboard class stores temporary test data. The scoreboard should include fields for the current operation, operands, and result.
+
+**Monitor**
+
+The monitor class passively observes the DUV signals and updates the scoreboard based on the stimuli applied to the DUV and the DUV's responses. The monitor class contains the check task.
+
+**Testbench**
+
+Edit the tb.sv file to create the testbench with the generator class,
+
+scoreboard class, monitor class, and interface. Use the
+
+`FAIL_UNLESS_EQUAL and `FAIL macros to compare the expected result
+
+with the tested result.
+
+**Lab Submission**
+
+Zip the entire contents of the lab directory and submit it to Canvas.
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