From b34cb1b631d7979307bec26905a1a9298ec4f17a Mon Sep 17 00:00:00 2001 From: Graydon Hoare Date: Thu, 19 Aug 2010 18:41:55 -0700 Subject: Fix a bunch of typestate bugs in handling if and while statement wirings. --- src/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'src/Makefile') diff --git a/src/Makefile b/src/Makefile index f213cac1..5e1be788 100644 --- a/src/Makefile +++ b/src/Makefile @@ -555,6 +555,7 @@ TEST_XFAILS_LLVM := $(TASK_XFAILS) \ vec-lib.rs \ vec-slice.rs \ vec.rs \ + while-flow-graph.rs \ writealias.rs \ yield.rs \ yield2.rs \ -- cgit v1.2.3