From e4f904587bf05dadc615f60d1f0b1519442451e4 Mon Sep 17 00:00:00 2001 From: Fuwn Date: Mon, 13 Nov 2023 17:44:12 -0800 Subject: feat: initial release --- .gitignore | 6 ++++++ Makefile | 17 +++++++++++++++++ README.md | 19 +++++++++++++++++++ UNLICENSE | 7 +++++++ bcd_adder.v | 13 +++++++++++++ bcd_to_seven.v | 26 ++++++++++++++++++++++++++ bcd_to_seven_test.v | 44 ++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 132 insertions(+) create mode 100644 .gitignore create mode 100644 Makefile create mode 100644 README.md create mode 100644 UNLICENSE create mode 100644 bcd_adder.v create mode 100644 bcd_to_seven.v create mode 100644 bcd_to_seven_test.v diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..1630bd2 --- /dev/null +++ b/.gitignore @@ -0,0 +1,6 @@ +# Visual Studio Code +.vscode + +# Icarus Verilog +*.vvp +*.vcd diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..79eeef9 --- /dev/null +++ b/Makefile @@ -0,0 +1,17 @@ +TOP = bcd_to_seven_test +SRC = bcd_to_seven.v bcd_adder.v +TEST_SRC = bcd_to_seven_test.v +BIN = $(TOP).vvp + +$(BIN): $(SRC) $(TEST_SRC) + iverilog -gsupported-assertions -o $(BIN) -s $(TOP) $(SRC) $(TEST_SRC) + +.PHONY: all clean test + +all: $(BIN) + +test: $(BIN) + vvp $(BIN) + +clean: + rm -f *.vvp *.vcd diff --git a/README.md b/README.md new file mode 100644 index 0000000..9765dbd --- /dev/null +++ b/README.md @@ -0,0 +1,19 @@ +# Icarus Verilog Test-bench + +## Dependencies + +- [Icarus Verilog](https://steveicarus.github.io/iverilog/) +- [GTKWave](https://github.com/gtkwave/gtkwave) (Optional) + +## Usage + +```shell +make # Build all + +make test # Build all and run test-bench + +# Build all, run test-bench, and open test waveform in GTKWave +make test && gtkwave ./wave.vcd + +make clean # Clean all build artifacts +``` diff --git a/UNLICENSE b/UNLICENSE new file mode 100644 index 0000000..d403438 --- /dev/null +++ b/UNLICENSE @@ -0,0 +1,7 @@ +This is free and unencumbered software released into the public domain. + +Anyone is free to copy, modify, publish, use, compile, sell, or distribute this software, either in source code form or as a compiled binary, for any purpose, commercial or non-commercial, and by any means. + +In jurisdictions that recognize copyright laws, the author or authors of this software dedicate any and all copyright interest in the software to the public domain. We make this dedication for the benefit of the public at large and to the detriment of our heirs and successors. We intend this dedication to be an overt act of relinquishment in perpetuity of all present and future rights to this software under copyright law. + +THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/bcd_adder.v b/bcd_adder.v new file mode 100644 index 0000000..16790bd --- /dev/null +++ b/bcd_adder.v @@ -0,0 +1,13 @@ +module bcd_adder( + input wire [3:0] a, + input wire [3:0] b, + output reg [7:0] x +); + always @(*) begin + assign x = a + b; + + if (x > 9) begin + x = x + 6; + end + end +endmodule diff --git a/bcd_to_seven.v b/bcd_to_seven.v new file mode 100644 index 0000000..072ee8f --- /dev/null +++ b/bcd_to_seven.v @@ -0,0 +1,26 @@ +module bcd_to_seven( + input wire [3:0] bin_in, + output reg [7:0] sseg_out +); + always @* begin + case(bin_in) + 4'b0000: sseg_out = 8'b11000000; // 0 + 4'b0001: sseg_out = 8'b11111001; // 1 + 4'b0010: sseg_out = 8'b10100100; // 2 + 4'b0011: sseg_out = 8'b10110000; // 3 + 4'b0100: sseg_out = 8'b10011001; // 4 + 4'b0101: sseg_out = 8'b10010010; // 5 + 4'b0110: sseg_out = 8'b10000010; // 6 + 4'b0111: sseg_out = 8'b11111000; // 7 + 4'b1000: sseg_out = 8'b10000000; // 8 + 4'b1001: sseg_out = 8'b10010000; // 9 + 4'b1010: sseg_out = 8'b10001000; // A + 4'b1011: sseg_out = 8'b10000011; // B + 4'b1100: sseg_out = 8'b11000110; // C + 4'b1101: sseg_out = 8'b10100001; // D + 4'b1110: sseg_out = 8'b10000110; // E + 4'b1111: sseg_out = 8'b10001110; // F + default: sseg_out = 8'b11111111; // Off + endcase + end +endmodule diff --git a/bcd_to_seven_test.v b/bcd_to_seven_test.v new file mode 100644 index 0000000..07aaca1 --- /dev/null +++ b/bcd_to_seven_test.v @@ -0,0 +1,44 @@ +`define test(EXPECTED) if (sseg_out !== EXPECTED) begin \ + $error(bin_in, sseg_out); $finish; end + +module bcd_to_seven_test; + reg [3:0] bin_in; + wire [7:0] sseg_out; + integer i; + + bcd_to_seven to (.bin_in(bin_in), .sseg_out(sseg_out)); + initial begin + $dumpfile("wave.vcd"); + $dumpvars(0, bcd_to_seven_test); + + for (i = 0; i < 16; i = i + 1) begin + bin_in = i; + + #10; + + $display("bin_in = %b, sseg_out = %b", bin_in, sseg_out); + + case(bin_in) + 4'b0000: begin `test(8'b11000000); end + 4'b0001: begin `test(8'b11111001); end + 4'b0010: begin `test(8'b10100100); end + 4'b0011: begin `test(8'b10110000); end + 4'b0100: begin `test(8'b10011001); end + 4'b0101: begin `test(8'b10010010); end + 4'b0110: begin `test(8'b10000010); end + 4'b0111: begin `test(8'b11111000); end + 4'b1000: begin `test(8'b10000000); end + 4'b1001: begin `test(8'b10010000); end + 4'b1010: begin `test(8'b10001000); end + 4'b1011: begin `test(8'b10000011); end + 4'b1100: begin `test(8'b11000110); end + 4'b1101: begin `test(8'b10100001); end + 4'b1110: begin `test(8'b10000110); end + 4'b1111: begin `test(8'b10001110); end + default: begin `test(8'b11111111); end + endcase + end + + $finish; + end +endmodule -- cgit v1.2.3