module duv (
    input logic clk,
    input logic op_start,
    input logic [1:0] operation,
    input logic [7:0] operand_a,
    input logic [7:0] operand_b,
    output logic [15:0] result
);
  logic [1:0] operation_d1;
  logic [7:0] operand_a_d1;
  logic [7:0] operand_b_d1;
  logic       valid_d1;
  logic [1:0] operation_d2;
  logic [7:0] operand_a_d2;
  logic [7:0] operand_b_d2;
  logic       valid_d2;

  always_ff @(posedge clk) begin
    valid_d1 <= op_start;

    if (op_start == 1'b1) begin
      operation_d1 <= operation;
      operand_a_d1 <= operand_a;
      operand_b_d1 <= operand_b;
    end

    valid_d2 <= valid_d1;

    if (valid_d1 == 1'b1) begin
      operation_d2 <= operation_d1;
      operand_a_d2 <= operand_a_d1;
      operand_b_d2 <= operand_b_d1;
    end

    if (valid_d2 == 1'b1) begin
      case (operation_d2)
        2'b00:   result <= (operand_a_d2 + operand_b_d2) & 16'h01FF;
        2'b01:   result <= operand_a_d2 * operand_b_d2;
        2'b10:   result <= (operand_a_d2 | operand_b_d2) & 16'h00FF;
        2'b11:   result <= (operand_a_d2 & operand_b_d2) & 16'h00FF;
        default: result <= 16'h0000;
      endcase
    end
  end
endmodule : duv