// the design checks two valid sequence patterns and compares
// expected output to monitored output in each cycle.
class scoreboard extends uvm_scoreboard;
  `uvm_component_utils(scoreboard)
  function new(string name = "scoreboard", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  `define LENGTH 4
  bit                                  [`LENGTH-1:0] act_pattern;
  bit                                                exp_out;
  bit                                                seen_1011;
  bit                                                seen_1100;

  uvm_analysis_imp #(Item, scoreboard)               m_analysis_imp;

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    m_analysis_imp = new("m_analysis_imp", this);
    act_pattern = '0;
    exp_out = 0;
    seen_1011 = 0;
    seen_1100 = 0;
  endfunction

  virtual function write(Item item);
    act_pattern = act_pattern << 1 | item.inp;
    exp_out = ((act_pattern == 4'b1011) || (act_pattern == 4'b1100));

    `uvm_info("SCBD", $sformatf("inp=%0d outp=%0d act=0b%0b", item.inp, item.outp, act_pattern),
              UVM_LOW)

    if (act_pattern == 4'b1011) begin
      seen_1011 = 1;

      `uvm_info("SCBD", $sformatf("Pattern found to match"), UVM_LOW)
    end

    if (act_pattern == 4'b1100) begin
      seen_1100 = 1;

      `uvm_info("SCBD", $sformatf("Pattern found to match"), UVM_LOW)
    end

    if (item.outp != exp_out) begin
      `uvm_error("SCBD", $sformatf("ERROR ! out=%0d exp=%0d", item.outp, exp_out))
    end else if (exp_out) begin
      `uvm_info("SCBD", $sformatf("PASS ! out=%0d exp=%0d", item.outp, exp_out), UVM_LOW)
    end
  endfunction

  virtual function void report_phase(uvm_phase phase);
    super.report_phase(phase);

    if (!seen_1011 || !seen_1100)
      `uvm_error(
          "SCBD", $sformatf(
          "Both patterns were not observed (seen_1011=%0d seen_1100=%0d)", seen_1011, seen_1100))
  endfunction
endclass