module duv (
    input  logic clk,
    input  logic reset,
    input  logic inp,
    output logic outp
);
  localparam S0 = 3'b000, S1 = 3'b001, S11 = 3'b010, S10 = 3'b011, S110 = 3'b100, S101 = 3'b101;

  logic [2:0] state;
  logic [2:0] next_state;

  // State register with asynchronous active-high reset
  always_ff @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end

  // Mealy next-state and output logic for 1011 and 1100
  always_comb begin
    next_state = state;
    outp = 1'b0;

    case (state)
      S0: begin
        if (inp) next_state = S1;
        else next_state = S0;
      end

      S1: begin
        if (inp) next_state = S11;
        else next_state = S10;
      end

      S11: begin
        if (inp) next_state = S11;
        else next_state = S110;
      end

      S10: begin
        if (inp) next_state = S101;
        else next_state = S0;
      end

      S110: begin
        if (inp) begin
          next_state = S101;
        end else begin
          next_state = S0;
          outp = 1'b1;  // Detected 1100
        end
      end

      S101: begin
        if (inp) begin
          next_state = S11;
          outp = 1'b1;  // Detected 1011
        end else begin
          next_state = S10;
        end
      end

      default: next_state = S0;
    endcase
  end
endmodule