From db40dbfb19b40d4c245407bbb289cb184e516f51 Mon Sep 17 00:00:00 2001 From: Fuwn Date: Fri, 13 Feb 2026 23:26:29 -0800 Subject: feat(lab_5): Add initial files --- lab_5/CST456 LAB5.rar | Bin 0 -> 149069 bytes lab_5/CST456 Lab5.pdf | Bin 0 -> 159957 bytes lab_5/SIM/xsim_cfg.tcl | 3 +++ lab_5/SRC/duv.sv | 28 +++++++++++++++++++ lab_5/SRC/generator.sv | 19 +++++++++++++ lab_5/SRC/interface.sv | 43 +++++++++++++++++++++++++++++ lab_5/SRC/macro.svh | 14 ++++++++++ lab_5/SRC/monitor.sv | 1 + lab_5/SRC/scoreboard.sv | 1 + lab_5/SRC/tb.sv | 67 ++++++++++++++++++++++++++++++++++++++++++++++ lab_5/SRC/typedef_pkg.sv | 14 ++++++++++ lab_5/vivado_commands.txt | 28 +++++++++++++++++++ 12 files changed, 218 insertions(+) create mode 100644 lab_5/CST456 LAB5.rar create mode 100644 lab_5/CST456 Lab5.pdf create mode 100644 lab_5/SIM/xsim_cfg.tcl create mode 100644 lab_5/SRC/duv.sv create mode 100644 lab_5/SRC/generator.sv create mode 100644 lab_5/SRC/interface.sv create mode 100644 lab_5/SRC/macro.svh create mode 100644 lab_5/SRC/monitor.sv create mode 100644 lab_5/SRC/scoreboard.sv create mode 100644 lab_5/SRC/tb.sv create mode 100644 lab_5/SRC/typedef_pkg.sv create mode 100644 lab_5/vivado_commands.txt diff --git a/lab_5/CST456 LAB5.rar b/lab_5/CST456 LAB5.rar new file mode 100644 index 0000000..188a8dd Binary files /dev/null and b/lab_5/CST456 LAB5.rar differ diff --git a/lab_5/CST456 Lab5.pdf b/lab_5/CST456 Lab5.pdf new file mode 100644 index 0000000..1abc56a Binary files /dev/null and b/lab_5/CST456 Lab5.pdf differ diff --git a/lab_5/SIM/xsim_cfg.tcl b/lab_5/SIM/xsim_cfg.tcl new file mode 100644 index 0000000..b7c49f5 --- /dev/null +++ b/lab_5/SIM/xsim_cfg.tcl @@ -0,0 +1,3 @@ +log_wave -recursive * +run all +exit \ No newline at end of file diff --git a/lab_5/SRC/duv.sv b/lab_5/SRC/duv.sv new file mode 100644 index 0000000..0829654 --- /dev/null +++ b/lab_5/SRC/duv.sv @@ -0,0 +1,28 @@ + +module duv ( +input logic clk, +input logic op_start, +input logic [1:0] operation, +input logic [7:0] operand_a, +input logic [7:0] operand_b, +output logic [15:0] result +); + +logic [15:0] result_tmp; + +always_ff @(posedge clk) +begin +if( op_start == 1'b1) +begin +case (operation) + 0: result_tmp = operand_a + operand_b; + 1: result_tmp = operand_a * operand_b; + 2: result_tmp = operand_a | operand_b; + 3: result_tmp = operand_a & operand_b; + endcase + end + + result <= result_tmp; +end + +endmodule : duv \ No newline at end of file diff --git a/lab_5/SRC/generator.sv b/lab_5/SRC/generator.sv new file mode 100644 index 0000000..b85d7ec --- /dev/null +++ b/lab_5/SRC/generator.sv @@ -0,0 +1,19 @@ +import typedef_pkg::*; +class generator; +logic [7:0] a; +logic [7:0] b; +logic [15:0] out_put; +operation_t op; +virtual intf ALUintf; +function new (virtual interface intf alu_if_in); + ALUintf = alu_if_in; +endfunction +task sitimulus(); + ALUintf.execute_op( op, a, b, out_put); + `RND_CHECK(std::randomize(op) with {op inside {op};}) + `RND_CHECK(std::randomize(a)) + `RND_CHECK(std::randomize(b)) + ALUintf.execute_op( op, a, b, out_put); +endtask + +endclass \ No newline at end of file diff --git a/lab_5/SRC/interface.sv b/lab_5/SRC/interface.sv new file mode 100644 index 0000000..8770534 --- /dev/null +++ b/lab_5/SRC/interface.sv @@ -0,0 +1,43 @@ + + +interface intf (input logic clk); + // [Step 1] Wildcard import the enumeration typedef from the typedef_pkg package. + import typedef_pkg::*; + + // [Step 2] Declare the signals, other than clk, that will connect to the DUV. + logic op_start = 1'b0; + operation_t operation; + logic [7:0] operand_a; + logic [7:0] operand_b; + logic [15:0] result; + + + // [Step 3] Implement the execute_op task. + task execute_op + ( + input operation_t op, + input logic [7:0] op_a, + input logic [7:0] op_b, + output logic [15:0] res + ); + + // Set inputs latch inputs + // + @(negedge clk); + op_start = 1'b1; + operation = op; + operand_a = op_a; + operand_b = op_b; + + @(negedge clk); + op_start = 1'b0; + + // Capture the MSB's + @(negedge clk); + res[15:0] = result; + + + + endtask: execute_op + +endinterface : intf \ No newline at end of file diff --git a/lab_5/SRC/macro.svh b/lab_5/SRC/macro.svh new file mode 100644 index 0000000..72bf471 --- /dev/null +++ b/lab_5/SRC/macro.svh @@ -0,0 +1,14 @@ +`ifndef MACRO_SVH + `define MACRO_SVH + + `define FAIL_UNLESS_EQUAL(a,b,c="") \ + if ((a) !== (b)) begin \ + $display ("FAIL_UNLESS_EQUAL[%s]: Expected %h but actual value is %h.", c, a, b); \ + end + + `define RND_CHECK(a) \ + if (!a) begin \ + $display ("Randomization failure. Simulation halted."); \ + $finish; \ + end +`endif diff --git a/lab_5/SRC/monitor.sv b/lab_5/SRC/monitor.sv new file mode 100644 index 0000000..2ce97c7 --- /dev/null +++ b/lab_5/SRC/monitor.sv @@ -0,0 +1 @@ +//create a monitor class \ No newline at end of file diff --git a/lab_5/SRC/scoreboard.sv b/lab_5/SRC/scoreboard.sv new file mode 100644 index 0000000..9d05cc0 --- /dev/null +++ b/lab_5/SRC/scoreboard.sv @@ -0,0 +1 @@ +// create scoreboard class \ No newline at end of file diff --git a/lab_5/SRC/tb.sv b/lab_5/SRC/tb.sv new file mode 100644 index 0000000..6ace7a4 --- /dev/null +++ b/lab_5/SRC/tb.sv @@ -0,0 +1,67 @@ +// Contains the FAIL_UNLESS_EQUAL and RND_CHECK macros. +`include "macro.svh" +`include "typedef_pkg.sv" +`include "interface.sv" +`include "scoreboard.sv" +`include "monitor.sv" +`include "generator.sv" +module tb; +import typedef_pkg::*; + +// [Step 1] Declare signals that connect to DUV. Intialize the clk signal with a value of 1'b0 + +// [Step 2] Instantiate the interface, scoreboard, monitor and generator. + + +// [Step 3] Instantiate the DUV module. + + +// [Step 4] Always block to generate the clock. + + +// [Step 5] Create the covergroup for functional covarege. + + +// [Step 6] Instantiate the covergroup. + + + initial begin + + + // [Step 7] Create a new isntance of covergroup. + + repeat (500) begin + @(negedge clk); + + // [Step 8] Call sitimulus task from generator. + + // [Step 9] Pass randomized variables to scoreboard. + + + @(negedge clk); + // [Step 10] Pass result to scoreboard. + + // [Step 11] Start sampling of the functional covarege. + + // Write a randomized parameters and result on screen (in decimal) + + + // [Step 12] call check task from monitor. + + end //Repeat + + + + end //Initial; + + + + +initial begin: B + + #10300; + $display ("finished successfully"); + $finish(); + + end: B +endmodule : tb \ No newline at end of file diff --git a/lab_5/SRC/typedef_pkg.sv b/lab_5/SRC/typedef_pkg.sv new file mode 100644 index 0000000..a7786e6 --- /dev/null +++ b/lab_5/SRC/typedef_pkg.sv @@ -0,0 +1,14 @@ +package typedef_pkg; + + typedef enum logic [1:0] + { + ADD = 2'b00, + MULT = 2'b01, + OR = 2'b10, + AND = 2'b11 + } operation_t; + + typedef logic [7:0] operand_t; + typedef logic [15:0] result_t; + +endpackage : typedef_pkg \ No newline at end of file diff --git a/lab_5/vivado_commands.txt b/lab_5/vivado_commands.txt new file mode 100644 index 0000000..078f0dc --- /dev/null +++ b/lab_5/vivado_commands.txt @@ -0,0 +1,28 @@ +// Help: simulation: (https://itsembedded.com/dhd/vivado_sim_1/) + +call C:\Xilinx\Vivado\2024.2\bin\xvlog --sv ../SRC/duv.sv ../SRC/tb.sv + +call C:\Xilinx\Vivado\2024.2\bin\xelab -debug typical -top tb -snapshot duv_tb_snapshot + +call C:\Xilinx\Vivado\2024.2\bin\xsim duv_tb_snapshot -R + + +call C:\Xilinx\Vivado\2024.2\bin\xsim duv_tb_snapshot --tclbatch xsim_cfg.tcl + +call C:\Xilinx\Vivado\2024.2\bin\xsim --gui duv_tb_snapshot.wdb + + +------------------------------------------------------------------------------------------------------------------------- +// Help: coverage report: (https://docs.xilinx.com/r/en-US/ug900-vivado-logic-simulation/Code-Coverage-Support) + +call C:\Xilinx\Vivado\2024.2\bin\xelab -svlog ../SRC/duv.sv -svlog ../SRC/tb.sv -cc_type sbct -cc_db DB1 -cc_dir ./cRun1 -R + +//To create code coverage report in html + +call C:\Xilinx\Vivado\2024.2\bin\xcrg -cc_db DB1 -cc_dir ./cRun1 -cc_report ./cReport1 + +//To create functional coverage report in html + +call C:\Xilinx\Vivado\2024.2\bin\xcrg -report_format html -dir ./xsim.covdb/ -report_dir ./ + +--------------------------------------------------------------------------------------------------------------------------- \ No newline at end of file -- cgit v1.2.3