feat: Implement homework 1

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diff --git a/homework_1/CST456 Embedded System Testing-HW1.md b/homework_1/CST456 Embedded System Testing-HW1.md
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+# CST456 Embedded System Testing-HW1
+
+**CST456 Embedded System Testing**
+
+**Homework 1**
+
+We wish to design a one-input one-output sequence detector (Mealy Machine) that produces an output value 1 every time the sequences 1100 or 1011 is detected and an output value 0 at all other times. Overlapping sequences are accepted; for example, if the input sequence is **11110000101101100** then the corresponding output sequence is **00000100000100101**. a)Draw a state diagram (State diagram must have the minimum number of states).
+
+b)Write a SystemVerilog code **(duv.sv)** to implement it.
+
+c)Write a simple SytemVerilog testbench **(tb.sv)** to test it.
+
+*Design must have an active high reset. The design should be asynchronous. Time step, current state, reset, input, and output must be printed in the **cmd** command window.*
+
+**Note:** In your simulation use **Vivado** in command line mode. But first create a directory as HW1 and create two more directories under HW1: SRC and SIM. Put your tb.sv and duv.sv codes under SRC directory.
+
+Create a new file and name it as *xsim_cfg.tcl* with the following content: log_wave -recursive *
+
+run all
+
+exit
+
+and save it under SIM directory.
+
+Now open up a command prompt (cmd) and change the directory to SIM. In cmd, under SIM directory run the following commands:
+
+*call C:\Xilinx\Vivado\2023.2\bin\xvlog --sv ../SRC/duv.sv ../SRC/tb.sv*
+
+*call C:\Xilinx\Vivado\2023.2\bin\xelab -debug typical -top tb -snapshot duv_tb_snapshot call C:\Xilinx\Vivado\2023.2\bin\xsim duv_tb_snapshot -R*
+
+*call C:\Xilinx\Vivado\2023.2\bin\xsim duv_tb_snapshot --tclbatch xsim_cfg.tcl*
+
+*call C:\Xilinx\Vivado\2023.2\bin\xsim --gui duv_tb_snapshot.wdb*
+
+We also want to check the code coverage of our design for that purpose run the following
+
+commands in cmd under SIM directory:
+
+*call C:\Xilinx\Vivado\2023.2\bin\xelab -svlog ../SRC/duv.sv -svlog ../SRC/tb.sv -cc_type sbct*
+
+- *cc_db DB1 -cc_dir ./cRun1 -R*
+
+*call C:\Xilinx\Vivado\2023.2\bin\xcrg -cc_db DB1 -cc_dir ./cRun1 -cc_report ./cReport1*
+
+You can find the coverage report in *./cReport1/dashboard.html*
+
+Submit your state diagram and HW1 directory.
diff --git a/homework_1/SIM/build_simulation.bat b/homework_1/SIM/build_simulation.bat
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+@echo off
+call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv ../SRC/duv.sv ../SRC/tb.sv
+call C:\Xilinx\Vivado\2022.1\bin\xelab -debug typical -top tb -snapshot duv_tb_snapshot
+pause
diff --git a/homework_1/SIM/run_simulation.bat b/homework_1/SIM/run_simulation.bat
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+++ b/homework_1/SIM/run_simulation.bat
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+@echo off
+call C:\Xilinx\Vivado\2022.1\bin\xvlog -nolog -sv ../SRC/duv.sv ../SRC/tb.sv
+call C:\Xilinx\Vivado\2022.1\bin\xelab -debug typical -top tb -snapshot duv_tb_snapshot
+call C:\Xilinx\Vivado\2022.1\bin\xsim duv_tb_snapshot -R
+call C:\Xilinx\Vivado\2022.1\bin\xsim duv_tb_snapshot --tclbatch xsim_cfg.tcl
+call C:\Xilinx\Vivado\2022.1\bin\xsim --gui duv_tb_snapshot.wdb
+pause
diff --git a/homework_1/SIM/run_waveform.bat b/homework_1/SIM/run_waveform.bat
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+++ b/homework_1/SIM/run_waveform.bat
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+@echo off
+call C:\Xilinx\Vivado\2022.1\bin\xsim duv_tb_snapshot --tclbatch xsim_cfg.tcl
+call C:\Xilinx\Vivado\2022.1\bin\xsim --gui duv_tb_snapshot.wdb
diff --git a/homework_1/SIM/xsim_cfg.tcl b/homework_1/SIM/xsim_cfg.tcl
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+++ b/homework_1/SIM/xsim_cfg.tcl
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+log_wave -recursive *

+run all

+exit
\ No newline at end of file
diff --git a/homework_1/SRC/duv.sv b/homework_1/SRC/duv.sv
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+++ b/homework_1/SRC/duv.sv
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+module duv (
+    input  logic clock,
+    input  logic reset,
+    input  logic input_,
+    output logic output_
+);
+  localparam S0 = 3'b000,  // Initial
+  S1 = 3'b001,  // Seen "1"
+  S2 = 3'b010,  // Seen "11"
+  S3 = 3'b011,  // Seen "10"
+  S4 = 3'b100,  // Seen "110"
+  S5 = 3'b101;  // Seen "101"
+
+  logic [2:0] state, next_state;
+
+  // State register with asynchronous reset
+  always_ff @(posedge clock or posedge reset) begin
+    if (reset) state <= S0;
+    else state <= next_state;
+  end
+
+  // Next state and output logic
+  always_comb begin
+    next_state = state;
+    output_ = 1'b0;
+
+    case (state)
+      S0: next_state = input_ ? S1 : S0;
+      S1: next_state = input_ ? S2 : S3;
+      S2: next_state = input_ ? S2 : S4;
+      S3: next_state = input_ ? S5 : S0;
+      S4: begin
+        if (input_) begin
+          next_state = S5;
+        end else begin
+          next_state = S0;
+          output_ = 1'b1;  // Detected "1100"
+        end
+      end
+      S5: begin
+        if (input_) begin
+          next_state = S2;
+          output_ = 1'b1;  // Detected "1011"
+        end else begin
+          next_state = S3;
+        end
+      end
+      default: next_state = S0;
+    endcase
+  end
+endmodule
diff --git a/homework_1/SRC/macro.svh b/homework_1/SRC/macro.svh
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+++ b/homework_1/SRC/macro.svh
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+`ifndef MACRO_SVH
+    `define MACRO_SVH
+
+    `define FAIL_UNLESS_EQUAL(a,b,c="") \
+    if ((a) !== (b)) \
+    begin \
+        $display ("FAIL_UNLESS_EQUAL[%s]: Expected %h but actual value is %h.", c, a, b); \
+		$finish; \
+    end
+`endif
diff --git a/homework_1/SRC/tb.sv b/homework_1/SRC/tb.sv
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+++ b/homework_1/SRC/tb.sv
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+`include "macro.svh"
+
+module tb;
+  logic clock = 1'b0;
+  logic reset;
+  logic input_;
+  logic output_;
+
+  localparam int SEQUENCE_LENGTH = 17;
+
+  logic [0:SEQUENCE_LENGTH-1] test_input = 17'b11110000101101100;
+  logic [0:SEQUENCE_LENGTH-1] expected_output = 17'b00000100000100101;
+
+  duv DUT (
+      .clock,
+      .reset,
+      .input_,
+      .output_
+  );
+
+  always #1ns clock = ~clock;
+
+  // Test sequence
+  initial begin
+    automatic int test_count = 0;
+
+    // Initialise
+    reset  = 1'b1;
+    input_ = 1'b0;
+
+    // Hold reset for 2 cycles
+    repeat (2) @(posedge clock);
+
+    reset = 1'b0;
+
+    // Apply test sequence
+    for (int i = 0; i < SEQUENCE_LENGTH; i++) begin
+      input_ = test_input[i];
+
+      @(posedge clock);
+
+      // Check output
+      `FAIL_UNLESS_EQUAL(expected_output[i], output_, $sformatf("step=%0d input=%b", i + 1, input_))
+
+      test_count += 1;
+    end
+
+    $display("All tests passed! Total tests: %0d", test_count);
+    $display("Finished successfully!");
+    $finish;
+  end
+endmodule
diff --git a/homework_1/state_diagram/state_diagram.mmd b/homework_1/state_diagram/state_diagram.mmd
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+stateDiagram-v2
+    [*] --> S0
+    
+    S0: Initial
+    S1: Seen "1"
+    S2: Seen "11"
+    S3: Seen "10"
+    S4: Seen "110"
+    S5: Seen "101"
+    
+    S0 --> S0: 0/0
+    S0 --> S1: 1/0
+    
+    S1 --> S3: 0/0
+    S1 --> S2: 1/0
+    
+    S2 --> S4: 0/0
+    S2 --> S2: 1/0
+    
+    S3 --> S0: 0/0
+    S3 --> S5: 1/0
+    
+    S4 --> S0: 0/1 (1100)
+    S4 --> S5: 1/0
+    
+    S5 --> S3: 0/0
+    S5 --> S2: 1/1 (1011)
diff --git a/homework_1/state_diagram/state_diagram.png b/homework_1/state_diagram/state_diagram.png
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+++ b/homework_1/state_diagram/state_diagram.png