feat(tb.sv): Implement testbench

2 files changed, 103 insertions, 22 deletions

diff --git a/.gitignore b/.gitignore
index e43b0f9..b43521c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,7 @@
 .DS_Store
+*.log
+*.pb
+*.jou
+*.wdb
+xsim.dir
+.Xil
diff --git a/SRC/tb.sv b/SRC/tb.sv
index cc9c3c8..0230705 100644
--- a/SRC/tb.sv
+++ b/SRC/tb.sv
@@ -1,8 +1,8 @@
 // Contains the FAIL_UNLESS_EQUAL macro.
 `include "macro.svh"
 
-    /* [Step 2] Instantiate the DUV module. The module is declared as
-	
+/* [Step 2] Instantiate the DUV module. The module is declared as
+
         module duv
         (
             input logic clk,
@@ -17,24 +17,99 @@
     */
 
 module tb;
+  parameter FULL_TEST = 1;
+
+  // [Step 1] Declare signals. Intialize the clk signal with a value of 1'b0.
+
+  logic clk = 1'b0;
+  logic op_start;
+  logic [1:0] operation;
+  logic [7:0] operand_a;
+  logic [7:0] operand_b;
+  logic [15:0] result;
+
+  // [Step 2] Instantiate the DUV module. The module is declared as
+
+  duv ALU0 (
+      .clk,
+      .op_start,
+      .operation,
+      .operand_a,
+      .operand_b,
+      .result
+  );
+
+  // [Step 3] Always block to generate the clock.
+
+  always #1ns clk = ~clk;
+
+  // [Step 4] Test the DUV using an initial block. Be sure to initialize all DUV input variables, and use the $finish system task
+
+  initial begin
+    automatic logic [15:0] expected_result;
+    automatic int test_count = 0;
+
+    // Initialise all inputs
+    op_start  = 1'b0;
+    operation = 2'b00;
+    operand_a = 8'h00;
+    operand_b = 8'h00;
+
+    // Wait for initial setup and reset
+    repeat (3) @(posedge clk);
+
+    // Exhaustively test all combinations
+    for (int op = 0; op < 4; op++) begin
+      for (int a = 0; a < (FULL_TEST ? 256 : 16); a++) begin
+        for (int b = 0; b < (FULL_TEST ? 256 : 16); b++) begin
+          // Set up inputs and calculate expected result first
+          operation = op[1:0];
+          operand_a = a[7:0];
+          operand_b = b[7:0];
+
+          // Calculate expected result before starting operation
+          case (operation)
+            2'b00: expected_result = (operand_a + operand_b) & 16'h01FF;  // ADD
+            2'b01: expected_result = operand_a * operand_b;               // MULT
+            2'b10: expected_result = (operand_a | operand_b) & 16'h00FF;  // OR
+            2'b11: expected_result = (operand_a & operand_b) & 16'h00FF;  // AND
+          endcase
+
+          // Start the operation
+          op_start = 1'b1;
+
+          // Wait for rising edge to latch inputs
+          @(posedge clk);
+
+          op_start = 1'b0;
+
+          // Wait 2 more clock cycles for result
+          @(posedge clk);
+          @(posedge clk);
+
+          // Compare only relevant bits based on operation
+          case (operation)
+            2'b00:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h01FF, $sformatf(
+                               "ADD a=%0d b=%0d", operand_a, operand_b))
+            2'b01:
+            `FAIL_UNLESS_EQUAL(expected_result, result, $sformatf(
+                               "MULT a=%0d b=%0d", operand_a, operand_b))
+            2'b10:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h00FF, $sformatf(
+                               "OR a=%0d b=%0d", operand_a, operand_b))
+            2'b11:
+            `FAIL_UNLESS_EQUAL(expected_result, result & 16'h00FF, $sformatf(
+                               "AND a=%0d b=%0d", operand_a, operand_b))
+          endcase
+
+          test_count += 1;
+        end
+      end
+    end
 
-// [Step 1] Declare signals. Intialize the clk signal with a value of 1'b0.
-	
-// [Step 2] Instantiate the DUV module. The module is declared as
-
-	duv ALU0 (.clk, .op_start, .operation, .operand_a, .operand_b, .result);	
-	
-// [Step 3] Always block to generate the clock.
-	
-	always #1ns clk = ~clk;
-
-// [Step 4] Test the DUV using an initial block. Be sure to initialize all DUV input variables, and use the $finish system task
-	
-initial begin	
-					
-		$display("Finished Successfully!");
-		$finish;
-	
-	end // Initial end
-
-endmodule : tb
\ No newline at end of file
+    $display("All tests passed! Total tests: %0d", test_count);
+    $display("Finished Successfully!");
+    $finish;
+  end // Initial end
+endmodule : tb